Method for manufacturing power semiconductor device

Abstract

The purpose of the present disclosure is to form a wide buffer layer with less damage accumulation and no interface. In a method for manufacturing a power semiconductor device according to the present disclosure: hydrogen is introduced into a region of a silicon wafer (1) having a first main surface (S1) and a second main surface (S2) opposite to the first main surface (S1), the region including at least a first region which is a region at a predetermined depth from the second main surface (S2); the silicon wafer (1) is irradiated with an electron beam to form a defect in the first region and a second region between the first region and the first main surface; the silicon wafer (1) is subjected to heat treatment to cause reaction of hydrogen and the defect to form a donor; and laser annealing is performed from the first main surface (S1) or the second main surface (S2) of the silicon wafer (1), thereby deactivating the donor in the second region and making the first region a buffer layer (11).

Description

Method for manufacturing a power semiconductor device

[0001] The present disclosure relates to a method for manufacturing a power semiconductor device.

[0002] A vertical IGBT (Insulated Gate Bipolar Transistor) is composed of a region including, from the surface side, a MOS (Metal Oxide Semiconductor) structure, an n-type drift layer, an n-type buffer layer, and a p-type collector layer. A vertical diode is composed of, from the surface side, a p-type anode, an n-type drift layer, an n-type buffer layer, and an n-type cathode layer. Patent Document 1 discloses an IGBT with a vertical structure. Thinning the IGBT and diode is effective in reducing losses, but it also has the adverse effect of reducing the margin for voltage snap-off. As a countermeasure, a wide n-type buffer layer is adopted.

[0003] Patent Document 1 describes a method for manufacturing a buffer layer using proton (hydrogen ion) irradiation or implantation (hereinafter, both will be referred to as "irradiation") and annealing. This method limits the width of the buffer layer that can be created with a single proton irradiation. To form a buffer layer of the desired thickness on the backside of a device, multiple proton irradiations with different irradiation ranges are required.

[0004] Patent Documents 2 and 3 describe methods for producing a buffer layer without using proton irradiation. Patent Document 2 describes a method for bonding wafers with different concentrations. Patent Document 3 describes a method for producing a buffer layer by multi-stage epitaxial growth.

[0005] Patent No. 6090329 Patent No. 2878488 Patent No. 3113156

[0006] When forming a wide n-type buffer layer in an IGBT or diode, the methods described in Patent Documents 1 to 3 have the following problems. In the multistage proton irradiation described in Patent Document 1, the number of irradiations is increased, which causes excess damage to accumulate in the silicon wafer. There is also a problem of interfaces occurring between regions where donors are formed by each irradiation. The bonding method described in Patent Document 2 inevitably causes a problem of bonding interfaces occurring. The multistage epitaxial growth described in Patent Document 3 is vapor phase growth, which inherently takes a long time to manufacture.

[0007] The present disclosure has been made to solve the above problems, and aims to form a wide buffer layer with little accumulation of damage and without an interface.

[0008] The method for manufacturing a power semiconductor device of the present disclosure includes: introducing hydrogen into a region of a silicon wafer having a first main surface and a second main surface opposite the first main surface, the region including at least a first region that is a region from the second main surface to a predetermined depth; irradiating the silicon wafer with a penetrating electron beam to form defects in the first region and a second region between the first region and the first main surface; heat-treating the silicon wafer to react the hydrogen with the defects to form donors; and performing laser annealing from the first main surface or the second main surface of the silicon wafer to inactivate the donors in the second region and turn the first region into a buffer layer.

[0009] According to the method for manufacturing a power semiconductor device of the present disclosure, donors are left only in the first region by introducing hydrogen, penetrating electron beam irradiation, heat treatment, and laser annealing, and the first region can be formed as a buffer layer. Therefore, a wide buffer layer can be formed with little damage accumulation and no interface. Objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0010] 1. A flowchart showing a method for manufacturing a power semiconductor device according to a first embodiment. 2. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 3. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 4. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 5. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 6. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 7. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 8. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 9. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 10. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 11. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 12. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 13. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 14. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 15. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 16. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 17. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 18. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 19. A cross-sectional view showing a manufacturing process of a power semiconductor device according to the first embodiment. 20. A diagram showing the temperature dependence of donor areal density. 21. A diagram showing a hydrogen concentration distribution in a power semiconductor device according to the first embodiment. 21. A flowchart showing a method for manufacturing a power semiconductor device according to a second embodiment. 22. A cross- 10A to 10C are cross-sectional views showing a manufacturing process of a power semiconductor device according to a third embodiment.

[0011] <A. Prerequisite Technology> First, a method for forming a buffer layer by proton irradiation will be described as a prerequisite technology for the technology of the present disclosure.

[0012] Donors that contribute to the formation of buffer layers are formed by combining point defects and hydrogen present in silicon wafers. Point defects are localized disturbances in the crystal lattice and are classified as vacancy-type and interstitial silicon-type. Generally, when point defects and hydrogen combine, the dangling bonds of the point defects are shielded by hydrogen, resulting in no intraband level. However, if the shielding effect of the dangling bonds is insufficient, shallow donor-type levels may form. By utilizing this physical phenomenon, it is possible to control the carrier concentration by controlling the donors formed in silicon wafers and form buffer layers in power semiconductor devices. This results in softer switching waveforms in power semiconductor devices, preventing snap-off or oscillation. Donors are usually formed in silicon wafers using proton irradiation, but they can also be formed by combining helium ion irradiation with some kind of hydrogen introduction process.

[0013] When forming a buffer layer on a silicon wafer, an appropriate annealing process is required after proton irradiation. This is because annealing expands the donor generation region to the backside of the silicon wafer, allowing a buffer layer of the desired thickness to be formed on the backside of the device. If this expansion width is small, a high-resistivity region remains on the backside of the device, resulting in deterioration of the characteristics of the power semiconductor device. However, if multi-stage irradiation is performed to obtain a wide buffer layer, unnecessary damage accumulates in the silicon. Therefore, the following embodiment describes a method for forming a buffer layer of the desired width without using multi-stage irradiation.

[0014] <B. First Embodiment> Fig. 1 is a flowchart showing a method for manufacturing a power semiconductor device according to a first embodiment. Figs. 2 to 11 are cross-sectional views showing the manufacturing process of the power semiconductor device according to the first embodiment. The method for manufacturing the power semiconductor device according to the first embodiment will be described below with reference to these figures. Note that, as an example, a method for manufacturing a vertical IGBT or a vertical diode from an n-type or n-type silicon wafer will be described here.

[0015] Before starting the flow of Fig. 1, a silicon wafer 1 shown in Fig. 2 is prepared. The silicon wafer 1 is cut from an ingot and has a first main surface S1, which is the front surface, and a second main surface S2, which is the back surface opposite to the first main surface S1. The hydrogen concentration of the silicon wafer 1 is, for example, 1 × 10 １３ cm －３ The thickness of the silicon wafer 1 at this stage is W1.

[0016] In step S101 of FIG. 1 , a hydrogen introduction process is performed to control the hydrogen concentration in the silicon wafer 1. In the hydrogen introduction process, the silicon wafer 1 is annealed in either a hydrogen gas or hydrogen plasma atmosphere. For example, the silicon wafer 1 is exposed to a hydrogen atmosphere and annealed in a furnace such as a vertical furnace at a temperature range of 1000°C to 1300°C (627K to 1027K). For example, when annealing is performed at 1100°C for 5 hours, the penetration depth of hydrogen in the silicon is 1.7 cm. Therefore, hydrogen can be impregnated throughout the entire depth direction of the silicon wafer 1 for power semiconductors. FIG. 3 shows the silicon wafer 1 in this state, with the hydrogen-introduced areas indicated by matte hatching.

[0017] A region of the silicon wafer 1 that will become a buffer layer in a later process is referred to as a first region, and a region that will become a drift layer and an anode layer or a MOS structure in a later process is referred to as a second region. In the hydrogen introduction step described above, hydrogen is introduced into the entire depth direction of the silicon wafer 1, i.e., into both the first region and the second region, but it is sufficient that hydrogen is introduced into at least the first region.

[0018] 1, an electron beam irradiation step is performed in which an electron beam is irradiated from the second main surface S2 of the silicon wafer 1. Here, an accelerator is used to irradiate the second main surface S2 of the silicon wafer 1 with electrons accelerated to between several hundred KeV and several tens of MeV. As a result, the electron beam penetrates the silicon wafer 1 for use as a power semiconductor, and point defects 2 are formed throughout the entire thickness direction of the silicon wafer 1, as shown in FIG. 4. That is, point defects 2 are formed in both the first region and the second region.

[0019] The dose of the electron beam depends on the amount of point defects to be formed, but is, for example, 1×10 １２ 1x10 or more １６ cm －２ The second main surface S2 of the silicon wafer 1 may be irradiated with protons or helium ions instead of electron beams to form point defects 2 in localized portions of the silicon wafer.

[0020] 1, a donor activation annealing step is performed to form donors 3. Specifically, the silicon wafer 1 is exposed to an inert gas atmosphere such as nitrogen, and annealed at a temperature of 200° C. to 500° C. This treatment causes hydrogen in the silicon wafer 1 to react with the point defects 2, and donors 3 are formed throughout the entire thickness of the silicon wafer 1, as shown in FIG.

[0021] FIG. 12 shows the donor areal density (cm －２ ) shows the temperature dependence. As shown in FIG. 12, annealing at a temperature lower than 200°C is not preferable because the efficiency of donor formation decreases. Also, annealing at a temperature higher than 500°C is not preferable because the annihilation of donors becomes significant. Therefore, the annealing temperature for donor activation is preferably 200°C or higher and 500°C or lower. The concentration of donor 3 can also be adjusted by the annealing time.

[0022] Next, in step S104 of Fig. 1, a donor local passivation annealing step is performed to locally passivate the donors 3 formed in the second region of the silicon wafer 1. Specifically, as shown in Fig. 6, light in a wavelength band absorbed by silicon is irradiated onto the first main surface S1 of the silicon wafer 1. This causes a local temperature rise near the first main surface S1 of the silicon wafer 1, and heat is conducted in a direction from the first main surface S1 toward the second main surface S2. As shown in Fig. 12, the donors 3 are passivated in the region where the temperature of the silicon rises to 500°C or higher.

[0023] For example, a laser annealing device or a lamp annealing device is used for the light irradiation in this process. The wavelength, power density, and irradiation time of the light are adjusted so as not to passivate the donor 3 in the first region of the silicon wafer 1. By annealing out only the donor 3 in the second region of the silicon wafer 1, the first region where the donor 3 is not passivated becomes a buffer layer 11. This buffer layer 11 is also referred to as a first buffer layer.

[0024] Next, in step S105 of FIG. 1 , a surface structure formation process is performed to form a surface structure of a device on the first main surface S1 side of the silicon wafer 1. The surface structure is also referred to as a first main surface structure. When manufacturing a diode, in the surface structure formation process, as shown in FIG. 7 , a p+ type anode layer 14 is formed on the first main surface S1 of the silicon wafer 1, and an anode electrode 15 is formed on the anode layer 14. When manufacturing an IGBT, a p-type base region is formed on the surface of the silicon wafer 1, an n-type source region is formed, the silicon wafer 1 is dry-etched to form a trench gate, a gate oxide film is formed, a gate electrode made of polysilicon or the like is formed, an interlayer insulating film made of TEOS or the like is formed, and a source electrode is formed.

[0025] 1, a wafer grinding process is performed in which the second main surface S2 is ground to reduce the silicon wafer 1 to a desired thickness. For example, after protecting the first main surface structure, the second main surface S2 of the silicon wafer 1 is ground using a grinding method such as CMP (Chemical Mechanical Polishing). Hereinafter, the silicon wafer 1 after grinding will be referred to as the semiconductor region. The thickness of the silicon wafer 1 after grinding will be referred to as W2.

[0026] 1, a second buffer layer formation step is performed to form a second buffer layer on the second main surface S2 of the silicon wafer 1. For example, as shown in FIG. 9, an n-type second buffer layer 12 is formed by implanting n-type dopant ions such as phosphorus into the second main surface S2. The second buffer layer 12 may be formed by multiple ion implantations. Alternatively, the second buffer layer 12 may be omitted and substituted with the first buffer layer 11.

[0027] Next, in step S108 of FIG. 1 , a back surface structure forming process is performed to form a back surface structure of the device on the second main surface S2 of the silicon wafer 1. Hereinafter, the back surface structure of the device will also be referred to as the second main surface structure. When manufacturing a diode, in the back surface structure forming process, an n+ type cathode layer 16 is formed on the second main surface S2 of the silicon wafer 1, as shown in FIG. 10 . When manufacturing an RFC (Relaxed Field of Cathode) diode, a p+ type cathode layer is partially formed in addition to the n+ type cathode layer. When manufacturing an IGBT, a p+ type collector layer is formed on the back surface of the silicon wafer 1. When manufacturing an RC (Reverse Conductive) IGBT, an n+ cathode layer is partially formed in addition to the collector layer.

[0028] 1, a back electrode is formed on the second main surface S2 of the silicon wafer 1. When a diode is manufactured, the back electrode is the cathode electrode 17 shown in FIG. 11. When an IGBT is manufactured, the back electrode is a collector electrode. This completes the method for manufacturing the power semiconductor device according to the first embodiment.

[0029] 13 schematically shows the hydrogen concentration distribution of the power semiconductor device according to the first embodiment. The solid line shows the hydrogen concentration when the annealing temperature is high or the annealing time is long in the range of 200° C. or higher and 500° C. or lower. The dashed line shows the hydrogen concentration when the annealing temperature is low or the annealing time is short compared to the solid line in the range of 200° C. or higher and 500° C. or lower.

[0030] According to the method for manufacturing a power semiconductor device according to the first embodiment, it is possible to form a wide first buffer layer 11 having no internal interface in a short time without accumulating damage to the silicon wafer 1 by the hydrogen introduction step, the electron beam irradiation step, the donor activation annealing step, and the donor local passivation annealing step.

[0031] In this embodiment, the surface structure forming process, wafer grinding process, second buffer forming process, back surface structure forming process, and back surface electrode forming process are not limited to the above example, and other general IGBT or diode manufacturing methods can be applied.

[0032] C. Second Embodiment In the first embodiment, the first buffer layer (steps S101 to S104 in FIG. 1) is formed before the device structure (steps S105 to S109 in FIG. 1).

[0033] In contrast, in the second embodiment, the first buffer layer is formed after the device structure is formed. However, once the device structure is formed on the silicon wafer 1, the device structure imposes limitations on the subsequent annealing temperature and annealing time. Furthermore, because metal electrodes are generally used for the front surface electrodes of power devices, it is not possible to input heat to the silicon wafer 1 by irradiating it with light from the front surface side after the front surface structure is formed. Therefore, in the method for manufacturing a power semiconductor device according to the second embodiment, heat is input to the silicon wafer 1 by irradiating it with light from the back surface side.

[0034] Fig. 14 is a flowchart showing a method for manufacturing a power semiconductor device according to embodiment 2. The method for manufacturing a power semiconductor device according to embodiment 2 will be described below in accordance with the flow of Fig. 14. Note that, as an example, a method for manufacturing a vertical IGBT or a vertical diode from an n-type or n-type silicon wafer will be described here.

[0035] Before starting the flow of FIG. 14 , a silicon wafer 1 having a thickness W1 is prepared as in the first embodiment. Then, in step S201 of FIG. 14 , a surface structure of a device is formed on the first main surface S1 of the silicon wafer 1. When manufacturing a diode, in the surface structure formation step, as shown in FIG. 15 , a p+ type anode layer 14 is formed on the first main surface S1 of the silicon wafer 1, and an anode electrode 15 is formed on the anode layer 14. The region of the silicon wafer 1 other than the anode layer 14 becomes the drift layer 13. This step is similar to step S105 of FIG. 1 .

[0036] Next, in step S202, a wafer grinding step is performed in which the second main surface S2 is ground to reduce the silicon wafer 1 to a desired thickness. This step is similar to step S106 in Fig. 1. As a result of this step, the thickness of the silicon wafer 1 becomes W2.

[0037] Thereafter, in step S203, a second buffer layer forming step is performed in which a second buffer layer 12 is formed on the second main surface S2 of the silicon wafer 1. This step is similar to step S107 in FIG.

[0038] Next, in step S204, a back surface structure formation step is performed to form a back surface structure of a device on the second main surface S2 of the silicon wafer 1. When a diode is manufactured, in the back surface structure formation step, an n+ type cathode layer 16 is formed on the second main surface S2 of the silicon wafer 1, as shown in Fig. 17. This step is similar to step S108 in Fig. 1.

[0039] Thereafter, in step S205, a hydrogen introduction step is performed to control the hydrogen concentration in the silicon wafer 1. This step is similar to step S101 in Fig. 1, but the upper limit of the annealing temperature is set to a condition that does not destroy the surface structure, for example, 500°C or less. In this step, it is sufficient that hydrogen is introduced into at least the first region of the silicon wafer 1.

[0040] Next, in step S206, an electron beam irradiation step is performed in which an electron beam is irradiated from the second main surface S2 of the silicon wafer 1 to form point defects 2. This step is similar to step S102 in Fig. 1. Fig. 18 shows the silicon wafer 1 in a state in which point defects 2 have been formed by this step.

[0041] Thereafter, in step S207, a donor activation annealing step is performed to form donors 3. This step is similar to step S103 in Fig. 1. Fig. 19 shows the silicon wafer 1 in a state where donors 3 have been formed by this step.

[0042] Next, in step S208, a local donor passivation annealing process is performed to locally passivate the donors 3 formed in the second region of the silicon wafer 1. In the first embodiment, the first main surface S1 is irradiated with light in a wavelength band absorbed by silicon. In this embodiment, the second main surface S2 is irradiated with pulsed laser light in a wavelength band not absorbed by silicon. In this case, if the optical power is strong, localized light absorption can occur only at the focal position of the incident light due to a nonlinear optical effect. That is, the temperature of only the deep portion can be raised to 500°C or higher without heating the second main surface S2 of the silicon wafer 1. In this way, a portion of the donors 3 generated in the donor activation annealing process is passivated. By scanning the focus of the pulsed laser from the first main surface S1 to the bottom of the second region, the donors 3 in the second region can be passivated. As a result, as shown in FIG. 20 , the region of the drift layer 13 where the donors 3 remain becomes the buffer layer 11.

[0043] Thereafter, in step S209, a backside electrode is formed on the second main surface S2 of the silicon wafer 1. This step is the same as step S109 in Fig. 1. This completes the method for manufacturing the power semiconductor device according to the second embodiment.

[0044] Fig. 21 schematically shows the hydrogen concentration distribution in the power semiconductor device according to embodiment 2. In Fig. 21, W3 is the total thickness of the first buffer layer 11, the second buffer layer 12, and the back surface structure. Fig. 21 shows the case where hydrogen is introduced mainly into the first region of the silicon wafer 1 in step S205.

[0045] According to the method for manufacturing a power semiconductor device according to the second embodiment, it is possible to form a wide first buffer layer 11 having no internal interface in a short time without accumulating damage to the silicon wafer 1 by the hydrogen introduction step, the electron beam irradiation step, the donor activation annealing step, and the donor local passivation annealing step.

[0046] In this embodiment, the surface structure forming process, wafer grinding process, second buffer forming process, back surface structure forming process, and back surface electrode forming process are not limited to the above example, and other general IGBT or diode manufacturing methods can be applied.

[0047] <D. Third Embodiment> In a method for manufacturing a power semiconductor device according to a third embodiment, donors 3 are formed in the first region and the second region of the silicon wafer 1, and then the donors 3 are locally inactivated in the second region, thereby forming the donors 3 only in the first region.

[0048] In contrast to this, in the method for manufacturing a power semiconductor device according to the third embodiment, donors 3 are formed locally in the first region of silicon wafer 1 by annealing using light.

[0049] Fig. 22 is a flowchart showing a method for manufacturing a power semiconductor device according to embodiment 3. The method for manufacturing a power semiconductor device according to embodiment 3 will be described below in accordance with the flow of Fig. 22. Note that, as an example, a method for manufacturing a vertical IGBT or a vertical diode from an n-type or n-type silicon wafer will be described here.

[0050] Before starting the flow of Fig. 22, a silicon wafer 1 having a thickness W1 is prepared as in the first and second embodiments. The subsequent processes of steps S301 to S306 are the same as steps S201 to S206 in Fig. 14, and the processes shown in Fig. 15 to Fig. 18 are performed.

[0051] After step S306, in step S307, a donor local activation annealing step is performed to locally convert point defects 2 in the semiconductor region into donors. For example, as shown in Fig. 23, an annealing process is performed in which light such as laser annealing or lamp annealing is irradiated onto the second main surface S2 of the silicon wafer 1. This raises the temperature of the first region of the silicon wafer 1 to a donor formation temperature or higher, for example, 200°C or higher, and donors 3 are locally formed in the first region.

[0052] If the annealing temperature is lower than 200°C, the donor formation efficiency decreases, as shown in Figure 12. Furthermore, if the annealing temperature is higher than 500°C, the annihilation of donors becomes significant. Therefore, the annealing temperature in this process is preferably 200°C or higher and 500°C or lower. The light intensity and irradiation time are adjusted so that the donor concentration becomes the desired value. In this process, of the point defects 2 formed in the silicon wafer 1 by electron beam irradiation, only those point defects 2 present in the first region are converted into donors 3, and the first region becomes the first buffer layer 11.

[0053] Next, in step S308, a back surface structure forming step is performed to form a back surface structure of the device on the second main surface S2 of the silicon wafer 1. This step is similar to step S108 in Fig. 1 and step S204 in Fig. 14. This completes the method for manufacturing the power semiconductor device according to the third embodiment.

[0054] The hydrogen concentration distribution of the power semiconductor device according to the third embodiment is as shown in FIG.

[0055] According to the method for manufacturing a power semiconductor device according to the third embodiment, it is possible to form a wide first buffer layer 11 having no internal interface in a short time without accumulating damage to the silicon wafer 1 by the hydrogen introduction step, the electron beam irradiation step, and the donor local activation annealing step.

[0056] In this embodiment, the surface structure forming process, wafer grinding process, second buffer forming process, back surface structure forming process, and back surface electrode forming process are not limited to the above example, and other general IGBT or diode manufacturing methods can be applied.

[0057] E. Modifications In the first, second and third embodiments, an electron beam irradiation step is performed. However, if point defects are inherently present in the silicon wafer 1, the electron beam irradiation step is not essential.

[0058] In the first embodiment, the hydrogen introduction step, electron beam irradiation step, donor activation annealing step, and donor local deactivation annealing step were performed before the surface structure formation step. Performing the hydrogen introduction step before the surface structure formation step has the advantage of allowing the processing temperature of the hydrogen introduction step to be higher. However, the hydrogen introduction step, electron beam irradiation step, donor activation annealing step, and donor local deactivation annealing step may be appropriately incorporated after the surface structure formation step. The order of the hydrogen introduction step and the electron beam irradiation step may also be reversed. That is, the hydrogen introduction step and the electron beam irradiation step are performed in this order, and the order of the steps can be appropriately changed as long as the silicon temperature does not subsequently exceed 500°C (more preferably 400°C).

[0059] Similarly, in the second embodiment, the hydrogen introduction step, electron beam irradiation step, donor activation annealing step, and donor local passivation annealing step were performed after the rear surface structure formation step, but these steps may be appropriately incorporated after the front surface structure formation step and before the rear surface structure formation step. The order of the hydrogen introduction step and the electron beam irradiation step may also be reversed. That is, after the hydrogen introduction step and the electron beam irradiation step are performed, the donor activation annealing step and the donor local passivation annealing step are performed in this order, and the order of the steps can be appropriately changed as long as the silicon temperature does not subsequently exceed 500°C (more preferably 400°C).

[0060] Similarly, in the third embodiment, the hydrogen introduction step, the electron beam irradiation step, and the donor local activation annealing step are performed after the rear surface structure formation step, but these steps may be appropriately incorporated after the front surface structure formation step and before the rear surface structure formation step. The order of the hydrogen introduction step and the electron beam irradiation step may also be reversed. That is, the order of the steps can be appropriately changed as long as the donor local activation annealing step is performed after the hydrogen introduction step and the electron beam irradiation step, and the silicon temperature does not rise above 500°C (more preferably 400°C) thereafter.

[0061] Furthermore, in the first, second and third embodiments, the hydrogen introduction step is performed on the surface of the silicon wafer, but the hydrogen introduction step may be performed not only on the surface but also on the side surface or the like.

[0062] In addition, in the first, second, and third embodiments, the hydrogen introduction step involves annealing the silicon wafer 1 in either a hydrogen gas or hydrogen plasma atmosphere. However, hydrogen can also be introduced into the silicon wafer 1 by annealing the silicon wafer 1 in a state where a hydrogen-containing film has been deposited on the silicon wafer 1, or by immersing the silicon wafer 1 in a chemical solution containing hydrogen, i.e., an acidic liquid.

[0063] Furthermore, the above description does not specifically address the electrode material, film formation method, concentration of each p-type or n-type region, etc. General design conditions for power semiconductor devices may be applied to these depending on the application.

[0064] In the above description, a diode or an IGBT has been cited as an example of a power semiconductor device manufactured by the manufacturing method according to each embodiment, but a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an SBD (Schottky Barrier Diode), a Thyristor, etc. may also be formed.

[0065] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate. The above description is an example in all respects. It is understood that countless variations not illustrated can be envisioned.

[0066] REFERENCE SIGNS LIST 1 silicon wafer, 2 point defect, 3 donor, 11 first buffer layer, 12 second buffer layer, 13 drift layer, 14 anode layer, 15 anode electrode, 16 cathode layer, 17 cathode electrode, S1 first main surface, S2 second main surface.

Claims

1. A method for manufacturing a power semiconductor device, comprising: introducing hydrogen into a region of a silicon wafer having a first main surface and a second main surface opposite the first main surface, the region including at least a first region being a region from the second main surface to a predetermined depth; irradiating the silicon wafer with a penetrating electron beam to form defects in the first region and a second region between the first region and the first main surface; heat-treating the silicon wafer to react the hydrogen with the defects to form donors; and performing laser annealing from the first main surface or the second main surface of the silicon wafer to inactivate the donors in the second region and use the first region as a buffer layer.

2. The method for manufacturing a power semiconductor device according to claim 1, wherein the introduction of hydrogen is carried out by any one of annealing the silicon wafer in a hydrogen atmosphere, annealing the silicon wafer in hydrogen plasma, annealing the silicon wafer with a hydrogen-containing film deposited on the silicon wafer, or immersing the silicon wafer in an acidic liquid.

3. The method for manufacturing a power semiconductor device according to claim 1 or 2, wherein the laser annealing is a process for locally heating the second region by irradiating the first main surface with light in a wavelength band that is absorbed by silicon.

4. The method for manufacturing a power semiconductor device according to claim 1 or 2, wherein the laser annealing is a process for locally heating the second region by irradiating the second main surface with light in a wavelength band that is not absorbed by silicon and scanning the focal point in the depth direction from the first main surface of the silicon wafer to the bottom of the second region.

5. The method for manufacturing a power semiconductor device according to any one of claims 1 to 4, wherein the second region is heated to 500°C or higher by the laser annealing.

6. A method for manufacturing a power semiconductor device, comprising: introducing hydrogen into a region of a silicon wafer having a first main surface and a second main surface opposite the first main surface, the region including at least a first region that is a region from the second main surface to a predetermined depth; irradiating the silicon wafer with a penetrating electron beam to form defects in the first region and a second region between the first region and the first main surface; and laser annealing the silicon wafer from the second main surface to react the hydrogen with the defects locally in the first region to form donors.

7. The method for manufacturing a power semiconductor device according to claim 6, wherein the introduction of hydrogen is carried out by any one of annealing the silicon wafer in a hydrogen atmosphere, annealing the silicon wafer in hydrogen plasma, annealing the silicon wafer with a hydrogen-containing film deposited on the silicon wafer, or immersing the silicon wafer in an acidic liquid.

8. The method for manufacturing a power semiconductor device according to claim 6 or 7, wherein the laser annealing is a process for locally heating the first region by irradiating the second main surface with light in a wavelength band that is absorbed by silicon.

9. The method for manufacturing a power semiconductor device according to any one of claims 6 to 8, wherein the first region is heated to 250°C or higher by the laser annealing.

Images