Solar cell and manufacturing method therefor

Abstract

The present invention provides a method for manufacturing a solar cell, comprising a step of forming a first semiconductor layer on one surface of a substrate, wherein the step of forming a first semiconductor layer comprises repeatedly performing a cycle that includes a step of forming an amorphous semiconductor layer and a step of crystallizing at least a portion of the amorphous semiconductor layer, the step of forming an amorphous semiconductor layer comprises supplying a silicon-containing gas and a first gas, and the step of crystallizing at least a portion of the amorphous semiconductor layer comprises forming plasma that includes a second gas.

Description

Solar cell and manufacturing method thereof

[0001] The present invention relates to a solar cell and a method for manufacturing the same.

[0002] A solar cell is a device that converts light energy into electrical energy by utilizing the properties of semiconductors.

[0003] A solar cell has a PN junction structure that joins a P (positive) type semiconductor and an N (negative) type semiconductor, and when sunlight is incident on a solar cell of this structure, holes and electrons are generated within the semiconductor due to the energy of the incident sunlight, and at this time, the holes (+) move toward the P-type semiconductor and the electrons (-) move toward the N-type semiconductor due to the electric field generated at the PN junction, so that a potential is generated and power can be generated.

[0004] Solar cells of this type can generally be divided into substrate-type solar cells and thin-film solar cells.

[0005] The above substrate-type solar cell is a solar cell manufactured using a semiconductor material such as silicon as a substrate, and the above thin-film solar cell is a solar cell manufactured by forming a semiconductor in the form of a thin film on a substrate such as glass.

[0006] The above substrate-type solar cell has the advantage of being somewhat more efficient than the above thin-film solar cell, and the above thin-film solar cell has the advantage of having a reduced manufacturing cost compared to the above substrate-type solar cell.

[0007] Various attempts are being made to implement solar cells that can achieve high efficiency even with a thin thickness by forming a crystalline semiconductor layer on an amorphous semiconductor layer of the solar cell.

[0008] The present invention is designed to overcome the disadvantages of the above-mentioned solar cell, and the present invention provides a solar cell having high efficiency even with a thin thickness and a manufacturing method thereof by depositing an amorphous semiconductor layer, then partially crystallizing the deposited semiconductor layer by plasma treatment, and repeating this process in a method for forming a crystalline semiconductor layer.

[0009] In order to achieve the above object, the present invention provides a method for manufacturing a solar cell, comprising: forming a first semiconductor layer on one surface of a substrate; forming the first semiconductor layer comprises a process of repeatedly performing a cycle including a process of forming an amorphous semiconductor layer and a process of crystallizing at least a portion of the amorphous semiconductor layer; forming the amorphous semiconductor layer comprises a process of supplying a silicon-containing gas and a first gas; and crystallizing at least a portion of the amorphous semiconductor layer comprises a process of forming a plasma including a second gas.

[0010] Furthermore, the present invention provides a method for manufacturing a solar cell, wherein the second gas includes a gas comprising one or more of a hydrogen-containing gas, a helium gas, and an argon gas.

[0011] Furthermore, the present invention provides a method for manufacturing a solar cell, wherein the step of forming the amorphous semiconductor layer further includes the step of forming a plasma including a first gas, and the power for forming the plasma including the first gas is lower than the power for forming the plasma including the second gas.

[0012] Furthermore, the present invention provides a method for manufacturing a solar cell, wherein the first gas includes a hydrogen-containing gas.

[0013] Furthermore, the present invention provides a method for manufacturing a solar cell, wherein the step of forming the amorphous semiconductor layer further includes a step of supplying a P-type dopant or an N-type dopant.

[0014] Furthermore, the present invention provides a method for manufacturing a solar cell, wherein the step of forming a buffer layer is further included before the step of forming the first semiconductor layer, and the step of forming the buffer layer includes a step of supplying a silicon-containing gas.

[0015] Furthermore, the present invention provides a method for manufacturing a solar cell, wherein the step of forming the buffer layer further includes a step of forming a plasma containing a fourth gas after the step of supplying the silicon-containing gas, wherein the fourth gas includes a gas comprising one or more of a hydrogen-containing gas, a helium gas, and an argon gas.

[0016] Furthermore, the present invention provides a method for manufacturing a solar cell in which the power for forming a plasma including the second gas is greater than the power for forming a plasma including the fourth gas.

[0017] Furthermore, the present invention provides a method for manufacturing a solar cell, wherein the step of forming the buffer layer further includes a step of forming a plasma containing a third gas, and the third gas includes a hydrogen-containing gas.

[0018] Furthermore, the present invention provides a method for manufacturing a solar cell in which the power for forming a plasma including the fourth gas is lower than the power for forming a plasma including the third gas.

[0019] Furthermore, the present invention provides a method for manufacturing a solar cell, wherein the substrate is made of a semiconductor substrate, and further includes a step of forming an intrinsic semiconductor layer on one surface of the substrate prior to the step of forming the first semiconductor layer.

[0020] Furthermore, the present invention provides a method for manufacturing a solar cell in which the crystallization rate on one surface of the first semiconductor layer is different from the crystallization rate on the other surface of the first semiconductor layer.

[0021] Furthermore, the present invention provides a method for manufacturing a solar cell, wherein a crystallization rate on one surface of the first semiconductor layer is higher than a crystallization rate on the other surface of the first semiconductor layer, and one surface of the first semiconductor layer is closer to the substrate than the other surface of the first semiconductor layer.

[0022] Furthermore, the present invention provides a method for manufacturing a solar cell, including the steps of supplying a first gas into a chamber through a first gas supply pipe from a first gas supply unit; and supplying the silicon-containing gas into the chamber through a second gas supply pipe from a second gas supply unit, wherein the first gas supply unit and the second gas supply unit each supply the first gas and the silicon-containing gas into the chamber simultaneously.

[0023] Furthermore, the present invention provides a solar cell manufacturing method in which the first gas supply pipe and the second gas supply pipe each supply gas into the chamber.

[0024] Furthermore, the present invention provides a method for manufacturing a solar cell, wherein the step of forming the amorphous semiconductor layer further includes the step of forming a plasma containing a first gas, and the plasma containing the first gas is formed after supplying the first gas and the silicon-containing gas.

[0025] Furthermore, the present invention provides a method for manufacturing a solar cell in which the supply of the silicon-containing gas is terminated and the supply of the first gas is maintained when the formation of the plasma including the first gas is terminated.

[0026] Furthermore, the present invention provides a method for manufacturing a solar cell in which a plasma including the second gas is formed while supplying the silicon-containing gas is terminated and supplying the first gas is maintained after formation of the plasma including the first gas is terminated.

[0027] Furthermore, the present invention provides a solar cell comprising a substrate; and a first semiconductor layer provided on the substrate, wherein the first semiconductor layer is formed using the solar cell manufacturing method described above.

[0028] Furthermore, the present invention provides a solar cell including a first buffer layer provided between the substrate and the first semiconductor layer, wherein the first buffer layer has a thickness of 2 Å or more and 5 Å or less.

[0029] According to the present invention as described above, the following effects are achieved.

[0030] According to one embodiment of the present invention, by repeatedly performing a process of depositing an amorphous semiconductor layer and then crystallizing it, a semiconductor layer having a high crystal ratio at a thin thickness can be formed.

[0031] According to one embodiment of the present invention, since a semiconductor layer having a high crystal ratio can be formed at a thin thickness, a solar cell having high electrical conductivity and improved efficiency can be implemented even at a thin thickness.

[0032] According to one embodiment of the present invention, by providing a buffer layer between an amorphous semiconductor layer and a crystalline semiconductor layer, the amorphous semiconductor layer can be prevented from being crystallized or damaged during the process of forming the crystalline semiconductor layer.

[0033] The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

[0034] FIG. 1 is a schematic cross-sectional view of a solar cell according to one embodiment of the present invention.

[0035] FIG. 2 is a schematic cross-sectional view of a solar cell according to another embodiment of the present invention.

[0036] Figure 3 is a flowchart of a solar cell manufacturing method according to one embodiment of the present invention.

[0037] Figure 4 is a flowchart of a solar cell manufacturing method according to another embodiment of the present invention.

[0038] FIG. 5 is a graph showing the supply of a source, etc. over time in a method for manufacturing a solar cell according to one embodiment of the present invention.

[0039] FIG. 6 is a cross-sectional view of a substrate processing device for manufacturing a solar cell according to one embodiment of the present invention.

[0040] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0041] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative and are not limited to the matters illustrated in the drawings. Like reference numerals refer to like components throughout the specification. In addition, in describing the present invention, if a detailed description of a related known technology is judged to unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. When the terms “includes,” “has,” and “consists of” are used in this specification, other parts may be added unless “only” is used. When a component is expressed in the singular, it includes a case where the plural is included unless there is a specifically explicit description.

[0042] When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

[0043] When describing a positional relationship, for example, when the positional relationship between two parts is described as 'on top of', 'upper part of', 'lower part of', 'next to', etc., one or more other parts may be located between the two parts, unless 'right away' or 'directly' is used.

[0044] When describing a temporal relationship, for example, when the temporal continuity is described as 'after', 'following', 'next to', 'before', etc., it can also include cases where it is not continuous, as long as 'right away' or 'directly' is not used.

[0045] While terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, a "first" component referred to below may also be a "second" component within the technical scope of the present invention.

[0046] The features of each of the various embodiments of the present invention can be partially or wholly combined or combined with each other, and various technical connections and operations are possible, and each embodiment can be implemented independently of each other or implemented together in a related relationship.

[0047] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

[0048] FIG. 1 is a schematic cross-sectional view of a solar cell according to one embodiment of the present invention.

[0049] As can be seen in FIG. 1, a solar cell according to one embodiment of the present invention may include a substrate (110), a buffer layer (120), and a first semiconductor layer (130).

[0050] The substrate (110) may be formed of a semiconductor wafer, for example, a silicon wafer, and specifically, may be formed of an N-type silicon wafer or a P-type silicon wafer. As another example, the substrate (110) may be formed of glass or plastic, in which case an N-type semiconductor layer or a P-type semiconductor layer may be deposited on the substrate (110) and used. For convenience of explanation, the following description will focus on the case where the substrate (110) is a semiconductor wafer.

[0051] Although not shown, a rough structure may be formed on at least one of the upper or lower surfaces of the substrate (110). When a rough structure is formed on the upper and lower surfaces of the substrate (110), a rough structure may also be formed on the surfaces of the buffer layer (120) and the first semiconductor layer (130).

[0052] The buffer layer (120) is formed on the substrate (110). The buffer layer (120) is formed on the substrate (110), so that the substrate (110) can be prevented from being damaged during the process of forming the first semiconductor layer (130) on the buffer layer (120).

[0053] The buffer layer (120) may be formed by including an amorphous semiconductor layer. For example, the buffer layer (120) may be formed by depositing an amorphous silicon (Si) layer, or the buffer layer (120) may be formed by depositing an amorphous silicon (Si) thin film layer, plasma treating the amorphous silicon (Si) thin film layer, and then repeating this process in one cycle. In this case, the plasma treatment may be defined as forming a plasma using any one of gases including hydrogen gas and an inert gas. Meanwhile, a method for forming the buffer layer (120) will be described in more detail with reference to FIGS. 3 and 4 below.

[0054] The first semiconductor layer (130) is formed in the form of a thin film on the upper surface of the substrate (110) made of the semiconductor wafer. Specifically, the first semiconductor layer (130) is formed in the form of a thin film on the substrate (110) and the buffer layer (120). The first semiconductor layer (130) can form a PN junction with the substrate (110), and therefore, when the substrate (110) is made of an N-type silicon wafer, the first semiconductor layer (130) can be made of a P-type semiconductor layer. In particular, the first semiconductor layer (130) can be made of P-type silicon doped with a Group III element such as boron (B). Meanwhile, the present invention is not limited thereto, and when the substrate (110) is made of a P-type silicon wafer, the first semiconductor layer (130) can also be made of an N-type semiconductor layer. In this case, the first semiconductor layer (130) may be made of N-type silicon doped with a group 5 element such as phosphorus (P).

[0055] In general, since the drift mobility of holes is lower than that of electrons, it is desirable to form a P-type semiconductor layer close to the light-receiving surface in order to maximize the efficiency of collecting holes by incident light, and therefore, it is desirable that the first semiconductor layer (130) close to the light-receiving surface be formed of a P-type semiconductor layer.

[0056] According to one embodiment of the present invention, the first semiconductor layer (130) may include an amorphous semiconductor layer and a crystalline semiconductor layer. For example, the first semiconductor layer (130) may be formed by depositing an amorphous silicon (Si) thin film layer, plasma treating the amorphous silicon (Si) thin film layer, and then repeating this process in one cycle. By forming the first semiconductor layer (130) in this manner, a plurality of crystalline silicon (Si) layers can be formed, thereby securing high electrical conductivity characteristics. Meanwhile, a method for forming the first semiconductor layer (130) will be described in more detail with reference to FIGS. 3 and 4 below.

[0057] According to one embodiment of the present invention, the first semiconductor layer (130) may include one surface adjacent to the substrate (110), for example, a lower surface, and the other surface opposite to the one surface of the first semiconductor layer (130), for example, an upper surface, and the crystallization rate of the one surface of the first semiconductor layer (130) may be different from the crystallization rate of the other surface of the first semiconductor layer (130). In this case, the crystallization rate may be defined as the ratio of crystalline silicon (Si) formed on any virtual surface formed parallel between the one surface and the other surface of the first semiconductor layer (130).

[0058] Specifically, the crystallization rate on one surface of the first semiconductor layer (130) adjacent to the substrate (110) may be formed to be lower than the crystallization rate on the other surface of the first semiconductor layer (130), and the crystallization rate of the first semiconductor layer (130) may gradually increase from one surface of the first semiconductor layer (130) to the other surface of the first semiconductor layer (130).

[0059] FIG. 2 is a schematic cross-sectional view of a solar cell according to another embodiment of the present invention.

[0060] As can be seen in FIG. 2, a solar cell according to another embodiment of the present invention comprises a substrate (110), a first buffer layer (120a), a second buffer layer (120b), a first semiconductor layer (130a), a second semiconductor layer (130b), a third semiconductor layer (140a), a fourth semiconductor layer (140b), a first transparent conductive layer (200a), a second transparent conductive layer (200b), a first electrode (300a), and a second electrode (300b).

[0061] The substrate (110) may be formed of a semiconductor wafer, for example, a silicon wafer, and specifically, may be formed of an N-type silicon wafer or a P-type silicon wafer. As another example, the substrate (110) may be formed of glass or plastic, in which case an N-type semiconductor layer or a P-type semiconductor layer may be deposited on the substrate (110) and used. For convenience of explanation, the following description will focus on the case where the substrate (110) is a semiconductor wafer.

[0062] Although not shown, a rough structure may be formed on at least one of the upper or lower surfaces of the substrate (110). When the rough structure is formed on the upper and lower surfaces of the substrate (110), the rough structure may also be formed on the surfaces of the first buffer layer (120a), the second buffer layer (120b), the first semiconductor layer (130a), the second semiconductor layer (130b), the third semiconductor layer (140a), the fourth semiconductor layer (140b), the first transparent conductive layer (200a), and the second transparent conductive layer (200b).

[0063] In another embodiment of the present invention illustrated in FIG. 2, a third semiconductor layer (140a) is formed on the upper surface of the substrate (110), and then the first buffer layer (120a) and the first semiconductor layer (130a) are formed on the third semiconductor layer (140a), thereby preventing the occurrence of defects on the upper surface of the substrate (110).

[0064] The third semiconductor layer (140a) may be formed of an intrinsic semiconductor layer, or the third semiconductor layer (140a) may be a semiconductor layer doped at a lower concentration than the first semiconductor layer (130a).

[0065] For example, the third semiconductor layer (140a) may be formed of an intrinsic semiconductor layer.

[0066] Since the third semiconductor layer (140a) is formed as an intrinsic semiconductor layer, a defect may not occur on the upper surface of the substrate (110) during the process of forming the first semiconductor layer (130a) on the substrate (110).

[0067] For another example, the third semiconductor layer (140a) may be a semiconductor layer doped at a relatively lower concentration than the first semiconductor layer (130a).

[0068] The dopant doped in the third semiconductor layer (140a) and the dopant doped in the first semiconductor layer (130a) may be of the same type, for example, the same P type.

[0069] By forming the third semiconductor layer (140a) between the substrate (110) and the first semiconductor layer (130a), the occurrence of defects on the upper surface of the substrate (110) can be prevented.

[0070] At this time, it is preferable that the dopant concentration of the low-concentration doped third semiconductor layer (140a) be controlled to such an extent that no defects occur on the surface of the substrate (110).

[0071] In the case where the dopant concentration of the third semiconductor layer (140a) is formed relatively lower than the dopant concentration of the first semiconductor layer (130a), the first semiconductor layer (130a) and the third semiconductor layer (140a) can be performed in a continuous process within one chamber, so that separate deposition equipment or processes may not be added, and as a result, the solar cell of the present invention has the advantage of excellent productivity.

[0072] The first buffer layer (120a) is formed on the substrate (110). Specifically, the first buffer layer (120a) is formed on the third semiconductor layer (140a). The first buffer layer (120a) is formed on the third semiconductor layer (140a), so that the third semiconductor layer (140a) can be prevented from being damaged in the process of forming the first semiconductor layer (130a) on the first buffer layer (120a). More specifically, the first buffer layer (120a) can prevent the third semiconductor layer (140a) from being partially crystallized in the process of forming the first semiconductor layer (130a).

[0073] The first buffer layer (120a) may be formed by including an amorphous semiconductor layer. For example, the first buffer layer (120a) may be formed by depositing an amorphous silicon (Si) layer, or the first buffer layer (120a) may be formed by depositing an amorphous silicon (Si) thin film layer, plasma-treating the amorphous silicon (Si) thin film layer, and then repeating this process in one cycle.

[0074] The first buffer layer (120a) may be formed to a thickness of 2 Å or more and 20 Å or less. Preferably, the first buffer layer (120a) may be formed to a thickness of 2 Å or more and 10 Å or less. Preferably, the buffer layer (120a) may be formed to a thickness of 2 Å or more and 5 Å or less. When the first buffer layer (120a) is formed to a thickness of less than 2 Å, the substrate (110) and the third semiconductor layer (140a) may be damaged during the plasma treatment process of the first semiconductor layer (130a).

[0075] The first semiconductor layer (130a) is formed in the form of a thin film on the upper surface of the substrate (110) made of the semiconductor wafer. Specifically, the first semiconductor layer (130a) is formed in the form of a thin film on the substrate (110) and the first buffer layer (120a). The first semiconductor layer (130a) can form a PN junction together with the substrate (110), and therefore, when the substrate (110) is made of an N-type silicon wafer, the first semiconductor layer (130a) can be made of a P-type semiconductor layer. In particular, the first semiconductor layer (130a) can be made of P-type silicon doped with a Group III element such as boron (B).

[0076] In general, since the drift mobility of holes is lower than that of electrons, it is desirable to form a P-type semiconductor layer close to the light-receiving surface in order to maximize the efficiency of collecting holes by incident light, and therefore, it is desirable for the first semiconductor layer (130a) close to the light-receiving surface to be formed of a P-type semiconductor layer.

[0077] According to one embodiment of the present invention, the first semiconductor layer (130a) may include an amorphous semiconductor layer and a crystalline semiconductor layer. For example, the first semiconductor layer (130a) may be formed by depositing an amorphous silicon (Si) thin film layer, plasma treating the amorphous silicon (Si) thin film layer, and then repeating this process in one cycle. By forming the first semiconductor layer (130a) in this manner, a plurality of crystalline silicon (Si) layers can be formed, thereby ensuring high electrical conductivity characteristics. Meanwhile, a method for forming the first semiconductor layer (130a) will be described in more detail with reference to FIGS. 3 and 4 below.

[0078] According to one embodiment of the present invention, the first semiconductor layer (130a) may include one surface, for example, a lower surface, adjacent to the third semiconductor layer (140a) formed as the intrinsic semiconductor layer, and the other surface, for example, an upper surface, opposite to the one surface of the first semiconductor layer (130a), and the crystallization rate of the one surface of the first semiconductor layer (130a) may be different from the crystallization rate of the other surface of the first semiconductor layer (130a). In this case, the crystallization rate may be defined as the ratio of crystalline silicon (Si) formed on any virtual surface formed parallel between the one surface and the other surface of the first semiconductor layer (130a).

[0079] Specifically, the crystallization rate on one surface of the first semiconductor layer (130a) adjacent to the third semiconductor layer (140a) formed of the intrinsic semiconductor layer may be formed to be lower than the crystallization rate on the other surface of the first semiconductor layer (130a), and the crystallization rate of the first semiconductor layer (130a) may gradually increase from one surface of the first semiconductor layer (130a) to the other surface of the first semiconductor layer (130a).

[0080] The above first transparent conductive layer (200a) is provided on the upper surface of the above first semiconductor layer (130a).

[0081] The first transparent conductive layer (200a) is formed in the form of a thin film on the upper surface of the first semiconductor layer (130a). The first transparent conductive layer (200a) collects carriers, for example, holes, generated in the substrate (110) and moves the collected carriers to the first electrode (300a).

[0082] The first transparent conductive layer (200a) may be made of a transparent conductive material such as ITO (Indium Tin Oxide), ZnOH, ZnO:B, ZnO:Al, SnO2, SnO2:F, etc., and among them, ITO may be selected.

[0083] The above first transparent conductive layer (200a) may be formed by a sputtering process or a chemical vapor deposition (CVD) process.

[0084] The first electrode (300a) is formed on the first transparent conductive layer (200a) to form the front surface of the solar cell. Accordingly, the first electrode (300a) is patterned into a predetermined shape so that sunlight can penetrate into the interior of the solar cell.

[0085] The first electrode (300a) may be made of any one metal selected from the group consisting of Ag, Cu, Al, Mo, and W. Meanwhile, the first electrode (300a) is not limited thereto and may be formed into one or more multilayer structures.

[0086] In another embodiment of the present invention illustrated in FIG. 2, furthermore, the fourth semiconductor layer (140b) is formed on the lower surface of the substrate (110), and then the second semiconductor layer (130b) is formed on the second buffer layer (120b) and the fourth semiconductor layer (140b), thereby preventing the occurrence of defects on the lower surface of the substrate (110). Meanwhile, although FIG. 2 illustrates a state in which both the third semiconductor layer (140a) and the fourth semiconductor layer (140b) are formed, only one semiconductor layer among the third semiconductor layer (140a) and the fourth semiconductor layer (140b) may be formed.

[0087] The fourth semiconductor layer (140b) may be formed of an intrinsic semiconductor layer, or the fourth semiconductor layer (140b) may be a semiconductor layer doped at a lower concentration than the second semiconductor layer (130b).

[0088] For example, the fourth semiconductor layer (140b) may be formed of an intrinsic semiconductor layer.

[0089] Since the fourth semiconductor layer (140b) is formed as an intrinsic semiconductor layer, a defect may not occur on the lower surface of the substrate (110) during the process of forming the second semiconductor layer (130b) on the substrate (110).

[0090] For another example, the fourth semiconductor layer (140b) may be a semiconductor layer doped at a relatively lower concentration than the second semiconductor layer (130b).

[0091] The dopant doped in the fourth semiconductor layer (140b) and the dopant doped in the second semiconductor layer (130b) may be of the same type, for example, the same N type.

[0092] By forming the fourth semiconductor layer (140b) between the substrate (110) and the second semiconductor layer (130b), the occurrence of defects on the lower surface of the substrate (110) can be prevented.

[0093] At this time, it is preferable that the dopant concentration of the fourth semiconductor layer (140b) doped at a low concentration is controlled to a degree that no defects occur on the surface of the substrate (110).

[0094] In the case where the dopant concentration of the fourth semiconductor layer (140b) is formed relatively lower than the dopant concentration of the second semiconductor layer (130b), the second semiconductor layer (130b) and the fourth semiconductor layer (140b) can be performed in a continuous process within one chamber, so that separate deposition equipment or processes may not be added, and as a result, the solar cell of the present invention has the advantage of excellent productivity.

[0095] The second buffer layer (120b) is formed on the substrate (110). Specifically, the second buffer layer (120b) is formed on the fourth semiconductor layer (140b). The second buffer layer (120b) is formed on the fourth semiconductor layer (140b), so that the fourth semiconductor layer (140b) can be prevented from being damaged in the process of forming the second semiconductor layer (130b) on the second buffer layer (120b). More specifically, the second buffer layer (120b) can prevent the fourth semiconductor layer (140b) from being partially crystallized in the process of forming the second semiconductor layer (130b).

[0096] The second buffer layer (120b) may be formed by including an amorphous semiconductor layer. For example, the second buffer layer (120b) may be formed by depositing an amorphous silicon (Si) layer, or the second buffer layer (120b) may be formed by depositing an amorphous silicon (Si) thin film layer, plasma-treating the amorphous silicon (Si) thin film layer, and then repeating this process in one cycle. Meanwhile, a method for forming the second buffer layer (120b) will be described in more detail with reference to FIGS. 3 and 4 below.

[0097] The second buffer layer (120b) may be formed with a thickness of 2 Å or more and 20 Å or less. Preferably, the second buffer layer (120b) may be formed with a thickness of 2 Å or more and 10 Å or less. Preferably, the buffer layer (120a) may be formed with a thickness of 2 Å or more and 5 Å or less. When the second buffer layer (120b) is formed with a thickness of less than 2 Å, the substrate (110) and the fourth semiconductor layer (140a) may be damaged during the plasma treatment process of the second semiconductor layer (130b).

[0098] The second semiconductor layer (130b) is formed in the form of a thin film on the lower surface of the substrate (110) made of the semiconductor wafer. The second semiconductor layer (130b) is formed to have a different polarity from the first semiconductor layer (130a). When the first semiconductor layer (130a) is formed of a P-type semiconductor layer doped with a Group 3 element such as boron (B), the second semiconductor layer (130b) is formed of an N-type semiconductor layer doped with a Group 5 element such as phosphorus (P). In particular, the second semiconductor layer (130b) may be formed of N-type amorphous silicon.

[0099] According to one embodiment of the present invention, the second semiconductor layer (130b) may include an amorphous semiconductor layer and a crystalline semiconductor layer. For example, the second semiconductor layer (130b) may be formed by depositing an amorphous silicon (Si) thin film layer, plasma treating the amorphous silicon (Si) thin film layer, and then repeating this process in one cycle. By forming the second semiconductor layer (130b) in this manner, a plurality of crystalline silicon (Si) layers can be formed, thereby ensuring high electrical conductivity characteristics. Meanwhile, a method for forming the second semiconductor layer (130b) will be described in more detail with reference to FIGS. 3 and 4 below.

[0100] According to one embodiment of the present invention, the second semiconductor layer (130b) may include one surface, for example, an upper surface, adjacent to the fourth semiconductor layer (140b) formed as the intrinsic semiconductor layer, and the other surface, for example, a lower surface, opposite to one surface of the second semiconductor layer (130b), and the crystallization rate of one surface of the second semiconductor layer (130b) may be different from the crystallization rate of the other surface of the second semiconductor layer (130b). In this case, the crystallization rate may be defined as the ratio of crystalline silicon (Si) formed on any virtual surface formed parallel between the one surface and the other surface of the second semiconductor layer (130b).

[0101] Specifically, the crystallization rate on one surface of the second semiconductor layer (130b) adjacent to the fourth semiconductor layer (140b) formed of the intrinsic semiconductor layer may be formed to be lower than the crystallization rate on the other surface of the second semiconductor layer (130b), and the crystallization rate of the second semiconductor layer (130b) may gradually increase from one surface of the second semiconductor layer (130b) to the other surface of the second semiconductor layer (130b).

[0102] The second transparent conductive layer (200b) is formed in the form of a thin film on the lower surface of the second semiconductor layer (130b). The second transparent conductive layer (200b) collects carriers, for example, electrons, generated in the substrate (110) and transfers the collected carriers to the second electrode (300b).

[0103] The second transparent conductive layer (200b) may be made of a transparent conductive material such as ITO (Indium Tin Oxide), ZnOH, ZnO:B, ZnO:Al, SnO2, SnO2:F, etc., and among them, ITO may be selected.

[0104] The above second transparent conductive layer (200b) may be formed by a sputtering process or a CVD process.

[0105] The second electrode (300b) is formed on the lower surface of the second transparent conductive layer (200b). Since the second electrode (300b) is formed on the very back surface of the solar cell, it may be formed on the entire lower surface of the second transparent conductive layer (200b). However, as illustrated, the second electrode (300b) may be patterned so that reflected sunlight can be incident through the back surface of the solar cell.

[0106] The second electrode (300b) is pattern-formed on the lower surface of the second transparent conductive layer (200b). The second electrode (300b) may be formed of any one metal selected from the group consisting of Ag, Cu, Al, Mo, and W. Meanwhile, the second electrode (300b) is not limited thereto and may be formed in a multilayer structure of one or more layers.

[0107] FIG. 3 is a flowchart of a solar cell manufacturing method according to one embodiment of the present invention. In this case, the embodiment of FIG. 3 relates to a manufacturing method for forming the first buffer layer (or second buffer layer) and the first semiconductor layer (or second semiconductor layer) of FIG. 2.

[0108] As can be seen from FIG. 3, a method for manufacturing a solar cell according to one embodiment of the present invention may include a step of forming a buffer layer and a step of forming a first semiconductor layer (or a second semiconductor layer).

[0109] The step of forming the above buffer layer may include a first deposition process (S11) and a first plasma treatment process (S12).

[0110] First, the first deposition process (S11) may be performed. In this case, the first deposition process (S11) may include a step of injecting a silicon (Si)-containing gas (S111) and a step of forming a first plasma containing a first gas (S112).

[0111] After performing the first deposition process (S11), a semiconductor layer containing amorphous silicon (Si) can be formed on the substrate (see 110 of FIGS. 1 and 2).

[0112] First, a step (S111) of injecting the silicon (Si)-containing gas and a step (S112) of forming a first plasma containing the first gas may be performed as the first deposition process (S11). For example, when the first deposition process (S11) is performed using plasma enhanced chemical vapor deposition (PECVD), the step (S111) of injecting the silicon (Si)-containing gas and the step (S112) of forming the first plasma containing the first gas may be performed simultaneously. However, the present invention is not limited thereto.

[0113] According to one embodiment of the present invention, the gas containing silicon (Si) may include silane (SiH4), and the first gas may include hydrogen (H2), but is not limited thereto.

[0114] Next, the first plasma treatment process (S12) may be performed. The first plasma treatment process (S12) may include a step of forming a second plasma containing a second gas. In this case, the second gas may include any one of a hydrogen (H2)-containing gas and an inert gas, or a gas combining the two. For example, when the second gas contains an inert gas, the second gas may be, but is not limited to, helium (He) or argon (Ar) gas.

[0115] By performing the first plasma treatment process (S12), a partially crystallized seed layer can be formed on the upper surface of the buffer layer (see 120 of FIG. 1, 120a, 120b of FIG. 2), for example, on the surface adjacent to the first semiconductor layer (see 130 of FIG. 1, 130a of FIG. 2) or the second semiconductor layer (see 130b of FIG. 2), and by forming the seed layer, crystals can grow at a rapid rate in the process of forming the first semiconductor layer (or the second semiconductor layer).

[0116] In the step of forming a second plasma including a second gas in the first plasma treatment process (S12), the power for forming the second plasma may be applied at a lower intensity than the power for forming the first plasma in the step of forming the first plasma including the first gas (S112). For example, power of 2.0 kW or less may be applied to form the first plasma, but is not limited thereto.

[0117] The buffer layer (see 120 of FIG. 1 or 120a, 120b of FIG. 2) can be formed by repeatedly performing the first deposition process (S11) and the first plasma treatment process (S12) as one cycle. In this case, by performing one cycle including the first deposition process (S11) and the first plasma treatment process (S12) multiple times, the thickness of the buffer layer (see 120 of FIG. 1 or 120a, 120b of FIG. 2) can be formed to a thickness of, for example, 2 Å or more and 20 Å or less. Preferably, the buffer layer (see 120 of FIG. 1 or 120a, 120b of FIG. 2) can be formed to a thickness of 2 Å or more and 10 Å or less. Preferably, the buffer layer (see 120 in FIG. 1 or 120a, 120b in FIG. 2) can be formed with a thickness of 2 Å or more and 5 Å or less.

[0118] The step of forming the first semiconductor layer (or the second semiconductor layer) may be performed after the step of forming the buffer layer. Accordingly, the step of forming the first semiconductor layer (or the second semiconductor layer) may be performed on the buffer layer (see 120 of FIG. 1 or 120a, 120b of FIG. 2) formed by performing the step of forming the buffer layer.

[0119] The step of forming the first semiconductor layer (or second semiconductor layer) may include a second deposition process (S21) and a second plasma treatment process (S22).

[0120] First, the second deposition process (S21) may be performed. In this case, the second deposition process (S21) may include a step of injecting a silicon (Si)-containing gas (S211) and a step of forming a third plasma containing a third gas (S212).

[0121] After performing the second deposition process (S21), a semiconductor layer containing amorphous silicon (Si) can be formed on the buffer layer (see 120 in FIG. 1 or 120a, 120b in FIG. 2).

[0122] First, a step (S211) of injecting the silicon (Si)-containing gas and a step (S212) of forming a third plasma containing the third gas may be performed as the second deposition process (S21). For example, when the second deposition process (S21) is performed using plasma enhanced chemical vapor deposition (PECVD), the step (S211) of injecting the silicon (Si)-containing gas and the step (S212) of forming a third plasma containing the third gas may be performed simultaneously. However, the present invention is not limited thereto.

[0123] According to one embodiment of the present invention, the gas containing silicon (Si) may include silane (SiH4), and the third gas may include hydrogen (H2), but is not limited thereto.

[0124] In the step (S212) of forming a third plasma including the third gas, the power for forming the third plasma may be the same as the power for forming the first plasma in the step (S112) of forming the first plasma including the first gas. In this case, the amorphous semiconductor layer of the buffer layer or the first semiconductor layer (or the second semiconductor layer) may be formed through the same process in the same chamber.

[0125] Next, the second plasma treatment process (S22) may be performed. The second plasma treatment process (S22) may include a step of forming a fourth plasma containing a fourth gas. In this case, the fourth gas may include any one of a hydrogen (H2)-containing gas and an inert gas, or a gas comprising a combination thereof. For example, when the fourth gas contains an inert gas, the fourth gas may be, but is not limited to, helium (He) or argon (Ar) gas.

[0126] In the step of forming a fourth plasma including a fourth gas in the second plasma treatment process (S22), the power for forming the fourth plasma may be applied at a lower intensity than the power for forming the third plasma in the step of forming a third plasma including the third gas (S212). For example, power of 7.0 kW or more may be applied to form the third plasma, but is not limited thereto.

[0127] By repeatedly performing the second deposition process (S21) and the second plasma treatment process (S22) as one cycle, the first semiconductor layer (see 130 of FIG. 1 or 130a of FIG. 2) or the second semiconductor layer (see 130b of FIG. 2) can be formed. According to one embodiment of the present invention, by continuously and repeatedly performing one cycle in which the second deposition process (S21) and the second plasma treatment process (S22) are each performed once, the first semiconductor layer (see 130a of FIG. 2) or the second semiconductor layer (see 130b of FIG. 2) having a high degree of crystallinity even at a thin thickness can be formed.

[0128] Furthermore, according to an embodiment of the present invention, in the step of forming the fourth plasma including the fourth gas in the second plasma treatment process (S22), the power for forming the fourth plasma may be higher in intensity than the power for forming the second plasma in the step of forming the second plasma including the second gas in the first plasma treatment process (S12).

[0129] By forming in this manner, it is possible to prevent the substrate (see 110 of FIGS. 1 and 2), the third semiconductor layer (see 140a of FIG. 2), or the fourth semiconductor layer (see 140b of FIG. 2) from being damaged by the first plasma formed in the first plasma treatment process (S12) in the step of forming the buffer layer. In addition, in the step of forming the first semiconductor layer, a part of the amorphous semiconductor layer formed in the second deposition process (S21) is crystallized, thereby improving electrical conductivity and realizing a high-efficiency solar cell. Furthermore, a high-efficiency solar cell can be realized even if a relatively small amount of gas is used.

[0130] FIG. 4 is a flowchart of a solar cell manufacturing method according to another embodiment of the present invention. The embodiment of FIG. 4 relates to a manufacturing method for forming the first buffer layer (or second buffer layer) and the first semiconductor layer (or second semiconductor layer) of FIG. 2. Meanwhile, the embodiment of FIG. 4 is identical to the embodiment of FIG. 3 except for the method for forming the first buffer layer (or second buffer layer), and therefore, the following description will focus on the different configurations.

[0131] As can be seen from FIG. 4, a method for manufacturing a solar cell according to one embodiment of the present invention may include a step of forming a buffer layer and a step of forming a first semiconductor layer (or a second semiconductor layer).

[0132] The step of forming the above buffer layer may include a third deposition process (S31). In this case, in the embodiment of FIG. 4, unlike the embodiment of FIG. 3, a separate plasma treatment process may not be performed. In this case, according to the embodiment of FIG. 4, the process time can be shortened by not performing an additional process.

[0133] First, the third deposition process (S31) may be performed. In this case, the third deposition process (S31) may include a step of injecting a silicon (Si)-containing gas (S311) and a step of forming a first plasma containing a first gas (S312).

[0134] After performing the third deposition process (S31), a semiconductor layer containing amorphous silicon (Si) can be formed on the substrate (see 110 in FIGS. 1 and 2).

[0135] First, a step (S311) of injecting the silicon (Si)-containing gas and a step (S312) of forming a first plasma containing the first gas may be performed as the third deposition process (S31). For example, when the third deposition process (S31) is performed using plasma enhanced chemical vapor deposition (PECVD), the step (S311) of injecting the silicon (Si)-containing gas and the step (S312) of forming the first plasma containing the first gas may be performed simultaneously. However, the present invention is not limited thereto.

[0136] According to one embodiment of the present invention, the gas containing silicon (Si) may include silane (SiH4), and the first gas may include hydrogen (H2), but is not limited thereto.

[0137] By repeatedly performing the third deposition process (S31), the buffer layer (see 120 of FIG. 1 or 120a, 120b of FIG. 2) can be formed. In this case, by performing one cycle including the third deposition process (S31) multiple times, the thickness of the buffer layer (see 120 of FIG. 1 or 120a, 120b of FIG. 2) can be formed to a thickness of, for example, 2 Å or more and 20 Å or less. Preferably, the buffer layer (see 120 of FIG. 1 or 120a, 120b of FIG. 2) can be formed to a thickness of 2 Å or more and 10 Å or less. Preferably, the buffer layer (see 120 of FIG. 1 or 120a, 120b of FIG. 2) can be formed to a thickness of 2 Å or more and 5 Å or less.

[0138] FIG. 5 is a graph showing the supply of a silicon (Si)-containing gas, a hydrogen (H2)-containing gas, and a plasma power source over time for forming a first semiconductor layer (or a second semiconductor layer) in a method for manufacturing a solar cell according to one embodiment of the present invention.

[0139] As can be seen in FIG. 5, when a deposition process is performed, for example, in a second deposition process (see S21 of FIG. 3 or FIG. 4) for forming a first semiconductor layer (or a second semiconductor layer), a silicon (Si)-containing gas and a hydrogen (H2)-containing gas may be supplied first, and after the silicon (Si)-containing gas and the hydrogen (H2)-containing gas are supplied, a plasma power source for the deposition process may be driven to form the third plasma (see S21 of FIG. 3 or FIG. 4).

[0140] When a plasma treatment process is performed, for example, in a second plasma treatment process (see S22 of FIG. 3 or FIG. 4) for forming a first semiconductor layer (or a second semiconductor layer), the supply of a silicon (Si)-containing gas is stopped, but the supply of the hydrogen (H2)-containing gas can be maintained. In this case, the plasma power source can be turned off, thereby stopping the formation of the third plasma.

[0141] Next, the plasma power source may be driven again to form the fourth plasma (see S22 of FIG. 3 or FIG. 4). In this case, the power of the plasma power source for forming the third plasma and the power of the plasma power source for forming the fourth plasma may be different from each other.

[0142] FIG. 6 is a cross-sectional view of a substrate processing device for manufacturing a solar cell according to one embodiment of the present invention.

[0143] As can be seen in FIG. 6, a substrate processing device for manufacturing a solar cell according to an embodiment of the present invention includes a chamber (40), a substrate support device (50) provided in the chamber (40) and installed inside the chamber (40) to support a substrate (S) provided in the chamber (40), a gas supply device (600) installed inside the chamber (40) to spray gas to the substrate support device (50), and a power supply device (400) connected to the gas supply device (600) to supply power to the gas supply device (600) to generate plasma in the chamber (40). In addition, the substrate processing device may further include a control device (not shown) for controlling the power supply device (400).

[0144] The chamber (40) provides a predetermined reaction space and maintains it airtight. The chamber (40) may include a body (44) having a predetermined reaction space, including a flat surface of approximately circular or rectangular shape and a side wall extending upward from the flat surface, and a lid (42) positioned on the body (44) in an approximately circular or rectangular shape to maintain the reaction space airtight. However, the chamber (40) is not limited thereto and may be manufactured in various shapes corresponding to the shape of the substrate (S).

[0145] An exhaust port (not shown) may be formed in a predetermined area on the lower surface of the chamber (40), and an exhaust pipe (not shown) connected to the exhaust port may be provided on the outside of the chamber (40). In addition, the exhaust pipe may be connected to an exhaust device (not shown). A vacuum pump such as a turbo molecular pump may be used as the exhaust device. Therefore, the inside of the chamber (40) may be vacuum-sucked to a predetermined reduced pressure atmosphere, for example, a predetermined pressure of 0.1 mTorr or less, by the exhaust device. The exhaust pipe may be installed not only on the lower surface of the chamber (40) but also on the side surface of the chamber (40) below the substrate support device (50) described below. In addition, it goes without saying that a plurality of exhaust pipes and corresponding exhaust devices may be further installed in order to reduce the exhaust time.

[0146] Meanwhile, the substrate (S) provided into the chamber (40) for a substrate processing process, for example, a thin film deposition process, can be mounted on the substrate support device (50). The substrate support device (50) can be equipped with, for example, an electrostatic chuck to hold the substrate (S) by electrostatic force so that the substrate (S) can be mounted and supported, or the substrate (S) can be supported by vacuum suction or mechanical force.

[0147] The substrate support device (50) may be provided in a shape corresponding to the shape of the substrate (S), for example, a circle or a square. The substrate support device (50) may include the substrate support (52) on which the substrate (S) is mounted, and an elevator (54) disposed below the substrate support (52) to move the substrate support (52) up and down. Here, the substrate support (52) may be manufactured to be larger than the substrate (S), and the elevator (54) is provided to support at least one area, for example, the center, of the substrate support (52), and when the substrate (S) is mounted on the substrate support (52), the substrate support (52) may be moved closer to the gas injection device (600). In addition, a heater (not shown) may be installed inside the substrate support (52). The heater generates heat to a predetermined temperature to heat the substrate support (52) and the substrate (S) mounted on the substrate support (52), so that a thin film is uniformly deposited on the substrate (S).

[0148] A gas providing device may be installed in the lid (42) of the chamber (40). The gas providing device may be installed to penetrate the lid (42) of the chamber (40), and may include a first gas providing unit (410) and a second gas providing unit (420) to provide a first gas and a second gas to the gas injection device (600), respectively. Here, the first gas may include a source gas, and the second gas may include a reaction gas. However, the present invention is not limited thereto, and the first gas may include a reaction gas, the second gas may include a source gas, or at least one of the first gas and the second gas may include a mixed gas in which the source gas and the reaction gas are mixed. In addition, it goes without saying that at least one of the first gas and the second gas may be a purge gas. That is, the first gas providing unit (410) and the second gas providing unit (420) do not necessarily provide only one gas, and the first gas providing unit (410) and the second gas providing unit (420) may be configured to supply multiple gases simultaneously or to supply a gas selected from among multiple gases.

[0149] The gas injection device (600) is installed inside the chamber (40), for example, on the lower surface of the lid (42), and a first gas supply path for supplying a first gas by injecting it onto a substrate and a second gas supply path for supplying a second gas by injecting it onto the substrate are formed inside the gas injection device (600). The first gas supply path and the second gas supply path are provided to be independent and separate from each other, so that the first gas and the second gas can be supplied onto the substrate separately without being mixed within the gas injection device (600).

[0150] More specifically, the gas injection device (600) is provided with a first gas supply path and a second gas supply path separated from each other, and includes a first plate having a first gas supply port (612) and a second gas supply port (614) connected to the first gas supply path and the second gas supply path, respectively, and a second plate (630) having a plurality of openings (632) spaced apart from the first plate and arranged in an alternating manner with the first gas supply port (612) and the second gas supply port (614).

[0151] The first plate may include an upper frame (610) and a lower frame (620). Here, the upper frame (610) is detachably attached to the lower surface of the lid (42) and a portion of the upper surface, for example, a central portion of the upper surface, is spaced apart from the lower surface of the lid (42) by a predetermined distance. Accordingly, the first gas provided from the first gas providing unit (410) can diffuse in the space between the upper surface of the upper frame (610) and the lower surface of the lid (42). In addition, the lower frame (620) is installed at a predetermined distance from the lower surface of the upper frame (610). Accordingly, the second gas provided from the second gas providing unit (420) can diffuse in the space between the upper surface of the lower frame (620) and the lower surface of the upper frame (610). The upper frame (610) and the lower frame (620) may be formed integrally so that a separation space is provided inside by being connected along the outer circumference, and may also be formed to have a structure in which the outer circumference is sealed by a first sealing member (650). In this case, the first sealing member (650) may be formed of an insulating material for electrically insulating the upper frame (610) and the lower frame (620) from each other, or conversely, may be formed of a conductive material for electrically connecting the upper frame (610) and the lower frame (620) to each other.

[0152] The first gas supply path may be formed so that the first gas provided from the first gas provider (410) diffuses in the space between the lower surface of the lid (42) and the upper frame (610), and is supplied into the chamber (40) by penetrating the upper frame (610) and the lower frame (620). At this time, the first gas supply port (612) may be formed to be connected to the first gas supply path, and may be formed by penetrating the upper frame (610) and the lower frame (620) so as to be isolated from the space between the upper surface of the upper frame (610) and the lower surface of the lid (42) by penetrating the upper frame (610) and the lower frame (620).

[0153] In addition, the second gas supply path may be formed so that the second gas provided from the second gas provider (420) diffuses in the space between the lower surface of the upper frame (610) and the upper surface of the lower frame (620) and is supplied into the chamber (40) by penetrating the lower frame (620). At this time, the second gas supply port (622) may be formed by being connected to the second gas supply path, and may be formed at the lower portion of the space between the lower surfaces of the upper frame (610) and penetrating the lower frame (620).

[0154] Accordingly, the first gas supply path and the second gas supply path may not be connected to each other, and the first gas and the second gas may be separately supplied downward from the gas supply device through the first plate.

[0155] The second plate (630) may be installed spaced apart from the lower side of the lower frame (620). That is, the second plate (630) is installed spaced apart from the lower side of the lower frame (620) by a predetermined distance (D1). Accordingly, the first gas and the second gas supplied downward through the first plate may diffuse in the space between the upper surface of the second plate (630) and the lower side of the lower frame (620). The lower frame (620) and the second plate (630) may be formed integrally so that a spaced apart space is provided inside by being connected along the outer circumference, but may be formed in a structure in which the outer circumference is sealed by a second sealing member (660). At this time, the second sealing member (660) may be formed of an insulating material for electrically insulating the lower frames (620) from each other, or conversely, may be formed of a conductive material for electrically connecting the lower frame (620) and the second plate (630) to each other.

[0156] Here, the second plate (630) may be installed below the first plate at a distance such that a plasma sheath region that may be formed on the surface of the first plate, i.e., the lower surface of the lower frame (620), and a plasma sheath region that may be formed on the surface of the second plate (630), i.e., the upper surface of the second plate (630) overlap each other. Here, the plasma sheath region refers to a dark field region where positive (+) ions are densely packed between the plasma and the surface of the structure, so that energy exchange occurs, but plasma is hardly formed.

[0157] If the plasma sheath region that can be formed on the lower surface of the lower frame (620) and the plasma sheath region that can be formed on the upper surface of the second plate (630) do not overlap, plasma can be formed between the plasma sheath regions, but in the embodiment of the present invention, the lower frame (620) and the second plate (630) are spaced apart from each other by a distance such that the plasma sheath region that can be formed on the lower surface of the lower frame (620) and the plasma sheath region that can be formed on the upper surface of the second plate (630) overlap each other, thereby preventing plasma from being generated between the lower surface of the lower frame (620) and the upper surface of the second plate (630).

[0158] In addition, the second plate (630) has a plurality of openings (632) that are arranged alternately with the first gas supply port (612) and the second gas supply port (622) described above. That is, as illustrated in FIG. 2, the second plate (630) has the plurality of openings (632) formed so that they do not overlap with any of the first gas supply port (612) and the second gas supply port (622) when the first plate and the second plate (630) are viewed from above or below. The plurality of openings (632) may be formed so as to be arranged between the first gas supply port (612) and the second gas supply port (622) along at least one direction when the first plate and the second plate (630) are viewed from above or below. In addition, the plurality of openings (632) may be formed to be respectively arranged at a central position between the first gas supply port (612) and the second gas supply port (622) along at least one direction. When the openings (632) are arranged to be staggered from the first gas supply port (612) and the second gas supply port (614), particles may not be formed when the gas injected from the first gas supply port (612) and the second gas supply port (622) flows uniformly without stagnation to form plasma.

[0159] Each of the above openings (632) may include a first opening formed on the first plate side and a second opening connected to the first opening and having a larger diameter than the first opening. That is, each opening (632) may include a first opening formed at a predetermined length from the upper surface of the second plate (630) and a second opening formed at a predetermined length from the lower surface of the second plate (630). At this time, the first opening serves as an inlet for gas, and gas diffused in the space between the lower surface of the lower frame (620) and the upper surface of the second plate (630) flows into the opening (632) through the first opening. On the other hand, the second opening serves as an outlet for gas, and gas flowing into the opening (632) is sprayed to the lower side of the second plate (630) through the second opening. The first opening is arranged to be staggered with respect to the first gas supply port (612) and the second gas supply port (622), and the second opening can be formed to extend downward from the first opening so as to have a larger diameter than the first opening.

[0160] Meanwhile, although FIG. 6 only discloses a configuration in which the opening (632) is arranged to be staggered from the first gas supply port (612) and the second gas supply port (622), the substrate processing device according to one embodiment of the present invention is not limited thereto. As another example, the substrate processing device according to another embodiment of the present invention may be formed such that the opening (632) does not stagger from the first gas supply port (612) and the second gas supply port (622) but overlaps with each other. In this case, a plurality of protruding members may be coupled to the first plate, so that the protruding members may protrude from the lower surface of the first plate toward the second plate (630). At least one of the first gas supply port (612) and the second gas supply port (622) may be formed by penetrating the protruding member. Furthermore, the plurality of protruding members may be arranged to correspond to the opening (632), and the plurality of protruding members may be formed to a length that is inserted into the opening (632), or may be formed to a length that protrudes downward from the second plate (630), but is not limited thereto.

[0161] The power supply (400) may be connected to the gas injection device (600) to supply power to the gas injection device for generating plasma within the chamber (40). That is, the power supply (400) may supply RF power for generating plasma within the chamber (40).

[0162] Here, the power supply device (400) is connected to the second plate (630) to supply RF power only to the second plate (630), and the first plate can be grounded. At this time, the first plate and the second plate (630) can be insulated by the second sealing member (660) formed of an insulating material. In this way, when the power supply device (400) supplies RF power to the second plate (630) and the first plate is grounded, the first plate and the second plate (630) each form electrodes for generating capacitively coupled plasma (CCP). In addition, the substrate support (52) is also grounded, so that capacitively coupled plasma can be generated between the second plate (630) and the support (52).

[0163] Alternatively, the power supply device (400) may of course supply power to the first plate and the second plate (630). In this case, the second sealing member (660) may be formed of a conductive material so that the power supply device (400) supplies RF power to the first plate or the second plate (630), or the power supply device (400) may be configured to supply RF power to each of the first plate and the second plate (630). At this time, the same RF power may be supplied to the first plate and the second plate (630). In this way, when the power supply device (400) supplies the same RF power to the first plate and the second plate (630), the plasma sheath area formed between the first plate and the second plate (630) is reduced compared to the case where the first plate is grounded as described above. Accordingly, a relatively high density capacity-coupled plasma can be generated between the grounded substrate support (52).

[0164] In another example of the present invention, for example, in a case where a plurality of protruding members are combined with the first plate as described above and the protruding members protrude from the lower surface of the first plate toward the second plate (630), when the power supply device (400) supplies RF power to the first plate, the protruding members can perform the function of protruding electrodes.

[0165] Meanwhile, in FIG. 6, only an embodiment including a first gas providing unit (410) and a second gas providing unit (420) for supplying gas, a total of two gas providing units, and having two or more diffusion spaces is illustrated, but the substrate processing device according to an embodiment of the present invention is not limited thereto. As another example, a substrate processing device according to another embodiment of the present invention may be formed including one gas providing unit and one diffusion space, and a plurality of gases may be mixed from an external storage through a separate space and introduced into the chamber (40) through the gas providing unit, and the gases introduced into the chamber (40) may flow through one diffusion space and be sprayed onto the substrate (S).

[0166] Using the substrate processing device of the present invention, a thin film can be deposited on a substrate (S) using a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method.

[0167] First, when depositing a thin film on a substrate (S) by chemical vapor deposition (CVD), a source gas and a reaction gas may be supplied simultaneously onto the substrate (S). At this time, the first gas may include a source gas, and the second gas may include a reaction gas. However, the present invention is not limited thereto, and the first gas may include a reaction gas, the second gas may include a source gas, or at least one of the first gas and the second gas may include a mixed gas in which the source gas and the reaction gas are mixed. In addition, it goes without saying that at least one of the first gas and the second gas may be a purge gas. At this time, by supplying RF power to the gas injection device (600) through the power supply device (400), plasma may be formed within the chamber (40), thereby improving the deposition efficiency.

[0168] Meanwhile, when depositing a thin film on a substrate (S) by the atomic layer deposition (ALD) method, a source gas and a reaction gas may be alternately supplied onto the substrate (S). At this time, the first gas may include the source gas and the second gas may include the reaction gas, or the first gas may include the reaction gas and the second gas may include the source gas. Furthermore, it goes without saying that at least one of the first gas and the second gas may be a purge gas. At this time, the step of supplying the source gas, the step of supplying the purge gas, the step of supplying the reaction gas, and the step of supplying the purge gas constitute one process cycle, and the process cycle may be repeated multiple times to deposit a thin film on the substrate (S). At this time, plasma may be formed within the chamber (40) by supplying RF power to the gas injection device (600) through the power supply device (400), which may be performed in the step of supplying the reaction gas to improve deposition efficiency.

[0169] Although the embodiments of the present invention have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be implemented without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain it, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be interpreted by the claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

Claims

1. A step of forming a first semiconductor layer on one surface of a substrate, The step of forming the first semiconductor layer includes a process of repeatedly performing a cycle including the step of forming an amorphous semiconductor layer and the step of crystallizing at least a portion of the amorphous semiconductor layer, The step of forming the amorphous semiconductor layer includes a process of supplying a silicon-containing gas and a first gas, A method for manufacturing a solar cell, wherein the step of crystallizing at least a portion of the amorphous semiconductor layer comprises a process of forming a plasma containing a second gas.

2. In paragraph 1, A method for manufacturing a solar cell, wherein the second gas comprises a gas comprising one or more of hydrogen-containing gas, helium gas, and argon gas.

3. In paragraph 1, The step of forming the amorphous semiconductor layer further includes the step of forming a plasma containing a first gas, A method for manufacturing a solar cell, wherein the power for forming a plasma including the first gas is lower than the power for forming a plasma including the second gas.

4. In paragraph 3, A method for manufacturing a solar cell, wherein the first gas comprises a hydrogen-containing gas.

5. In paragraph 1, A method for manufacturing a solar cell, wherein the step of forming the amorphous semiconductor layer further includes a step of supplying a P-type dopant or an N-type dopant.

6. In paragraph 1, It further includes a step of forming a buffer layer prior to the step of forming the first semiconductor layer, A method for manufacturing a solar cell, wherein the step of forming the buffer layer includes a step of supplying a silicon-containing gas.

7. In paragraph 6, The step of forming the buffer layer further includes a step of forming a plasma containing a fourth gas after the step of supplying the silicon-containing gas, A method for manufacturing a solar cell, wherein the fourth gas comprises a gas comprising one or more of hydrogen-containing gas, helium gas, and argon gas.

8. In paragraph 7, A method for manufacturing a solar cell, wherein the power for forming a plasma including the second gas is greater than the power for forming a plasma including the fourth gas.

9. In paragraph 7, The step of forming the buffer layer further includes the step of forming a plasma containing a third gas, The third gas step is a method for manufacturing a solar cell including a hydrogen-containing gas.

10. In paragraph 9, A method for manufacturing a solar cell, wherein the power for forming a plasma containing the fourth gas is lower than the power for forming a plasma containing the third gas.

11. In paragraph 1, The above substrate is made of a semiconductor substrate, A method for manufacturing a solar cell further comprising a step of forming an intrinsic semiconductor layer on one surface of the substrate prior to the step of forming the first semiconductor layer.

12. In paragraph 1, A method for manufacturing a solar cell, wherein the crystallization rate on one surface of the first semiconductor layer is different from the crystallization rate on the other surface of the first semiconductor layer.

13. In paragraph 12, The crystallization rate on one surface of the first semiconductor layer is higher than the crystallization rate on the other surface of the first semiconductor layer, A method for manufacturing a solar cell, wherein one surface of the first semiconductor layer is closer to the substrate than the other surface of the first semiconductor layer.

14. In paragraph 1, A step of supplying the first gas into the chamber through the first gas supply pipe from the first gas supply unit; and A step of supplying the silicon-containing gas into the chamber through a second gas supply pipe from a second gas supply unit, A solar cell manufacturing method in which the first gas supply unit and the second gas supply unit simultaneously supply the first gas and the silicon-containing gas into the chamber, respectively.

15. In paragraph 14, A solar cell manufacturing method in which the first gas supply pipe and the second gas supply pipe each supply gas into the chamber.

16. In paragraph 14, The step of forming the amorphous semiconductor layer further includes the step of forming a plasma containing a first gas, A solar cell manufacturing method in which a plasma including the first gas is formed after supplying the first gas and the silicon-containing gas.

17. In paragraph 16, A solar cell manufacturing method in which the supply of the silicon-containing gas is terminated and the supply of the first gas is maintained when the formation of the plasma containing the first gas is terminated.

18. In paragraph 16, A solar cell manufacturing method in which the plasma containing the second gas is formed while the supply of the silicon-containing gas is stopped and the supply of the first gas is maintained after the formation of the plasma containing the first gas is terminated.

19. Substrate; and Including a first semiconductor layer provided on the above substrate, A solar cell in which the first semiconductor layer is formed by a solar cell manufacturing method according to any one of claims 1 to 18.

20. In paragraph 19, Including a first buffer layer provided between the substrate and the first semiconductor layer, A solar cell wherein the first buffer layer has a thickness of 2 Å or more and 5 Å or less.

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