Light-emitting diode chip, light-emitting diode chip group and display module

Abstract

A light-emitting diode chip, a light-emitting diode chip group and a display module, which relate to the technical field of semiconductors. The light-emitting diode chip comprises an N-type electrode, a P-type electrode, and a light-emitting layer arranged between the N-type electrode and the P-type electrode, wherein the light-emitting layer is separately electrically connected to the N-type electrode and the P-type electrode; the light-emitting layer comprises N light-emitting materials, the light emission wavelengths of which are unequal and which form M sub-pixels; among the M sub-pixels, the light emission wavelengths of at least some of the sub-pixels are unequal, M and N both being positive integers greater than or equal to 3, and M being greater than or equal to N; and when the P-type electrode and the N-type electrode are energized, the light emission mechanism for the N light-emitting materials is at least an electroluminescence mechanism.

Description

Light-emitting diode chips and chipsets, display modules

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on March 20, 2024, with application number 202410327961.7, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, for example, to a light emitting diode chip and its chipset, and a display module. Background Art

[0003] In semiconductor lighting technology, light emitting diodes (LEDs), as light-emitting devices that convert electrical energy into light energy, have the advantages of energy saving and environmental protection, long service life and high luminous efficiency. They are widely used in many fields such as indication, display, decoration, and lighting.

[0004] In the display field, ultra-high-density display products based on micro-LEDs (micro LEDs) typically use three independent chips to form a pixel unit, that is, three single-chip, single-color sub-pixels to form a pixel unit. The large number of chips in micro LEDs and their small size require a mass transfer process in the micro LED manufacturing process.

[0005] However, the above-mentioned micro LED manufacturing process has problems such as high process difficulty, low yield rate and high cost. Summary of the Invention

[0006] The present application provides a light-emitting diode chip, a chipset thereof, and a display module, which can flexibly adjust the size of the light-emitting diode chip and the full-color chipset, reduce the number of transfers and the difficulty of transfers in mass transfer, and thus overcome the process, yield and cost problems represented by mass transfer in ultra-high-density pixel display products.

[0007] In a first aspect, the present application provides a light-emitting diode chip, comprising an N-type electrode, a P-type electrode, and a light-emitting layer disposed between the N-type electrode and the P-type electrode, wherein the light-emitting layer is electrically connected to the N-type electrode and the P-type electrode respectively;

[0008] The light-emitting layer includes N light-emitting materials, the light-emitting wavelengths of the N light-emitting materials are different, and M sub-pixels are formed. Among the M sub-pixels, at least some of the sub-pixels have different light-emitting wavelengths. Both M and N are positive integers greater than or equal to 3, and M is greater than or equal to N.

[0009] When the P-type electrode and the N-type electrode are powered on, the light emitting mechanism of the N light emitting materials is at least electroluminescence.

[0010] In a second aspect, the present application provides a light-emitting diode chip set, comprising a plurality of the above-mentioned light-emitting diode chips, wherein the plurality of light-emitting diode chips are arranged in an array.

[0011] In a third aspect, the present application provides a display module, including a display module, a driving backplane and the above-mentioned light-emitting diode chipset, wherein the light-emitting diode chipset is arranged on the driving backplane and electrically connected to the driving backplane. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG1 is a top view of a first light-emitting diode chip provided in an embodiment of the present application;

[0013] FIG2 is a cross-sectional view of a first light-emitting diode chip provided in an embodiment of the present application;

[0014] FIG3 is a top view of a second light-emitting diode chip provided in an embodiment of the present application;

[0015] FIG4 is a cross-sectional view of a second light-emitting diode chip provided in an embodiment of the present application;

[0016] FIG5 is a top view of a third light-emitting diode chip provided in an embodiment of the present application;

[0017] FIG6 is a cross-sectional view of a third light-emitting diode chip provided in an embodiment of the present application;

[0018] FIG7 is a cross-sectional view of a fourth light-emitting diode chip provided in an embodiment of the present application;

[0019] FIG8 is a cross-sectional view of a fifth light-emitting diode chip provided in an embodiment of the present application;

[0020] FIG9 is a cross-sectional view of a sixth light-emitting diode chip provided in an embodiment of the present application;

[0021] FIG10 is a cross-sectional view of a seventh light-emitting diode chip provided in an embodiment of the present application;

[0022] FIG11 is a cross-sectional view of an eighth light-emitting diode chip provided in an embodiment of the present application;

[0023] FIG12 is a cross-sectional view of a ninth light-emitting diode chip provided in an embodiment of the present application;

[0024] FIG13 is a cross-sectional view of a tenth light-emitting diode chip provided in an embodiment of the present application;

[0025] FIG14 is a cross-sectional view of an eleventh light-emitting diode chip provided in an embodiment of the present application;

[0026] FIG15 is a cross-sectional view of a twelfth light-emitting diode chip provided in an embodiment of the present application;

[0027] FIG16 is a cross-sectional view of a thirteenth light-emitting diode chip provided in an embodiment of the present application;

[0028] FIG17 is a cross-sectional view of a fourteenth light-emitting diode chip provided in an embodiment of the present application;

[0029] FIG18 is a cross-sectional view of a fifteenth light-emitting diode chip provided in an embodiment of the present application;

[0030] FIG19 is a cross-sectional view of a sixteenth light-emitting diode chip provided in an embodiment of the present application;

[0031] FIG20 is a cross-sectional view of a seventeenth light-emitting diode chip provided in an embodiment of the present application;

[0032] FIG21 is a cross-sectional view of an eighteenth light-emitting diode chip provided in an embodiment of the present application;

[0033] FIG22 is a cross-sectional view of an eighteenth light-emitting diode chip provided in an embodiment of the present application;

[0034] FIG23 is a cross-sectional view of a nineteenth light-emitting diode chip provided in an embodiment of the present application;

[0035] FIG24 is a cross-sectional view of the twentieth light-emitting diode chip provided in an embodiment of the present application;

[0036] FIG25 is a cross-sectional view of a twenty-first light-emitting diode chip provided in an embodiment of the present application;

[0037] FIG26 is a cross-sectional view of a twenty-second light-emitting diode chip provided in an embodiment of the present application;

[0038] FIG27 is a cross-sectional view of a twenty-third light-emitting diode chip provided in an embodiment of the present application;

[0039] FIG28 is a cross-sectional view of a twenty-fourth light-emitting diode chip provided in an embodiment of the present application;

[0040] FIG29 is a cross-sectional view of a twenty-fifth light-emitting diode chip provided in an embodiment of the present application;

[0041] FIG30 is a cross-sectional view of a twenty-sixth light-emitting diode chip provided in an embodiment of the present application;

[0042] FIG31 is a cross-sectional view of a twenty-seventh light-emitting diode chip provided in an embodiment of the present application;

[0043] FIG32 is a cross-sectional view of a twenty-eighth light-emitting diode chip provided in an embodiment of the present application;

[0044] FIG33 is a cross-sectional view of a twenty-ninth light-emitting diode chip provided in an embodiment of the present application;

[0045] FIG34 is a cross-sectional view of a thirtieth light-emitting diode chip provided in an embodiment of the present application;

[0046] FIG35 is a cross-sectional view of a thirty-first light-emitting diode chip provided in an embodiment of the present application;

[0047] FIG36 is a cross-sectional view of a thirty-second light-emitting diode chip provided in an embodiment of the present application;

[0048] FIG37 is a cross-sectional view of a thirty-third light-emitting diode chip provided in an embodiment of the present application;

[0049] FIG38 is a cross-sectional view of a thirty-fourth light-emitting diode chip provided in an embodiment of the present application;

[0050] FIG39 is a cross-sectional view of a thirty-fifth light-emitting diode chip provided in an embodiment of the present application;

[0051] FIG40 is a cross-sectional view of a thirty-sixth light-emitting diode chip provided in an embodiment of the present application;

[0052] FIG41 is a cross-sectional view of a thirty-seventh light-emitting diode chip provided in an embodiment of the present application;

[0053] FIG42 is a schematic diagram showing a structure in which a portion of sub-pixels of a light-emitting diode chip share an N-type electrode according to an embodiment of the present application;

[0054] FIG43 is a schematic diagram showing a structure in which a portion of sub-pixels of a light-emitting diode chip share a P-type electrode according to an embodiment of the present application;

[0055] FIG44 is a top view of a first light-emitting diode chip provided in an embodiment of the present application;

[0056] FIG45 is a top view of a second light-emitting diode chip provided in an embodiment of the present application;

[0057] FIG46 is a top view of a third light-emitting diode chip provided in an embodiment of the present application;

[0058] FIG47 is a top view of a fourth light-emitting diode chip provided in an embodiment of the present application;

[0059] FIG48 is a top view of a fifth light-emitting diode chip provided in an embodiment of the present application;

[0060] FIG49 is a top view of a sixth light-emitting diode chip provided in an embodiment of the present application;

[0061] FIG50 is a top view of a seventh light-emitting diode chip provided in an embodiment of the present application;

[0062] FIG51 is a top view of an eighth light-emitting diode chip provided in an embodiment of the present application;

[0063] FIG52 is a top view of a ninth light-emitting diode chip provided in an embodiment of the present application;

[0064] FIG53 is a top view of a tenth light-emitting diode chip provided in an embodiment of the present application;

[0065] FIG54 is a top view of an eleventh light-emitting diode chip provided in an embodiment of the present application;

[0066] FIG55 is a top view of a twelfth light-emitting diode chip provided in an embodiment of the present application;

[0067] FIG56 is a top view of a thirteenth light-emitting diode chip provided in an embodiment of the present application;

[0068] FIG57 is a top view of a fourteenth light-emitting diode chip provided in an embodiment of the present application;

[0069] FIG58 is a schematic diagram of a first integrated structure of a light-emitting diode chip provided in an embodiment of the present application;

[0070] FIG59 is a schematic diagram of a second package structure of a light-emitting diode chip provided in an embodiment of the present application;

[0071] FIG60 is a schematic diagram of a third package structure of a light-emitting diode chip provided in an embodiment of the present application;

[0072] FIG61 is a schematic diagram of a fourth package structure of a light-emitting diode chip provided in an embodiment of the present application;

[0073] FIG62 is a schematic flow chart of a first method for preparing a light-emitting diode chip according to an embodiment of the present application;

[0074] FIG63 is a schematic flow chart of a second method for preparing a light-emitting diode chip according to an embodiment of the present application;

[0075] FIG64 is a schematic flow chart of a third method for preparing a light-emitting diode chip according to an embodiment of the present application;

[0076] FIG65 is a schematic flow chart of a fourth method for preparing a light-emitting diode chip according to an embodiment of the present application;

[0077] FIG66 is a schematic flow chart of a fifth method for preparing a light-emitting diode chip according to an embodiment of the present application;

[0078] FIG67 is a schematic flow chart of a sixth method for preparing a light-emitting diode chip according to an embodiment of the present application;

[0079] FIG68 is a schematic flow chart of a seventh method for preparing a light-emitting diode chip according to an embodiment of the present application;

[0080] FIG69 is a schematic flow chart of an eighth method for preparing a light-emitting diode chip according to an embodiment of the present application;

[0081] FIG70 is a schematic flow chart of a ninth method for preparing a light-emitting diode chip according to an embodiment of the present application;

[0082] FIG71 is a dimensional diagram of a light-emitting diode chipset provided in an embodiment of the present application;

[0083] FIG72 is a top view of a first light-emitting diode chip group provided in an embodiment of the present application;

[0084] FIG73 is a top view of a second light-emitting diode chip group provided in an embodiment of the present application;

[0085] FIG74 is a top view of a third light-emitting diode chip group provided in an embodiment of the present application;

[0086] FIG75 is a top view of a fourth light-emitting diode chip group provided in an embodiment of the present application;

[0087] FIG76 is a top view of a fifth light-emitting diode chip group provided in an embodiment of the present application;

[0088] FIG77 is a top view of a sixth light-emitting diode chip group provided in an embodiment of the present application;

[0089] FIG78 is a top view of a seventh light-emitting diode chip group provided in an embodiment of the present application;

[0090] FIG79 is a top view of an eighth light-emitting diode chip group provided in an embodiment of the present application;

[0091] FIG80 is a top view of a ninth light-emitting diode chip group provided in an embodiment of the present application;

[0092] FIG81 is a top view of a tenth light-emitting diode chip group provided in an embodiment of the present application;

[0093] FIG82 is a top view of the eleventh light-emitting diode chip group provided in an embodiment of the present application;

[0094] FIG83 is a top view of a twelfth light-emitting diode chip group provided in an embodiment of the present application;

[0095] FIG84 is a schematic diagram of a first structure of a display module provided in an embodiment of the present application;

[0096] Figure 85 is a second structural schematic diagram of the display module provided in an embodiment of the present application.

[0097] Description of reference numerals: 100, substrate; 101, buffer layer; 102, N-type electrode; 103, N-type semiconductor layer; 104, P Type electrode; 105, P-type semiconductor layer; 106, current spreading layer; 107, reflective layer; 108, first insulating layer; 109, second insulating layer; 110, bonding substrate; 111, binding layer; 112, color conversion layer; 113-1, first light-emitting material; 113-2, second light-emitting material; 113-3, third light-emitting material; 113-n-1, n-1th light-emitting material; 113-n, nth light-emitting material; 114, isolation structure; 114a-isolation material; 115, hole blocking layer; 116, light-blocking layer; 117a, first filter layer; 117b, second filter layer; 117c, third filter layer; 118, protective layer; 200, driving backplane; 201, driving substrate; 202, driving unit. DETAILED DESCRIPTION

[0098] In LED display products, three single-core monochrome single-pixel chips are usually used to form a pixel unit. The size of a single chip in ultra-high-density display products represented by micro LED is relatively small, and the number of chips that make up the display product is relatively large. In the manufacturing process of display products, micro LED chips need to be grown on wafers, and then transferred to a specific substrate through mass transfer technology to complete the binding assembly. In the mass transfer process, due to the small size and large number of chips, the transfer operation is more difficult, the number of operations is numerous, and the operation alignment requirements on the substrate are high. As a result, the manufacturing process of micro LED display products is more difficult, the yield is lower, the production cycle is longer, and the cost is higher.

[0099] In related technologies, in LED display products, several chips are packaged together through the MIP (Micro LED in Package) packaging process to form an integrated chipset that can emit multiple wavelengths. The traditional MIP packaging process is suitable for LED display products with pixel sizes greater than 0.3 mm. Due to the limitations of mass transfer technology, the MIP packaging process requires the use of single-core monochrome single-sub-pixel chips to be larger, that is, the sub-pixel size must be larger. A single chipset is usually an RGB pixel unit, and a large number of chips and chipsets are used in the application end.

[0100] The light-emitting diode chip, chipset, and display module provided by the present application are configured such that the electrons provided by the N-type electrode and the holes provided by the P-type electrode are combined in the light-emitting layer to excite the light-emitting material in the light-emitting layer to emit light. The light-emitting layer includes N light-emitting materials, the emission wavelengths of the N light-emitting materials are different, and M sub-pixels are formed. Among the M sub-pixels, at least some of the sub-pixels have different emission wavelengths. M and N are both positive integers greater than or equal to 3, and M is greater than or equal to N. The present application adopts a single-core dual-color multi-sub-pixel arrangement, that is, a plurality of sub-pixels are used to form pixel subgroups, and an RGB full-color pixel unit is formed by arranging the pixel subgroups, thereby forming an RGB full-color chip set. In the present application, some or all of the sub-pixels in a single chip can form a complete full-color pixel unit, making the chip more convenient to use. Some of the sub-pixels in multiple chips can also be spliced ​​into a complete full-color pixel unit. The splicing method of the chip is relatively flexible and can meet diverse display needs.

[0101] When the P-type electrode and the N-type electrode are energized, the light-emitting mechanism of the N light-emitting materials is at least electroluminescence. The present application can flexibly adjust the size of the light-emitting diode chip and the chipset, reduce the difficulty of the transfer operation in the mass transfer process, and reduce the number of mass transfers, thereby overcoming the process, yield and cost issues represented by mass transfer in ultra-high-density pixel display products.

[0102] Compared to the related art, which integrates several chips together to form an integrated chipset that emits multiple wavelengths, the related art needs to overcome the process difficulties of integrating multiple chips, resulting in greater process difficulty, lower yield, and higher cost. This application directly obtains multi-color and multi-sub-pixels in a single LED chip, which is simpler in process, less technically difficult, and lower in cost.

[0103] By adopting the single-core, multi-color, multi-sub-pixel LED chip or LED chip group of the present application, under the conditions of the same light-emitting area and the same pixel density (Pixels Per Inch, PPI), the size of the LED chip can be flexibly adjusted while ensuring a small sub-pixel size. At the same time, the number of LED chips can be greatly reduced, thereby overcoming problems such as the difficulty of the preparation process, low product yield and high preparation cost, and helping to promote the mass production of mini LED and micro LED as soon as possible.

[0104] The single-core multi-color multi-sub-pixel chip in the present application contains n full-color pixel units, where n is a positive integer greater than or equal to 1. The single-core multi-color multi-sub-pixel chip can be directly combined with the backplane, and a single chip can achieve the effect of n MIP packages. The single-core multi-color multi-sub-pixel light-emitting diode chip of the present application can also be used to form a full-color integrated chipset (for example, three 3*n combination chips form a chipset), so that n*3 pixel units can be obtained. When combined with the backplane, the chipset used is 1 / 3n of the traditional MIP package, which greatly reduces the preparation time, reduces the process and raw material costs, and greatly improves the yield. The pixel size applicable to the full-color integrated package of the present application can be flexibly adjusted and can be much smaller than the pixel size applicable to the traditional MIP process.

[0105] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described in more detail below in conjunction with the drawings in the preferred embodiments of the present application. In the drawings, the same or similar reference numerals throughout represent the same or similar parts or parts with the same or similar functions. The described embodiments are part of the embodiments of the present application, not all of the embodiments. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. The embodiments of the present application are described in detail below in conjunction with the drawings.

[0106] In this application, some nouns can be understood as follows:

[0107] Sub-pixel (SP): A single blue light pixel, a single green light pixel, or a single red light pixel is called a sub-pixel. In this patent, a sub-pixel can also be a single arbitrary wavelength.

[0108] Pixel subgroup (PSG): A group of sub-pixels.

[0109] Pixel unit (PU): A unit that includes blue, green, and red sub-pixels, or three or more other sub-pixels of different colors that can constitute white light.

[0110] Single-core monochrome single-sub-pixel chip: A single light-emitting diode chip can only emit one wavelength of light and contains only one sub-pixel, such as one blue light sub-pixel, one green light sub-pixel, or one red light sub-pixel.

[0111] Single-chip monochrome multi-sub-pixel chip: A single chip can only emit one wavelength of light, but contains more than or equal to two sub-pixels, such as two red sub-pixels, three red sub-pixels, or more red sub-pixels.

[0112] Single-core multi-color multi-sub-pixel chip; a single chip can emit multiple wavelengths of light and contains greater than or equal to 3 sub-pixels, such as 1 red sub-pixel + 1 green sub-pixel + 1 blue sub-pixel, 1 red sub-pixel + 2 green sub-pixels + 3 blue sub-pixels, multiple blue sub-pixels + multiple red sub-pixels + multiple blue sub-pixels.

[0113] Light-emitting diode chip (C) is a solid-state semiconductor device with a light-emitting layer between a P-type electrode and an N-type electrode. It is referred to as "chip" in the following text.

[0114] Light-emitting diode chipset (CG): It is composed of two or more single-core multi-color multi-pixel chips, containing one or more pixel units.

[0115] Display mini block (DMB): A display device formed by electrically connecting a light-emitting diode chipset and a driver backplane.

[0116] In a first aspect, embodiments of the present application provide a light-emitting diode chip, as shown in Figures 1 to 40 . The light-emitting diode chip includes an N-type electrode 102, a P-type electrode 104, and a light-emitting layer disposed between the N-type electrode 102 and the P-type electrode 104. The light-emitting layer is electrically conductive with the N-type electrode 102 and the P-type electrode 104, respectively. The light-emitting layer includes N light-emitting materials, each of which has different emission wavelengths and forms M sub-pixels. Among the M sub-pixels, at least a portion of the sub-pixels have different emission wavelengths. M and N are both positive integers greater than or equal to 3, and M is greater than or equal to N. When power is applied to the P-type electrode 104 and the N-type electrode 102, the light-emitting mechanism of the N light-emitting materials is at least electroluminescence.

[0117] It should be noted that in the energized state, an electric field is formed between the N-type electrode and the P-type electrode, and the light-emitting layer is disposed between the N-type electrode and the P-type electrode. This can be understood as the light-emitting layer being located within this electric field. In the thickness direction of the chip, the entire light-emitting layer or a portion of the thickness of the light-emitting layer is located between the N-type electrode and the P-type electrode. The light-emitting layer being electrically conductive with the N-type electrode and the P-type electrode, respectively, means that the light-emitting layer is electrically conductive with the N-type electrode through the N-type semiconductor layer, and electrically conductive with the P-type electrode through the P-type semiconductor layer.

[0118] The light-emitting layer includes N light-emitting materials, where N is a positive integer greater than or equal to 3. In the subsequent text, multiple light-emitting materials have the same meaning as N light-emitting materials, and multiple sub-pixels have the same meaning as M sub-pixels. For example, on the basis of satisfying that the N light-emitting materials are not equal, the N light-emitting materials may include a first light-emitting material 113-1 that emits blue light, a second light-emitting material 113-2 that emits green light, a third light-emitting material 113-3 that emits red light, an n-1th light-emitting material 113-n-1 that emits purple light, and an nth light-emitting material 113-n that emits light of other colors that are not equal to the above-mentioned light wavelengths. In other embodiments, the light-emitting wavelengths of the above-mentioned light-emitting materials can also be adjusted, and this application does not limit this. Wherein, n is a positive integer greater than or equal to 1 and less than or equal to N.

[0119] Multiple light-emitting materials form M sub-pixels, where M is also a positive integer greater than or equal to 3, and M is greater than or equal to N. Referring to Figure 1, the chip includes a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and so on, to an m-th sub-pixel SPm, where m is a positive integer greater than or equal to 1 and less than or equal to M. Exemplarily, the first light-emitting material 113-1 corresponds to the first sub-pixel SP1, which is a blue light sub-pixel. The second light-emitting material 113-2 corresponds to the second sub-pixel SP2, which is a green light sub-pixel. The third light-emitting material 113-3 corresponds to the third sub-pixel SP3, which is a red light sub-pixel. The M sub-pixels can be arranged side by side. Arranging side by side can mean arranging in a direction perpendicular to the thickness of the chip, and can be located at the same thickness position of the chip; it can also mean being on the same layer of the chip, with a misalignment in the thickness direction of the chip.

[0120] Taking a single-core three-color three-sub-pixel as an example, the chip can include a first sub-pixel, a second sub-pixel and a third sub-pixel with different luminous colors. The first sub-pixel, the second sub-pixel and the third sub-pixel are any three of a plurality of color photon pixels such as red light sub-pixel, green light sub-pixel, blue light sub-pixel, purple light sub-pixel and ultraviolet light sub-pixel.

[0121] M is greater than or equal to N, which means that one luminescent material corresponds to at least one sub-pixel. M can be equal to N, that is, one luminescent material corresponds to one sub-pixel; M can also be greater than N, that is, one luminescent material can form two or more sub-pixels with equal luminous wavelengths. For example, M is equal to 4, N is equal to 3, and the chip is a single-core three-color four-sub-pixel. The three luminescent materials can be a first luminescent material 113-1 that emits blue light, a second luminescent material 113-2 that emits green light, and a third luminescent material 113-3 that emits red light. The four sub-pixels can be a blue sub-pixel, a blue sub-pixel, a green sub-pixel, and a red sub-pixel, or a blue sub-pixel, a green sub-pixel, a green sub-pixel, and a red sub-pixel, or a blue sub-pixel, a green sub-pixel, a red sub-pixel, and a red sub-pixel.

[0122] This application combines multiple sub-pixels with different luminous wavelengths into a light-emitting diode chip, that is, adopts a single-chip, multi-color, and multi-sub-pixel arrangement. Compared with the related art that uses a single sub-pixel to form a chip, this application can flexibly adjust the size of the light-emitting diode chip, reducing the transfer difficulty and alignment difficulty in mass transfer operations. In addition, it can effectively reduce the number of light-emitting diode chips required for display products with the same luminous area and the same pixel density, thereby reducing the complexity of mass transfer operations and reducing production costs. This can also improve the product yield of ultra-high-density pixel displays.

[0123] In the chip of this application, when the P-type electrode and the N-type electrode are energized, the N luminescent materials emit light through electroluminescence (EL). During chip operation, the N-type electrode, when energized, provides electrons, and the P-type electrode, when energized, provides holes. The holes and electrons migrate to the corresponding positions of each luminescent material, and after the holes and electrons recombine, they emit light of the corresponding wavelength of the luminescent material.

[0124] 7 to 10, 14, 20 to 23, and 27 to 40, the chip of the present application further includes a reflective layer 107, which is located on the backlight side of the light-emitting diode chip. The reflective layer 107 of the present application is arranged on the backlight side to ensure that light is emitted from the light-emitting side. The reflective layer 107 is located on the side of the N-type electrode 102 away from the P-type electrode 104, and the side of the P-type electrode 104 away from the N-type electrode 102 forms the light-emitting side of the light-emitting diode chip, or the reflective layer 107 is located on the side of the P-type electrode 104 away from the N-type electrode 102, and the side of the N-type electrode 102 away from the P-type electrode 104 forms the light-emitting side of the light-emitting diode chip. The reflective layer 107 can be a metal layer or a Bragg reflective layer.

[0125] In the chip of the present application, the driving modes of the multiple sub-pixels of the chip can be independent driving and synchronous driving.

[0126] 1 and 2 , the first sub-pixel, the second sub-pixel, the third sub-pixel ... the mth sub-pixel share an N-type electrode 102 and a P-type electrode 104 . When the N-type electrode 102 and the P-type electrode 104 are energized, each sub-pixel can emit light synchronously, and the driving mode is synchronous driving.

[0127] 3 and 4 , the P-type electrode 104 includes M separate sub-P-type electrodes, one side of the M sub-pixels close to the N-type electrode 102 is electrically connected to the N-type electrode 102 , and one side of the M sub-pixels close to the P-type electrode 104 is electrically connected to the M sub-P-type electrodes one by one.

[0128] It should be noted that, as shown in Figures 3 and 4 , P-type electrode 104 includes a first sub-P-type electrode, a second sub-P-type electrode, a third sub-P-type electrode, and so on, through the mth sub-P-type electrode, each of which is electrically conductive to the first sub-pixel, the second sub-pixel, the third sub-pixel, and so on. Each sub-P-type electrode can independently control its current state, allowing each corresponding sub-pixel to emit light independently, with the drive mode being independent.

[0129] 5 and 6 , the N-type electrode 102 includes M separate sub-N-type electrodes, the side of the M sub-pixels close to the P-type electrode 104 is electrically connected to the P-type electrode 104 , and the side of the M sub-pixels close to the N-type electrode 102 is electrically connected to the M sub-N-type electrodes one by one.

[0130] It should be noted that, as shown in Figures 5 and 6, N-type electrode 102 includes a first sub-N-type electrode, a second sub-N-type electrode, a third sub-N-type electrode, and so on, to the mth sub-N-type electrode, which are electrically connected to the first sub-pixel, the second sub-pixel, the third sub-pixel, and so on, respectively. Each sub-N-type electrode can independently control its power state, so that each corresponding sub-pixel can emit light independently, and the driving mode is independent drive.

[0131] 4 to 6, 8 to 14, 16 to 19, 21 to 23, 25, 26, 28 to 30, 33 to 37, 39 and 40, the chip of the present application further includes an isolation structure 114, which is located between any two adjacent sub-pixels. In the present application, the isolation structure 114 may only include a channel (CN), that is, the channel may not be filled with an isolation material. The channel can spatially isolate the isolated structure (as shown in Figures 11 and 12), and the electrically insulating isolation material 114a filled in the channel CN ​​(as shown in Figures 13 and 14) is, for example, silicon nitride or silicon oxide.

[0132] In some embodiments, the electrically insulating isolation material 114a can also have a light-blocking effect, such as a black organic material. This can reduce or prevent light mixing between adjacent sub-pixels, thereby improving the light-emitting effect of the LED chip. In other embodiments, the isolation structure can also be an ion-implanted layer, a structure formed by an ion implantation process that has both electrical isolation and light-blocking effects. In the following embodiments, the isolation structure is the same and will not be further described.

[0133] For example, as shown in FIG11 , when the P-type electrode 104 includes M mutually separate sub-P-type electrodes, the isolation structure 114 may also be located between adjacent sub-P-type electrodes. As shown in FIG12 , when the N-type electrode 102 includes M mutually separate sub-N-type electrodes, the isolation structure 114 may also be located between adjacent sub-N-type electrodes.

[0134] For example, as shown in FIG. 14 , when the multiple reflective layers 107 are respectively located on the side of the multiple discrete sub-N-type electrodes away from the P-type electrode 104 in a one-to-one correspondence, the isolation structure 114 may also be located between adjacent reflective layers 107 .

[0135] 1-14 , in some possible embodiments, in the chip of the present application, N light-emitting materials are arranged in parallel between the N-type electrode 102 and the P-type electrode 104 , and each light-emitting material is electrically conductive with the N-type electrode 102 and the P-type electrode 104 ; the multiple light-emitting materials arranged side by side correspond to multiple sub-pixels respectively.

[0136] Among them, the multiple light-emitting materials are respectively a first light-emitting material 113-1, a second light-emitting material 113-2, a third light-emitting material 113-3...the nth light-emitting material 113-n. All the light-emitting materials are arranged side by side, and along the thickness direction of the chip, all the light-emitting materials have no stacked parts. The first light-emitting material 113-1 corresponds to forming a first sub-pixel, the second light-emitting material 113-2 corresponds to forming a second sub-pixel, the third light-emitting material 113-3 corresponds to forming a third sub-pixel...the nth light-emitting material 113-n corresponds to forming an mth sub-pixel. In some possible examples, the same light-emitting material can correspond to forming multiple sub-pixels. For example, the first light-emitting material 113-1 can form two sub-pixels with equal luminous wavelengths.

[0137] When the chip is operating, holes and electrons can combine in the first, second, third, ..., and nth luminescent materials, thereby generating electroluminescence. All of the aforementioned luminescent materials, i.e., the first, second, third, ..., and nth luminescent materials, are electroluminescent.

[0138] As shown in Figures 1 and 2 , the chip's multiple sub-pixels are driven synchronously. As shown in Figures 3 and 4 , the P-type electrode 104 includes a first sub-P-type electrode, a second sub-P-type electrode, a third sub-P-type electrode, and so on, up to the mth sub-P-type electrode. The chip's multiple sub-pixels are driven independently. As shown in Figures 5 and 6 , the N-type electrode 102 includes a first sub-N-type electrode, a second sub-N-type electrode, a third sub-N-type electrode, and so on, up to the mth sub-N-type electrode. The chip's multiple sub-pixels are driven independently.

[0139] In the chip of this embodiment, an isolation structure may be provided between each sub-pixel. The isolation structure may be provided between adjacent light-emitting materials. When the chip's P-type electrode includes multiple discrete P-type electrodes, the isolation structure may be located between the sub-P-type electrodes corresponding to each sub-pixel. When the chip's N-type electrode includes multiple discrete N-type electrodes, the isolation structure may be located between the sub-N-type electrodes corresponding to each sub-pixel. The isolation structure may also be located between the reflective layers corresponding to each sub-pixel.

[0140] The aforementioned chip may further include a reflective layer. As shown in FIG10 , the reflective layer 107 may be located on the side of the P-type electrode 104 facing away from the N-type electrode 102, such that the side of the N-type electrode 102 facing away from the P-type electrode 104 forms the light-emitting side. Alternatively, as shown in FIG7 to FIG9 , the reflective layer 107 may be located on the side of the N-type electrode 102 facing away from the P-type electrode 104, such that the side of the P-type electrode 104 facing away from the N-type electrode 102 forms the light-emitting side.

[0141] In other possible embodiments, referring to Figures 15 to 41, in the chip of the present application, at least one of the N light-emitting materials is stacked with the remaining light-emitting materials along the thickness direction of the light-emitting diode chip. Among the stacked light-emitting materials, at least one light-emitting material is located on the side of the remaining light-emitting materials close to the N-type electrode 102. At least one light-emitting material is located on the side of the remaining light-emitting materials close to the N-type electrode 102. In this way, at least some of the light-emitting materials are stacked, enriching the structural form of the chip, and the side of the light-emitting material facing the N-type electrode is electrically conductive with the N-type electrode, so that electrons provided by the N-type electrode can migrate to the light-emitting material and then migrate to the remaining light-emitting materials through the light-emitting material.

[0142] As a possible implementation of the present application, referring to Figures 15 to 23, the light-emitting material closest to the N-type electrode 102 includes a first region and a second region arranged in parallel, and the first region and the second region are electrically connected to the N-type electrode 102 on the side facing the N-type electrode 102, and the first region corresponds to the side facing the P-type electrode 104. The side of the second region and the remaining light-emitting materials facing the P-type electrode 104 are both electrically connected to the P-type electrode 104, and the second region and the remaining light-emitting materials correspond to multiple sub-pixels respectively.

[0143] It is understandable that the light-emitting material closest to the N-type electrode may be the nth light-emitting material, and the remaining light-emitting materials may be the first light-emitting material, the second light-emitting material, the third light-emitting material, and so on, the n-1th light-emitting material. The first region and the second region of the nth light-emitting material are arranged side by side along a thickness direction that intersects the light-emitting diode chip. The remaining light-emitting materials are arranged side by side on the side of the first region of the nth light-emitting material facing the P-type electrode, and the second region of the nth light-emitting material is exposed to the remaining light-emitting materials. The side of the nth light-emitting material facing the N-type electrode is electrically conductive with the N-type electrode, and a portion of the side of the nth light-emitting material facing the P-type electrode is electrically conductive with the P-type electrode. All regions of the first to n-1th light-emitting materials facing the P-type electrode are electrically conductive with the P-type electrode.

[0144] The second region of the light-emitting material closest to the N-type electrode and the remaining light-emitting materials each correspond to multiple sub-pixels. For example, the first light-emitting material corresponds to the first sub-pixel, the second light-emitting material corresponds to the second sub-pixel, and the second region of the nth light-emitting material corresponds to the mth sub-pixel. The same light-emitting material can correspond to multiple sub-pixels, for example, the first light-emitting material corresponds to two sub-pixels with equal emission wavelengths.

[0145] As shown in Figures 20 to 23, the above chip may further include a reflective layer 107. As shown in Figures 20 to 22, the reflective layer 107 can be located on the side of the N-type electrode 102 facing away from the P-type electrode 104, so that the side of the P-type electrode 104 facing away from the N-type electrode 102 forms the light-emitting side. Alternatively, as shown in Figure 23, the reflective layer 107 can be located on the side of the P-type electrode 104 facing away from the N-type electrode 102, so that the side of the N-type electrode 102 facing away from the P-type electrode 104 forms the light-emitting side.

[0146] 19 and 20 , the chip may further include a filter layer disposed on the light-emitting side. The filter layer may include a first filter layer CF1, a second filter layer CF2, a third filter layer CF3, and so on, up to the n-1th filter layer CFn-1. The first filter layer CF1 corresponds to the first subpixel formed by the first luminescent material 113-1, the second filter layer CF2 corresponds to the second subpixel formed by the second luminescent material 113-2, the third filter layer CF3 corresponds to the third subpixel formed by the third luminescent material 113-3, and so on. The n-1th filter layer CFn-1 corresponds to the m-1th subpixel formed by the n-1th luminescent material 113-n-1.

[0147] It should be noted that when the chip includes a filter layer, the light-emitting wavelengths of multiple light-emitting materials are not limited along the thickness direction of the chip. The holes provided by the P-type electrode can migrate to each light-emitting material, that is, the holes provided by the P-type electrode can migrate to the light-emitting material closest to the N-type electrode. In some possible implementations, the thicknesses of multiple light-emitting materials are relatively thin, so that the sum of the thicknesses of multiple light-emitting materials is less than the hole diffusion length. The stacked portion of each light-emitting material can generate multiple wavelengths and filter them using the corresponding filter layer so that each sub-pixel emits only light of one wavelength. For example, the stacked portion of the first light-emitting material and the nth light-emitting material can generate light of a first wavelength and light of an nth wavelength, and the first sub-pixel emits light of the first wavelength through the first filter layer CF1.

[0148] It's understandable that when the luminescent materials in a stacked structure emit light, the light will be emitted from each side of the luminescent material layer, thereby stimulating the photoluminescence of luminescent materials with longer wavelengths. Therefore, except for the luminescent materials with the smallest wavelengths, other luminescent materials have two luminescence mechanisms: electroluminescence and photoluminescence.

[0149] As shown in Figures 20 and 21, the sides of two adjacent filter layers in the multiple filter layers can be in contact or isolated. The filter layer can be a color filter or a Bragg reflector (or a distributed Bragg reflector, DBR for short). Both the color filter and the Bragg reflector can filter the wavelength of the light passing through, thereby emitting light with different wavelengths. The Bragg reflector can be an alternating stack of two materials, aluminum nitrogen and gallium nitrogen, or an alternating stack of two materials, titanium oxide and silicon oxide, or an alternating stack of two materials, silicon oxide and silicon nitride. Optionally, the thickness of the Bragg reflector is 2-6 microns. In other embodiments, the thickness value can be adjusted as needed, and this application does not impose any restrictions on it.

[0150] In the above-mentioned chip, referring to Figures 17 to 20 and Figures 21 to 23, an isolation structure 114 can be provided between each sub-pixel. The isolation structure 114 can be located between the first region and the second region, as well as between the remaining light-emitting materials arranged side by side. When the P-type electrode 104 of the chip includes a plurality of discrete sub-P-type electrodes, the isolation structure 114 can be located between the sub-P-type electrodes corresponding to each sub-pixel. When the N-type electrode 102 of the chip includes a plurality of discrete sub-N-type electrodes, the isolation structure 114 can be located between the sub-N-type electrodes corresponding to each sub-pixel. The isolation structure 114 can also be located between the filter layers corresponding to each sub-pixel, as well as between the reflective layers 107.

[0151] Based on the fact that isolation structures can be provided between sub-pixels, in some possible examples, among the stacked plurality of light-emitting materials, the light-emitting wavelength of the light-emitting material closer to the P-type electrode is greater than the light-emitting wavelength of the light-emitting material farther from the P-type electrode. In this way, the light-emitting wavelength of the light-emitting material closer to the P-type electrode is longer, while the light-emitting wavelength of the light-emitting material farther from the P-type electrode is shorter. As a result, the light emitted by the light-emitting material closer to the P-type electrode will not excite the light-emitting material with a shorter wavelength closer to the N-type electrode.

[0152] Among the N luminescent materials, the luminescent material with the smallest emission wavelength is stacked on the side of the remaining luminescent materials closest to the N-type electrode. For example, the emission wavelength of the nth luminescent material is smaller than the emission wavelengths of the first through n-1th luminescent materials, i.e., the nth luminescent material includes a first region and a second region. The emission wavelengths of the first through n-1th luminescent materials are independent of their arrangement order, i.e., the emission wavelengths of the first through n-1th luminescent materials can be arbitrary.

[0153] In the above possible examples, it is necessary to ensure that holes in the stacked region diffuse only into the light-emitting material layer closest to the P-type electrode. If the thickness of the light-emitting material closest to the P-type electrode in the stacked region is greater than the hole diffusion length, the luminescence mechanism of each light-emitting material is electroluminescence. Referring to Figures 16 and 17, and Figures 21 to 23, the thicknesses of the first to n-1th light-emitting materials are all greater than the hole diffusion length. Thus, when the chip is operating, holes provided by the P-type electrode can migrate to the second region of the light-emitting material with the shortest wavelength (e.g., the second region of the nth light-emitting material), causing the second region of the light-emitting material with the shortest wavelength to emit electroluminescence. Furthermore, holes provided by the P-type electrode can migrate to the remaining light-emitting materials but cannot migrate to the first region of the light-emitting material with the shortest wavelength (e.g., the first region of the nth light-emitting material), causing the remaining light-emitting materials to emit electroluminescence, while the first region of the light-emitting material with the shortest wavelength does not emit electroluminescence. Furthermore, the first region of the light-emitting material with the shortest wavelength does not emit photoluminescence. This ensures that a single stacked area of ​​the chip can only emit a single wavelength, and multiple different stacked areas can produce light of multiple different wavelengths, so that a single chip has multiple wavelengths.

[0154] For another example, a hole-blocking layer is added to the stacked region. As shown in FIG18 , this layer also includes hole-blocking layer 115. Hole-blocking layer 115 is disposed at least between the luminescent material closest to P-type electrode 104 and the adjacent luminescent material layer. The combined thickness of hole-blocking layer 115 and the luminescent material layer closest to P-type electrode 104 is greater than the hole diffusion length. This allows electrons provided by the N-type electrode to migrate to every luminescent material, while holes provided by the P-type electrode can only migrate to the luminescent material closest to the P-type electrode. This allows holes and electrons to combine in the luminescent material closest to the P-type electrode, ensuring that the luminescent material can achieve electroluminescence. Furthermore, holes are prevented from migrating to the luminescent material with a shorter wavelength near the P-type electrode, and are unable to excite the luminescent material farther from the P-type electrode to emit light at a shorter wavelength. This ensures that a single stacked region of the chip can only emit light of a single wavelength, while multiple stacked regions can generate light of multiple wavelengths, enabling a single chip to have multiple wavelengths.

[0155] For example, as shown in Figure 18, the first light-emitting material 113-1, the second light-emitting material 113-2...the n-1 light-emitting material 113-n-1 are arranged in parallel, and the first light-emitting material 113-1, the second light-emitting material 113-2...the n-1 light-emitting material 113-n-1 are all closest to the P-type electrode 104, and the hole blocking layer 115 can be arranged between the first light-emitting material 113-1 and the n-th light-emitting material 113-n, between the second light-emitting material 113-2 and the n-th light-emitting material 113-n, between the third light-emitting material 113-3 and the n-th light-emitting material 113-n...between the n-1 light-emitting material 113-n-1 and the n-th light-emitting material 113-n.

[0156] The driving mode of the multiple sub-pixels of this chip can be synchronous driving or independent driving. Referring to Figures 15, 19 and 20, the P-type electrode 104 is in an integrated form, and the N-type electrode 102 is also in an integrated form. The driving mode of the multiple sub-pixels of this chip is independent driving. Referring to Figures 16, 18, 21 and 23, the P-type electrode 104 includes a first sub-P-type electrode, a second sub-P-type electrode, a third sub-P-type electrode...the mth sub-P-type electrode, and the driving mode of the multiple sub-pixels of this chip is independent driving. Referring to Figures 17 and 22, the N-type electrode 102 includes a first sub-N-type electrode, a second sub-N-type electrode, a third sub-N-type electrode...the mth sub-N-type electrode, and the driving mode of the multiple sub-pixels of the chip is independent driving.

[0157] As another possible implementation of the present application, as shown in Figures 24 to 41, the remaining light-emitting materials are stacked along the thickness direction of the light-emitting diode chip, and the light-emitting material closest to the N-type electrode 102 is electrically conductive with the N-type electrode 102 on the side facing the N-type electrode 102. That is, along the thickness direction of the chip, multiple light-emitting materials are stacked, and the electrons provided by the N-type electrode 102 can migrate from the light-emitting material on the side facing the N-type electrode 102 to the light-emitting material, and then migrate from the light-emitting material to other light-emitting materials. Along the direction from the P-type electrode 104 to the N-type electrode 102, the multiple light-emitting materials are, in order, the first light-emitting material 113-1, the second light-emitting material 113-2, the third light-emitting material 113-3...the nth light-emitting material 113-n.

[0158] In some examples, referring to Figures 24 to 31, among two adjacent light-emitting materials, a light-emitting material close to the N-type electrode 102 includes a first region and a second region arranged in parallel, and the first region corresponds to the other light-emitting material on the side facing the P-type electrode 104; the second regions of the multiple light-emitting materials are electrically connected to the P-type electrode 104 on the side facing the P-type electrode 104, and the second regions of the multiple light-emitting materials correspond to multiple sub-pixels respectively.

[0159] The above-mentioned luminescent materials are formed in a stepped shape. For example, the nth luminescent material includes a first region and a second region. The n-1th luminescent material is disposed on the side of the first region of the nth luminescent material away from the N-type electrode, and the second region of the n-1th luminescent material is electrically conductive to the P-type electrode. The n-1th luminescent material includes a first region and a second region. The n-2th luminescent material is disposed on the side of the first region of the n-1th luminescent material away from the N-type electrode, and the second region of the n-2th luminescent material is electrically conductive to the P-type electrode, and so on. The luminescent material closest to the P-type electrode includes only the second region and no first region. That is, the first luminescent material includes only the second region, and the second region of the first luminescent material is the entire region of the first luminescent material. The remaining luminescent materials may include both the first region and the second region.

[0160] The first luminescent material corresponds to the first subpixel, the second region of the second luminescent material corresponds to the second subpixel, and so on. The second region of the nth luminescent material corresponds to the mth subpixel. The side of the nth luminescent material facing the N-type electrode is electrically conductive with the N-type electrode. Partial regions of the sides of the nth through (n-1th) luminescent materials facing the P-type electrode are electrically conductive with the P-type electrode. The entire side of the first luminescent material facing the P-type electrode is electrically conductive with the P-type electrode.

[0161] Referring to Figures 29 to 31 , the aforementioned chip may further include a reflective layer 107. As shown in Figures 27 to 30 , the reflective layer 107 may be located on the side of the N-type electrode 102 facing away from the P-type electrode 104, such that the side of the P-type electrode 104 facing away from the N-type electrode 102 forms a light-emitting side. As shown in Figure 31 , the reflective layer 107 may also be located on the side of the P-type electrode 104 facing away from the N-type electrode 102, such that the side of the N-type electrode 102 facing away from the P-type electrode 104 forms a light-emitting side.

[0162] The chip may further include a filter layer disposed in the stacked region and on the light-emitting side. The filter layer may include a first filter layer CF1, a second filter layer CF2, a third filter layer CF3, and so on, up to the nth filter layer CFn. The first filter layer CF1 corresponds to the first subpixel of the first luminescent material 113-1, the second filter layer CF2 corresponds to the second subpixel of the second luminescent material 113-2, the third filter layer CF3 corresponds to the third subpixel formed by the third luminescent material 113-3, and the n-1th filter layer CFn-1 corresponds to the m-1th subpixel formed by the n-1th luminescent material 113-n-1.

[0163] It should be noted that, as shown in Figures 24, 28 and 32, when the chip includes a filter layer, the emission wavelengths of the multiple light-emitting materials are not limited along the thickness direction of the chip, and the holes provided by the P-type electrode 104 can migrate to each light-emitting material, that is, the holes provided by the P-type electrode 104 can migrate to the light-emitting material closest to the N-type electrode 102. In some possible implementations, the thicknesses of the multiple light-emitting materials are relatively thin, so that the sum of the thicknesses of the multiple light-emitting materials is less than the hole diffusion length. The stacked portion of each light-emitting material can generate multiple wavelengths and be filtered using the corresponding filter layer so that each sub-pixel emits only light of one wavelength. For example, the stacked portion of the first light-emitting material 113-1 and the nth light-emitting material 113-n can generate light of a first wavelength and light of an nth wavelength, and the first sub-pixel emits light of the first wavelength through the first filter layer CF1.

[0164] It is understood that when the luminescent materials in the stacked structure emit light, the light will be emitted from each surface of the luminescent material layer, thereby stimulating the photoluminescence of the luminescent materials with longer wavelengths. As a result, except for the luminescent material with the smallest emission wavelength, the remaining luminescent materials have both electroluminescence and photoluminescence mechanisms.

[0165] As shown in Figures 28 and 30, the sides of two adjacent filter layers in the multiple filter layers can be in contact or isolated. The filter layer can be a color filter or a Bragg reflector (or a distributed Bragg reflector, DBR for short). Both the color filter and the Bragg reflector can filter the wavelength of the light passing through, thereby emitting light with different wavelengths. The Bragg reflector can be an alternating stack of two materials, aluminum nitrogen and gallium nitrogen, or an alternating stack of two materials, titanium oxide and silicon oxide, or an alternating stack of two materials, silicon oxide and silicon nitride. Optionally, the thickness of the Bragg reflector is 2-6 microns. In other embodiments, the thickness value can be adjusted as needed, and this application does not impose any restrictions on it.

[0166] In the above-mentioned chip, referring to Figures 25 to 27 and Figures 29 to 31, an isolation structure 114 can be provided between each sub-pixel. The isolation structure 114 can be between the first and second regions of each light-emitting material and extend into the light-emitting material closest to the N-type electrode 102. Referring to Figure 31, when the P-type electrode 104 of the chip includes a plurality of discrete sub-P-type electrodes, the isolation structure 114 can be located between the sub-P-type electrodes corresponding to each sub-pixel. Referring to Figures 27 and 30, when the N-type electrode 102 of the chip includes a plurality of discrete sub-N-type electrodes, the isolation structure 114 can be located between the sub-N-type electrodes corresponding to each sub-pixel. The isolation structure 114 can also be located between the filter layers corresponding to each sub-pixel and between the reflective layers 107.

[0167] Based on the fact that isolation structures can be provided between the sub-pixels, in some possible examples, referring to FIG. 25 , FIG. 27 , and FIG. 29 , among the stacked light-emitting materials, the light-emitting material near the P-type electrode 104 emits light at a wavelength greater than the light-emitting material farther from the P-type electrode 104. Thus, the light-emitting material near the P-type electrode emits light at a longer wavelength, while the light-emitting material farther from the P-type electrode emits light at a shorter wavelength. Consequently, the light emitted by the light-emitting material near the P-type electrode does not excite the light-emitting material near the N-type electrode, which emits light at a shorter wavelength.

[0168] Among the N luminescent materials, the one with the smallest wavelength is layered on the side of the remaining luminescent materials closest to the N-type electrode. The wavelengths of each luminescent material gradually increase from the N-type electrode to the P-type electrode. In this chip, the wavelengths of the first luminescent material 113-1, the second luminescent material 113-2, the third luminescent material 113-3, and so on to the nth luminescent material 113-n gradually increase from the N-type electrode to the P-type electrode, and they are arranged sequentially.

[0169] In the above possible examples, it is necessary to ensure that holes in the stacked regions diffuse only into the light-emitting material layer closest to the P-type electrode. For example, in the stacked regions, the thickness of the light-emitting material closest to the P-type electrode is greater than the hole diffusion length, that is, the thicknesses of the first to n-1th light-emitting materials are all greater than the hole diffusion length. Thus, when the chip is operating, holes provided by the P-type electrode in the light-emitting material stacked regions can migrate to the light-emitting material closest to the P-type electrode, causing the light-emitting material near the P-type electrode to emit electroluminescence. They will not migrate to the light-emitting material farther from the P-type electrode, nor will they stimulate its emission. This ensures that a single stacked region of the chip can emit only a single wavelength, while multiple different stacked regions can generate light of multiple wavelengths, enabling a single chip to have multiple wavelengths. Specifically, holes provided by the P-type electrode can migrate to the second region of each light-emitting material and not to the first region of each light-emitting material, causing the second region of each light-emitting material to emit electroluminescence. The first region of each light-emitting material will not emit electroluminescence and will not be stimulated by the light emitted by the second region of each light-emitting material. In other words, the first region of each light-emitting material will not emit photoluminescence, resulting in only the second region of each light-emitting material emitting light.

[0170] Another example is the addition of a hole-blocking layer. As shown in FIG26 , the chip further includes a hole-blocking layer 115, which is disposed at least between the luminescent material closest to the P-type electrode 104 and the adjacent luminescent material layer. The thickness of hole-blocking layer 115 and the combined thickness of the luminescent material layer closest to the P-type electrode 104 is greater than the hole diffusion length. This allows electrons provided by the N-type electrode to migrate to every luminescent material, while holes provided by the P-type electrode can only migrate to the luminescent material closest to the P-type electrode. This allows holes and electrons to combine in the luminescent material closest to the P-type electrode, ensuring that the luminescent material can achieve electroluminescence. Furthermore, holes are prevented from migrating to the luminescent material with a shorter wavelength near the P-type electrode, and are unable to excite the luminescent material farther from the P-type electrode to emit light at a shorter wavelength. This ensures that a single stacked region of the chip can only emit light of a single wavelength, while multiple stacked regions can generate light of multiple wavelengths, enabling a single chip to have multiple wavelengths.

[0171] For example, a hole blocking layer can be provided between any two adjacent luminescent materials, that is, between each luminescent material in the stack. For each of the first, second, third, and nth luminescent materials, a hole blocking layer (not shown) is provided between the first and second luminescent materials, between the second and third luminescent materials, and between the (n-1)th and nth luminescent materials.

[0172] The driving mode of the multiple sub-pixels of the chip can be synchronous driving or independent driving. Referring to Figures 24 and 28, the P-type electrode 104 is in an integrated form, and the N-type electrode 102 is also in an integrated form. The driving mode of the multiple sub-pixels of the chip is independent driving. Referring to Figures 25, 26, 29 and 31, the P-type electrode 104 includes a first sub-P-type electrode, a second sub-P-type electrode, a third sub-P-type electrode...the mth sub-P-type electrode, and the driving mode of the multiple sub-pixels of the chip is independent driving. Referring to Figures 27 and 30, the N-type electrode 102 includes a first sub-N-type electrode, a second sub-N-type electrode, a third sub-N-type electrode...the mth sub-N-type electrode, and the driving mode of the multiple sub-pixels of the chip is independent driving.

[0173] As shown in Figures 32 to 41, in other examples, the side of the light-emitting material farthest from the N-type electrode 102 facing the P-type electrode 104 is electrically connected to the P-type electrode 104, and different regions arranged along a direction intersecting the thickness of the LED chip correspond to different sub-pixels. That is, N light-emitting materials are stacked along the thickness direction of the LED chip, and the light-emitting material closest to the N-type electrode is electrically connected to the side facing the N-type electrode. Electrons provided by the N-type electrode are injected into the light-emitting material from this side and migrate to other light-emitting materials. The light-emitting material closest to the P-type electrode is electrically connected to the P-type electrode from the side facing the P-type electrode. Holes provided by the P-type electrode are injected into the light-emitting material from this side and migrate to other light-emitting materials. That is, holes provided by the P-type electrode can migrate to the light-emitting material closest to the N-type electrode, thereby generating light generated by the recombination of electrons and holes in each light-emitting material, and each light-emitting material can generate electroluminescence.

[0174] Along the direction from the P-type electrode to the N-type electrode, the multiple light-emitting materials are respectively a first light-emitting material, a second light-emitting material, a third light-emitting material, and so on. Along the thickness of the chip, the first light-emitting material, the second light-emitting material, the third light-emitting material, and so on are stacked in sequence. The sum of the thicknesses of the first, second, third, and n-th light-emitting materials is less than the hole diffusion length, allowing holes provided by the P-type electrode to migrate to the first, second, third, and n-th light-emitting materials, allowing the first, second, third, and n-th light-emitting materials to all produce electroluminescence. The first light-emitting material can emit light of a first wavelength, the second light-emitting material can emit light of a second wavelength, the third light-emitting material can emit light of a third wavelength, and so on. In this way, light of the first, second, and n-th wavelengths is emitted from the light-emitting surface of the chip.

[0175] It should be noted that the holes provided by the P-type electrode can migrate to each luminescent material, that is, the holes provided by the P-type electrode can migrate to the luminescent material closest to the N-type electrode. In some possible implementations, the thicknesses of the multiple luminescent materials are relatively thin, so that the sum of the thicknesses of the multiple luminescent materials is less than the hole diffusion length. The relationship between the emission wavelengths of the first luminescent material, the second luminescent material, the third luminescent material, ... the nth luminescent material is not limited, and the positions of the first luminescent material, the second luminescent material, the third luminescent material, ... the nth luminescent material can be interchanged. That is, the emission wavelength of each luminescent material is unrelated to its distance from the P-type electrode.

[0176] It is understood that when the luminescent materials in the stacked structure emit light, the light will be emitted from each surface of the luminescent material layer, thereby stimulating the photoluminescence of the luminescent materials with longer wavelengths. As a result, except for the luminescent material with the smallest emission wavelength, the remaining luminescent materials have both electroluminescence and photoluminescence mechanisms.

[0177] 39 to 41 , in stacking a plurality of light-emitting materials, several light-emitting materials form a light-emitting material group, and the light-emitting layer includes a plurality of light-emitting material groups; along the direction from the N-type electrode 102 to the P-type electrode 104, the plurality of light-emitting material groups are arranged in sequence. The number of light-emitting material groups may be 2, 3 or more groups. In different groups, the arrangement method and number of light-emitting materials may be the same or different. In FIG39 to FIG41 , the first light-emitting material 113-1, the second light-emitting material 113-2, the third light-emitting material 113-3...the nth light-emitting material 113-n, which are arranged in sequence along the direction from the P-type electrode 104 to the N-type electrode 102, constitute a light-emitting material group, and each figure includes a plurality of light-emitting material groups. In addition, referring to FIG32 to FIG38 , the number of light-emitting material groups may also be 1 group.

[0178] As shown in Figures 32 to 41, the above-mentioned chip may further include a reflective layer 107 and a filter layer. The reflective layer 107 may be located on the side of the N-type electrode 102 facing away from the P-type electrode 104, so that the side of the P-type electrode 104 facing away from the N-type electrode 102 forms a light-exiting side, and the corresponding filter layer is disposed on this light-exiting side. The filter layer may include a first filter layer CF1, a second filter layer CF2, a third filter layer CF3, ..., and an nth filter layer CFn. The first filter layer CF1 corresponds to a first sub-pixel of the first luminescent material 113-1, the second filter layer CF2 corresponds to a second sub-pixel of the second luminescent material 113-2, the third filter layer CF3 corresponds to a third sub-pixel formed by the third luminescent material 113-3, ..., and the nth filter layer CFn corresponds to an mth sub-pixel formed by the nth luminescent material 113-n.

[0179] It should be noted that, as shown in Figures 31 and 32, the sides of two adjacent filter layers in the multiple filter layers can be in contact or isolated. The filter layer can be a color filter or a Bragg reflector (or a distributed Bragg reflector, DBR for short). Both the color filter and the Bragg reflector can filter the wavelength of the light passing through, thereby emitting light with different wavelengths. The Bragg reflector can be an alternating stack of two materials, aluminum nitrogen and gallium nitrogen, or an alternating stack of two materials, titanium oxide and silicon oxide, or an alternating stack of two materials, silicon oxide and silicon nitride. Optionally, the thickness of the Bragg reflector is 2-6 microns. In other embodiments, the thickness value can be adjusted as needed, and this application does not impose any restrictions on it.

[0180] Continuing with reference to Figures 32 and 39 , the chip's multiple sub-pixels are driven synchronously. Referring to Figures 33 , 35 , 37 , and 40 , the P-type electrode 104 includes a first sub-P-type electrode, a second sub-P-type electrode, a third sub-P-type electrode ... an m-th sub-P-type electrode, and the chip's multiple sub-pixels are driven independently. Referring to Figures 32 , 34 , 36 , 38 , and 41 , the N-type electrode 102 includes a first sub-N-type electrode, a second sub-N-type electrode, a third sub-N-type electrode ... an m-th sub-N-type electrode, and the chip's multiple sub-pixels are driven independently.

[0181] In the above-mentioned chip, as shown in Figures 33 to 38, Figure 40 and Figure 41, an isolation structure 114 can be set between each sub-pixel, and the isolation structure 114 can be located between different regions of each light-emitting material of each light-emitting material group. As shown in Figures 33 and 40, when the P-type electrode 104 of the chip includes a plurality of discrete sub-P-type electrodes, the isolation structure 114 can be located between the sub-P-type electrodes corresponding to each sub-pixel. As shown in Figures 34 and 41, when the N-type electrode 102 of the chip includes a plurality of discrete sub-N-type electrodes, the isolation structure 114 can be located between the sub-N-type electrodes corresponding to each sub-pixel. The isolation structure 114 can also be located between the filter layers corresponding to each sub-pixel, and between the reflective layers 107.

[0182] The chip of each of the above embodiments may further include an N-type semiconductor layer and a P-type semiconductor layer, the N-type semiconductor and the P-type semiconductor being located on opposite sides of the light-emitting layer in a thickness direction, the N-type electrode being electrically connected to the light-emitting layer via the N-type semiconductor, and the P-type electrode being electrically connected to the light-emitting layer via the P-type semiconductor.

[0183] When the N-type electrode 102 includes M separate sub-N-type electrodes, the isolation structure 114 is located between adjacent sub-N-type electrodes and can extend into the P-type semiconductor layer 105. For example, as shown in Figures 36 and 38, the isolation structure 114 extends into the P-type semiconductor.

[0184] When the P-type electrode 104 includes M separate sub-P-type electrodes, the isolation structure 114 is located between adjacent sub-P-type electrodes and can extend into the N-type semiconductor layer 103. For example, as shown in Figures 35 and 37, the isolation structure 114 extends into the N-type semiconductor.

[0185] The above-mentioned setting of the isolation structure can not only reduce the process difficulty, but also improve the isolation effect of the isolation structure on each sub-pixel. It should be noted that the solution of extending the isolation structure to the P-type semiconductor or N-type semiconductor can also be applied to the chip structures of the other embodiments above.

[0186] In the above chip embodiment, in the independently driven driving mode, each sub-pixel corresponds to a separate sub-N-type electrode or sub-P-type electrode. In other embodiments, in the independently driven chip, a portion of the sub-pixels may also share a separate sub-N-type electrode or sub-P-type electrode.

[0187] As a first feasible implementation, the N-type electrode includes m mutually discrete sub-N-type electrodes, and the P-type electrode includes M mutually discrete sub-P-type electrodes; a side of the M sub-pixels close to the P-type electrode is electrically connected to each sub-P-type electrode one by one, and a side of the M sub-pixels close to the N-type electrode is electrically connected to the m sub-N-type electrodes; m is less than M, and a portion of the sub-pixels share one sub-N-type electrode.

[0188] As shown in Figure 45 , sub-pixels G and B share a sub-N-type electrode N1. Sub-pixel G is electrically connected to sub-P-type electrode P11, and sub-pixel B is electrically connected to sub-P-type electrode P21. Two sub-pixels R share another sub-N-type electrode N2. Sub-pixels R are electrically connected to sub-P-type electrode P22 and sub-P-type electrode P12, respectively. This improves the uniformity of light emission across sub-pixels that share a single sub-N-type electrode.

[0189] As a second feasible implementation, the P-type electrode includes m mutually discrete sub-P-type electrodes, and the N-type electrode includes M mutually discrete sub-N-type electrodes; one side of the M sub-pixels close to the N-type electrode is electrically connected to each sub-N-type electrode one by one, and one side of the M sub-pixels close to the P-type electrode is electrically connected to the m sub-P-type electrodes; m is less than M, and a part of the sub-pixels share one sub-P-type electrode.

[0190] As shown in FIG43 , sub-pixels G and B share a sub-P-type electrode P1. Sub-pixel G is electrically connected to sub-N-type electrode N11, and sub-pixel B is electrically connected to sub-N-type electrode N21. Two sub-pixels R share another sub-P-type electrode P2. The two sub-pixels R are electrically connected to sub-N-type electrode P22 and sub-N-type electrode P12, respectively. In this way, the light emission uniformity can be improved by sharing a sub-P-type electrode.

[0191] Referring to Figures 44 to 49, in the chip of the present application, in some embodiments, M sub-pixels form a pixel subgroup. For example, referring to Figure 44, sub-pixel B, sub-pixel G, and sub-pixel R together constitute a chip. Referring to Figures 44 and 46, the arrangement order of sub-pixel B, sub-pixel G, and sub-pixel R can be changed. The number of sub-pixels in a chip shown in Figures 44 to 46 can be 3. Referring to Figure 47, the number of sub-pixels in a chip can also be 4, or referring to Figures 48 and 49, the number of sub-pixels in a chip can be 5. In other embodiments, the number of sub-pixels in the chip can be more (for example, as shown in Figure 50, the chip includes 8 sub-pixels), and the arrangement of each sub-pixel can be flexibly adjusted.

[0192] In other embodiments, M sub-pixels form a plurality of pixel subgroups, and the plurality of pixel subgroups are arranged in an array in a direction intersecting the thickness of the light-emitting diode chip. For example, with reference to Figures 51 to 56, sub-pixel B, sub-pixel G, and sub-pixel R can form a pixel subgroup, and the chip includes a plurality of pixel subgroups arranged in an array. The arrangement of sub-pixels B, sub-pixels G, and sub-pixels R in different pixel subgroups can be the same or different. For example, with reference to Figure 54, a pixel subgroup can include four sub-pixels. For example, with reference to Figures 55 and 56, a pixel subgroup can include five sub-pixels.

[0193] As a feasible implementation, among the multiple sub-pixels in the above-mentioned pixel subgroup, the light-emitting wavelengths of the multiple sub-pixels are different, or the multiple sub-pixels include at least two sub-pixels with the same light-emitting wavelength.

[0194] For example, as shown in Figures 44 to 46, the sub-pixels of a pixel subgroup are respectively sub-pixel B, sub-pixel G, and sub-pixel R. As shown in Figure 48, sub-pixel G1 and sub-pixel G2 may represent sub-pixels with different luminous wavelengths. Alternatively, as shown in Figure 47, the sub-pixels of a pixel subgroup may include sub-pixel B, sub-pixel G, and two sub-pixels R. As shown in Figure 49, the sub-pixels of a pixel subgroup may include sub-pixel B, sub-pixel G, and three sub-pixels R.

[0195] In the chip of the present application, M sub-pixels form a plurality of pixel units, and the plurality of pixel units are arranged in an array along a thickness direction intersecting the light-emitting diode chip;

[0196] A pixel unit includes Y sub-pixels, and the Y sub-pixels include X colors; X is a positive integer greater than or equal to 3, and Y is a positive integer greater than or equal to X.

[0197] It should be noted that, as shown in Figures 44 to 46 , a chip includes three sub-pixels, which form a pixel unit. The three sub-pixels each have three colors. In this embodiment, X and Y are both 3. Furthermore, as shown in Figures 35 to 37 , a pixel unit includes 3*n sub-pixels, each of which has three colors. In this embodiment, X is 3 and Y is 3*n.

[0198] As shown in FIG47 , a chip includes four sub-pixels, which form a pixel unit. These four sub-pixels include three colors. In this embodiment, X is 3 and Y is 4. Furthermore, as shown in FIG54 , a pixel unit includes 4*n sub-pixels, each of which includes three colors. In this embodiment, X is 3 and Y is 4*n.

[0199] As shown in FIG48 , a chip includes five sub-pixels, which form a pixel unit. The five sub-pixels include four colors (taking the different emission wavelengths of sub-pixel G1 and sub-pixel G2 as an example). In this embodiment, X is 4 and Y is 5. Furthermore, as shown in FIG55 , a pixel unit includes 5*n sub-pixels, each of which includes four colors. In this embodiment, X is 4 and Y is 5*n.

[0200] As shown in FIG49 , a chip includes five sub-pixels, which form a pixel unit. The five sub-pixels include three colors. In this embodiment, X is 3 and Y is 5. Furthermore, as shown in FIG56 , a pixel unit includes 5*n sub-pixels, which include three colors. In this embodiment, X is 3 and Y is 5*n.

[0201] In the above embodiment, when Y is greater than X, the light emission wavelengths of at least a portion of the sub-pixels in a pixel unit are equal.

[0202] According to the above method, pixel units with different structures can be designed in the chip to achieve a diversified chip structure to adjust the chip's light mixing effect, thereby realizing a chip with a flexible structure and rich light output effects.

[0203] As a feasible implementation, in the chip of the embodiment of the present application, all sub-pixels in the same pixel unit are only used by the pixel unit to which they belong. Referring to Figures 44 to 46, three sub-pixels in the same chip can form a pixel unit, and all sub-pixels are only used by this pixel unit. Referring to Figure 47, the chip includes 2 sub-pixels R, 1 sub-pixel B and 1 sub-pixel G. 2 sub-pixels R, 1 sub-pixel B and 1 sub-pixel G can form a complete pixel unit and are only used by this pixel unit. In this way, a complete full-color pixel unit can be formed in the chip, ensuring that the chip is more convenient to use.

[0204] It should be noted that in two adjacent pixel units, for example, the first pixel unit and the second pixel unit. When the sub-pixels in the second pixel unit are not bright enough, part or all of the sub-pixels in the adjacent first pixel unit can be flexibly borrowed to complete the light emission of the second pixel unit. That is, the borrowed sub-pixels in the first pixel unit can be used not for the light emission of the first pixel unit, but for the light emission of the second pixel unit. In this way, the structural flexibility and light emission effect of the chip can be improved. Among them, the second pixel unit can also borrow the light emission of the first pixel unit for other reasons, which is not limited in this application.

[0205] As another achievable implementation, in the chip of the embodiment of the present application, two sub-pixels in a pixel unit are shared with the adjacent pixel unit, and the total number of sub-pixels in a single chip is M=a*(2X-2), where a is a positive integer greater than or equal to 1. Referring to FIG50 , in a chip, sub-pixel R in pixel unit PU2 is shared with its adjacent pixel unit PU1, and sub-pixel B in pixel unit PU2 is shared with its adjacent pixel unit PU3. The number of sub-pixels in the chip is 8, and X is 3 and a is 2 in the chip. Wherein, a is the number of pixel sub-groups composed of all sub-pixels in a single chip. For example, in the chip shown in the figure, sub-pixel B, sub-pixel G, sub-pixel R, and sub-pixel G together form a pixel sub-group. There are two pixel sub-groups in the chip, so a is 2.

[0206] In the same chip, some sub-pixels are shared to form different pixel units, which can ensure the flexible structure of the chip and meet diverse display needs.

[0207] In some embodiments, the size of the LED chip is greater than or equal to 50 microns. The size of the pixel subgroup of the chip may also be greater than or equal to 50 microns. For example, it may be 50-100 microns, or 100-150 microns, or greater than 150 microns. Of course, in some embodiments, the size of the LED chip may also be less than 50 microns. The size of the LED chip can be selected according to different usage scenarios.

[0208] In some embodiments, the shape of the LED chip is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram, and a polygon with more than four sides; wherein different sub-pixels have the same or different shapes. That is, the shape of the first sub-pixel B and the second sub-pixel G can both be a rectangle as shown in FIG. 43 .

[0209] When a plurality of LED chips form a LED chip group, the shapes of different LED chips may be the same or different.

[0210] In some embodiments, the sub-pixel size ranges from 0.001 to 200 microns. When the sub-pixel size is between 0.001 microns and 0.1 microns, the sub-pixel size is at the nanometer level, representing a nano-LED. During the nano-LED manufacturing process, the single-core, multi-color, multi-sub-pixel arrangement of the present application can be referenced, thereby facilitating an increase in the size of a single nano-LED chip containing multiple sub-pixels, bringing the size of the single chip close to or within the size range of LED chips currently accessible by mass transfer processes. This reduces the operational difficulty of the nano-LED manufacturing process and improves its operability.

[0211] In other embodiments, for example, a LED chip with 2*2 sub-pixels for large televisions can have a single sub-pixel size of 50 microns, with a spacing of 10 microns between two adjacent sub-pixels. The LED chip has a length and width of 110 microns, resulting in a size of 110*110 microns. LED chips of this size can utilize mini LED packaging processes.

[0212] The size of the LED chip and the size of the sub-pixel may vary depending on the usage scenario of the LED chip. Below, exemplary descriptions of the size of the LED chip and the size of the sub-pixel in different usage scenarios are given.

[0213] When the LED chip is used in display products such as home televisions and desktop computers, at a pixel density of 50-150, the size (pitch) of a pixel unit composed of several sub-pixels in multiple LED chips can be 150-700 microns, the size (sub pitch) of the sub-pixels in the LED chip can be less than 250 microns, and the size of the LED chip can be greater than 100 microns.

[0214] When the LED chip is used in display products such as laptops and tablets, when the pixel density is 150-250, the sub-pixel size can be less than 70 microns, the pixel unit size is 100-200 microns, and the LED chip size can be greater than 60 microns.

[0215] When the LED chip is used in display products such as mobile phones and electronic watches, when the pixel density is greater than 300, the sub-pixel size can be less than 30 microns, the pixel unit size is less than 100 microns, and the LED chip size can be greater than 50 microns.

[0216] Based on this, the light-emitting diode chip provided in the embodiment of the present application adopts a single-core, multi-color, multi-sub-pixel arrangement. The size of the sub-pixels and the size range of the light-emitting diode chip are relatively large, which can be applied to different usage scenarios, thereby increasing the applicability of the light-emitting diode chip.

[0217] In some embodiments, the shape of the sub-pixel is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram, and a polygon with more than four sides.

[0218] In some embodiments, the sizes of different sub-pixels are equal or different. The size of a sub-pixel affects its luminous area. That is, the luminous areas of different sub-pixels can be equal or different. The sizes of different sub-pixels can be adjusted according to the brightness attenuation of the sub-pixels. For example, if the brightness attenuation rate of a certain sub-pixel is large, the size of the sub-pixel can be appropriately increased to ensure uniform light output requirements. The sizes of different sub-pixels can also be adjusted according to whether the sub-pixels are shared between different pixel units (PU for short). For example, as shown in Figure 50, sub-pixel (B) and sub-pixel (R) are shared by two pixel units respectively in the process of forming pixel units PU1 and PU2, while sub-pixel (G) is not shared, but all belong to pixel unit PU1. Therefore, the sizes of sub-pixel (B) and sub-pixel (R) are larger than the size of sub-pixel (G). In this way, the luminous brightness of the shared sub-pixels in each pixel unit can be guaranteed.

[0219] It should be pointed out that the above-mentioned "size" can be understood as the extension length of the sub-pixel in a certain extension direction, for example, it can be the length or width of a rectangular sub-pixel, the major axis length or minor axis length of an elliptical sub-pixel, or the diameter of a circular sub-pixel, etc.

[0220] As shown in FIG58 , the chip provided in the embodiment of the present application further includes a buffer layer 101, an N-type semiconductor layer 103, a P-type semiconductor layer 105, a current spreading layer 106, a reflective layer 107, and a first insulating layer 108. The buffer layer 101 and the N-type semiconductor layer 103 are stacked, the light-emitting layer is disposed on the side of the N-type semiconductor layer 103 facing away from the buffer layer 101, and the P-type semiconductor layer 105 is disposed on the side of the light-emitting layer facing away from the buffer layer 101. The current spreading layer 106 contacts the side of the P-type semiconductor layer 105 facing away from the buffer layer 101. The N-type electrode 102 contacts the N-type semiconductor layer 103, and the P-type electrode 104 contacts both the P-type semiconductor layer 105 and the current spreading layer 106. The first insulating layer 108 is disposed on the side of the current spreading layer 106 facing away from the buffer layer 101.

[0221] The light emitting layer includes a first light emitting material 113 - 1 , a second light emitting material 113 - 2 , and a third light emitting material 113 - 3 disposed between the P-type electrode 104 and the N-type electrode 102 .

[0222] Alternatively, as shown in FIG59 , the reflective layer 107 can be disposed on the side of the light-emitting layer away from the buffer layer 101. In this way, the light-emitting diode chip emits light in a direction away from the buffer layer 101, as indicated by the downward arrow in the figure. The chip is a thin-film flip-chip structure.

[0223] 58 , the reflective layer 107 is disposed on the side of the first insulating layer 108 away from the buffer layer 101, and a second insulating layer 109 is further disposed on the side of the reflective layer 107 away from the buffer layer 101. The second insulating layer can protect the reflective layer.

[0224] The buffer layer can be made of one or more of gallium nitride, aluminum gallium nitride, and aluminum indium gallium nitride, and its thickness can be 10-40 nanometers. The N-type semiconductor layer can be made of N-type doped gallium nitride, and the P-type semiconductor layer can be made of P-type doped gallium nitride. The current spreading layer can be made of a transparent conductive material (indium tin oxide, ITO) or silver, and its function is to improve the distribution of the P-type electrode, allowing the holes to be distributed as evenly as possible in the area where the P-type semiconductor layer is located. The first insulating layer can be made of silicon oxide or silicon nitride.

[0225] As shown in FIG58 , the LED chip provided in this embodiment further includes a substrate 100, which is disposed on the side of the buffer layer 101 facing away from the light-emitting layer. The substrate material can be a composite of one or more of sapphire, gallium nitride, aluminum nitride, silicon, and silicon carbide. The chip has a flip-chip structure.

[0226] As shown in Figure 60, the chip provided in the embodiment of the present application may also include a bonding substrate 110, a binding layer 111, an N-type semiconductor layer 103, a P-type semiconductor layer 105 and a reflective layer 107.

[0227] The bonding substrate 110 and the binding layer 111 are sequentially disposed on the P-type electrode 104. The P-type semiconductor layer 105 is disposed on the side of the binding layer 111 facing away from the bonding substrate 110 and in contact with the binding layer 111. The light-emitting layer is disposed on the side of the P-type semiconductor layer 105 facing away from the bonding substrate 110, and the N-type semiconductor layer 103 is disposed on the side of the light-emitting layer facing away from the bonding substrate 110. The N-type electrode 102 contacts the side of the N-type semiconductor layer 103 facing away from the bonding substrate 110. The reflective layer 107 is disposed on the side of the P-type semiconductor layer 105 closer to the bonding substrate 110. The light-emitting layer includes a first light-emitting material 113-1, a second light-emitting material 113-2, and a third light-emitting material 113-3 arranged side by side. A first insulating layer 108 is disposed on top of the N-type semiconductor layer 103. The light emission direction in Figure 60 is upward, as indicated by the arrow in the figure, forming a vertical, upright structured light-emitting diode chip.

[0228] As shown in FIG61 , the chip provided in this embodiment of the present application further includes a light-blocking layer 116, which is located on the light-emitting side of the LED chip and between two adjacent sub-pixels. Light-blocking layer 116 can be located between the first filter layer CF1 and the second filter layer CF2, or between the second filter layer CF2 and the third filter layer CF3. Light-blocking layer 116 can be made of a black resin material and has the function of absorbing and blocking light. Positioning light-blocking layer 116 between two adjacent sub-pixels prevents light mixing between the two sub-pixels, ensuring optimal light extraction from the LED chip.

[0229] As shown in FIG61 , the chip provided in the embodiment of the present application further includes a color conversion layer 112 . The color conversion layer 112 is disposed on a portion of the light-emitting side of the light-emitting diode chip and corresponds to at least a portion of the sub-pixel area.

[0230] It should be noted that the orthographic projection of the color conversion layer 112 on the surface where the corresponding sub-pixel is located can cover the entire area of ​​a single sub-pixel, or only cover a portion of the area of ​​a single sub-pixel. The material of the color conversion layer 112 can be quantum dot material, phosphor material, etc. The use of the color conversion layer 112 can adjust the light emission wavelength of the LED chip, enriching the variety of its light emission wavelengths.

[0231] As shown in FIG61 , taking a chip with a front-mounted structure as an example, the sub-pixels corresponding to the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3 emit light at different wavelengths. The color conversion layer 112 is located on the light-emitting side of the first filter layer CF1 and faces a portion of the first filter layer CF1. This allows the color conversion layer 112 to convert a portion of the light emitted by the first filter layer CF1 into light of wavelengths other than the wavelengths transmitted by the first filter layer CF1, the second filter layer CF2, and the third filter layer CF3. Therefore, the chip can emit light of multiple wavelengths.

[0232] In a second aspect, embodiments of the present application provide a method for manufacturing a light-emitting diode chip. This method can be used to manufacture the aforementioned light-emitting diode chip. A single-core, three-color, multi-sub-pixel chip is used as an example. It should be noted that the first filter layer 117a, second filter layer 117b, and third filter layer 117c in the method for manufacturing a light-emitting diode chip in embodiments of the present application are equivalent to the first filter layer CF1, second filter layer CF2, and third filter layer CF3 of the light-emitting diode chip described in the first aspect, respectively.

[0233] As a method for preparing a light-emitting diode chip, as shown in FIG62 , the method includes:

[0234] A substrate 100 is provided ( FIG. 62 ( a )); a buffer layer 101, an N-type semiconductor layer 103 and a third light-emitting material 113-3 are sequentially formed on the substrate 100 by an epitaxial growth process ( FIG. 62 ( b )); a portion of the third light-emitting material 113-3 is removed by a photolithography and etching process ( FIG. 62 ( c )); a protective layer 118 covering the remaining third light-emitting material 113-3 and the exposed N-type semiconductor layer 103 is formed by a film-forming process ( FIG. 62 ( d )); a portion of the protective layer 118 is removed by a photolithography and etching process to expose the N-type semiconductor layer 103 next to the remaining third light-emitting material 113-3 ( FIG. 62 ( e )); a second light-emitting material 113-2 is formed on the exposed N-type semiconductor layer 103 and the remaining protective layer by an epitaxial growth process ( FIG. 62 ( f )); the protective layer 118 is removed and the second light-emitting material 113-2 thereon (Figure 62(g)); a new protective layer 118 covering the third light-emitting material 113-3, the second light-emitting material 113-2 and the N-type semiconductor layer 103 is formed by an epitaxial growth process (Figure 62(h)); the protective layer 118 on the N-type semiconductor layer 103 is removed by photolithography and etching processes (Figure 62(i)); a first light-emitting material 113-1 covering the remaining protective layer 118 and the N-type semiconductor layer 103 is formed by an epitaxial growth process (Figure 62(j)); the protective layer 118 and the first light-emitting material 113-1 thereon are removed (Figure 62(k)); a P-type semiconductor layer 105 covering the third light-emitting material 113-3, the second light-emitting material 113-2 and the first light-emitting material 113-1 is formed by an epitaxial growth process (Figure 62(l)). The chip is then obtained through chip processing.

[0235] On the basis of the above, referring to FIG. 63 , the preparation method includes forming an isolation structure 114 ( FIG. 63 ( m )).

[0236] As a method for preparing a light emitting diode chip, as shown in FIG64 and FIG65 , the method includes:

[0237] A substrate 100 is provided, and a buffer layer 101, an N-type semiconductor layer 103, and a third light-emitting material 113-3 are sequentially formed on the substrate 100 by an epitaxial growth process (Figure 64(a)). A second light-emitting material 113-2 is formed on a portion of the surface of the third light-emitting material 113-3 by a selective epitaxial growth process (Figure 64(b)). A first light-emitting material 113-1 is formed adjacent to the second light-emitting material 113-2 by a selective epitaxial growth process, with the first light-emitting material 113-1 in contact with the third light-emitting material 113-3 (Figure 64(c)). A P-type semiconductor layer 105 covering the third light-emitting material 113-3, the second light-emitting material 113-2, and the first light-emitting material 113-1 is formed by an epitaxial growth process (Figure 64(d)). A chip is then obtained by a chip process.

[0238] Alternatively, the process includes: providing a substrate 100, and sequentially forming a buffer layer 101, an N-type semiconductor layer 103, and a third light-emitting material 113-3 on the substrate 100 by an epitaxial growth process ( FIG. 65( a )); forming a second light-emitting material 113-2 on a portion of the surface of the third light-emitting material 113-3 by a selective epitaxial growth process ( FIG. 65( b )); forming a first light-emitting material 113-1 next to the second light-emitting material 113-2 by a selective epitaxial growth process, with the first light-emitting material 113-1 and the third light-emitting material 113-3 spaced apart by a selective epitaxial growth process ( FIG. 65( c )); and forming a P-type semiconductor layer 105 covering the third light-emitting material 113-3, the second light-emitting material 113-2, and the first light-emitting material 113-1 by an epitaxial growth process ( FIG. 65( d )). The chip is then obtained by a chip process.

[0239] Based on the above, as shown in FIG66 , the preparation method includes forming an isolation structure 114 ( FIG66 ( f )).

[0240] As a method for preparing a light-emitting diode chip, as shown in FIG67 , the method includes:

[0241] A substrate 100 is provided, and a buffer layer 101, an N-type semiconductor layer 103, and a third light-emitting material 113-3 are sequentially formed on the substrate 100 by an epitaxial growth process ( FIG. 67( a )). A second light-emitting material 113-2 is formed on a portion of the surface of the third light-emitting material 113-3 by a selective epitaxial growth process ( FIG. 67( b )). A first light-emitting material 113-1 is formed on a portion of the surface of the second light-emitting material 113-2 by a selective epitaxial growth process ( FIG. 67( c )). A P-type semiconductor layer 105 covering the third light-emitting material 113-3, the second light-emitting material 113-2, and the first light-emitting material 113-1 is formed by an epitaxial growth process ( FIG. 67( d )). A chip is then obtained by a chip process.

[0242] On the basis of the above, referring to FIG. 68 , the preparation method includes forming an isolation structure 114 ( FIG. 68 ( f )).

[0243] As a method for preparing a light-emitting diode chip, as shown in FIG69 , the method includes:

[0244] A substrate 100 is provided (FIG. 69(a)); a buffer layer 101, an N-type semiconductor layer 103, a third light-emitting material 113-3, a second light-emitting material 113-2, a first light-emitting material 113-1, and a P-type semiconductor layer are sequentially formed on the substrate 100 by an epitaxial growth process (FIG. 69(b)); steps and trenches (isolation structures not filled with isolation materials) are formed (FIG. 69(c)); a patterned current spreading layer 106 is formed (FIG. 69(d)); a patterned first insulating layer covering the current spreading layer 106 is formed. Insulating layer 108, part of the first insulating layer 108 is located at the step (Figure 69(e)); a patterned reflective layer 107 covering the first insulating layer 108 is formed (Figure 69(f)); a patterned second insulating layer 109 covering the reflective layer 107 is formed (Figure 69(g)); an N-type electrode 102 and a P-type electrode 104 are formed (Figure 69(h)); a first filter layer 117a, a second filter layer 117b and a third filter layer 117c are formed on the side of the substrate 100 away from the reflective layer 107 (Figure 69(i)).

[0245] As a method for preparing a light-emitting diode chip, as shown in FIG. 70 , the method includes:

[0246] A substrate 100 is provided ( FIG. 70 ( a )); a buffer layer 101, an N-type semiconductor layer 103, a third light-emitting material 113-3, a second light-emitting material 113-2, a first light-emitting material 113-1, and a P-type semiconductor layer are sequentially formed on the substrate 100 by an epitaxial growth process ( FIG. 70 ( b )); steps and a plurality of spaced trenches (an isolation structure not filled with an isolation material) are formed ( FIG. 70 ( c )); a patterned current spreading layer 106 is formed ( FIG. 70 ( d )); and a patterned substrate covering the current spreading layer 106 is formed. a first insulating layer 108 is formed, with part of the first insulating layer 108 located at the step ( FIG. 70 ( e )); a patterned reflective layer 107 covering the first insulating layer 108 is formed ( FIG. 70 ( f )); a patterned second insulating layer 109 covering the reflective layer 107 is formed ( FIG. 70 ( g )); an N-type electrode 102 and a P-type electrode 104 are formed ( FIG. 70 ( h )); and a first filter layer 117 a , a second filter layer 117 b and a third filter layer 117 c are formed on the side of the substrate 100 facing away from the reflective layer 107 ( FIG. 70 ( i )).

[0247] In a third aspect, an embodiment of the present application provides a light-emitting diode chip set, comprising a plurality of the above-mentioned light-emitting diode chips, wherein the plurality of light-emitting diode chips are arranged in an array along a thickness direction intersecting the light-emitting diode chips.

[0248] As shown in FIG71 , multiple chips can be arranged in an array along a plane formed by the x-direction and the y-direction, for example, chip C1, chip C2, chip C3, and chip C4. The x-direction and the y-direction can intersect with each other, and in some embodiments, the two can be perpendicular to each other. Multiple chips can be arranged only along the x-direction, such as chip C1 and chip C2. Multiple chips can also be arranged only along the y-direction, such as chip C1 and chip C3. The arrangement of the chipset provided in this application can be flexibly adjusted.

[0249] 71 , in the chipset of the present application, the sub-pixels in a single chip can form a complete pixel unit. For example, in chip C1, sub-pixel B, sub-pixel G, and sub-pixel R can form a pixel unit.

[0250] In the chipset of the present application, pixels of multiple chips can form a complete pixel unit.

[0251] As a first achievable embodiment, as shown in FIG83 , in two adjacent LED chips, the entire subpixel area of ​​one LED chip and the entire subpixel area of ​​the other LED chip together form a pixel unit. For example, subpixel B in chip C1 and subpixel G and subpixel R in chip C3 together form a pixel unit.

[0252] As a second achievable embodiment, referring to Figures 77-59, in two adjacent LED chips, a partial area of ​​a sub-pixel of one LED chip and a partial area of ​​a sub-pixel of the other LED chip together form a pixel unit. For example, in Figure 77, a partial area of ​​sub-pixel R and sub-pixel G in chip C1 and a partial area of ​​sub-pixel B in chip C2 together form a pixel unit PU2. Sub-pixel R of chip C1 can also be used to form pixel unit PU1, and sub-pixel B of chip C2 can also be used to form pixel unit PU3. Therefore, sub-pixel R and sub-pixel B are sub-pixels shared by two pixel units, respectively. Compared with Figure 77, Figure 78 shows a different arrangement of sub-pixels in the two chips, but the shared sub-pixels are still sub-pixels R and sub-pixels B.

[0253] 79 , the sub-pixels that are shared may also be sub-pixels G and R. Referring to FIG. 80 , the sub-pixels that are shared may also be sub-pixels G and B.

[0254] 72 to 76 , in the LED chip group provided in the embodiment of the present application, two adjacent LED chips are of irregular shape, one of the two adjacent LED chips has a protruding area, and the other has a concave area; the shapes of the protruding area and the concave area are adapted to each other and fit together.

[0255] It should be noted that the protruding area can be a cube, a pyramid, a hemisphere, or other irregular shape, and the protruding area and the concave area are compatible and interlocking. The number of protruding areas and the number of concave areas can be one, two, or more, and the number of both can be equal. For example, adjacent LED chips can include a first LED chip and a second LED chip.

[0256] It should be noted that, using Figures 72-53 as an example, the first LED chip C1 and the second LED chip C2 are both stepped, and the convex area of ​​the step of the first LED chip C1 is relatively aligned with the concave area of ​​the step of the second LED chip C2, so that the first LED chip C1 and the second LED chip C2 are completely joined.

[0257] 72 and 73 , the sub-pixels in the first LED chip C1 have the same size. In this application, the convex and concave regions are aligned and joined together to form a "mortise and tenon structure," thereby facilitating self-alignment assembly of different LED chips, reducing alignment difficulty and improving manufacturing efficiency and yield.

[0258] The shape of the assembled LED chip can also be convex or concave (as shown in FIG73 ); or, in the stepped LED chip, different sub-pixels have different sizes (as shown in FIG74 ); or, the LED chip has a serrated edge (as shown in FIG75 ); or, the LED chip has an arc-shaped edge (as shown in FIG76 ).

[0259] In other embodiments, as shown in FIG. 77 to FIG. 82 , in the assembled chips of the LED chip group, the shapes of different LED chips may be the same and regular.

[0260] In the chipset provided in the embodiment of the present application, a plurality of light-emitting diode chips form a plurality of chip groups arranged in an array and a plurality of pixel units arranged in an array; in the same light-emitting diode chip, the spacing between adjacent sub-pixels is d1; the spacing between adjacent chip groups is d2; the spacing between adjacent pixel units is d3; and the spacing between adjacent light-emitting diode chips is d4; d1, d2, d3, and d4 are all equal, or d1, d2, d3, and d4 are not equal to each other.

[0261] As shown in FIG71 , in the chip set, along the y direction, the sum of the size of subpixel B of chip C1 and the pitch between subpixel B and subpixel G is a first size. Subpixel B has a size a, and the pitch between subpixel B and subpixel G is b. The first size = a + b, and is the subpixel size (sub pitch) of subpixel B.

[0262] In chip C1, the sum of the size of subpixel G and the spacing between subpixel G and subpixel R is the second size. Subpixel G size is c, and the spacing between subpixel G and subpixel R is d. The second size = c + d, and the second size is the subpixel size of subpixel G.

[0263] The sum of the size of subpixel R in chip C1 and the spacing between subpixel R in chip C1 and subpixel B in chip C2 is the third size. The size of subpixel R is e, and the spacing between subpixel R in chip C1 and subpixel B in chip C2 is f. The third size = e + f, and is the subpixel size of subpixel R.

[0264] Optionally, the first size, the second size, and the third size are all equal; or the first size, the second size, and the third size may be unequal. The sum of the first size, the second size, and the third size may be the pixel size (Pitch) of a pixel unit consisting of sub-pixel B, sub-pixel G, and sub-pixel R of chip C1.

[0265] Similarly, in chip C2, the pixel unit formed by sub-pixel B, sub-pixel G, and sub-pixel R also has a pixel size. The pixel sizes of chip C1 and chip C2 can be equal or different.

[0266] 82 , along the first direction x, in chip group CG1 , the size of the sub-pixel B of chip C1 is a′, and the distance between the sub-pixel B of chip C1 and the sub-pixel B of chip C3 is g.

[0267] The sum of a' and g can be the pixel size of the pixel unit in chip C1 along the first direction x. The sum of a, b, c, d, e, and f can be the pixel size of the pixel unit along the second direction y. The sum of m and n can be equal to or different from the sum of a, b, c, d, e, and f.

[0268] When the number of sub-pixels in a chipset along the first direction x is 1, the sum of the chip size and the spacing between chipsets along the first direction x can be flexibly adjusted. That is, the sum of a' and g shown in FIG82 can be flexibly adjusted. This can accommodate display panels with different pixel sizes.

[0269] In each LED chip, the spacing between two adjacent sub-pixels can be d1. The spacing between adjacent chip groups can be d2. The spacing between adjacent pixel units can be d3. The spacing between two adjacent LED chips can be d4. d1, d2, d3, and d4 can all be equal. This effectively improves the regularity of the arrangement of each sub-pixel, each LED chip, each LED chip group, and each pixel unit, thereby enhancing light uniformity.

[0270] Alternatively, d1, d2, d3, and d4 can each be unequal. That is, d1 may not equal d2, d3, or d4; d2 may not equal d3, d4; and d3 may not equal d4. d3 can be determined by the PPI of the full-color display screen fabricated using the LED chipset. Flexible adjustment of d3 enables efficient layout for a variety of applications, from watches to large-screen TVs.

[0271] In a fourth aspect, an embodiment of the present application provides a display module, comprising a driving backplane 200 and the light-emitting diode chipset of the above embodiment, wherein the light-emitting diode chipset is disposed on the driving backplane 200 and electrically connected to the driving backplane 200 .

[0272] It should be noted that the driving backplane 200 may be a TFT (Thin Film Transistor) driving backplane or a CMOS (Complementary Metal Oxide Semiconductor) driving backplane.

[0273] It should be noted that, as a first achievable embodiment, as shown in FIG84 , there are multiple LED chip groups, which are arranged in an array on the driver backplane 200. The driver backplane 200 can provide driving current to the multiple LED chip groups, thereby driving the multiple LED chip groups to emit light. FIG66 shows LED chip group CG1 and LED chip group CG2 arranged on the driver backplane 200. In some embodiments, there may be three, four, or more LED chip groups, arranged in an array.

[0274] LED chip group CG1 and LED chip group CG2 each include LED chip C1 and LED chip C2. Each LED chip includes a pixel subgroup, each of which includes three sub-pixels. In some embodiments, the number of LED chips in the LED chip group, and the number of pixel subgroups and sub-pixels in the LED chip, can be adjusted, and this embodiment does not impose any limitations thereto.

[0275] As a second achievable embodiment, as shown in FIG85 , a driving backplane 200 includes a driving substrate 201 and a plurality of driving units 202. One driving unit 202 is electrically connected to one corresponding light-emitting diode chipset, and the plurality of driving units 202 are all electrically connected to the driving substrate 201. The driving units 202 and the driving substrate 201 may also be TFTs and CMOSs.

[0276] A driving unit 202 and an LED chipset can form a micro-display module. FIG85 shows micro-display modules DMB1 and DMB2, both of which are electrically connected to a driving substrate 201. The driving substrate 201 can provide driving current to the driving unit 202 in the micro-display module, thereby driving the LED chipset to emit light. In some embodiments, the number of micro-display modules can be three, four, five, or more, and this embodiment does not impose any limitation on this number.

[0277] FIG85 shows that LED chip group CG1 and LED chip group CG2 are electrically connected to two different drive units 202, respectively. Both drive units 202 are electrically connected to a drive substrate 201. Both LED chip group CG1 and LED chip group CG2 include LED chips C1 and C2. Each LED chip includes a pixel subgroup, each of which includes three sub-pixels. In this embodiment, the number of LED chip groups, the number of LED chips in an LED chip group, and the number of pixel subgroups and sub-pixels in an LED chip can be adjusted, and this embodiment also does not impose any limitations on this.

[0278] In a fifth aspect, an embodiment of the present application provides a full-color display screen, which can be manufactured by encapsulating the above-mentioned display module.

[0279] In a sixth aspect, embodiments of the present application provide an electronic device comprising the aforementioned full-color display. The electronic device may be a television, an electronic watch, an e-book, a desktop computer, a laptop computer, a tablet computer, a mobile phone, an AR device (Augmented Reality) or a VR device (Virtual Reality). When the light-emitting diode chip of the electronic device includes ultraviolet light pixels, the electronic device may also be a UV curing lamp or a UV detection lamp.

[0280] In the description of the embodiments of the present application, it should be understood that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances. The orientation or position relationship indicated by the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or position relationship shown in the accompanying drawings. It is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In the description of this application, the meaning of "multiple" is two or more, unless otherwise precisely and specifically specified.

[0281] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the numbers used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0282] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A light-emitting diode chip, comprising an N-type electrode, a P-type electrode, and a light-emitting layer disposed between the N-type electrode and the P-type electrode, wherein the light-emitting layer is electrically connected to the N-type electrode and the P-type electrode respectively; The light-emitting layer includes N light-emitting materials, the light-emitting wavelengths of the N light-emitting materials are different, and M sub-pixels are formed. Among the M sub-pixels, at least some of the sub-pixels have different light-emitting wavelengths. Both M and N are positive integers greater than or equal to 3, and M is greater than or equal to N. When the P-type electrode and the N-type electrode are powered on, the light emitting mechanism of the N light emitting materials is at least electroluminescence.

2. The light-emitting diode chip according to claim 1, wherein: N light-emitting materials are arranged in parallel between the N-type electrode and the P-type electrode, and each of the light-emitting materials is electrically connected to the N-type electrode and the P-type electrode; The N light-emitting materials arranged side by side correspond to the M sub-pixels.

3. The light-emitting diode chip according to claim 1, wherein: Along the thickness direction of the light-emitting diode chip, at least one of the N light-emitting materials is stacked with the remaining light-emitting materials; Among the stacked plurality of light-emitting materials, at least one of the light-emitting materials is located on a side of the remaining light-emitting materials close to the N-type electrode.

4. The light-emitting diode chip according to claim 3, wherein: The light-emitting material closest to the N-type electrode includes a first region and a second region arranged in parallel, the first region and the second region being electrically connected to the N-type electrode on a side facing the N-type electrode, and the first region facing the P-type electrode corresponding to the remaining light-emitting materials arranged in parallel except for the light-emitting material closest to the N-type electrode; The second region and the remaining light-emitting materials are electrically connected to the P-type electrode on one side thereof and the other side thereof. The second region and the remaining light-emitting materials correspond to M sub-pixels respectively.

5. The light-emitting diode chip according to claim 3, wherein: The remaining light-emitting materials except the light-emitting material closest to the N-type electrode are stacked along the thickness direction of the light-emitting diode chip, and the light-emitting material closest to the N-type electrode is electrically connected to the N-type electrode on the side facing the N-type electrode. The light-emitting diode chip according to claim 5 , wherein: Of the two adjacent light-emitting materials, the light-emitting material close to the N-type electrode includes a first region and a second region arranged in parallel, and a side of the first region facing the P-type electrode corresponds to the other light-emitting material; One side of the N second regions of the light-emitting materials facing the P-type electrode is electrically connected to the P-type electrode, and the N second regions of the light-emitting materials correspond to the M sub-pixels respectively.

7. The light-emitting diode chip according to claim 5, wherein: The side of the light-emitting material farthest from the N-type electrode facing the P-type electrode is electrically connected to the P-type electrode, and different regions arranged along a thickness direction crossing the light-emitting diode chip correspond to different sub-pixels.

8. The light-emitting diode chip according to claim 7, wherein: Among the N luminescent materials stacked in layers, several of the luminescent materials form a luminescent material group, and the luminescent layer has a plurality of the luminescent material groups; Along the direction from the N-type electrode to the P-type electrode, a plurality of the light-emitting material groups are arranged in sequence.

9. The light-emitting diode chip according to any one of claims 3 to 8, further comprising a plurality of filter layers with different filtering wavelengths, wherein the plurality of filter layers are arranged side by side on the light-emitting side of the light-emitting diode chip, and the filter layers correspond one-to-one to the sub-pixels.

10. The light-emitting diode chip according to any one of claims 1 to 8, further comprising an isolation structure, wherein the isolation structure is located between any two adjacent sub-pixels; The isolation structure includes a channel; or, the isolation structure includes a channel and an isolation material disposed in the channel; or, the isolation structure is an ion implantation layer. The light-emitting diode chip according to claim 10 , wherein: When at least part of the area on one side of the N light-emitting materials facing the P-type electrode is electrically connected to the P-type electrode, among the stacked light-emitting materials, the light-emitting wavelength of the light-emitting material close to the P-type electrode is greater than the light-emitting wavelength of the light-emitting material far from the P-type electrode.

12. The light-emitting diode chip according to claim 11, wherein: Among the N light-emitting materials, the light-emitting material with the smallest light-emitting wavelength is stacked on a side of the remaining light-emitting materials close to the N-type electrode. 13 . The light-emitting diode chip according to claim 11 , further comprising a hole blocking layer, wherein the hole blocking layer is at least disposed between the light-emitting material closest to the P-type electrode and the light-emitting material adjacent to the light-emitting material layer closest to the P-type electrode.

14. The light-emitting diode chip according to claim 13, wherein: The hole blocking layer is also located between any two adjacent light-emitting materials among the stacked light-emitting materials.

15. The light-emitting diode chip according to claim 10, further comprising an N-type semiconductor layer and a P-type semiconductor layer, wherein the N-type semiconductor and the P-type semiconductor are located on opposite sides of the light-emitting layer in a thickness direction, the N-type electrode is electrically connected to the light-emitting layer through the N-type semiconductor, and the P-type electrode is electrically connected to the light-emitting layer through the P-type semiconductor; When the N-type electrode includes M separate sub-N-type electrodes, the isolation structure is located between adjacent sub-N-type electrodes, and at least a portion of the isolation structure extends into the P-type semiconductor layer; When the P-type electrode includes M separate sub-P-type electrodes, the isolation structure is located between adjacent sub-P-type electrodes, and at least a portion of the isolation structure extends into the N-type semiconductor layer.

16. The light-emitting diode chip according to any one of claims 1 to 8, wherein: The N-type electrode includes M separate sub-N-type electrodes, the sides of the M sub-pixels close to the P-type electrode are electrically connected to the P-type electrode, and the sides of the M sub-pixels close to the N-type electrode are electrically connected to the M sub-N-type electrodes in a one-to-one correspondence; Alternatively, the P-type electrode includes M separate sub-P-type electrodes, the side of the M sub-pixels close to the N-type electrode is electrically connected to the N-type electrode, and the side of the M sub-pixels close to the P-type electrode is electrically connected to the M sub-P-type electrodes one by one.

17. The light-emitting diode chip according to any one of claims 1 to 8, wherein: The N-type electrode includes m mutually separate sub-N-type electrodes, the sides of the M sub-pixels close to the P-type electrode are electrically connected to the P-type electrode, and the sides of the M sub-pixels close to the N-type electrode are electrically connected to the m sub-N-type electrodes; m is less than M, and a portion of the sub-pixels share one sub-N-type electrode; Alternatively, the P-type electrode includes m separate sub-P-type electrodes, a side of the M sub-pixels close to the N-type electrode is electrically connected to the N-type electrode, and a side of the M sub-pixels close to the P-type electrode is electrically connected to the m sub-P-type electrodes; m is less than M, and a part of the sub-pixels shares one sub-P-type electrode.

18. The light-emitting diode chip according to any one of claims 1 to 8, wherein: The M sub-pixels form a pixel subgroup; Alternatively, the M sub-pixels form a plurality of pixel subgroups, and the plurality of pixel subgroups are arranged in an array in a direction intersecting the thickness direction of the light-emitting diode chip.

19. The light-emitting diode chip according to claim 18, wherein: Among the plurality of sub-pixels in the pixel subgroup, the light-emitting wavelengths of the plurality of sub-pixels are different from each other, or the plurality of sub-pixels include at least two sub-pixels with the same light-emitting wavelength.

20. The light-emitting diode chip according to any one of claims 1 to 8, wherein: M sub-pixels form a plurality of pixel units, and the plurality of pixel units are arranged in an array along a thickness direction intersecting the light-emitting diode chip; One pixel unit includes Y sub-pixels, and the Y sub-pixels include X colors; X is a positive integer greater than or equal to 3, and Y is a positive integer greater than or equal to X.

21. The light-emitting diode chip according to claim 20, wherein: When Y is greater than X, in one pixel unit, at least a portion of the sub-pixels have the same light emission wavelength.

22. The light-emitting diode chip according to any one of claims 20, wherein: All the sub-pixels in the same pixel unit are only used by the pixel unit to which they belong.

23. The light-emitting diode chip according to claim 20, wherein: One pixel unit has two sub-pixels shared with two adjacent pixel units. The number of all sub-pixels of a single light-emitting diode chip is M=a*(2X-2), where a is a positive integer greater than or equal to 1, and a is the number of pixel subgroups composed of all sub-pixels of a single light-emitting diode chip. 24 . The light-emitting diode chip according to claim 1 , further comprising a reflective layer, wherein the reflective layer is located on a backlight side of the light-emitting diode chip. 25 . The light-emitting diode chip according to claim 1 , further comprising a light-blocking layer, wherein the light-blocking layer is located on a light-emitting side of the light-emitting diode chip and between two adjacent sub-pixels.

26. The light-emitting diode chip according to any one of claims 1 to 8, wherein: The light-emitting diode chip satisfies at least one of the following requirements: The size of the light emitting diode chip is greater than or equal to 50 microns; The shape of the light emitting diode chip is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram and a polygon with more than four sides; The size of the sub-pixel ranges from 0.001 to 200 microns; The shape of the sub-pixel is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram and a polygon with more than four sides; The shapes of the different sub-pixels are the same or different; The sizes of different sub-pixels are equal or different.

27. The light-emitting diode chip according to any one of claims 1 to 8, further comprising a buffer layer, an N-type semiconductor layer, a P-type semiconductor layer, a current spreading layer, a reflective layer, and a first insulating layer; The buffer layer and the N-type semiconductor layer are stacked, the light-emitting layer is arranged on a side of the N-type semiconductor layer away from the buffer layer, and the P-type semiconductor layer is arranged on a side of the light-emitting layer away from the buffer layer; The current spreading layer contacts a side of the P-type semiconductor layer facing away from the buffer layer, the N-type electrode contacts the N-type semiconductor layer, and the P-type electrode contacts the P-type semiconductor layer and the current spreading layer; The first insulating layer is arranged on a side of the current spreading layer away from the buffer layer; The reflective layer is arranged on a side of the buffer layer away from the light-emitting layer, or the reflective layer is arranged on a side of the first insulating layer away from the buffer layer, and a second insulating layer is further arranged on the side of the reflective layer away from the buffer layer.

28. The light-emitting diode chip according to claim 27, further comprising a substrate, wherein the substrate is disposed on a side of the buffer layer away from the light-emitting layer; When the reflective layer is disposed on a side of the buffer layer away from the light-emitting layer, the reflective layer is disposed on a side of the substrate away from the buffer layer.

29. The light-emitting diode chip according to any one of claims 1 to 8, further comprising a bonding substrate, a binding layer, an N-type semiconductor layer, a P-type semiconductor layer, and a reflective layer; The bonding substrate and the binding layer are sequentially arranged on the P-type electrode, and the P-type semiconductor layer is arranged on a side of the binding layer away from the bonding substrate and in contact with the binding layer; The light-emitting layer is provided on a side of the P-type semiconductor layer away from the bonding substrate, the N-type semiconductor layer is provided on a side of the light-emitting layer away from the bonding substrate, and the N-type electrode contacts the side of the N-type semiconductor layer away from the bonding substrate; The reflective layer is arranged on a side of the P-type semiconductor layer close to the bonding substrate. 30 . The light-emitting diode chip according to claim 1 , further comprising a color conversion layer, wherein the color conversion layer is disposed on a portion of the light-emitting side of the light-emitting diode chip and corresponds to at least a portion of the sub-pixel.

31. A light emitting diode chip group, comprising a plurality of light emitting diode chips according to any one of claims 1 to 30, wherein the plurality of light emitting diode chips are arranged in an array along a thickness direction intersecting the light emitting diode chips.

32. The light emitting diode chip set according to claim 31, wherein: In two adjacent LED chips, the entire area of ​​the sub-pixel of one LED chip and the entire area of ​​the sub-pixel of the other LED chip together constitute one pixel unit.

33. The light emitting diode chip set according to claim 31, wherein: In two adjacent LED chips, a partial area of ​​a sub-pixel of one LED chip and a partial area of ​​a sub-pixel of the other LED chip together constitute a pixel unit.

34. The light-emitting diode chip set according to any one of claims 31 to 33, wherein: The two adjacent light-emitting diode chips are both irregular in shape; one of the two adjacent light-emitting diodes has a protruding area, and the other has a concave area; the protruding area and the concave area are adapted in shape and fit together.

35. The light-emitting diode chip set according to any one of claims 31 to 33, wherein: The plurality of light-emitting diode chips form a plurality of light-emitting diode chip groups arranged in an array and a plurality of pixel units arranged in an array; In the same LED chip, the spacing between adjacent sub-pixels is d1; the spacing between adjacent LED chip groups is d2; the spacing between adjacent pixel units is d3; and the spacing between adjacent LED chips is d4. d1, d2, d3 and d4 are all equal, or d1, d2, d3 and d4 are not equal to each other.

36. A display module comprising a driving backplane and the light-emitting diode chipset according to any one of claims 31 to 35, wherein the light-emitting diode chipset is arranged on the driving backplane and electrically connected to the driving backplane.

37. The display module according to claim 36, wherein: There are multiple light emitting diode chip groups; The plurality of light emitting diode chip groups are arranged in an array on the driving backplane; Alternatively, the driving backplane includes a driving substrate and a plurality of driving units, one driving unit is electrically connected to one light emitting diode chip group, and the plurality of driving units are electrically connected to the driving substrate.

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