Light-emitting diode chip and chip group thereof, and display module

Abstract

The present application relates to the technical field of semiconductors. Provided are a light-emitting diode chip and a chip group thereof, and a display module. The light-emitting diode chip comprises an N-type electrode, a P-type electrode and a light-emitting layer. The light-emitting layer comprises N light-emitting materials with different light-emitting wavelengths, wherein at least one of the N light-emitting materials is in a stacked arrangement together with the remaining light-emitting materials, and light emitted from the light-emitting material is used for exciting the remaining light-emitting materials to emit light; the N light-emitting materials are configured to form M sub-pixels arranged side by side, and the light-emitting wavelengths of at least some sub-pixels are unequal; and both N and M are positive integers greater than or equal to 3.

Description

Light-emitting diode chip and chipset, display module

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on March 20, 2024, with application number 202410327711.3, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, for example, to a light emitting diode chip and its chipset, and a display module. Background Art

[0003] In semiconductor lighting technology, light emitting diodes (LEDs), as light-emitting devices that convert electrical energy into light energy, have the advantages of energy saving and environmental protection, long service life and high luminous efficiency. They are widely used in many fields such as indication, display, decoration, and lighting.

[0004] In the display field, ultra-high-density display products based on micro-LEDs (micro LEDs) typically use three independent chips to form a pixel unit, that is, three single-chip, single-color sub-pixels to form a pixel unit. The large number of chips in micro LEDs and their small size require a mass transfer process in the micro LED manufacturing process.

[0005] However, the above-mentioned micro LED manufacturing process has problems such as high process difficulty, low yield rate and high cost. Summary of the Invention

[0006] The present application provides a light-emitting diode chip, a chipset thereof, and a display module, which can flexibly adjust the size of the light-emitting diode chip and the full-color chipset, reduce the number of transfers and the difficulty of transfers in mass transfer, and thus overcome the process, yield and cost problems represented by mass transfer in ultra-high-density pixel display products.

[0007] In a first aspect, the present application provides a light-emitting diode chip comprising an N-type electrode, a P-type electrode, and a light-emitting layer disposed between the N-type electrode and the P-type electrode; the light-emitting layer is electrically connected to the N-type electrode and the P-type electrode, respectively.

[0008] The light-emitting layer includes N light-emitting materials, and the light-emitting wavelengths of the N light-emitting materials are different; along the thickness direction of the light-emitting diode chip, at least one of the N light-emitting materials is stacked with the other light-emitting materials.

[0009] Among the stacked light-emitting materials, at least one light-emitting material is located on a side of the remaining light-emitting materials close to the P-type electrode, and the light emitted by the light-emitting material is used to excite the remaining light-emitting materials to emit light.

[0010] N luminescent materials are arranged to form M sub-pixels arranged side by side, and among the M sub-pixels, at least some of the sub-pixels have different luminous wavelengths; wherein N and M are both positive integers greater than or equal to 3.

[0011] In a second aspect, the present application provides a light-emitting diode chip set, comprising a plurality of the above-mentioned light-emitting diode chips, wherein the plurality of light-emitting diode chips are arranged in an array along a thickness direction intersecting the light-emitting diode chips.

[0012] In a third aspect, the present application provides a display module, including a display module, a driving backplane and the above-mentioned light-emitting diode chipset, wherein the light-emitting diode chipset is arranged on the driving backplane and electrically connected to the driving backplane. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG1 is a top view of a first light-emitting diode chip provided in an embodiment of the present application;

[0014] FIG2 is a cross-sectional view of a first light-emitting diode chip provided in an embodiment of the present application;

[0015] FIG3 is a top view of a second light-emitting diode chip provided in an embodiment of the present application;

[0016] FIG4 is a cross-sectional view of a second light-emitting diode chip provided in an embodiment of the present application;

[0017] FIG5 is a top view of a third light-emitting diode chip provided in an embodiment of the present application;

[0018] FIG6 is a cross-sectional view of a third light-emitting diode chip provided in an embodiment of the present application;

[0019] FIG7 is a cross-sectional view of a fourth light-emitting diode chip provided in an embodiment of the present application;

[0020] FIG8 is a cross-sectional view of a fifth light-emitting diode chip provided in an embodiment of the present application;

[0021] FIG9 is a cross-sectional view of a sixth light-emitting diode chip provided in an embodiment of the present application;

[0022] FIG10 is a cross-sectional view of a seventh light-emitting diode chip provided in an embodiment of the present application;

[0023] FIG11 is a cross-sectional view of an eighth light-emitting diode chip provided in an embodiment of the present application;

[0024] FIG12 is a cross-sectional view of a ninth light-emitting diode chip provided in an embodiment of the present application;

[0025] FIG13 is a cross-sectional view of a tenth light-emitting diode chip provided in an embodiment of the present application;

[0026] FIG14 is a cross-sectional view of an eleventh light-emitting diode chip provided in an embodiment of the present application;

[0027] FIG15 is a cross-sectional view of a twelfth light-emitting diode chip provided in an embodiment of the present application;

[0028] FIG16 is a cross-sectional view of a thirteenth light-emitting diode chip provided in an embodiment of the present application;

[0029] FIG17 is a cross-sectional view of a fourteenth light-emitting diode chip provided in an embodiment of the present application;

[0030] FIG18 is a cross-sectional view of a fifteenth light-emitting diode chip provided in an embodiment of the present application;

[0031] FIG19 is a cross-sectional view of a sixteenth light-emitting diode chip provided in an embodiment of the present application;

[0032] FIG20 is a cross-sectional view of a seventeenth light-emitting diode chip provided in an embodiment of the present application;

[0033] FIG21 is a cross-sectional view of an eighteenth light-emitting diode chip provided in an embodiment of the present application;

[0034] FIG22 is a cross-sectional view of a nineteenth light-emitting diode chip provided in an embodiment of the present application;

[0035] FIG23 is a cross-sectional view of the twentieth light-emitting diode chip provided in an embodiment of the present application;

[0036] FIG24 is a cross-sectional view of a twenty-first light-emitting diode chip provided in an embodiment of the present application;

[0037] FIG25 is a cross-sectional view of a twenty-second light-emitting diode chip provided in an embodiment of the present application;

[0038] FIG26 is a cross-sectional view of a twenty-third light-emitting diode chip provided in an embodiment of the present application;

[0039] FIG27 is a schematic diagram showing a structure in which a portion of sub-pixels of a light-emitting diode chip share an N-type electrode according to an embodiment of the present application;

[0040] FIG28 is a schematic diagram showing a structure in which a portion of sub-pixels of a light-emitting diode chip share a P-type electrode according to an embodiment of the present application;

[0041] FIG29 is a top view of a first light-emitting diode chip provided in an embodiment of the present application;

[0042] FIG30 is a top view of a second light-emitting diode chip provided in an embodiment of the present application;

[0043] FIG31 is a top view of a third light-emitting diode chip provided in an embodiment of the present application;

[0044] FIG32 is a top view of a fourth light-emitting diode chip provided in an embodiment of the present application;

[0045] FIG33 is a top view of a fifth light-emitting diode chip provided in an embodiment of the present application;

[0046] FIG34 is a top view of a sixth light-emitting diode chip provided in an embodiment of the present application;

[0047] FIG35 is a top view of a seventh light-emitting diode chip provided in an embodiment of the present application;

[0048] FIG36 is a top view of an eighth light-emitting diode chip provided in an embodiment of the present application;

[0049] FIG37 is a top view of a ninth light-emitting diode chip provided in an embodiment of the present application;

[0050] FIG38 is a top view of a tenth light-emitting diode chip provided in an embodiment of the present application;

[0051] FIG39 is a top view of an eleventh light-emitting diode chip provided in an embodiment of the present application;

[0052] FIG40 is a top view of a twelfth light-emitting diode chip provided in an embodiment of the present application;

[0053] FIG41 is a top view of a thirteenth light-emitting diode chip provided in an embodiment of the present application;

[0054] FIG42 is a top view of a fourteenth light-emitting diode chip provided in an embodiment of the present application;

[0055] FIG43 is a schematic diagram of a first integrated structure of a light-emitting diode chip provided in an embodiment of the present application;

[0056] FIG44 is a schematic diagram of a second package structure of a light-emitting diode chip provided in an embodiment of the present application;

[0057] FIG45 is a schematic diagram of a third package structure of a light-emitting diode chip provided in an embodiment of the present application;

[0058] FIG46 is a schematic diagram of a fourth package structure of a light-emitting diode chip provided in an embodiment of the present application;

[0059] FIG47 is a schematic flow chart of a first method for preparing a light-emitting diode chip according to an embodiment of the present application;

[0060] FIG48 is a schematic flow chart of a second method for preparing a light-emitting diode chip according to an embodiment of the present application;

[0061] FIG49 is a schematic flow chart of a third method for preparing a light-emitting diode chip according to an embodiment of the present application;

[0062] FIG50 is a schematic flow chart of a fourth method for preparing a light-emitting diode chip according to an embodiment of the present application;

[0063] FIG51 is a schematic flow chart of a fifth method for preparing a light-emitting diode chip according to an embodiment of the present application;

[0064] FIG52 is a dimensional diagram of a light-emitting diode chipset provided in an embodiment of the present application;

[0065] FIG53 is a top view of a first light-emitting diode chip group provided in an embodiment of the present application;

[0066] FIG54 is a top view of a second light-emitting diode chip group provided in an embodiment of the present application;

[0067] FIG55 is a top view of a third light-emitting diode chip group provided in an embodiment of the present application;

[0068] FIG56 is a top view of a fourth light-emitting diode chip group provided in an embodiment of the present application;

[0069] FIG57 is a top view of a fifth light-emitting diode chip group provided in an embodiment of the present application;

[0070] FIG58 is a top view of a sixth light-emitting diode chip group provided in an embodiment of the present application;

[0071] FIG59 is a top view of a seventh light-emitting diode chip group provided in an embodiment of the present application;

[0072] FIG60 is a top view of an eighth light-emitting diode chip group provided in an embodiment of the present application;

[0073] FIG61 is a top view of a ninth light-emitting diode chip group provided in an embodiment of the present application;

[0074] FIG62 is a top view of a tenth light-emitting diode chip group provided in an embodiment of the present application;

[0075] FIG63 is a top view of an eleventh light-emitting diode chip group provided in an embodiment of the present application;

[0076] FIG64 is a top view of a twelfth light-emitting diode chip group provided in an embodiment of the present application;

[0077] FIG65 is a schematic diagram of a first structure of a display module provided in an embodiment of the present application;

[0078] FIG66 is a second structural schematic diagram of the display module provided in an embodiment of the present application.

[0079] Description of reference numerals: 100, substrate; 101, buffer layer; 102, N-type electrode; 103, N-type semiconductor layer; 104, P Type electrode; 105, P-type semiconductor layer; 106, current spreading layer; 107, reflective layer; 108, first insulating layer; 109, second insulating layer; 110, bonding substrate; 111, binding layer; 112, color conversion layer; 113, light-emitting layer; 113-1, first light-emitting material; 113-2, second light-emitting material; 113-3, third light-emitting material; 113-n-1, n-1th light-emitting material; 113-n, nth light-emitting material; 114, isolation structure; 114a, isolation material; 115, hole blocking layer; 116, light-blocking layer; 117a, first filter layer; 117b, second filter layer; 117c, third filter layer; 200, driving backplane; 201, driving substrate; 202, driving unit. DETAILED DESCRIPTION

[0080] In LED display products, three single-core monochrome single-pixel chips are usually used to form a pixel unit. The size of a single chip in ultra-high-density display products represented by micro LED is relatively small, and the number of chips that make up the display product is relatively large. In the manufacturing process of display products, micro LED chips need to be grown on wafers, and then transferred to a specific substrate through mass transfer technology to complete the binding assembly. In the mass transfer process, due to the small size and large number of chips, the transfer operation is more difficult, the number of operations is numerous, and the operation alignment requirements on the substrate are high. As a result, the manufacturing process of micro LED display products is more difficult, the yield is lower, the production cycle is longer, and the cost is higher.

[0081] In related technologies, several chips are packaged together in LED display products using the MIP (Micro LED in Package) packaging process to form an integrated chipset capable of emitting multiple wavelengths. Traditional MIP packaging is suitable for LED display products with pixel sizes greater than 0.3 mm. Limited by the capabilities of mass transfer technology, the MIP packaging process requires a larger single-core, monochrome, single-sub-pixel chip, meaning a larger sub-pixel size. A single chipset typically represents a single pixel unit, and a large number of chips and chipsets are used in applications.

[0082] The light-emitting diode chip, chipset, and display module provided in this application are constructed by placing a light-emitting layer between an N-type electrode and a P-type electrode, electrically conducting the light-emitting layer. This allows electrons provided by the N-type electrode to combine with holes provided by the P-type electrode in the light-emitting layer, thereby exciting the light-emitting material in the light-emitting layer to emit light. The light-emitting layer includes N light-emitting materials, each of which has different emission wavelengths. The N light-emitting materials are arranged to form M sub-pixels arranged side by side, each of which has different emission wavelengths; wherein N and M are both positive integers greater than or equal to 3. Thus, the present application adopts a single-core, multi-color, multi-sub-pixel arrangement, that is, using multiple sub-pixels to form pixel sub-groups, and forming a full-color pixel unit through the arrangement of the pixel sub-groups, thereby forming a full-color chip set. In this application, a portion of the sub-pixels in a single chip can form a complete full-color pixel unit, making the chip more convenient to use. A portion of the sub-pixels in multiple chips can also be pieced together to form a complete full-color pixel unit. The chip's splicing method is relatively flexible and can meet diverse display needs.

[0083] At least one of the N light-emitting materials is stacked with the remaining light-emitting materials along the thickness direction of the light-emitting diode chip. In this way, among the stacked light-emitting materials, at least one light-emitting material is located on the side of the remaining light-emitting materials close to the P-type electrode, and the light emitted by the light-emitting material is used to excite the remaining light-emitting materials to emit light. In this way, both electroluminescence and photoluminescence light-emitting mechanisms can be integrated into the light-emitting diode chip. The present application can flexibly adjust the size of the light-emitting diode chip and the chipset, reduce the difficulty of the transfer operation in the mass transfer process, and reduce the number of mass transfers, thereby overcoming the process, yield and cost issues represented by mass transfer in ultra-high-density pixel display products.

[0084] Compared to the related art, which integrates several chips together to form an integrated chipset that emits multiple wavelengths, the related art needs to overcome the process difficulties of integrating multiple chips, resulting in greater process difficulty, lower yield, and higher cost. This application directly obtains multi-color and multi-sub-pixels in a single LED chip, which is simpler in process, less technically difficult, and lower in cost.

[0085] Furthermore, by adopting the single-core multi-color multi-sub-pixel LED chip or LED chip group of the present application, under the conditions of the same light-emitting area and the same pixel density (Pixels Per Inch, abbreviated as PPI), the size of the LED chip can be flexibly adjusted while ensuring a small sub-pixel size, and the number of LED chips can be greatly reduced. This can overcome the problems of difficult preparation process, low product yield and high preparation cost, and help promote the mass production of mini LED and micro LED as soon as possible.

[0086] The single-core multi-color multi-sub-pixel chip in the present application contains n full-color pixel units, where n is a positive integer greater than or equal to 1. The single-core multi-color multi-sub-pixel chip can be directly combined with the backplane, and a single chip can achieve the effect of n MIP packages. When the single-core multi-color multi-sub-pixel light-emitting diode chip of the present application is used to form a full-color integrated chipset (for example, three 3*n combination chips form a chipset), n*3 pixel units can be obtained. When combined with the backplane, the chipset used is 1 / 3n of the traditional MIP package, which greatly reduces the preparation time, reduces the process and raw material costs, and greatly improves the yield. Furthermore, the pixel size applicable to the full-color integrated package of the present application can be flexibly adjusted and can be much smaller than the pixel size applicable to the traditional MIP process.

[0087] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described in more detail below in conjunction with the drawings in the preferred embodiments of the present application. In the drawings, the same or similar reference numerals throughout represent the same or similar parts or parts with the same or similar functions. The described embodiments are part of the embodiments of the present application, not all of the embodiments. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. The embodiments of the present application are described in detail below in conjunction with the drawings.

[0088] In this application, some nouns can be understood as follows:

[0089] Sub-pixel (SP): A single blue light pixel, a single green light pixel, or a single red light pixel is called a sub-pixel. In this patent, a sub-pixel can also be a single arbitrary wavelength.

[0090] Pixel subgroup (PSG): A group of sub-pixels.

[0091] Pixel unit (PU): A unit that includes blue, green, and red primary colors, or includes three or more other sub-pixels of different wavelengths that can constitute white light.

[0092] Single-core monochrome single-sub-pixel chip: A single light-emitting diode chip can only emit one wavelength of light and contains only one sub-pixel, such as one blue light sub-pixel, one green light sub-pixel, or one red light sub-pixel.

[0093] Single-chip monochrome multi-sub-pixel chip: A single chip can only emit one wavelength of light, but contains more than or equal to two sub-pixels, such as two red sub-pixels, three red sub-pixels, or more red sub-pixels.

[0094] Single-core multi-color multi-sub-pixel chip; a single chip can emit multiple different wavelengths of light and contains greater than or equal to 3 sub-pixels, such as 1 red sub-pixel + 1 green sub-pixel + 1 blue sub-pixel, 2 red sub-pixels + 2 green sub-pixels + 2 blue sub-pixels, multiple blue sub-pixels + multiple red sub-pixels + multiple green sub-pixels.

[0095] Light-emitting diode chip (C): A solid-state semiconductor device with a light-emitting layer between a P-type electrode and an N-type electrode. Hereinafter referred to as "chip."

[0096] Light-emitting diode chipset (CG): It is composed of two or more single-core dual (single) color multi-sub-pixel chips, containing one or more pixel units.

[0097] Display mini block (DMB): A display device formed by electrically connecting a light-emitting diode chipset and a driver backplane.

[0098] In a first aspect, as shown in Figures 1-26, the present application provides a light-emitting diode chip. The chip includes an N-type electrode 102, a P-type electrode 104, and a light-emitting layer 113 disposed between the N-type electrode 102 and the P-type electrode 104; the light-emitting layer 113 is electrically connected to the N-type electrode 102 and the P-type electrode 104 respectively;

[0099] The light-emitting layer 113 includes N light-emitting materials, each of which has different emission wavelengths. At least one of the N light-emitting materials is stacked with the remaining light-emitting materials along the thickness direction of the chip.

[0100] Among the stacked light-emitting materials, at least one light-emitting material is located on a side of the remaining light-emitting materials close to the P-type electrode 104, and the light emitted by the light-emitting material is used to excite the remaining light-emitting materials to emit light;

[0101] N luminescent materials are arranged to form M sub-pixels arranged side by side, and at least some of the M sub-pixels have different luminescent wavelengths; wherein N and M are both positive integers greater than or equal to 3.

[0102] It should be noted that an electric field is formed between the N-type electrode 102 and the P-type electrode 104, and the light-emitting layer 113 is disposed between the N-type electrode 102 and the P-type electrode 104. This can be understood as the light-emitting layer 113 being located in the electric field. Referring to Figures 2, 4, 6, and 7-26, in the thickness direction of the chip, the entire light-emitting layer 113 or a portion of the light-emitting layer 113 is located between the N-type electrode 102 and the P-type electrode 104. The light-emitting layer 113 is electrically conductive with the N-type electrode 102 and the P-type electrode 104, respectively. This can mean that the light-emitting layer 113 is in contact with and conductive with the N-type electrode 102 and the P-type electrode 104, respectively, or that the light-emitting layer 113 is electrically conductive with the N-type electrode 102 through the N-type semiconductor layer 103, and is electrically conductive with the P-type electrode 104 through the P-type semiconductor layer 105.

[0103] Wherein, the light-emitting layer 113 includes N light-emitting materials, where N is a positive integer greater than or equal to 3. In the subsequent text, multiple light-emitting materials and N light-emitting materials have the same meaning. For example, on the basis of satisfying that the N light-emitting materials are unequal, the N light-emitting materials may include a first light-emitting material 113-1 that emits blue light, a second light-emitting material 113-2 that emits green light, a third light-emitting material 113-3 that emits red light, an n-1th light-emitting material 113-n-1 that emits purple light, and an nth light-emitting material 113-n that emits other wavelengths that are not equal to the above-mentioned light wavelengths. In other embodiments, the light-emitting wavelengths of the above-mentioned light-emitting materials can also be adjusted, and this application does not limit this. Wherein, n is a positive integer greater than or equal to 1 and less than or equal to N.

[0104] Among the N light-emitting materials, at least one light-emitting material is stacked on the side of the remaining light-emitting materials close to the P-type electrode 104 along the thickness direction of the chip. Among the stacked light-emitting materials, the light emitted by the at least one light-emitting material can be used to excite the remaining light-emitting materials to emit light. Referring to Figures 2, 4 and 6, the first light-emitting material 113-1 is stacked on the side of the second light-emitting material 113-2 to the n-th light-emitting material 113-n close to the P-type electrode 104. The light emitted by the first light-emitting material 113-1 can be used to excite the second light-emitting material 113-2 to the n-th light-emitting material 113-n to emit light. The light-emitting mechanism of the first light-emitting material 113-1 is electroluminescence, and the light-emitting mechanism of the second light-emitting material 113-2 to the n-th light-emitting material 113-n is photoluminescence.

[0105] The above-mentioned luminescent materials can be used to form M sub-pixels arranged side by side on the chip, where M is also a positive integer greater than or equal to 3. Referring to Figures 1, 3 and 5, the chip includes a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3...an m-th sub-pixel SPm. Wherein, m is a positive integer greater than or equal to 1 and less than or equal to M. For example, the first luminescent material 113-1 corresponds to the first sub-pixel SP1, and the first sub-pixel SP1 is a blue light sub-pixel. The second luminescent material 113-2 corresponds to the second sub-pixel SP2, and the second sub-pixel SP2 is a green light sub-pixel. The third luminescent material 113-3 corresponds to the third sub-pixel SP3, and the third sub-pixel SP3 is a red light sub-pixel.

[0106] In this application, "side by side" or "arranged side by side" can refer to being arranged perpendicular to the thickness of the chip, i.e., located at the same thickness of the chip. It can also refer to being on the same layer of the chip, but being offset in the thickness direction of the chip can still be considered side by side or arranged side by side.

[0107] Taking a single-core three-color three-sub-pixel as an example, the chip can include a first sub-pixel, a second sub-pixel and a third sub-pixel with different light-emitting wavelengths. The first sub-pixel, the second sub-pixel and the third sub-pixel are any three of a plurality of wavelength sub-pixels such as red light sub-pixel, green light sub-pixel, blue light sub-pixel, purple light sub-pixel and ultraviolet light sub-pixel.

[0108] This application combines multiple sub-pixels with different luminous wavelengths into a light-emitting diode chip, that is, adopts a single-chip, multi-color, and multi-sub-pixel arrangement. Compared with the related art that uses a single sub-pixel to form a chip, this application can flexibly adjust the size of the light-emitting diode chip, reducing the transfer difficulty and alignment difficulty in mass transfer operations. In addition, it can effectively reduce the number of light-emitting diode chips required for display products with the same luminous area and the same pixel density, thereby reducing the complexity of mass transfer operations and reducing production costs. This can also improve the product yield of ultra-high-density pixel displays.

[0109] In some embodiments, M is greater than or equal to N. Referring to Figures 1-6 , M can be equal to N, meaning that one luminescent material forms one sub-pixel. M can also be greater than N, meaning that one luminescent material can form two or more sub-pixels with equal luminescent wavelengths during the manufacturing process.

[0110] In the chip of the present application, among the stacked light-emitting materials, the light-emitting wavelength of the light-emitting material close to the P-type electrode 104 is smaller than the light-emitting wavelength of the light-emitting material far away from the P-type electrode 104. During the operation of the chip, after the N-type electrode 102 is energized, it can provide electrons, and after the P-type electrode 104 is energized, it can provide holes. Among them, holes and electrons can migrate to the corresponding positions of each light-emitting material, and after the holes and electrons recombine, they can emit light of the corresponding wavelength of the light-emitting material. Based on the fact that the extension length of the hole is smaller than the extension length of the electron, the diffusion length of the hole determines the binding position of the hole and the electron. The light-emitting material with a smaller light-emitting wavelength is arranged closer to the P-type electrode 104 side relative to the light-emitting material with a larger light-emitting wavelength. In this way, holes can be enabled to migrate to the light-emitting material with a smaller light-emitting wavelength, thereby ensuring that the light-emitting material emits light. The light emitted by the light-emitting material can further excite the light-emitting material with a smaller light-emitting wavelength, which is closer to the N-type electrode 102 side, to emit light.

[0111] If so, the light-emitting material with a smaller emission wavelength is placed close to the N-type electrode 102, and the light-emitting material with a larger emission wavelength is placed close to the P-type electrode 104. In this way, there is a possibility that holes cannot migrate to the location of the light-emitting material with a smaller emission wavelength, resulting in the light-emitting material being unable to emit light. The light emitted by the light-emitting material with a larger emission wavelength cannot excite the light-emitting material with a smaller emission wavelength to emit light, affecting the light-emitting performance of the chip. Therefore, the present application places the light-emitting material with a smaller emission wavelength close to the P-type electrode 104, so that the light-emitting material of the chip can emit light normally, thereby ensuring the light-emitting performance of the chip.

[0112] In the chip of the present application, the luminescent material with the shortest wavelength among the N luminescent materials is stacked on the side of the remaining luminescent materials near the P-type electrode 104. This ensures that when the chip is operating, electrons and holes can combine at the location of the luminescent material with the shortest wavelength, thereby ensuring that the luminescent material can achieve electroluminescence. Furthermore, the luminescent material with the shortest wavelength can also excite the remaining luminescent materials to produce photoluminescence.

[0113] In the chip of the present application, as shown in FIG. 2 , 4 , 6 , 7 and FIG. 8 to 16 , at least a portion of each light-emitting material is electrically connected to the N-type electrode 102 .

[0114] 2 , 4 , 6 , 7 and 8 to 10 , among the multiple luminescent materials, except for the luminescent material with the smallest luminescent wavelength, the remaining luminescent materials are arranged side by side;

[0115] The light-emitting material with the smallest emission wavelength includes a first portion and a second portion connected to each other, with the first portion stacked with the remaining light-emitting materials; a side of the first portion close to the P-type electrode 104 is electrically connected to the P-type electrode 104, and different positions of the side of the first portion close to the N-type electrode 102 correspond to different light-emitting materials arranged side by side;

[0116] The second part is arranged side by side with the remaining light-emitting materials, and the second part and the remaining light-emitting materials are electrically connected to the N-type electrode 102 on one side thereof; the multiple light-emitting materials arranged side by side correspond to multiple sub-pixels respectively.

[0117] It should be noted that the luminescent material with the shortest emission wavelength may be the first luminescent material 113-1, and the remaining luminescent materials may be the second luminescent material 113-2, the third luminescent material 113-3, ..., and the nth luminescent material 113-n. The first portion of the first luminescent material 113-1 may extend perpendicular to the thickness of the chip, and the second portion may extend along the thickness of the chip. The first portion may be electrically conductive with the P-type electrode 104 and layered on the side of the second luminescent material 113-2, the third luminescent material 113-3, ..., and the nth luminescent material 113-n that is closest to the P-type electrode 104. The second portion may be arranged side by side with the remaining luminescent materials.

[0118] The first light-emitting material 113 - 1 forms a first sub-pixel, the second light-emitting material 113 - 2 forms a second sub-pixel, the third light-emitting material 113 - 3 forms a third sub-pixel, and the nth light-emitting material 113 - n forms an mth sub-pixel.

[0119] In some embodiments, the same luminescent material can form multiple sub-pixels. For example, the first luminescent material 113-1 can form two sub-pixels with the same luminescent wavelength.

[0120] When the chip is operating, if the thickness of the first portion of the first luminescent material 113-1 is relatively small, holes and electrons can combine within the first luminescent material 113-1, thereby generating electroluminescence from the first luminescent material 113-1. Holes can also pass through the first luminescent material 113-1 and enter the second luminescent material 113-2, the third luminescent material 113-3, and so on, the nth luminescent material 113-n, thereby generating electroluminescence from the second luminescent material 113-2, the third luminescent material 113-3, and so on, the nth luminescent material 113-n. Of course, the light emitted by the first luminescent material 113-1 can also excite the second luminescent material 113-2, the third luminescent material 113-3, and so on, the nth luminescent material 113-n, generating photoluminescence from the second luminescent material 113-2, the third luminescent material 113-3, and so on, the nth luminescent material 113-n.

[0121] However, when the thickness of the first part of the first light-emitting material 113-1 is large, holes cannot pass through the first light-emitting material 113-1 and enter the second light-emitting material 113-2, the third light-emitting material 113-3...the nth light-emitting material 113-n, so that the second light-emitting material 113-2, the third light-emitting material 113-3...the nth light-emitting material 113-n can only be excited to emit light by the light emitted by the first light-emitting material 113-1.

[0122] As shown in FIG7 , the chip of the present application further includes a hole blocking layer 115. Hole blocking layer 115 is disposed at least between the light-emitting material closest to the P-type electrode 104 and the light-emitting material stacked adjacent to the light-emitting material closest to the P-type electrode 104. Specifically, hole blocking layer 115 can be disposed between the first light-emitting material 113-1 and the second, third, and nth light-emitting materials 113-2, 113-3, and 113-n light-emitting materials stacked with the first light-emitting material 113-1. This prevents holes from passing through hole blocking layer 115 and entering the second, third, and nth light-emitting materials 113-2, 113-3, and 113-n light-emitting materials. As a result, the second, third, and nth light-emitting materials 113-2, 113-3, and 113-n light-emitting materials can only emit light from the first light-emitting material 113-1.

[0123] As shown in Figures 8-10 , the chip of the present application also includes a reflective layer 107, which is located on the backlight side of the LED chip. The reflective layer 107 of the present application is disposed on the backlight side to ensure that light is emitted from the light-emitting side. The reflective layer 107 shown in the figures is located on the side of the N-type electrode 102 facing away from the P-type electrode 104. The side of the P-type electrode 104 facing away from the N-type electrode 102 forms the light-emitting side of the LED chip. The reflective layer 107 can be a metal layer or a Bragg reflector 107.

[0124] Continuing with Figures 8-10 , the chip of the present application also includes multiple filter layers that filter different wavelengths. These filter layers are arranged side by side on the light-emitting side of the LED chip, with each filter layer corresponding to a sub-pixel. The filter layers are disposed on the side of the P-type electrode 104 facing away from the N-type electrode 102. The filter layers include a second filter layer CF2, a third filter layer CF3, and so on and so forth. The second filter layer CF2 corresponds to the second sub-pixel formed by the second luminescent material 113-2, the third filter layer CF3 corresponds to the third sub-pixel formed by the third luminescent material 113-3, and so on. The nth filter layer CFn corresponds to the mth sub-pixel formed by the nth luminescent material 113-n.

[0125] It should be noted that the filter layer can be a color filter or a Bragg reflector (or a distributed Bragg reflector, DBR). The Bragg reflector can also filter the wavelength of the light passing through, thereby emitting light with different wavelengths. The Bragg reflector can be an alternating stack of two materials: aluminum nitrogen and gallium nitrogen, or an alternating stack of two materials: titanium oxide and silicon oxide, or an alternating stack of two materials: silicon oxide and silicon nitride. Optionally, the thickness of the Bragg reflector is 2-6 microns. In other embodiments, the thickness value can be adjusted as needed, and this application does not impose any restrictions on it.

[0126] In the chip of the present application, the driving modes of the multiple sub-pixels of the chip can be independent driving and synchronous driving.

[0127] 1 , the first sub-pixel, the second sub-pixel, the third sub-pixel ... the mth sub-pixel share an N-type electrode 102 and a P-type electrode 104. When the N-type electrode 102 and the P-type electrode 104 are energized, each sub-pixel can emit light synchronously, and the driving mode is synchronous driving.

[0128] 3 and 4 , the P-type electrode 104 includes M separate sub-P-type electrodes (P1, P2, P3...Pm), one side of the M sub-pixels close to the N-type electrode 102 is electrically connected to the N-type electrode 102, and one side of the M sub-pixels close to the P-type electrode 104 is electrically connected to the M sub-P-type electrodes one by one.

[0129] It should be noted that, as shown in Figures 3 and 4 , P-type electrode 104 includes a first sub-P-type electrode, a second sub-P-type electrode, a third sub-P-type electrode, and so on, through the mth sub-P-type electrode, each of which is electrically conductive to the first sub-pixel, the second sub-pixel, the third sub-pixel, and so on. Each sub-P-type electrode can independently control its power state, allowing each corresponding sub-pixel to emit light independently, with the drive mode being independent.

[0130] 5 and 6 , the N-type electrode 102 includes M separate sub-N-type electrodes (N1, N2, N3…Nm), one side of the M sub-pixels close to the P-type electrode 104 is electrically connected to the P-type electrode 104, and one side of the M sub-pixels close to the N-type electrode 102 is electrically connected to the M sub-N-type electrodes one by one.

[0131] It should be noted that, as shown in Figures 5 and 6, N-type electrode 102 includes a first sub-N-type electrode, a second sub-N-type electrode, a third sub-N-type electrode, and so on, to the mth sub-N-type electrode, which are electrically connected to the first sub-pixel, the second sub-pixel, the third sub-pixel, and so on, respectively. Each sub-N-type electrode can independently control its power state, so that each corresponding sub-pixel can emit light independently, and the driving mode is independent drive.

[0132] As shown in Figures 3-7, 9, and 10, the chip of the present application also includes an isolation structure 114, which is located between any two adjacent sub-pixels. Isolation structure 114 is located between the second portion, the second luminescent material 113-2, the third luminescent material 113-3, and so on, the nth luminescent material 113-n, which are arranged side by side. Because different regions in the first portion correspond to the second luminescent material 113-2, the third luminescent material 113-3, and so on, the nth luminescent material 113-n, the isolation structure 114 can also be located between different regions in the first portion.

[0133] For example, as shown in FIG. 10 , when the N-type electrode 102 includes M separate sub-N-type electrodes, the isolation structure 114 may also be located between adjacent sub-N-type electrodes.

[0134] For example, as shown in FIG. 4 , when the P-type electrode 104 includes M separate sub-P-type electrodes, the isolation structure 114 may also be located between adjacent sub-P-type electrodes.

[0135] For example, as shown in FIG. 10 , when the multiple reflective layers 107 are respectively located on the side of the multiple discrete sub-N-type electrodes away from the P-type electrode 104 in a one-to-one correspondence, the isolation structure 114 may also be located between adjacent reflective layers 107 .

[0136] In the present application, the isolation structure 114 may only include a channel (CN), that is, the isolation material 114a may not be filled in the channel. The channel can spatially isolate the isolated structure. As shown in Figures 7 and 8, the electrically insulating isolation material 114a filled in the channel CN ​​(refer to Figures 22 and 23) is, for example, silicon nitride or silicon oxide. In some embodiments, the electrically insulating isolation material 114a may also have a light-shielding effect, such as black organic material, so that the mixing of light between the first sub-pixel and the second sub-pixel can be reduced or avoided, thereby improving the light-emitting effect of the light-emitting diode chip. In other embodiments, the isolation structure 114 may also be an ion implantation layer, a structure with electrical isolation and light-blocking effects formed by an ion implantation process. In the following embodiments, the isolation structure 114 is the same as this and will not be described in detail later.

[0137] It should be noted that a chip that is not provided with the isolation structure 114 and is driven in a synchronous manner can achieve multi-spectrum or full-spectrum light emission and is usually used in the field of lighting.

[0138] In the chip of the present application, as shown in FIG11 to FIG16 , except for the light-emitting material closest to the N-type electrode 102 , the remaining light-emitting materials include a first portion and a second portion connected to each other;

[0139] Along the thickness direction of the light emitting diode chip, the first portion of the remaining light emitting materials is stacked;

[0140] Along a thickness direction intersecting the LED chip, the second portion of the remaining light-emitting materials and the light-emitting material closest to the N-type electrode 102 are arranged side by side in sequence and correspond to different sub-pixels respectively.

[0141] It should be noted that the light-emitting material closest to the N-type electrode 102 is the nth light-emitting material 113 - n , and the remaining light-emitting materials include the first light-emitting material 113 - 1 , the second light-emitting material 113 - 2 . . . and the (n-1)th light-emitting material 113 - n-1.

[0142] In the first light-emitting material 113-1, the second light-emitting material 113-2, ..., and the n-1th light-emitting material 113-n-1, the first portion extends in a direction intersecting the chip thickness, and the second portion extends in the chip thickness. The first portion of each light-emitting material is stacked along the thickness of the chip, with the light-emitting material with the smallest wavelength located on the side of the remaining light-emitting materials close to the P-type electrode 104. When power is applied to the N-type electrode 102 and the P-type electrode 104, the light-emitting material with the smallest wavelength emits electroluminescence. When holes provided by the P-type electrode 104 can enter the remaining light-emitting materials, the remaining light-emitting materials emit both photoluminescence and electroluminescence. When holes provided by the P-type electrode 104 cannot enter the remaining light-emitting materials, the remaining light-emitting materials emit photoluminescence. The n-th light-emitting material 113-n is stacked on the side of the n-1th light-emitting material 113-n-1 close to the N-type electrode 102.

[0143] In the first luminescent material 113-1, the second luminescent material 113-2, ..., and the n-1th luminescent material 113-n-1, the second portion of each luminescent material can correspond to a different sub-pixel. For example, the second portion of the first luminescent material 113-1 corresponds to the first sub-pixel, the second portion of the second luminescent material 113-2 corresponds to the second sub-pixel, and the sub-pixel of the nth luminescent material corresponds to the mth sub-pixel. The same luminescent material can correspond to multiple sub-pixels. For example, the second portion of the first luminescent material 113-1 corresponds to two sub-pixels with equal emission wavelengths. The nth luminescent material 113-n is arranged side by side with the second portion of each luminescent material and is also used to correspond to at least one sub-pixel.

[0144] As shown in Figure 12 , the aforementioned chip may further include a reflective layer 107 and a filter layer. The reflective layer 107 may be located on the side of the N-type electrode 102 facing away from the P-type electrode 104, such that the side of the P-type electrode 104 facing away from the N-type electrode 102 forms a light-exiting side, with the corresponding filter layer disposed on this light-exiting side. The filter layer may include a second filter layer CF2, a third filter layer CF3, and so on, and an nth filter layer CFn. The second filter layer CF2 corresponds to the second subpixel formed by the second luminescent material 113-2, the third filter layer CF3 corresponds to the third subpixel formed by the third luminescent material 113-3, and so on. The nth filter layer CFn corresponds to the mth subpixel formed by the nth luminescent material 113-n.

[0145] As shown in Figures 11 and 12 , the chip's multiple sub-pixels are driven synchronously. As shown in Figures 13 and 14 , the P-type electrode 104 includes a first sub-P-type electrode, a second sub-P-type electrode, a third sub-P-type electrode, and so on, up to the mth sub-P-type electrode. The chip's multiple sub-pixels are driven independently. As shown in Figures 14 and 16 , the N-type electrode 102 includes a first sub-N-type electrode, a second sub-N-type electrode, a third sub-N-type electrode, and so on, up to the mth sub-N-type electrode. The chip's multiple sub-pixels are driven independently.

[0146] In the chip of this embodiment, an isolation structure 114 (not shown in the figure) can be set between each sub-pixel. The isolation structure 114 can be located between the second parts of the light-emitting materials arranged side by side, and can also be further located between the respective regions of the first part of the light-emitting materials corresponding to each sub-pixel. When the P-type electrode 104 of the chip includes a plurality of discrete sub-P-type electrodes, the isolation structure 114 can be located between the sub-P-type electrodes corresponding to each sub-pixel. When the N-type electrode 102 of the chip includes a plurality of discrete sub-N-type electrodes, the isolation structure 114 can be located between the sub-N-type electrodes corresponding to each sub-pixel. The isolation structure 114 can also be located between the filter layers corresponding to each sub-pixel, and between the reflective layers 107.

[0147] In the chip of this embodiment, a hole blocking layer 115 (not shown) may be provided between the stacked luminescent materials. The hole blocking layer 115 may be provided at least between the first luminescent material 113-1 and the luminescent material stacked with the second luminescent material 113-2. As shown in FIG11 , the second luminescent material 113-2 is stacked with the first luminescent material 113-1, with the hole blocking layer 115 provided therebetween. In other embodiments, if the third luminescent material 113-3 is stacked with the first luminescent material 113-1, the hole blocking layer 115 may also be provided therebetween. Of course, the hole blocking layer 115 may also be provided between other stacked luminescent materials, for example, between the second luminescent material 113-2 and the third luminescent material 113-3.

[0148] Based on the embodiments of Figures 11-16 above, in other embodiments, a portion of the luminescent material may include only the first portion, without the second portion. For example, based on the structure shown in Figure 11, the first luminescent material 113-1 may include only the first portion, without the second portion. The remaining luminescent material may include both the first portion and the second portion.

[0149] Based on the embodiments of Figures 11-16 above, in some other embodiments, a portion of the luminescent material may include only the second portion, without the first portion. For example, based on the structure shown in Figure 11, the second luminescent material 113-2 may include only the second portion, without the first portion. The remaining luminescent material may include both the first portion and the second portion.

[0150] 17-26 , among the plurality of light-emitting materials, except for the light-emitting material with the smallest light-emitting wavelength, the remaining light-emitting materials are stacked along the thickness direction of the light-emitting diode chip.

[0151] In this chip, the luminescent material with the smallest emission wavelength is stacked on the side of the remaining luminescent materials near the P-type electrode 104. Specifically, the first luminescent material 113-1 is stacked on the side of the remaining luminescent materials near the P-type electrode 104. The first luminescent material 113-1 can generate electroluminescence. The light emitted by the first luminescent material 113-1 can excite the remaining luminescent materials, which then emit photoluminescence. Of course, if the holes provided by the P-type electrode 104 and the electrons provided by the N-type electrode 102 can migrate to the remaining luminescent materials, the remaining luminescent materials can also generate electroluminescence.

[0152] Among the remaining light-emitting materials, the wavelength of each light-emitting material gradually increases along the direction from P-type electrode 104 to N-type electrode 102. That is, along the direction from P-type electrode 104 to N-type electrode 102, the wavelengths of the second light-emitting material 113-2, the third light-emitting material 113-3, and so on to the nth light-emitting material 113-n gradually increase, and they are arranged in this order. This way, light emitted by the light-emitting material closer to P-type electrode 104 can excite light-emitting materials farther from P-type electrode 104.

[0153] In other embodiments, the remaining light-emitting materials may not be arranged in the order of their emission wavelengths along the direction from the P-type electrode 104 to the N-type electrode 102. For example, the second light-emitting material 113-2 having a shorter emission wavelength may be located on the side of the third light-emitting material 113-3 having a longer emission wavelength that is closer to the N-type electrode 102.

[0154] In the chip of this embodiment, in the stacked light-emitting materials, different regions arranged along a direction intersecting the thickness of the light-emitting diode chip correspond to different sub-pixels.

[0155] As shown in Figures 18 and 19, the chip may further include a reflective layer 107 and a filter layer. The reflective layer 107 may be located on the side of the N-type electrode 102 facing away from the P-type electrode 104, such that the side of the P-type electrode 104 facing away from the N-type electrode 102 forms a light-exiting side, with the corresponding filter layer disposed on this light-exiting side. The filter layer may include a first filter layer CF1, a second filter layer CF2, a third filter layer CF3, and so on, and an nth filter layer CFn. The first filter layer CF1 corresponds to a first subpixel of the first luminescent material 113-1, the second filter layer CF2 corresponds to a second subpixel of the second luminescent material 113-2, the third filter layer CF3 corresponds to a third subpixel formed by the third luminescent material 113-3, and so on. The nth filter layer CFn corresponds to an mth subpixel formed by the nth luminescent material 113-n.

[0156] As shown in Figure 17 , the chip's multiple sub-pixels are driven synchronously. As shown in Figure 18 , the P-type electrode 104 includes a first sub-P-type electrode, a second sub-P-type electrode, a third sub-P-type electrode, and so on, up to the mth sub-P-type electrode. The chip's multiple sub-pixels are driven independently. As shown in Figure 19 , the N-type electrode 102 includes a first sub-N-type electrode, a second sub-N-type electrode, a third sub-N-type electrode, and so on, up to the mth sub-N-type electrode. The chip's multiple sub-pixels are driven independently.

[0157] In the chip of this embodiment, as shown in Figures 22 and 23, an isolation structure 114 can be set between each sub-pixel, and the isolation structure 114 can be located between different areas of each light-emitting material. When the P-type electrode 104 of the chip includes multiple discrete P-type electrodes 104, the isolation structure 114 can be located between the sub-P-type electrodes corresponding to each sub-pixel. When the N-type electrode 102 of the chip includes multiple discrete N-type electrodes 102, the isolation structure 114 can be located between the sub-N-type electrodes corresponding to each sub-pixel. The isolation structure 114 can also be located between the filter layers corresponding to each sub-pixel, and between the reflective layers 107.

[0158] In the chip of this embodiment, a hole blocking layer 115 (not shown) can be provided between the stacked light-emitting materials. Hole blocking layer 115 can be provided at least between the first light-emitting material 113-1 and the light-emitting material stacked with the second light-emitting material 113-2. As shown in FIG17 , the second light-emitting layer 113 is stacked with the first light-emitting material 113-1, with hole blocking layer 115 provided between the two. In other embodiments, if the third light-emitting material 113-3 is stacked with the first light-emitting material 113-1, hole blocking layer 115 can also be provided between the two. Of course, hole blocking layer 115 can also be provided between other stacked light-emitting materials, for example, between the second light-emitting material 113-2 and the third light-emitting material 113-3.

[0159] As shown in Figures 24 to 26 , in the chip of the present application, among the multiple stacked light-emitting materials, several light-emitting materials form a light-emitting material group. Light-emitting layer 113 includes multiple light-emitting material groups. These multiple light-emitting material groups are arranged sequentially along P-type electrode 104 to N-type electrode 102. Figures 24 to 26 illustrate light-emitting material groups Group 1 through Group n.

[0160] It should be noted that the number of luminescent material groups can be 2, 3 or more. In different groups, the arrangement and number of luminescent materials can be the same or different.

[0161] Among the luminescent materials closest to the P-type electrode 104, the luminescent material closest to the P-type electrode 104 may have the smallest emission wavelength. That is, in FIG24 , the first luminescent material 113-1 closest to the P-type electrode 104 has the smallest emission wavelength. The light emitted by this luminescent material can excite the remaining luminescent materials in the same luminescent material group, and can also excite the luminescent materials in the remaining luminescent material groups to emit light.

[0162] As shown in FIG24 , the chip described above may further include a reflective layer 107 and a filter layer. The reflective layer 107 may be located on the side of the N-type electrode 102 facing away from the P-type electrode 104, such that the side of the P-type electrode 104 facing away from the N-type electrode 102 forms a light-exiting side, with the corresponding filter layer disposed on this light-exiting side. The filter layer may include a first filter layer CF1, a second filter layer CF2, a third filter layer CF3, and so on, up to an nth filter layer CFn. The first filter layer CF1 corresponds to a first subpixel of the first luminescent material 113-1, the second filter layer CF2 corresponds to a second subpixel of the second luminescent material 113-2, the third filter layer CF3 corresponds to a third subpixel formed by the third luminescent material 113-3, and so on. The nth filter layer CFn corresponds to an mth subpixel formed by the nth luminescent material 113-n.

[0163] Continuing with FIG24 , the chip's multiple sub-pixels are driven synchronously. Referring to FIG25 , the P-type electrode 104 includes a first sub-P-type electrode, a second sub-P-type electrode, a third sub-P-type electrode, and so on, up to the mth sub-P-type electrode. The chip's multiple sub-pixels are driven independently. Referring to FIG26 , the N-type electrode 102 includes a first sub-N-type electrode, a second sub-N-type electrode, a third sub-N-type electrode, and so on, up to the mth sub-N-type electrode. The chip's multiple sub-pixels are driven independently.

[0164] In the chip of this embodiment, as shown in Figures 25 and 26, an isolation structure 114 can be set between each sub-pixel, and the isolation structure 114 can be located between different regions of each light-emitting material of each light-emitting material group. When the P-type electrode 104 of the chip includes a plurality of discrete sub-P-type electrodes, the isolation structure 114 can be located between the sub-P-type electrodes corresponding to each sub-pixel. When the N-type electrode 102 of the chip includes a plurality of discrete sub-N-type electrodes, the isolation structure 114 can be located between the sub-N-type electrodes corresponding to each sub-pixel. The isolation structure 114 can also be located between the filter layers corresponding to each sub-pixel, and between the reflective layers 107.

[0165] In the chip of this embodiment, a hole blocking layer 115 (not shown) may be provided between each stacked light-emitting material. The hole blocking layer 115 may be provided at least between the first light-emitting material 113-1 and the light-emitting material stacked with the second light-emitting material 113-2 in the same light-emitting material group. As shown in FIG24 , the second light-emitting layer 113 in the light-emitting material group near the P-type electrode 104 is stacked with the first light-emitting material 113-1, with the hole blocking layer 115 provided between the two. In other embodiments, if the third light-emitting material 113-3 is stacked with the first light-emitting material 113-1, the hole blocking layer 115 may also be provided between the two. Of course, the hole blocking layer 115 may also be provided between other stacked light-emitting materials, for example, between the second light-emitting material 113-2 and the third light-emitting material 113-3. Of course, the hole blocking layer 115 may also be provided between adjacent light-emitting material groups.

[0166] The chip of each of the above embodiments may further include an N-type semiconductor layer 103 and a P-type semiconductor layer 105, wherein the N-type semiconductor and the P-type semiconductor are respectively located on opposite sides of the light-emitting layer 113 in the thickness direction, the N-type electrode 102 is electrically connected to the light-emitting layer 113 through the N-type semiconductor, and the P-type electrode 104 is electrically connected to the light-emitting layer 113 through the P-type semiconductor.

[0167] When the N-type electrode 102 includes M separate sub-N-type electrodes, the isolation structure 114 is located between adjacent sub-N-type electrodes, and at least a portion of the isolation structure 114 extends into the P-type semiconductor layer 105. For example, as shown in Figures 20 and 22, the isolation structure 114 extends into the P-type semiconductor.

[0168] When the P-type electrode 104 includes M separate sub-P-type electrodes, the isolation structure 114 is located between adjacent sub-P-type electrodes, and at least a portion of the isolation structure 114 extends into the N-type semiconductor layer 103. For example, as shown in Figures 21 and 23, the isolation structure 114 extends into the N-type semiconductor.

[0169] The above-mentioned configuration of the isolation structure 114 can not only reduce the process difficulty, but also improve the isolation effect of the isolation structure 114 on each sub-pixel. It should be noted that the solution of extending the isolation structure 114 to the P-type semiconductor or N-type semiconductor can also be applied to the chip structures of the other embodiments above.

[0170] In the above chip embodiment, in the independently driven driving mode, each sub-pixel corresponds to a separate sub-N-type electrode or sub-P-type electrode. In other embodiments, in the independently driven chip, a portion of the sub-pixels can also share a separate sub-N-type electrode or sub-P-type electrode. Specifically:

[0171] As a first feasible implementation, the N-type electrode 102 includes m mutually discrete sub-N-type electrodes, and the P-type electrode 104 includes M mutually discrete sub-P-type electrodes; a side of the M sub-pixels close to the P-type electrode 104 is electrically connected to each sub-P-type electrode one by one, and a side of the M sub-pixels close to the N-type electrode 102 is electrically connected to the m sub-N-type electrodes; m is less than M, and a portion of the sub-pixels share one sub-N-type electrode.

[0172] As shown in Figure 27 , sub-pixels G and B share a sub-N-type electrode N1. Sub-pixel G is electrically connected to sub-P-type electrode P11, and sub-pixel B is electrically connected to sub-P-type electrode P21. Two sub-pixels R share another sub-N-type electrode N2. Sub-pixels R are electrically connected to sub-P-type electrode P22 and sub-P-type electrode P12, respectively. This improves the uniformity of light emission across sub-pixels that share a single sub-N-type electrode.

[0173] As a second feasible implementation, the P-type electrode 104 includes m mutually discrete sub-P-type electrodes 104, and the N-type electrode 102 includes M mutually discrete sub-N-type electrodes; one side of the M sub-pixels close to the N-type electrode 102 is electrically connected to each sub-N-type electrode one by one, and one side of the M sub-pixels close to the P-type electrode 104 is electrically connected to the m sub-P-type electrodes 104; m is less than M, and a part of the sub-pixels share one sub-P-type electrode 104.

[0174] As shown in Figure 28, sub-pixels G and B share a sub-P-type electrode P1. Sub-pixel G is electrically connected to sub-N-type electrode N11, and sub-pixel B is electrically connected to sub-N-type electrode N21. Two sub-pixels R share another sub-P-type electrode P2. The two sub-pixels R are electrically connected to sub-N-type electrode N22 and sub-N-type electrode N12, respectively. In this way, the sub-pixels that share a sub-P-type electrode have higher light uniformity.

[0175] 29 to 34 , in the chip of the present application, in some embodiments, M sub-pixels form a pixel subgroup. For example, as shown in FIG29 , sub-pixel B, sub-pixel G, and sub-pixel R together constitute a chip. As shown in FIG30 and FIG31 , the arrangement order of sub-pixel B, sub-pixel G, and sub-pixel R can be changed. The number of sub-pixels in a chip shown in FIG29-31 can be 3. As shown in FIG32 , the number of sub-pixels in a chip can also be 4, or as shown in FIG33 and FIG34 , the number of sub-pixels in a chip can be 5. In other embodiments, the number of sub-pixels in the chip can be more (for example, as shown in FIG35 , the chip includes 8 sub-pixels), and the arrangement of each sub-pixel can be flexibly adjusted.

[0176] In other embodiments, M sub-pixels form a plurality of pixel subgroups, and the plurality of pixel subgroups are arranged in an array in a direction intersecting the thickness of the light-emitting diode chip. For example, with reference to Figures 36-42, sub-pixel B, sub-pixel G, and sub-pixel R can form a pixel subgroup, and the chip includes a plurality of pixel subgroups arranged in an array. The arrangement of sub-pixels B, sub-pixels G, and sub-pixels R in different pixel subgroups can be the same or different. For example, with reference to Figure 38, a pixel subgroup can include four sub-pixels. For example, with reference to Figures 40 and 41, a pixel subgroup can include five sub-pixels.

[0177] As a feasible implementation, among the multiple sub-pixels in the above-mentioned pixel subgroup, the light-emitting wavelengths of the multiple sub-pixels are different, or the multiple sub-pixels include at least two sub-pixels with the same light-emitting wavelength.

[0178] For example, as shown in Figures 29-31, the sub-pixels of a pixel subgroup are respectively sub-pixel B, sub-pixel G, and sub-pixel R. As shown in Figure 33, sub-pixel G1 and sub-pixel G2 may represent sub-pixels with different luminous wavelengths. Alternatively, as shown in Figure 32, the sub-pixels of a pixel subgroup may include sub-pixel B, sub-pixel G, and two sub-pixels R. As shown in Figure 34, the sub-pixels of a pixel subgroup may include sub-pixel B, sub-pixel G, and three sub-pixels R.

[0179] In the chip of the present application, M sub-pixels form a plurality of pixel units, and the plurality of pixel units are arranged in an array along a thickness direction intersecting the light-emitting diode chip;

[0180] One pixel unit includes Y sub-pixels, and the Y sub-pixels include X wavelengths; X is a positive integer greater than or equal to 3, and Y is a positive integer greater than or equal to X.

[0181] It should be noted that, as shown in Figures 29-31 , a chip includes three sub-pixels, which form a pixel unit. The three sub-pixels each represent three wavelengths. In this embodiment, X and Y are both 3. Furthermore, as shown in Figures 36-38 , a multi-color, multi-sub-pixel chip includes 3*a sub-pixels, each representing three wavelengths, and comprises a pixel unit. In this embodiment, X is 3 and Y is 3*a.

[0182] As shown in Figure 32 , a chip includes four sub-pixels, which form a pixel unit. These four sub-pixels cover three wavelengths. In this embodiment, X is 3 and Y is 4. Furthermore, as shown in Figure 39 , a multi-color, multi-sub-pixel chip includes 4*a sub-pixels, which cover three wavelengths and comprise a pixel unit. In this embodiment, X is 3 and Y is 4*a.

[0183] As shown in FIG33 , a chip includes five sub-pixels, which form a pixel unit. The five sub-pixels include four wavelengths (taking the different wavelengths of sub-pixel G1 and sub-pixel G2 as an example). In this embodiment, X is 4 and Y is 5. Furthermore, as shown in FIG40 , a multi-color, multi-sub-pixel chip includes 5*a sub-pixels, each of which includes four wavelengths, and comprises a pixel unit. In this embodiment, X is 4 and Y is 5*a.

[0184] As shown in FIG34 , a chip includes five sub-pixels, which form a pixel unit. The five sub-pixels include three wavelengths. In this embodiment, X is 3 and Y is 5. Furthermore, as shown in FIG41 , a multi-color, multi-sub-pixel chip includes 5*a sub-pixels, which include three wavelengths and comprise a pixel unit. In this embodiment, X is 3 and Y is 5*a.

[0185] In the above embodiment, when Y is greater than X, the light-emitting wavelengths of at least a portion of the sub-pixels in one pixel unit are equal.

[0186] According to the above method, pixel units with different structures can be designed in the chip to achieve a diversified chip structure to adjust the chip's light mixing effect, thereby realizing a chip with a flexible structure and rich light output effects.

[0187] As a feasible implementation method, in the chip of the embodiment of the present application, all sub-pixels in the same pixel unit are only used by the pixel unit to which they belong. Referring to Figures 29-31, three sub-pixels in the same chip can form a pixel unit, and all sub-pixels are only used by this pixel unit. Referring to Figure 32, the chip includes 2 sub-pixels R, 1 sub-pixel B and 1 sub-pixel G. 1 sub-pixel R, 1 sub-pixel B and 1 sub-pixel G can form a complete pixel unit and are only used by this pixel unit. In this way, a complete full-color pixel unit can be formed in the chip, ensuring that the chip is more convenient to use.

[0188] It should be noted that in two adjacent pixel units, for example, the first pixel unit and the second pixel unit. When the sub-pixels in the first pixel unit are not bright enough, part or all of the sub-pixels in the adjacent second pixel unit can be flexibly borrowed to complete the light emission of the second pixel unit. That is, the borrowed sub-pixels in the first pixel unit can be used not for the light emission of the first pixel unit, but for the light emission of the second pixel unit. In this way, the structural flexibility and light emission effect of the chip can be improved. Among them, the first pixel unit can also borrow the second pixel unit to emit light for other reasons, which is not limited in this application.

[0189] As another achievable implementation, in the chip of the embodiment of the present application, a pixel unit has two sub-pixels that are shared with the adjacent pixel unit, and the number of all sub-pixels in a single chip is M=a*(2X-2), where a is a positive integer greater than or equal to 1. Referring to FIG35 , in a chip, sub-pixel R in pixel unit PU2 is shared with pixel unit PU1 adjacent to it, and sub-pixel B in pixel unit PU2 is shared with pixel unit PU3 adjacent to it. The number of sub-pixels in the chip is 8, and X is 3 and a is 2 in the chip. Wherein, a is the number of pixel sub-groups composed of all sub-pixels in a single chip. For example, in the chip shown in the figure, sub-pixel B, sub-pixel G, sub-pixel R, and sub-pixel G together form a pixel sub-group. There are two pixel sub-groups in the chip, so a is 2.

[0190] In the same chip, some sub-pixels are shared to form different pixel units, which can ensure the flexible structure of the chip and meet diverse display needs.

[0191] In some embodiments, the size of the LED chip is greater than or equal to 50 microns. The size of the pixel subgroup of the chip may also be greater than or equal to 50 microns. For example, it may be 50-100 microns, or 100-150 microns, or greater than 150 microns. Of course, in some embodiments, the size of the LED chip may also be less than 50 microns. The size of the LED chip can be selected according to different usage scenarios.

[0192] In some embodiments, the shape of the LED chip is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram, and a polygon with more than four sides; wherein different sub-pixels have the same or different shapes. That is, the shape of the first sub-pixel B and the second sub-pixel G can both be a rectangle as shown in FIG. 28 .

[0193] When a plurality of LED chips form a LED chip group, the shapes of different LED chips may be the same or different.

[0194] In some embodiments, the sub-pixel size ranges from 0.001 to 200 microns. When the sub-pixel size is between 0.001 microns and 0.1 microns, the sub-pixel size is at the nanometer level, representing a nano-LED. During the nano-LED manufacturing process, the single-core, multi-color, multi-sub-pixel arrangement of the present application can be referenced, thereby facilitating an increase in the size of a single nano-LED chip containing multiple sub-pixels, bringing the size of the single chip close to or within the size range of LED chips currently accessible by mass transfer processes. This reduces the operational difficulty of the nano-LED manufacturing process and improves its operability.

[0195] In other embodiments, for example, a LED chip with 3*3 sub-pixels for large televisions can have a single sub-pixel size of 30 microns, with a 10 micron spacing between two adjacent sub-pixels. The LED chip has a length and width of 110 microns, resulting in a size of 110*110 microns. LED chips of this size can utilize mini LED packaging processes.

[0196] The size of the LED chip and the size of the sub-pixel may vary depending on the usage scenario of the LED chip. Below, exemplary descriptions of the size of the LED chip and the size of the sub-pixel in different usage scenarios are given.

[0197] When the LED chip is used in display products such as home televisions and desktop computers, at a pixel density of 50-150, the size (pitch) of a pixel unit composed of several sub-pixels in multiple LED chips can be 150-700 microns, the size (sub pitch) of the sub-pixels in the LED chip can be less than 250 microns, and the size of the LED chip can be greater than 100 microns.

[0198] When the LED chip is used in display products such as laptops and tablets, when the pixel density is 150-250, the sub-pixel size can be less than 70 microns, the pixel unit size is 100-200 microns, and the LED chip size can be greater than 60 microns.

[0199] When the LED chip is used in display products such as mobile phones and electronic watches, when the pixel density is greater than 300, the sub-pixel size can be less than 30 microns, the pixel unit size is less than 100 microns, and the LED chip size can be greater than 50 microns.

[0200] Based on this, the light-emitting diode chip provided in the embodiment of the present application adopts a single-core, multi-color, multi-sub-pixel arrangement. The size of the sub-pixels and the size range of the light-emitting diode chip are relatively large, which can be applied to different usage scenarios, thereby increasing the applicability of the light-emitting diode chip.

[0201] In some embodiments, the shape of the sub-pixel is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram, and a polygon with more than four sides.

[0202] In some embodiments, the sizes of different sub-pixels are equal or different. The size of a sub-pixel affects its luminous area. That is, the luminous areas of different sub-pixels can be equal or different. The sizes of different sub-pixels can be adjusted according to the brightness attenuation of the sub-pixels. For example, if the brightness attenuation rate of a certain sub-pixel is large, the size of the sub-pixel can be appropriately increased to ensure uniform light output requirements. The sizes of different sub-pixels can also be adjusted according to whether the sub-pixels are shared between different pixel units (PU for short). For example, as shown in Figure 58, sub-pixel (B) and sub-pixel (R) are shared by two pixel units respectively in the process of forming pixel units PU1 and PU2, while sub-pixel (G) is not shared, but all belong to pixel unit PU1. Therefore, the sizes of sub-pixel (B) and sub-pixel (R) are larger than the size of sub-pixel (G). In this way, the luminous brightness of the shared sub-pixels in each pixel unit can be guaranteed.

[0203] It should be pointed out that the above-mentioned "size" can be understood as the extension length of the sub-pixel in a certain extension direction, for example, it can be the length or width of a rectangular sub-pixel, the major axis length or minor axis length of an elliptical sub-pixel, or the diameter of a circular sub-pixel, etc.

[0204] As shown in FIG43 , the chip provided in the embodiment of the present application further includes a buffer layer 101, an N-type semiconductor layer 103, a P-type semiconductor layer 105, a current spreading layer 106, a reflective layer 107, and a first insulating layer 108. The buffer layer 101 and the N-type semiconductor layer 103 are stacked, the light-emitting layer 113 is disposed on the side of the N-type semiconductor layer 103 facing away from the buffer layer 101, and the P-type semiconductor layer 105 is disposed on the side of the light-emitting layer 113 facing away from the buffer layer 101. The current spreading layer 106 is in contact with the side of the P-type semiconductor layer 105 facing away from the buffer layer 101. The N-type electrode 102 is in contact with the N-type semiconductor layer 103, and the P-type electrode 104 is in contact with both the P-type semiconductor layer 105 and the current spreading layer 106. The first insulating layer 108 is disposed on the side of the current spreading layer 106 facing away from the buffer layer 101.

[0205] The light emitting layer 113 includes a first light emitting material 113 - 1 , a second light emitting material 113 - 2 , and a third light emitting material 113 - 3 , which are sequentially stacked along the P-type electrode 104 to the N-type electrode 102 .

[0206] It should be noted that the first filter layer 117a, the second filter layer 117b and the third filter layer 117c mentioned below are respectively equivalent to the first filter layer CF1, the second filter layer CF2 and the third filter layer CF3 of the light emitting diode chip mentioned above.

[0207] Alternatively, referring to Figure 43 , the reflective layer 107 can be disposed on the side of the first insulating layer 108 facing away from the buffer layer 101. This allows the light from the LED chip to be emitted in a direction away from the buffer layer 101, as indicated by the downward arrow in the figure. The first filter layer 117a, the second filter layer 117b, and the third filter layer 117c are arranged side by side at the bottom of the buffer layer 101. This chip has a thin-film flip-chip structure.

[0208] 43 , the reflective layer 107 is disposed on the side of the first insulating layer 108 facing away from the buffer layer 101 , and a second insulating layer 109 is further disposed on the side of the reflective layer 107 facing away from the buffer layer 101 . The second insulating layer 109 can protect the reflective layer 107 .

[0209] The buffer layer 101 can be made of one or more of gallium nitride, aluminum gallium nitride, and aluminum indium gallium nitride, and its thickness can be 10-40 nanometers. The N-type semiconductor layer 103 can be made of N-type doped gallium nitride, and the P-type semiconductor layer 105 can be made of P-type doped gallium nitride. The current spreading layer 106 can be made of a transparent conductive material (indium tin oxide, ITO) or silver, and its function is to improve the distribution of the P-type electrode 104, ensuring that holes are distributed as evenly as possible in the area where the P-type semiconductor layer 105 is located. The first insulating layer 108 can be made of silicon oxide or silicon nitride.

[0210] As shown in FIG44 , the light-emitting diode chip provided in an embodiment of the present application may further include a substrate 100, which may be disposed on the side of the buffer layer 101 facing away from the light-emitting layer 113. The material of the substrate 100 may be a composite of one or more of sapphire, gallium nitride, aluminum nitride, silicon, and silicon carbide. The chip has a face-up structure. Specifically, when the reflective layer 107 is disposed on the side of the buffer layer 101 facing away from the light-emitting layer 113, the reflective layer 107 is located on the side of the substrate 100 facing away from the light-emitting layer 113, and the filter layer is located on the side of the light-emitting layer 113 facing away from the substrate 100. The filter layer includes a first filter layer 117a, a second filter layer 117b, and a third filter layer 117c. The light-emitting layer 113 includes a first light-emitting material 113-1, a second light-emitting material 113-2, and a third light-emitting material 113-3. That is, in the figure, the reflective layer 107 is located at the bottom of the substrate 100, and the filter layer is located on top of the first insulating layer 108. The top of the chip is the light-emitting side.

[0211] As shown in Figure 45, the light-emitting diode chip provided in the embodiment of the present application also includes a substrate 100, which is arranged on the side of the buffer layer 101 facing away from the light-emitting layer 113. The structure of the chip is a flip-chip structure, with the bottom side being the light-emitting side. Specifically, the reflective layer 107 is located on the side of the first insulating layer 108 facing away from the light-emitting layer 113, and the filter layer is located on the side of the substrate 100 facing away from the light-emitting layer 113. The filter layer includes a first filter layer 117a, a second filter layer 117b, and a third filter layer 117c. The light-emitting layer 113 includes a first light-emitting material 113-1, a second light-emitting material 113-2, and a third light-emitting material 113-3. That is, in the figure, the reflective layer 107 is located on top of the first insulating layer 108, and the filter layer is located at the bottom of the substrate 100.

[0212] As shown in FIG. 46 , the chip provided in the embodiment of the present application may further include a bonding substrate 110 , a binding layer 111 , an N-type semiconductor layer 103 , a P-type semiconductor layer 105 and a reflective layer 107 .

[0213] A bonding substrate 110 and a binding layer 111 are sequentially disposed on a P-type electrode 104. A P-type semiconductor layer 105 is disposed on the side of the binding layer 111 facing away from the bonding substrate 110 and in contact with the binding layer 111. A light-emitting layer 113 is disposed on the side of the P-type semiconductor layer 105 facing away from the bonding substrate 110, and an N-type semiconductor layer 103 is disposed on the side of the light-emitting layer 113 facing away from the bonding substrate 110. The N-type electrode 102 contacts the side of the N-type semiconductor layer 103 facing away from the bonding substrate 110. A reflective layer 107 is disposed on the side of the P-type semiconductor layer 105 closer to the bonding substrate 110. The light-emitting layer 113 includes a first light-emitting material 113-1, a second light-emitting material 113-2, and a third light-emitting material 113-3, stacked in sequence from the P-type electrode 104 to the N-type electrode 102. A first insulating layer 108 is disposed on top of the N-type semiconductor layer 103.

[0214] It should be noted that the light emitting direction of Figure 46 is the upward direction indicated by the arrow in the figure, forming a vertical upright structure light emitting diode chip, and the first filter layer 117a, the second filter layer 117b and the third filter layer 117c are arranged side by side at the bottom of the first insulating layer 108.

[0215] As shown in Figures 43-46, the chip provided in the embodiment of the present application also includes a light-blocking layer 116, which is located on the light-emitting side of the LED chip and between two adjacent sub-pixels. The light-blocking layer 116 can be located between the first filter layer 117a and the second filter layer 117b, or between the second filter layer 117b and the third filter layer 117c. The light-blocking layer 116 can be a black resin material with the function of absorbing and blocking light. The light-blocking layer 116 is located between two adjacent sub-pixels to avoid the problem of light mixing between the two sub-pixels and ensure the light output effect of the LED chip.

[0216] 43-46 , the chip provided in the embodiment of the present application further includes a color conversion layer 112 , which is disposed on a portion of the light-emitting side of the LED chip and corresponds to at least a portion of the sub-pixel area.

[0217] It should be noted that the orthographic projection of the color conversion layer 112 on the surface where the corresponding sub-pixel is located can cover the entire area of ​​a single sub-pixel, or only cover a portion of the area of ​​a single sub-pixel. The material of the color conversion layer 112 can be quantum dot material, phosphor material, etc. The use of the color conversion layer 112 can adjust the light emission wavelength of the LED chip, enriching the variety of its light emission wavelengths.

[0218] As shown in FIG46 , taking a chip with a front-mounted structure as an example, the sub-pixels corresponding to the first filter layer 117a, the second filter layer 117b, and the third filter layer 117c emit light at different wavelengths. The color conversion layer 112 is located on the light-emitting side of the first filter layer 117a and faces a portion of the first filter layer 117a. This allows the color conversion layer 112 to convert a portion of the light emitted by the first filter layer 117a into light of wavelengths other than the wavelengths transmitted by the first filter layer 117a, the second filter layer 117b, and the third filter layer 117c. Therefore, the chip can emit light of multiple wavelengths.

[0219] In a second aspect, an embodiment of the present application provides a method for preparing a light-emitting diode chip, which can be used to prepare the light-emitting diode chip described above.

[0220] As a first method for preparing a light-emitting diode chip, as shown in FIG47 , the preparation method includes:

[0221] A substrate 100 is provided ( FIG47( a) ); a buffer layer 101, an N-type semiconductor layer 103, and a third light-emitting material 113-3 are sequentially formed on the substrate 100 through an epitaxial growth process ( FIG47( b) ); a second light-emitting material 113-2 is formed on a portion of the surface of the third light-emitting material 113-3 through an epitaxial growth process ( FIG47( c) ); a first light-emitting material 113-1 is formed covering another portion of the surface of the third light-emitting material 113-3 through an epitaxial growth process ( FIG47( d) ); and a P-type semiconductor layer 105 covering the first light-emitting material 113-1, the second light-emitting material 113-2, and the third light-emitting material 113-3 through an epitaxial growth process ( FIG47( e) ). Conventional chip processing is then performed to obtain a single-core, multi-color, multi-sub-pixel chip.

[0222] Based on the above, and referring to FIG47 , the manufacturing method includes forming an isolation structure 114 ( FIG47( f )), and then performing conventional chip processing to obtain a single-core multi-color multi-sub-pixel chip.

[0223] As a second method for preparing a light-emitting diode chip, as shown in FIG48 , the method includes:

[0224] A substrate 100 is provided ( FIG48( a) ); a buffer layer 101, an N-type semiconductor layer 103, and a third light-emitting material 113-3 are sequentially formed on the substrate 100 through an epitaxial growth process ( FIG48( b) ); a second light-emitting material 113-2 is formed on a portion of the surface of the third light-emitting material 113-3 through an epitaxial growth process ( FIG48( c) ); a first light-emitting material 113-1 is formed on a portion of the surface of the second light-emitting material 113-2 through an epitaxial growth process ( FIG48( d) ); and a P-type semiconductor layer 105 covering the first light-emitting material 113-1, the second light-emitting material 113-2, and the third light-emitting material 113-3 is formed through an epitaxial growth process ( FIG48( e) ). Conventional chip processing is then performed to obtain a single-core, multi-color, multi-sub-pixel chip.

[0225] Based on the above, and referring to FIG48 , the manufacturing method includes forming an isolation structure 114 ( FIG48( f )), and then performing conventional chip processing to obtain a single-core multi-color multi-sub-pixel chip.

[0226] As a third method for preparing a light-emitting diode chip, as shown in FIG49 , the method includes:

[0227] A substrate 100 is provided ( FIG49( a) ); a buffer layer 101, an N-type semiconductor layer 103, and a third light-emitting material 113-3 are sequentially formed on the substrate 100 through an epitaxial growth process ( FIG49( b) ); a second light-emitting material 113-2 is formed on a portion of the surface of the third light-emitting material 113-3 through an epitaxial growth process ( FIG49( c) ); a first light-emitting material 113-1 is formed on a portion of the surface of the second light-emitting material 113-2 through an epitaxial growth process ( FIG49( d) ); and a P-type semiconductor layer 105 covering the first light-emitting material 113-1, the second light-emitting material 113-2, and the third light-emitting material 113-3 is formed through an epitaxial growth process ( FIG49( e) ). Conventional chip processing is then performed to obtain a single-core multi-color multi-sub-pixel chip.

[0228] Based on the above, and referring to FIG49 , the manufacturing method includes forming an isolation structure 114 ( FIG49( f )), and then performing conventional chip processing to obtain a single-core multi-color multi-sub-pixel chip.

[0229] As a fourth method for preparing a light-emitting diode chip, as shown in FIG50 , the method includes:

[0230] A substrate 100 is provided ( FIG. 50 ( a )); a buffer layer 101, an N-type semiconductor layer 103, a third light-emitting material 113-3, a second light-emitting material 113-2, a first light-emitting material 113-1, and a P-type semiconductor layer 105 are sequentially formed on the substrate 100 by an epitaxial growth process ( FIG. 50 ( b )); a step is formed ( FIG. 50 ( c )); a patterned current spreading layer 106 is formed ( FIG. 50 ( d )); a patterned first insulating layer 108 covering the current spreading layer 106 is formed, and a portion of the first insulating layer 108 is formed. The first insulating layer 108 is located at the step (Figure 50(e)); a patterned reflective layer 107 covering the first insulating layer 108 is formed (Figure 50(f)); a patterned second insulating layer 109 covering the reflective layer 107 is formed (Figure 50(g)); an N-type electrode 102 and a P-type electrode 104 are formed (Figure 50(h)); and a first filter layer 117a, a second filter layer 117b and a third filter layer 117c are formed on the side of the substrate 100 facing away from the reflective layer 107 (Figure 50(i)).

[0231] As a fifth method for preparing a light-emitting diode chip, as shown in FIG51 , the method includes:

[0232] A substrate 100 is formed by a deposition process ( FIG. 51 ( a )); a buffer layer 101, an N-type semiconductor layer 103, a third light-emitting material 113-3, a second light-emitting material 113-2, a first light-emitting material 113-1, and a P-type semiconductor layer 105 are sequentially formed on the substrate 100 by an epitaxial growth process ( FIG. 51 ( b )); steps and trenches (an isolation structure 114 not filled with an isolation material 114 a ) are formed ( FIG. 51 ( c )); a patterned current spreading layer 106 is formed ( FIG. 51 ( d )); and a covering current spreading layer 106 is formed. A patterned first insulating layer 108 is formed, and part of the first insulating layer 108 is located at the step (Figure 51(e)); a patterned reflective layer 107 covering the first insulating layer 108 is formed (Figure 51(f)); a patterned second insulating layer 109 covering the reflective layer 107 is formed (Figure 51(g)); an N-type electrode 102 and a P-type electrode 104 are formed (Figure 51(h)); and a first filter layer 117a, a second filter layer 117b and a third filter layer 117c are formed on the side of the substrate 100 facing away from the reflective layer 107 (Figure 51(i)).

[0233] In a third aspect, an embodiment of the present application provides a light-emitting diode chip set, comprising a plurality of the above-mentioned light-emitting diode chips, wherein the plurality of light-emitting diode chips are arranged in an array along a thickness direction intersecting the light-emitting diode chips.

[0234] As shown in FIG52 , multiple chips can be arranged in an array along a plane formed by the x-direction and the y-direction, for example, chip C1, chip C2, chip C3, and chip C4. The x-direction and the y-direction can intersect with each other, and in some embodiments, the two can be perpendicular to each other. Multiple chips can be arranged only along the x-direction, such as chip C1 and chip C2. Multiple chips can also be arranged only along the y-direction, such as chip C1 and chip C3. The arrangement of the chipset provided in this application can be flexibly adjusted.

[0235] 52 , in the chipset of the present application, the sub-pixels in a single chip can form a complete pixel unit. For example, in chip C1, sub-pixel B, sub-pixel G, and sub-pixel R can form a pixel unit.

[0236] In the chipset of the present application, pixels of multiple chips can form a complete pixel unit.

[0237] As a first achievable embodiment, as shown in FIG64 , in two adjacent LED chips, the entire subpixel area of ​​one LED chip and the entire subpixel area of ​​the other LED chip together form a pixel unit. For example, subpixel B in chip C1 and subpixel G and subpixel R in chip C3 together form a pixel unit.

[0238] As a second achievable embodiment, as shown in Figures 58-61, in two adjacent LED chips, a partial area of ​​the subpixel of one LED chip and a partial area of ​​the subpixel of the other LED chip together form a pixel unit. For example, in Figure 58, a partial area of ​​subpixel R and subpixel G in chip C1 and a partial area of ​​subpixel B in chip C2 together form a pixel unit PU2. Subpixel R of chip C1 can also be configured to form pixel unit PU1, and subpixel B of chip C2 can also be configured to form pixel unit PU3. Therefore, subpixel R and subpixel B are subpixels shared by two pixel units, respectively. Compared with Figure 58, the arrangement of subpixels in the two chips is different in Figure 59, but the shared subpixels are still subpixels R and subpixels B.

[0239] 60 , the sub-pixels that are shared may also be sub-pixels G and R. Referring to FIG. 61 , the sub-pixels that are shared may also be sub-pixels G and B.

[0240] 53 to 57 , in the LED chip group provided by the embodiment of the present application, two adjacent LED chips are of irregular shape, one of the two adjacent LED chips has a protruding area, and the other has a concave area; the shapes of the protruding area and the concave area are adapted to each other and fit together.

[0241] It should be noted that the protruding area can be a cube, a pyramid, a hemisphere, or other irregular shape, and the protruding area and the concave area are compatible and interlocking. The number of protruding areas and the number of concave areas can be one, two, or more, and the number of both can be equal. For example, adjacent LED chips can include a first LED chip and a second LED chip.

[0242] It should be noted that, using Figures 53-55 as an example, the first LED chip C1 and the second LED chip C2 are both stepped, and the convex area of ​​the step of the first LED chip C1 is relatively aligned with the concave area of ​​the step of the second LED chip C2, so that the first LED chip C1 and the second LED chip C2 are completely joined.

[0243] 53 and 54 , the sub-pixels in the first LED chip C1 have the same size. In this application, the convex and concave regions are aligned and joined together to form a "mortise and tenon structure," thereby facilitating self-alignment assembly of different LED chips, reducing alignment difficulty and improving manufacturing efficiency and yield.

[0244] The shape of the assembled LED chip can also be convex or concave (as shown in FIG54 ); or, in a stepped LED chip, different sub-pixels have different sizes (as shown in FIG55 ); or, the LED chip has a serrated edge (as shown in FIG56 ); or, the LED chip has an arc-shaped edge (as shown in FIG57 ).

[0245] In other embodiments, as shown in FIG. 58 to FIG. 63 , in the assembled chips of the LED chip group, the shapes of different LED chips may be the same and regular.

[0246] In the chipset provided in the embodiment of the present application, a plurality of light-emitting diode chips form a plurality of chip groups arranged in an array and a plurality of pixel units arranged in an array; in the same light-emitting diode chip, the spacing between adjacent sub-pixels is d1; the spacing between adjacent chip groups is d2; the spacing between adjacent pixel units is d3; and the spacing between adjacent light-emitting diode chips is d4; d1, d2, d3, and d4 are all equal, or d1, d2, d3, and d4 are not equal to each other.

[0247] 52 , in the chipset, along the y direction, the sum of the size of subpixel B of chip C1 and the pitch between subpixel B and subpixel G is a first size. Subpixel B's size is a, and the pitch between subpixel B and subpixel G is b. The first size = a + b, and is the subpixel size (sub pitch) of subpixel B.

[0248] In chip C1, the sum of the size of subpixel G and the spacing between subpixel G and subpixel R is the second size. Subpixel G size is c, and the spacing between subpixel G and subpixel R is d. The second size = c + d, and the second size is the subpixel size of subpixel G.

[0249] The sum of the size of subpixel R in chip C1 and the spacing between subpixel R in chip C1 and subpixel B in chip C2 is the third size. The size of subpixel R is e, and the spacing between subpixel R in chip C1 and subpixel B in chip C2 is f. The third size = e + f, and is the subpixel size of subpixel R.

[0250] Optionally, the first size, the second size, and the third size are all equal; or the first size, the second size, and the third size may be unequal. The sum of the first size, the second size, and the third size may be the pixel size (Pitch) of a pixel unit consisting of sub-pixel B, sub-pixel G, and sub-pixel R of chip C1.

[0251] Similarly, in chip C2, the pixel unit formed by sub-pixel B, sub-pixel G, and sub-pixel R also has a pixel size. The pixel sizes of chip C1 and chip C2 can be equal or different.

[0252] 52 , along the first direction x, in chip group CG1 , the size of the sub-pixel B of chip C1 is a′, and the distance between the sub-pixel B of chip C1 and the sub-pixel B of chip C3 is g.

[0253] The sum of a' and g can be the pixel size of the pixel unit in chip C1 along the first direction x. The sum of a, b, c, d, e, and f can be the pixel size of the pixel unit along the second direction y. The sum of m and n can be equal to or different from the sum of a, b, c, d, e, and f.

[0254] When the number of sub-pixels in a chipset along the first direction x is 1, the sum of the chip size and the spacing between chipsets along the first direction x can be flexibly adjusted. That is, the sum of a' and g shown in FIG52 can be flexibly adjusted. This can accommodate display panels with different pixel sizes.

[0255] In each LED chip, the spacing between two adjacent sub-pixels can be d1. The spacing between adjacent chip groups can be d2. The spacing between adjacent pixel units can be d3. The spacing between two adjacent LED chips can be d4. d1, d2, d3, and d4 can all be equal. This effectively improves the regularity of the arrangement of each sub-pixel, each LED chip, each LED chip group, and each pixel unit, thereby enhancing light output uniformity.

[0256] Alternatively, d1, d2, d3, and d4 can each be unequal. That is, d1 may not equal d2, d3, or d4; d2 may not equal d3, d4; and d3 may not equal d4. d3 can be determined by the PPI of the full-color display screen fabricated using the LED chipset. Flexible adjustment of d3 enables efficient layout for a variety of applications, from watches to large-screen TVs.

[0257] In the fourth aspect, as shown in Figures 65 and 66, an embodiment of the present application provides a display module, including a driving backplane 200 and the light-emitting diode chipset of the above embodiment, the light-emitting diode chipset is arranged on the driving backplane 200 and electrically connected to the driving backplane 200.

[0258] It should be noted that the driving backplane 200 may be a TFT (Thin Film Transistor) driving backplane 200 or a CMOS (Complementary Metal Oxide Semiconductor) driving backplane 200 .

[0259] It should be noted that, as a first achievable embodiment, as shown in FIG65 , there are multiple LED chip groups, which are arranged in an array on the driver backplane 200. The driver backplane 200 can provide driving current to the multiple LED chip groups, thereby driving the multiple LED chip groups to emit light. FIG65 shows LED chip group CG1 and LED chip group CG2 arranged on the driver backplane 200. In some embodiments, there may be three, four, or more LED chip groups, and the multiple LED chip groups may be arranged in an array.

[0260] LED chip group CG1 and LED chip group CG2 each include LED chip C1 and LED chip C2. Each LED chip includes a pixel subgroup, each of which includes three sub-pixels. In some embodiments, the number of LED chips in the LED chip group, and the number of pixel subgroups and sub-pixels in the LED chip, can be adjusted, and this embodiment does not impose any limitations thereto.

[0261] As a second achievable embodiment, as shown in FIG66 , the driving backplane 200 includes a driving substrate 201 and a plurality of driving units 202. One driving unit 202 is electrically connected to one corresponding light-emitting diode chip group, and the plurality of driving units 202 are electrically connected to the driving substrate 201. The driving units 202 and the driving substrate 201 may also be TFTs and CMOSs.

[0262] A driving unit 202 and an LED chipset can form a micro-display module. FIG66 shows micro-display modules DMB1 and DMB2. Both are electrically connected to a driving substrate 201. The driving substrate 201 can provide driving current to the driving unit 202 in the micro-display module, thereby driving the LED chipset to emit light. In some embodiments, the number of micro-display modules can be three, four, five, or more, and this embodiment does not impose a specific limit on this number.

[0263] FIG66 shows that LED chip group CG1 and LED chip group CG2 are electrically connected to two different drive units 202, respectively. Both drive units 202 are electrically connected to drive substrate 201. Both LED chip group CG1 and LED chip group CG2 include LED chips C1 and C2. Each LED chip includes a pixel subgroup, each of which includes three sub-pixels. In this embodiment, the number of LED chip groups, the number of LED chips in an LED chip group, and the number of pixel subgroups and sub-pixels in an LED chip can be adjusted, and this embodiment does not impose any limitations on this.

[0264] In a fifth aspect, an embodiment of the present application provides a full-color display screen, which can be manufactured by encapsulating the above-mentioned display module.

[0265] In a sixth aspect, embodiments of the present application provide an electronic device comprising the aforementioned full-color display. The electronic device may be a television, an electronic watch, an e-book, a desktop computer, a laptop computer, a tablet computer, a mobile phone, an AR device (Augmented Reality) or a VR device (Virtual Reality). When the light-emitting diode chip of the electronic device includes ultraviolet light pixels, the electronic device may also be a UV curing lamp or a UV detection lamp.

[0266] In the description of the embodiments of the present application, it should be understood that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances. The orientation or position relationship indicated by the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or position relationship shown in the accompanying drawings. It is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In the description of this application, the meaning of "multiple" is two or more, unless otherwise precisely and specifically specified.

[0267] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the numbers used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0268] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A light-emitting diode chip, comprising an N-type electrode, a P-type electrode, and a light-emitting layer disposed between the N-type electrode and the P-type electrode; the light-emitting layer being electrically connected to the N-type electrode and the P-type electrode, respectively; The light-emitting layer includes N light-emitting materials, and the light-emitting wavelengths of the N light-emitting materials are different; along the thickness direction of the light-emitting diode chip, at least one of the N light-emitting materials is stacked with the remaining light-emitting materials; Among the stacked plurality of light-emitting materials, at least one of the light-emitting materials is located on a side of the remaining light-emitting materials close to the P-type electrode, and light emitted by the at least one light-emitting material is used to excite the remaining light-emitting materials to emit light; The N luminescent materials are configured to form M sub-pixels arranged side by side, and at least some of the M sub-pixels have luminous wavelengths of different wavelengths; wherein, Both N and M are positive integers greater than or equal to 3.

2. The light-emitting diode chip according to claim 1, wherein: The M is greater than or equal to the N.

3. The light-emitting diode chip according to claim 1, wherein: Among the stacked light-emitting materials, the light-emitting wavelength of the light-emitting material close to the P-type electrode is smaller than the light-emitting wavelength of the light-emitting material far from the P-type electrode.

4. The light-emitting diode chip according to claim 1, wherein: Among the N light-emitting materials, the light-emitting material with the smallest light-emitting wavelength is stacked on a side of the remaining light-emitting materials close to the P-type electrode.

5. The light-emitting diode chip according to claim 4, wherein: At least a portion of each of the light-emitting materials is electrically connected to the N-type electrode. The light-emitting diode chip according to claim 5 , wherein: The luminescent materials except the luminescent material with the smallest luminescent wavelength are arranged side by side; The light-emitting material with the smallest emission wavelength includes a first portion and a second portion that are connected to each other, the first portion being stacked with the remaining light-emitting materials except the light-emitting material with the smallest emission wavelength; a side of the first portion close to the P-type electrode is electrically connected to the P-type electrode, and different positions of the side of the first portion close to the N-type electrode correspond to different light-emitting materials arranged side by side; The second portion is arranged side by side with the rest of the light-emitting materials except the light-emitting material with the smallest light-emitting wavelength, and the second portion and the rest of the light-emitting materials except the light-emitting material with the smallest light-emitting wavelength close to the N-type electrode are both electrically connected to the N-type electrode; The N luminescent materials arranged side by side correspond to the M sub-pixels respectively.

7. The light-emitting diode chip according to claim 5, wherein: Except for the light-emitting material closest to the N-type electrode, the rest of the light-emitting materials include a first portion and a second portion connected to each other; The remaining first portion of the light-emitting material is stacked along the thickness direction of the light-emitting diode chip; Along a thickness direction intersecting the light emitting diode chip, the rest of the second portion of the light emitting material and the light emitting material closest to the N-type electrode are arranged side by side in sequence and correspond to different sub-pixels respectively.

8. The light-emitting diode chip according to claim 4, wherein: The remaining luminescent materials except the luminescent material with the smallest luminescent wavelength are stacked along the thickness direction of the light emitting diode chip.

9. The light-emitting diode chip according to claim 4, wherein: In the stacked light-emitting materials, different regions arranged along a direction crossing the thickness of the light-emitting diode chip correspond to different sub-pixels.

10. The light-emitting diode chip according to claim 5, wherein: Among the plurality of luminescent materials stacked in layers, several of the luminescent materials form a luminescent material group, and the luminescent layer includes the plurality of luminescent material groups; Along the direction from the P-type electrode to the N-type electrode, a plurality of the light-emitting material groups are arranged in sequence.

11. The light-emitting diode chip according to any one of claims 1 to 10, wherein: The N-type electrode includes M separate sub-N-type electrodes, the sides of the M sub-pixels close to the P-type electrode are electrically connected to the P-type electrode, and the sides of the M sub-pixels close to the N-type electrode are electrically connected to the M sub-N-type electrodes in a one-to-one correspondence; Alternatively, the P-type electrode includes M separate sub-P-type electrodes, the side of the M sub-pixels close to the N-type electrode is electrically connected to the N-type electrode, and the side of the M sub-pixels close to the P-type electrode is electrically connected to the M sub-P-type electrodes one by one.

12. The light-emitting diode chip according to any one of claims 1 to 10, wherein: The N-type electrode includes m mutually separate sub-N-type electrodes, the sides of the M sub-pixels close to the P-type electrode are electrically connected to the P-type electrode, and the sides of the M sub-pixels close to the N-type electrode are electrically connected to the m sub-N-type electrodes; m is less than M, and a portion of the sub-pixels share one sub-N-type electrode; Alternatively, the P-type electrode includes m separate sub-P-type electrodes, a side of the M sub-pixels close to the N-type electrode is electrically connected to the N-type electrode, and a side of the M sub-pixels close to the P-type electrode is electrically connected to the m sub-P-type electrodes; m is less than M, and a part of the sub-pixels shares one sub-P-type electrode.

13. The light-emitting diode chip according to any one of claims 1 to 10, further comprising an isolation structure, wherein the isolation structure is located between any two adjacent sub-pixels; The isolation structure includes a channel; or, the isolation structure includes a channel and an isolation material disposed in the channel; or, the isolation structure is an ion implantation layer.

14. The light-emitting diode chip according to claim 13, further comprising an N-type semiconductor layer and a P-type semiconductor layer, wherein the N-type semiconductor and the P-type semiconductor are located on opposite sides of the light-emitting layer in a thickness direction, the N-type electrode is electrically connected to the light-emitting layer via the N-type semiconductor, and the P-type electrode is electrically connected to the light-emitting layer via the P-type semiconductor. When the N-type electrode includes M separate sub-N-type electrodes, the isolation structure is located between adjacent sub-N-type electrodes, and at least a portion of the isolation structure extends into the P-type semiconductor layer; When the P-type electrode includes M separate sub-P-type electrodes, the isolation structure is located between adjacent sub-P-type electrodes, and at least a portion of the isolation structure extends into the N-type semiconductor layer.

15. The light-emitting diode chip according to any one of claims 1 to 10, further comprising a plurality of filter layers for filtering different wavelengths, wherein the plurality of filter layers are arranged side by side on the light-emitting side of the light-emitting diode chip, and the filter layers correspond one to one to the sub-pixels.

16. The light-emitting diode chip according to any one of claims 1 to 10, further comprising a hole blocking layer, wherein the hole blocking layer is at least arranged between the light-emitting material closest to the P-type electrode and the light-emitting material adjacent to the light-emitting material stack closest to the P-type electrode.

17. The light-emitting diode chip according to claim 16, wherein: The hole blocking layer is also located between any two adjacent light-emitting materials among the stacked light-emitting materials.

18. The light-emitting diode chip according to any one of claims 1 to 10, wherein: The M sub-pixels form a pixel subgroup; Alternatively, the M sub-pixels form a plurality of pixel subgroups, and the plurality of pixel subgroups are arranged in an array in a direction intersecting the thickness direction of the light-emitting diode chip.

19. The light-emitting diode chip according to claim 18, wherein: Among the plurality of sub-pixels in the pixel subgroup, the light-emitting wavelengths of the plurality of sub-pixels are different from each other, or the plurality of sub-pixels include at least two sub-pixels with the same light-emitting wavelength.

20. The light-emitting diode chip according to any one of claims 1 to 10, wherein: M sub-pixels form a plurality of pixel units, and the plurality of pixel units are arranged in an array along a thickness direction intersecting the light-emitting diode chip; One pixel unit includes Y sub-pixels, and the Y sub-pixels include X wavelengths; X is a positive integer greater than or equal to 3, and Y is a positive integer greater than or equal to X.

21. The light-emitting diode chip according to claim 20, wherein: When Y is greater than X, in one pixel unit, at least a portion of the sub-pixels have the same light emission wavelength.

22. The light-emitting diode chip according to claim 20, wherein: All the sub-pixels in the same pixel unit are only used by the pixel unit to which they belong.

23. The light-emitting diode chip according to claim 20, wherein: One pixel unit has two sub-pixels shared with two adjacent pixel units. The number of all sub-pixels in a single light-emitting diode chip is M=a*(2X-2), where a is a positive integer greater than or equal to 1, and a is the number of pixel subgroups composed of all sub-pixels in a single chip. 24 . The light-emitting diode chip according to claim 1 , further comprising a reflective layer, wherein the reflective layer is located on a backlight side of the light-emitting diode chip. 25 . The light-emitting diode chip according to claim 1 , further comprising a light-blocking layer, wherein the light-blocking layer is located on a light-emitting side of the light-emitting diode chip and between two adjacent sub-pixels.

26. The light-emitting diode chip according to any one of claims 1 to 10, wherein: The light-emitting diode chip satisfies at least one of the following requirements: The size of the light emitting diode chip is greater than or equal to 50 microns; The shape of the light emitting diode chip is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram and a polygon with more than four sides; The size of the sub-pixel is in the range of 0.001-200 microns; The shape of the sub-pixel is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram and a polygon with more than four sides; The shapes of the different sub-pixels are the same or different; The sizes of different sub-pixels are equal or different.

27. The light-emitting diode chip according to any one of claims 1 to 10, further comprising a buffer layer, an N-type semiconductor layer, a P-type semiconductor layer, a current spreading layer, a reflective layer, and a first insulating layer; The buffer layer and the N-type semiconductor layer are stacked, the light-emitting layer is arranged on a side of the N-type semiconductor layer away from the buffer layer, and the P-type semiconductor layer is arranged on a side of the light-emitting layer away from the buffer layer; The current spreading layer contacts a side of the P-type semiconductor layer facing away from the buffer layer, the N-type electrode contacts the N-type semiconductor layer, and the P-type electrode contacts the P-type semiconductor layer and the current spreading layer; The first insulating layer is arranged on a side of the current spreading layer away from the buffer layer; The reflective layer is arranged on a side of the buffer layer away from the light-emitting layer, or the reflective layer is arranged on a side of the first insulating layer away from the buffer layer, and a second insulating layer is further arranged on the side of the reflective layer away from the buffer layer.

28. The light-emitting diode chip according to claim 27, further comprising a substrate, wherein the substrate is disposed on a side of the buffer layer away from the light-emitting layer; When the reflective layer is disposed on a side of the buffer layer away from the light-emitting layer, the reflective layer is disposed on a side of the substrate away from the buffer layer.

29. The light-emitting diode chip according to any one of claims 1 to 10, further comprising a bonding substrate, a binding layer, an N-type semiconductor layer, a P-type semiconductor layer, and a reflective layer; The bonding substrate and the binding layer are sequentially arranged on the P-type electrode, and the P-type semiconductor layer is arranged on a side of the binding layer away from the bonding substrate and in contact with the binding layer; The light-emitting layer is provided on a side of the P-type semiconductor layer away from the bonding substrate, the N-type semiconductor layer is provided on a side of the light-emitting layer away from the bonding substrate, and the N-type electrode contacts the side of the N-type semiconductor layer away from the bonding substrate; The reflective layer is arranged on a side of the P-type semiconductor layer close to the bonding substrate. 30 . The light-emitting diode chip according to claim 1 , further comprising a color conversion layer, wherein the color conversion layer is disposed on a portion of the light-emitting side of the light-emitting diode chip and corresponds to at least a portion of the sub-pixel. 31 . A light emitting diode chip group, comprising a plurality of light emitting diode chips according to claim 1 , wherein the plurality of light emitting diode chips are arranged in an array along a thickness direction intersecting the light emitting diode chips.

32. The light emitting diode chip set according to claim 31, wherein: In two adjacent LED chips, the entire area of ​​the sub-pixel of one LED chip and the entire area of ​​the sub-pixel of the other LED chip together constitute a pixel unit.

33. The light emitting diode chip set according to claim 32, wherein: In two adjacent LED chips, a partial area of ​​the sub-pixel of one LED chip and a partial area of ​​the sub-pixel of the other LED chip together constitute a pixel unit.

34. The light emitting diode chip set according to any one of claims 31 to 33, wherein: The two adjacent light-emitting diode chips are both irregular in shape; one of the two adjacent light-emitting diodes has a protruding area, and the other has a concave area; the protruding area and the concave area are adapted in shape and fit together.

35. The light emitting diode chip set according to any one of claims 31 to 33, wherein: The plurality of light-emitting diode chips form a plurality of light-emitting diode chip groups arranged in an array and a plurality of pixel units arranged in an array; in the same light-emitting diode chip, the spacing between adjacent sub-pixels is d1; the spacing between adjacent light-emitting diode chip groups is d2; the spacing between adjacent pixel units is d3; and the spacing between adjacent light-emitting diode chips is d4; d1, d2, d3 and d4 are all equal, or d1, d2, d3 and d4 are not equal to each other.

36. A display module comprising a driving backplane and the light-emitting diode chipset according to any one of claims 31 to 35, wherein the light-emitting diode chipset is disposed on the driving backplane and electrically connected to the driving backplane.

37. The display module according to claim 36, wherein the light emitting diode chip group has a plurality of light emitting diode chips; The plurality of light emitting diode chip groups are arranged in an array on the driving backplane; Alternatively, the driving backplane includes a driving substrate and a plurality of driving units, one driving unit is electrically connected to one light emitting diode chip group, and the plurality of driving units are electrically connected to the driving substrate.

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