Level shifter circuit

Abstract

A level shifter circuit (1) comprises first through fourth P-type transistors, first and second N-type transistors, and a pull-up circuit (30). The first N-type transistor and the first P-type transistor are provided between an input node and an output node, and the second P-type transistor is provided between a first power supply and the output node. The second N-type transistor and the third P-type transistor are provided between an inverting input node and an inverting output node, and the fourth P-type transistor is provided between the first power supply and the inverting output node. The pull-up circuit (30) is configured to pull a second node up to a third power supply when a first node transitions from high level to low level and to pull the first node up to the third power supply when the second node transitions from high level to low level.

Description

Level Shift Circuit

[0001] The present invention relates to a level shift circuit that converts the voltage of a signal to a required level when the signal is transmitted between circuits supplied with different power supply voltages.

[0002] A level shift circuit is used, for example, in an interface section that transmits a signal from a circuit that operates at a relatively low voltage inside an LSI to a circuit that operates at a relatively high voltage outside the LSI, and converts the voltage of the signal.

[0003] In recent years, as transistors have become smaller, the voltage stress (withstand voltage) that transistors can tolerate has been decreasing. Against this background, a level shift circuit that performs voltage conversion within a predetermined withstand voltage range has been disclosed in prior art documents.

[0004] The level shift circuit in Patent Document 1 is configured to boost the low-level voltage in addition to boosting the high-level voltage. By lowering the voltage between the low and high levels in this way, the voltage applied between the terminals of the transistor (for example, between the gate and source, or between the source and drain) is lowered, and voltage stress on the transistor is alleviated.

[0005] U.S. Patent No. 7,151,391

[0006] However, in the case of the configuration shown in FIG. 1 of Patent Document 1, a problem arises in that the operation of the level shift circuit cannot keep up with the demand for lower operating voltages due to the demand for lower power consumption and / or faster circuit operation to meet the demand for higher functionality.

[0007] The present disclosure aims to solve the above problems.

[0008] a second P-type transistor disposed between the output node and the first power supply and having a gate connected to the first node; an inverting input node receiving an inverted input signal obtained by inverting the input signal; a second N-type transistor disposed between the output node and the first power supply and having a gate connected to the first node; a third P-type transistor disposed between the second node and an inverting output node and having a gate connected to the first power supply; a fourth P-type transistor disposed between the inverting output node and the first power supply and having a gate connected to the second node; The device includes a first pull-up circuit that supplies the voltage of the third power supply to the output node when an inverted signal of the output signal transitions from a high level to a low level, and a second pull-up circuit that is provided between the third power supply and the inverted output node and that supplies the voltage of the third power supply to the inverted output node when the output signal transitions from a high level to a low level.

[0009] In the level shift circuit of this aspect, the first pull-up circuit supplies the voltage of the third power supply to the output node when the inverted signal of the output signal transitions from high to low, thereby quickly increasing the voltage at the output node. Similarly, the second pull-up circuit supplies the voltage of the third power supply to the inverted output node when the output signal transitions from high to low, thereby quickly decreasing the voltage at the output node. This prevents delays in the output signal output to the output node, enabling the circuit to operate at a higher speed than when no pull-up circuit is provided.

[0010] Furthermore, the level shift circuit of this embodiment is configured with two power supplies, the first power supply and the third power supply, and does not use a bias voltage (corresponding to VBIAS in Patent Document 1), meaning that a circuit for generating a bias voltage is not required.

[0011] In the present disclosure, a level shift circuit can achieve a lower operating voltage and / or faster circuit operation.

[0012] FIG. 1 is a circuit diagram showing an example of a level shift circuit according to a first embodiment; FIG. 2 is a diagram showing an example of a voltage waveform at each node of the level shift circuit according to the first embodiment; FIG. 3 is a circuit diagram showing a modified example of the level shift circuit according to the first embodiment; FIG. 4 is a circuit diagram showing an example of a level shift circuit according to a second embodiment; FIG. 5 is a diagram showing an example of a voltage waveform at each node of the level shift circuit according to the second embodiment;

[0013] The following describes embodiments. Note that specific numerical values ​​and the like shown in the following embodiments are merely examples to facilitate understanding of the invention and are not intended to limit the scope of the invention. In this disclosure, the term "connection" is used to refer to not only direct connections between elements, but also indirect connections between elements via elements such as transistors. Furthermore, in the following description, common symbols or names may be used for nodes or terminals of a circuit and signals passing through those nodes or terminals, and common symbols may be used for the names of power supplies and the power supply voltages of those power supplies. Furthermore, the voltage of a power supply may be described simply using the symbol of that power supply.

[0014] First Embodiment A level shift circuit 1 is configured with two power supplies, a first power supply VDD and a third power supply VDDIO, and is a circuit that boosts a high-level voltage from VDD to VDDIO and boosts a low-level voltage from VSS to VDD. The third power supply VDDIO is a power supply with a higher voltage than the first power supply VDD. In the following description, a low level may be simply referred to as 'L' and a high level may be simply referred to as 'H'.

[0015] The level shift circuit 1 receives an input signal in that transitions between a first power supply VDD and a ground VSS (corresponding to a second power supply) from an input terminal IN (input node in), and outputs an output signal out that transitions between a third power supply VDDIO and the first power supply VDD from an output terminal OUT (output node out). In other words, the input signal in is a signal with an amplitude of VDD, and the output signal out is a signal with an amplitude of (VDDIO-VDD).

[0016] FIG. 1 shows an example of a circuit diagram of a level shift circuit 1 according to the first embodiment.

[0017] Level shift circuit 1 includes voltage conversion circuits 10 and 20, pull-up circuits 30 and 40, pull-down circuits 50 and 60, a delay circuit 70, and an inverter 2 that inverts an input signal in to generate an inverted input signal inb. In level shift circuit 1, voltage conversion circuits 10 and 20 have symmetrical configurations. Similarly, pull-up circuits 30 and 40 have symmetrical configurations, and pull-down circuits 50 and 60 have symmetrical configurations.

[0018] The inverter 2 receives an input signal in via an input node in and outputs an inverted input signal inb to an inverted input node inb of the voltage conversion circuit 20. The power supply terminal of the inverter 2 is connected to a first power supply VDD, and the ground terminal is connected to a ground VSS. The inverter 2 may be omitted from the level shift circuit 1 of FIG. 1. In that case, for example, the input signal in and the inverted input signal inb are generated in a circuit (not shown) preceding the level shift circuit 1, and the input signal in is input to the input node in of the voltage conversion circuit 10, and the inverted input signal inb is input to the inverted input node inb of the voltage conversion circuit 20, thereby functioning in the same way as the circuit of FIG. 1. This also applies to other figures (other embodiments).

[0019] - Voltage Conversion Circuit - The voltage conversion circuits 10 and 20 are circuits that convert an input voltage input to an input terminal IN into a boost voltage and output the boost voltage from an output terminal OUT.

[0020] The voltage conversion circuit 10 includes an N-type transistor N1 and P-type transistors P1, P3, and P5. Note that the N-type transistor and the P-type transistor in the present disclosure are, for example, transistors with a MOS structure.

[0021] The input node in of the voltage conversion circuit 10 is connected to the input terminal IN, and receives the input signal in. In this disclosure, the term "connection" is a broad concept that encompasses electrical connection, and includes direct connection as well as indirect electrical connection via a passive element or the like (not shown).

[0022] An N-type transistor N1 (corresponding to a first N-type transistor) is provided between an input node in and a node n1 (corresponding to a first node), with its gate connected to a first power supply VDD. A P-type transistor P3 (corresponding to a first P-type transistor) is provided between the node n1 and an output node out, with its gate connected to the first power supply VDD. In other words, the N-type transistor N1 and the P-type transistor P3 are connected in series between the input node in and the output node out. A P-type transistor P1 (corresponding to a fifth P-type transistor) is provided between a third power supply VDDIO and the output node out, with its gate connected to an inverted output node outb. A P-type transistor P5 (corresponding to a second P-type transistor) is provided between the output node out and the first power supply VDD, with its gate connected to the node n1.

[0023] The voltage conversion circuit 20 includes an N-type transistor N2 and P-type transistors P2, P4, and P6. An inverting input node inb, which is an input node of the voltage conversion circuit 20, is connected to the output of the inverter 2 and receives an inverting input signal inb.

[0024] An N-type transistor N2 (corresponding to a second N-type transistor) is provided between the inverting input node inb and a node n2 (corresponding to a second node), with its gate connected to the first power supply VDD. A P-type transistor P4 (corresponding to a third P-type transistor) is provided between the node n2 and the inverting output node outb, with its gate connected to the first power supply VDD. In other words, the N-type transistor N2 and the P-type transistor P4 are connected in series between the inverting input node inb and the inverting output node outb. A P-type transistor P2 (corresponding to a sixth P-type transistor) is provided between the third power supply VDDIO and the inverting output node outb, with its gate connected to the output node out. A P-type transistor P6 (corresponding to a fourth P-type transistor) is provided between the inverting output node outb and the first power supply VDD, with its gate connected to the node n2.

[0025] As described above, the P-type transistor P1 is connected between the third power supply VDDIO and the output node out, and the P-type transistor P2 is connected between the third power supply VDDIO and the inverted output node outb. Furthermore, the gate of the P-type transistor P1 is connected to the inverted output node outb, and the gate of the P-type transistor P2 is connected to the output node out, forming a so-called cross-coupled connection.

[0026] -Delay Circuit- The delay circuit 70 generates a signal n4 (corresponding to a first delayed signal) by delaying the output signal out, and a signal n6 (corresponding to a second delayed signal) by delaying the inverted output signal outb (corresponding to an inverted signal).

[0027] In this example, the delay circuit 70 includes an inverter circuit 71 and an inverter circuit 72. The inverter circuit 71 receives the output signal out as an input and outputs a signal n6 obtained by inverting the output signal out to a node n6. In other words, the inverter circuit 71 outputs a signal n6 obtained by delaying the inverted output signal outb to a node n6. The signal n6 is a signal whose 'H' is equal to voltage VDDIO and whose 'L' is equal to voltage VDD. The inverter circuit 72 receives the inverted output signal outb as an input and outputs a signal n4 obtained by inverting the inverted output signal outb to a node n4. In other words, the inverter circuit 72 outputs a signal n4 obtained by delaying the output signal out to a node n4.

[0028] The delay circuit 70 is not limited to the configuration shown in FIG. 1 , and may have other circuit configurations to achieve the function of "outputting a signal n4 obtained by delaying the output signal out and a signal n6 obtained by delaying the inverted output signal outb." For example, instead of the inverted output signal outb, the signal n6 may be provided to the input of the inverter circuit 72. That is, the node n6 may be connected to the input of the inverter circuit 72. Alternatively, other conventionally known delay circuits may be used as the delay circuit 70. This also applies to the modified example of this embodiment, the second embodiment, and the modified example of the second embodiment.

[0029] The pull-up circuit 30 is provided between the third power supply VDDIO and the output node out, and supplies the voltage VDDIO (the voltage of the third power supply VDDIO) to the output node out for a predetermined period based on the inverted output signal outb (the signal at the inverted output node outb). Specifically, when the inverted output signal outb transitions from high to low, the pull-up circuit 30 supplies VDDIO to the output node out.

[0030] In this example, the pull-up circuit 30 includes a P-type transistor P7 (corresponding to the fifth and seventh P-type transistors) and a P-type transistor P8 (corresponding to the sixth and eighth P-type transistors) connected in series between the third power supply VDDIO and the output node out. The P-type transistor P7 is connected between the third power supply VDDIO and a node n3 (corresponding to the third node), and its gate is connected to a node n4. That is, a signal n4, which is a delayed version of the output signal out, is applied to the gate of the P-type transistor P7. The P-type transistor P8 is connected between the node n3 and the output node out, and its gate is connected to an inverted output node outb. Note that the pull-up circuit 30 is not limited to the configuration shown in FIG. 1 , and other circuit configurations may be used to realize the function of supplying VDDIO to the output node out when the inverted output signal outb transitions from high to low.

[0031] The pull-up circuit 40 is provided between the third power supply VDDIO and the inverting output node outb, and supplies the voltage VDDIO (the voltage of the third power supply VDDIO) to the inverting output node outb for a predetermined period based on the output signal out (the signal at the output node). Specifically, when the output signal out transitions from high level to low level, the pull-up circuit 40 supplies the voltage VDDIO to the inverting output node outb.

[0032] In this example, the pull-up circuit 40 includes a P-type transistor P9 (corresponding to the seventh and ninth P-type transistors) and a P-type transistor P10 (corresponding to the eighth and tenth P-type transistors) connected in series between the third power supply VDDIO and the inverting output node outb. The P-type transistor P9 is connected between the third power supply VDDIO and a node n5 (corresponding to the fourth node), and its gate is connected to the node n6. That is, the signal n6, which is a delayed version of the inverting output signal outb, is applied to the gate of the P-type transistor P9. The P-type transistor P10 is connected between the node n5 and the inverting output node outb, and its gate is connected to the output node out. Note that the pull-up circuit 40 is not limited to the configuration shown in FIG. 1 , and other circuit configurations may be used to realize the function of supplying VDDIO to the inverting output node outb when the output signal out transitions from high to low. The specific operations of the pull-up circuits 30 and 40 will be explained later.

[0033] The pull-down circuit 50 is provided between the output node out and the first power supply VDD, and supplies the voltage VDD (the voltage of the first power supply VDD) to the output node out for a predetermined period based on the signal n1 (the signal at the node n1). Specifically, when the signal n1 transitions from high to low, the pull-down circuit 50 supplies VDD to the output node out.

[0034] In this example, the pull-down circuit 50 includes a P-type transistor P11 (corresponding to the fifth P-type transistor or eleventh P-type transistor) and an N-type transistor N3 (corresponding to the third N-type transistor) connected in series between the output node out and the first power supply VDD. The P-type transistor P11 is connected between the output node out and a node n7 (corresponding to the third node or fifth node), and its gate is connected to the node n1. The N-type transistor N3 is connected between the node n7 and the first power supply VDD, and its gate is connected to the node n4. That is, a signal n4, which is a delayed version of the output signal out, is applied to the gate of the N-type transistor N3. Note that the pull-down circuit 50 is not limited to the configuration shown in FIG. 1 , and other circuit configurations may be used to realize the function of supplying VDD to the output node out when the signal n1 transitions from high to low.

[0035] The pull-down circuit 60 is provided between the inverting output node outb and the first power supply VDD, and supplies the voltage VDD (the voltage of the first power supply VDD) to the inverting output node outb for a predetermined period based on the signal n2 (the signal at the node n2). Specifically, when the signal n2 transitions from a high level to a low level, the pull-down circuit 60 supplies VDD to the inverting output node outb.

[0036] In this example, the pull-down circuit 60 includes a P-type transistor P12 (corresponding to a sixth P-type transistor or a twelfth P-type transistor) and an N-type transistor N4 (corresponding to a fourth N-type transistor) that are connected in series between the inverting output node outb and the first power supply VDD. The P-type transistor P12 is connected between the inverting output node outb and a node n8 (corresponding to a fourth node or a sixth node), and its gate is connected to a node n2. The N-type transistor N4 is connected between the node n8 and the first power supply VDD, and its gate is connected to a node n6. That is, a signal n6, which is a delayed version of the inverting output signal outb, is applied to the gate of the N-type transistor N4. Note that the pull-down circuit 60 is not limited to the configuration of FIG. 1 , and other circuit configurations may be used to realize the function of supplying VDD to the inverting output node outb when the signal n2 transitions from high to low.

[0037] 1, or alternatively, either the pull-up circuits 30 and 40 or the pull-down circuits 50 and 60 may be provided, depending on the characteristics of the level shift circuit 1. The same applies to the modified example of this embodiment, the second embodiment, and the modified example of the second embodiment.

[0038] [Operation of Level Shift Circuit] Next, the operation of the level shift circuit 1 according to this embodiment will be described with reference to FIG. 2 . In FIG. 2 , waveforms when the pull-up circuits 30, 40 and the pull-down circuits 50, 60 are provided are indicated by solid lines, and waveforms when the pull-up circuits 30, 40 and the pull-down circuits 50, 60 are not provided are indicated by dashed lines. In the following description, the voltage of a node or terminal may be written as "(node ​​name or terminal name) = (voltage)." For example, if the voltage of the input node in is VDD, it may be written as "in = VDD." Furthermore, the gate-source voltage Vgs of a transistor may be written simply as "Vgs" or "Vgs (denoting the voltage between two points)."

[0039] --Operation Example (1-1)-- Here, the operation when in=VSS and out=VDD, that is, the operation when 'L' is input and 'L' is output, will be described.

[0040] (Voltage Conversion Circuit) In the voltage conversion circuit 10, the input signal in is 'L', so the N-type transistor N1 turns on, n1=VSS, and the P-type transistor P5 turns on. As a result, out=VDD, the P-type transistor P3 turns off, and in the voltage conversion circuit 20, the P-type transistor P2 turns on. As a result, outb=VDDIO, and the P-type transistor P1 turns off. Furthermore, the P-type transistor P4 turns on, n2=VDDIO, and the P-type transistor P6 and the N-type transistor N2 turn off.

[0041] (Pull-up Circuit) As described above, since outb=VDDIO, P-type transistor P8 is turned off in pull-up circuit 30. Furthermore, in pull-up circuit 40, n6=VDDIO due to the output of delay circuit 70, so P-type transistor P9 is turned off. As a result, there is no conduction between the third power supply VDDIO and the output node out or inverted output node outb via pull-up circuits 30 and 40.

[0042] (Pull-down circuit) Because n4=VDD due to the output of delay circuit 70, N-type transistor N3 is turned off in pull-down circuit 50. As described above, n2=VDDIO, so P-type transistor P12 is turned off in pull-down circuit 60. As a result, there is no conduction between the first power supply VDD and the output node out or the inverted output node outb via pull-down circuits 50 and 60.

[0043] --Operation Example (1-2)-- Here, the operation when in=VDD and out=VDDIO, that is, the operation when 'H' is input and 'H' is output, will be described.

[0044] (Voltage Conversion Circuit) Because the voltage conversion circuits 10 and 20 have symmetrical configurations, the operation is contrary to the above-described "Operation Example (1-1)." Specifically, in the voltage conversion circuit 20, the inverted input signal inb is 'L', so the N-type transistor N2 turns on, n2=VSS, and the P-type transistor P6 turns on. As a result, outb=VDD, the P-type transistor P4 turns off, and in the voltage conversion circuit 10, the P-type transistor P1 turns on. As a result, out=VDDIO, and the P-type transistor P2 turns off. Furthermore, the P-type transistor P3 turns on, n1=VDDIO, and the P-type transistor P5 and the N-type transistor N1 turn off.

[0045] (Pull-up Circuit) As described above, since out=VDDIO, P-type transistor P10 is turned off in pull-up circuit 40. Furthermore, since n4=VDDIO due to the output of delay circuit 70, P-type transistor P7 is turned off in pull-up circuit 30. As a result, there is no conduction between the third power supply VDDIO and the output node out or inverted output node outb via pull-up circuits 30 and 40.

[0046] (Pull-down circuit) Because n6=VDD due to the output of delay circuit 70, N-type transistor N4 is turned off in pull-down circuit 60. As described above, n1=VDDIO, so P-type transistor P11 is turned off in pull-down circuit 50. As a result, there is no conduction between the first power supply VDD and the output node out and the inverted output node outb via pull-down circuits 50 and 60.

[0047] --Operation example (1-3)--Here, we will explain the operation when in=VSS changes to in=VDD and out=VDD changes to out=VDDIO, that is, the operation when the input signal in changes from 'L' to 'H' and the output signal out changes from 'L' to 'H'.

[0048] (Voltage Conversion Circuit) In the voltage conversion circuits 10 and 20, the on / off state of each transistor and the voltage of each node transition from the above-described "operation example (1-1)" to "operation example (1-2)."

[0049] 2, node n1 starts to rise from ground VSS as the input signal in rises. During this process, if Vgs (the voltage between VDD and in) of N-type transistor N1 falls below the threshold, N-type transistor N1 turns off, and the rise of signal n1 stops midway.

[0050] The voltage of node n2 drops from VDDIO toward VSS as the inverted input signal inb falls. Furthermore, the inverted output signal outb drops from VDDIO toward VDD until the Vgs (voltage between VDD and outb) of P-type transistor P4 falls below the threshold and P-type transistor P4 turns off. During this drop, if the Vgs (voltage between outb and VDDIO) of P-type transistor P1 exceeds the threshold, P-type transistor P1 turns on, and the output signal out begins to rise from VDD toward VDDIO. Furthermore, during the drop in the voltage of node n2 from VDDIO, if the Vgs (voltage between n2 and VDD) of P-type transistor P6 exceeds the threshold, P-type transistor P6 turns on.

[0051] As the voltage of the output node out rises from VDD toward VDDIO, if the Vgs (voltage between out and VDDIO) of the P-type transistor P2 falls below the threshold, the P-type transistor P2 turns off, causing the inverted output node outb to drop toward VDD. During this process, if the Vgs (voltage between VDD and out) of the P-type transistor P3 exceeds the threshold, the P-type transistor P3 turns on, and the voltage of the node n1 rises again together with the output signal out. Then, as the voltage of the node n1 rises and the Vgs (voltage between n1 and VDD) of the P-type transistor P5 falls below the threshold, the P-type transistor P5 turns off, causing the output signal out to rise to VDDIO.

[0052] (Pull-Up Circuit) First, the operation of the pull-up circuit 30 will be described. As described above, the voltage at the inverting output node outb drops from VDDIO toward VDD, but the voltage at node n4 remains at VDD until the inverter circuit 72 outputs an inverted signal of the inverting output signal outb, i.e., for the propagation delay time of the inverter circuit 72. During this propagation delay time, the P-type transistor P7 is turned on. As the voltage at the inverting output node outb drops, if the Vgs (voltage between outb and n3) of the P-type transistor P8 exceeds the threshold, the P-type transistor P8 turns on, establishing electrical continuity between the third power supply VDDIO and the output node out. As a result, the pull-up circuit 30 assists the voltage at the output node out in transitioning from VDD to VDDIO during the period when the P-type transistor P7 is turned on. In other words, when the inverted output signal outb transitions from a high level to a low level, the pull-up circuit 30 supplies VDDIO to the output node out, thereby assisting the voltage of the output node out in transitioning from a low level to a high level.

[0053] Next, the operation of the pull-up circuit 40 will be described. As described above, the voltage of the output node out rises from VDD toward VDDIO, but the voltage of the node n6 remains at VDDIO until the inverter circuit 71 outputs an inverted signal of the output signal out, i.e., for the propagation delay time of the inverter circuit 71. During this propagation delay time, the P-type transistor P9 is off. As the voltage of the output node out rises, if the Vgs of the P-type transistor P10 (the voltage between out and n5) falls below the threshold, the P-type transistor P10 turns off. As a result, the pull-up circuit 40 maintains a state in which no conduction is established between the third power supply VDDIO and the inverted output node outb.

[0054] (Pull-Down Circuit) First, the operation of the pull-down circuit 50 will be described. During the propagation delay time of the inverter circuit 72 described above, that is, when the voltage of node n4 is maintained at VDD, N-type transistor N3 is off. While N-type transistor N3 is off, the voltage of node n1 rises from VDD, and when Vgs (the voltage between n1 and n7) of P-type transistor P11 falls below the threshold, P-type transistor P11 is turned off. This maintains a state in which no conduction is established between the output node out and the first power supply VDD via the pull-down circuit 50.

[0055] Next, the operation of the pull-down circuit 60 will be described. During the propagation delay time of the inverter circuit 71 described above, i.e., when the voltage of node n6 is maintained at VDDIO, N-type transistor N4 is on. While N-type transistor N4 is on, the voltage of node n2 drops from VDDIO, and when Vgs (the voltage between n2 and n8) of P-type transistor P12 exceeds the threshold, P-type transistor P12 turns on. This brings the inverting output node outb and the first power supply VDD into electrical continuity. As a result, the pull-down circuit 60 assists the transition of the voltage of the inverting output node outb from VDDIO to VDD during the period when N-type transistor N4 is on. In other words, when the voltage of node n2 transitions from high to low, VDD is supplied to the inverting output node outb, thereby assisting the transition of the inverting output node outb from high to low. When the inverting output node outb transitions from high to low quickly, the P-type transistor P1 turns on quickly, which assists the output node out in transitioning from low (VDD) to high (VDDIO).

[0056] --Operation example (1-4)--Here, we will explain the operation when in=VDD changes to in=VSS and out=VDDIO changes to out=VDD, that is, the operation when the input signal in changes from 'H' to 'L' and the output signal out changes from 'H' to 'L'.

[0057] (Voltage Conversion Circuit) In the voltage conversion circuits 10 and 20, the on / off state of each transistor and the voltage of each node transition from the above-described "operation example (1-2)" to the "operation example (1-1)" state.

[0058] 2, node n2 starts to rise from ground VSS as the inverted input signal inb rises. During this process, if Vgs (the voltage between VDD and inb) of N-type transistor N2 falls below the threshold, N-type transistor N2 turns off, and the voltage rise at node n2 stops midway.

[0059] The voltage of node n1 begins to drop from VDDIO toward VSS as the input signal in falls. Furthermore, the output signal out drops from VDDIO toward VDD until the Vgs (voltage between VDD and out) of P-type transistor P3 falls below the threshold and P-type transistor P3 turns off. During this drop, if the Vgs (voltage between out and VDDIO) of P-type transistor P2 exceeds the threshold, P-type transistor P2 turns on, and the inverted output signal outb begins to rise from VDD toward VDDIO. Furthermore, during the drop in the voltage of node n1 from VDDIO, if the Vgs (voltage between n1 and VDD) of P-type transistor P5 exceeds the threshold, P-type transistor P5 turns on, and the output signal out begins to drop from VDDIO toward VDD.

[0060] As the voltage of the output node outb rises from VDD toward VDDIO, if the Vgs (voltage between VDD and outb) of the P-type transistor P4 exceeds the threshold, the P-type transistor P4 turns on, and the signal n2 rises again together with the inverted output signal outb. Then, as the voltage of the node n2 rises and the Vgs (voltage between n2 and VDD) of the P-type transistor P6 falls below the threshold, the P-type transistor P6 turns off, and the inverted output signal outb rises to VDDIO. During this process, if the Vgs (voltage between outb and VDDIO) of the P-type transistor P1 falls below the threshold, the P-type transistor P1 turns off, and the output node out drops to VDD.

[0061] (Pull-Up Circuit) First, the operation of the pull-up circuit 30 will be described. As described above, the voltage of the inverting output node outb rises from VDD toward VDDIO, but the voltage of node n4 remains at VDDIO until the inverter circuit 72 outputs an inverted signal of the inverting output signal outb, i.e., for the propagation delay time of the inverter circuit 72. During this propagation delay time, the P-type transistor P7 remains off. As the voltage of the inverting output node outb rises, if the Vgs of the P-type transistor P8 (the voltage between outb and n3) falls below the threshold, the P-type transistor P8 turns off. This maintains a non-conductive state between the third power supply VDDIO and the output node out in the pull-up circuit 30.

[0062] Next, the operation of the pull-up circuit 40 will be described. As described above, the voltage at the output node out drops from VDDIO toward VDD, but the voltage at the node n6 remains at VDD until the inverter circuit 71 outputs an inverted signal of the output signal out, i.e., during the propagation delay time of the inverter circuit 71. During this propagation delay time, the P-type transistor P9 is on. During this process of the voltage at the output node out dropping, if the Vgs (voltage between out and n5) of the P-type transistor P10 exceeds the threshold, the P-type transistor P10 turns on, establishing electrical continuity between the third power supply VDDIO and the inverted output node outb. As a result, the pull-up circuit 40 assists the voltage at the inverted output node outb in transitioning from VDD to VDDIO during the period when the P-type transistor P9 is on. In other words, when the output signal out transitions from high to low, the pull-up circuit 40 supplies VDDIO to the inverting output node outb, thereby assisting the transition of the voltage of the inverting output node outb from low to high. If the transition of the inverting output node outb from low to high becomes faster, the P-type transistor P1 turns off earlier, which also assists the transition of the output node out from high (VDDIO) to low (VDD).

[0063] (Pull-Down Circuit) First, the operation of the pull-down circuit 50 will be described. During the propagation delay time of the inverter circuit 72 described above, i.e., when the voltage of node n4 is maintained at VDDIO, N-type transistor N3 is on. While N-type transistor N3 is on, the voltage of node n1 drops from VDDIO, and when Vgs (the voltage between n1 and n7) of P-type transistor P11 exceeds the threshold, P-type transistor P11 turns on. This brings the output node out and the first power supply VDD into conduction. As a result, the pull-down circuit 50 assists the transition of the voltage of the output node out from VDDIO to VDD during the period when N-type transistor N3 is on. In other words, when the voltage of node n1 transitions from high to low, VDD is supplied to the output node out, thereby assisting the transition of the output node out from high to low.

[0064] Next, the operation of the pull-down circuit 60 will be described. During the propagation delay time of the inverter circuit 71 described above, that is, when the voltage of node n6 is maintained at VDD, N-type transistor N4 is off. While N-type transistor N4 is off, the voltage of node n2 rises from VDD, and when Vgs (the voltage between n2 and n8) of P-type transistor P12 falls below the threshold, P-type transistor P12 is turned off. This maintains a state in which conduction is not established between the inverting output node outb and the first power supply VDD via the pull-down circuit 60.

[0065] [Effects of the First Embodiment] As described above, by adopting the configuration of this embodiment, the output signal out is not delayed compared to when the pull-up circuits 30, 40 and the pull-down circuits 50, 60 are not provided, and the circuit can be made faster.

[0066] Specifically, in the operation example (1-3), the pull-up circuit 30 supplies VDDIO to the output node out when the inverted output signal outb transitions from high to low, thereby speeding up the voltage rise at the output node out. Furthermore, the pull-down circuit 60 supplies VDD to the inverted output node outb when the voltage at node n2 transitions from high to low, thereby speeding up the voltage drop at the inverted output node outb. When the inverted output node outb transitions from high to low, the P-type transistor P1 turns on earlier, which also assists in the transition of the output node out from low (VDD) to high (VDDIO). This prevents delays in the transition of the output signal out from low to high.

[0067] Similarly, in the operation example (1-4), the pull-up circuit 40 supplies VDDIO to the inverting output node outb when the output signal out transitions from high to low, thereby speeding up the voltage rise at the inverting output node outb. The faster the transition of the inverting output node outb from low to high, the faster the P-type transistor P1 turns off, thereby assisting the transition of the output node out from high (VDDIO) to low (VDD). Furthermore, the pull-down circuit 50 supplies VDD to the output node out when the voltage at node n1 transitions from high to low, thereby speeding up the voltage drop at the output node out. This prevents a delay in the transition of the output signal out from high to low.

[0068] In addition, since the level shift circuit 1 of this embodiment is provided with the inverter 2, the propagation time of the signal from the input terminal IN to the output terminal OUT is longer in the operation example (1-3) than in the operation example (1-4). Therefore, if the signal propagation time becomes longer as the operating voltage decreases, the difference will widen, but this embodiment can suppress this.

[0069] Furthermore, the level shift circuit 1 of this embodiment is configured with two power supplies, a first power supply VDD and a third power supply VDDIO, and does not use a bias voltage (corresponding to VBIAS in Patent Document 1), meaning that a circuit for generating a bias voltage is not required.

[0070] As described above, the level shift circuit 1 may be provided with either the pull-up circuits 30, 40 or the pull-down circuits 50, 60, and the same effect can be obtained.

[0071] <Modification> Fig. 3 shows a modification of the level shift circuit 1 according to the first embodiment. In Fig. 3, components corresponding to those in Fig. 1 are assigned the same reference numerals as in Fig. 1. The following description will focus on the differences from the first embodiment.

[0072] In addition to the configuration of the first embodiment, the level shift circuit 1 of this embodiment has a capacitance C1 (corresponding to a first capacitance) provided between the output node out and node n1, and a capacitance C2 (corresponding to a second capacitance) provided between the inverting output node outb and node n2. The configurations of the capacitances C1 and C2 are not particularly limited. For example, capacitance elements may be used as the capacitances C1 and C2, or transistor capacitances such as gate capacitance or S / D capacitance (source-drain capacitance) may be used. The same applies to a modified example of the second embodiment (including capacitances C3 and C4) described later.

[0073] [Operation of Level Shift Circuit] Next, the operation of the level shift circuit 1 according to this modification will be described. Here, the operations of the voltage conversion circuits 10 and 20, the pull-up circuits 30 and 40, and the pull-down circuits 50 and 60 will be described together. In addition, the differences from the first embodiment will be mainly described, and the description of the operation examples (1-1) and (1-2) common to the first embodiment will be omitted.

[0074] --Operation Example (1-3)-- Here, an operation when in changes from VSS to VDD and out changes from VDD to VDDIO will be described.

[0075] As in the first embodiment, in the voltage conversion circuits 10 and 20, the on / off states of each transistor and the voltages of each node transition from the state of "Operation Example (1-1)" to the state of "Operation Example (1-2)" described above. Here, by providing the capacitors C1 and C2, the transition of the voltages of some nodes differs from that of the first embodiment.

[0076] Due to AC coupling between node n1 and output node out by capacitor C1, the voltage of node n1 rises in conjunction with the rising edge of output node out, regardless of the on-state of P-type transistor P3. This reduces the stagnation period of the voltage rise at node n1, as shown in the first embodiment, and signal n1 rises earlier than in the first embodiment. This causes P-type transistor P5 to turn off earlier than in the first embodiment. Due to AC coupling between node n2 and inverting output node outb by capacitor C2, the voltage of inverting output node outb drops in conjunction with the falling edge of the voltage at node n2, regardless of the on-state of P-type transistor P6. This causes the voltage of inverting output node outb to drop earlier than in the first embodiment, so that P-type transistor P1 turns on earlier than in the first embodiment, and accordingly, P-type transistor P2 turns off earlier. As a result, output signal OUT rises from VDD to VDDIO earlier than in the first embodiment.

[0077] --Operation Example (1-4)-- Here, an operation when in changes from in=VDD to in=VSS and out changes from out=VDDIO to out=VDD will be described.

[0078] As in the first embodiment, in the voltage conversion circuits 10 and 20, the on / off state of each transistor and the voltage of each node transition from the state of "Operation Example (1-2)" described above to the state of "Operation Example (1-1)." Here, the provision of the capacitors C1 and C2 results in a difference in the transition of the voltage of some nodes compared to the first embodiment. Note that, since the voltage conversion circuits 10 and 20 have symmetrical configurations, the operation is opposite to that of "Operation Example (1-3)."

[0079] Specifically, due to AC coupling between node n2 and inverting output node outb by capacitor C2, the voltage of node n2 rises in conjunction with the rising edge of inverting output node outb, regardless of the on-state of P-type transistor P4. This reduces the stagnation period of the voltage rise at node n2, as shown in the first embodiment, and the voltage of node n2 rises more quickly than in the first embodiment. This causes P-type transistor P6 to turn off more quickly than in the first embodiment. Furthermore, due to AC coupling between node n1 and output node out by capacitor C1, output node out drops in conjunction with the falling edge of the voltage at node n1, regardless of the on-state of P-type transistor P5. This causes the voltage of output node out to drop more quickly than in the first embodiment, so P-type transistor P2 turns on more quickly than in the first embodiment, and accordingly, P-type transistor P1 turns off more quickly. As a result, the output signal out drops from VDDIO to VDD more quickly than in the first embodiment.

[0080] As described above, according to this modification, the output signal out rises from VDD to VDDIO earlier than in the first embodiment. Also, the output signal out falls from VDDIO to VDD earlier than in the first embodiment. This enables the circuit operation of the level shift circuit 1 to be speeded up.

[0081] Second Embodiment FIG. 4 shows an example of a circuit diagram of a level shift circuit 1 according to a second embodiment. In FIG. 4, components corresponding to those in FIG. 1 are assigned common reference numerals. The following description will focus on differences from the first embodiment. Note that elements (e.g., transistors and inverters) assigned the same reference numerals in FIGS. 1 and 4 are not intended to be limited to the same design parameters / process parameters, etc. In other words, the technical scope of the present disclosure includes configurations in which the various parameters of elements assigned the same reference numerals in FIGS. 1 and 4 differ from each other. The same applies to the relationships between the other drawings.

[0082] The level shift circuit 1 of this embodiment differs from the first embodiment in that the voltage conversion circuits 10 and 20 do not employ a cross-coupled connection as in the first embodiment.

[0083] Specifically, in the voltage conversion circuit 10, P-type transistors P15 and P17 are added to the components of the first embodiment. The P-type transistor P15 (corresponding to the seventh P-type transistor) is provided between node n9 (corresponding to the fourth node) and node n1, and its gate is connected to the first power supply VDD. The P-type transistor P17 (corresponding to the eighth P-type transistor) is provided between the first power supply VDD and node n9, and its gate is connected to node n1. In addition, in this embodiment, the gate of the P-type transistor P1 is connected to node n10 instead of the inverting output node outb in the first embodiment.

[0084] In the voltage conversion circuit 20, P-type transistors P16 and P18 are added to the components of the first embodiment. The P-type transistor P16 (corresponding to the ninth P-type transistor) is provided between node n10 (corresponding to the third node) and node n2, with its gate connected to the first power supply VDD. The P-type transistor P18 (corresponding to the tenth P-type transistor) is provided between the first power supply VDD and node n10, with its gate connected to node n2. In addition, in this embodiment, the gate of the P-type transistor P2 is connected to node n9 instead of the output node out of the first embodiment.

[0085] In the pull-up circuit 30, the gate of the P-type transistor P8 is connected to a node n10 instead of the inverting output node outb in the first embodiment. In this embodiment, the P-type transistor P7 corresponds to the eleventh P-type transistor, and the P-type transistor P8 corresponds to the twelfth P-type transistor.

[0086] In the pull-up circuit 40, the gate of the P-type transistor P10 is connected to a node n9 instead of the output node out in the first embodiment. In this embodiment, the P-type transistor P9 corresponds to the thirteenth P-type transistor, and the P-type transistor P10 corresponds to the fourteenth P-type transistor.

[0087] The configurations of the pull-down circuits 50 and 60 are the same as those in the first embodiment. In this embodiment, the P-type transistor P11 corresponds to the 15th P-type transistor, and the P-type transistor P12 corresponds to the 16th P-type transistor.

[0088] [Operation of Level Shift Circuit] Next, the operation of the level shift circuit 1 according to this embodiment will be described, focusing on differences from the operation description of the level shift circuit 1 according to the first embodiment, "Operation Example (1-1) to Operation Example (1-4)."

[0089] --Operation Example (2-1)-- Here, the operation when in=VSS and out=VDD, that is, the operation when 'L' is input and 'L' is output, will be described.

[0090] (Voltage Conversion Circuit) In the voltage conversion circuit 10, the input signal in is 'L', so the N-type transistor N1 turns on, n1=VSS, and the P-type transistor P17 turns on. This causes n9=VDD, the P-type transistor P15 turns off, and in the voltage conversion circuit 20, the P-type transistor P2 turns on. This causes outb=VDDIO, the P-type transistor P4 turns on, n2=VDDIO, the P-type transistor P16 turns on, and the P-type transistor P18 turns off. This causes n10=VDDIO, the P-type transistor P1 turns off, and out=VDD.

[0091] (Pull-up circuit) As described above, n10=VDDIO, so P-type transistor P8 is turned off in pull-up circuit 30. Furthermore, n6=VDDIO due to the output of delay circuit 70, so P-type transistor P9 is turned off in pull-up circuit 40. As a result, there is no conduction between the third power supply VDDIO and the output node out and the inverted output node outb via pull-up circuits 30 and 40.

[0092] The operations of the pull-down circuits 50 and 60 in this operation example are the same as those in the "operation example (1-1)" of the first embodiment.

[0093] --Operation Example (2-2)-- Here, the operation when in=VDD and out=VDDIO, that is, the operation when 'H' is input and 'H' is output, will be described.

[0094] (Voltage Conversion Circuit) Because the voltage conversion circuits 10 and 20 have symmetrical configurations, the operation is contrary to the above-mentioned "Operation Example (2-1)." Specifically, in the voltage conversion circuit 20, the inverted input signal inb is 'L,' so that the N-type transistor N2 turns on, n2=VSS, and the P-type transistor P18 turns on. As a result, n10=VDD, the P-type transistor P16 turns off, and in the voltage conversion circuit 10, the P-type transistor P1 turns on. As a result, out=VDDIO, the P-type transistor P3 turns on, n1=VDDIO, the P-type transistor P15 turns on, and the P-type transistor P17 turns off. As a result, n9=VDDIO, the P-type transistor P2 turns off, and outb=VDD.

[0095] (Pull-up Circuit) As described above, n9=VDDIO, so P-type transistor P10 is turned off in pull-up circuit 40. Also, n4=VDDIO due to the output of delay circuit 70, so P-type transistor P7 is turned off in pull-up circuit 30. As a result, there is no conduction between the third power supply VDDIO and the output node out and inverted output node outb via pull-up circuits 30 and 40.

[0096] The operations of the pull-down circuits 50 and 60 in this operation example are the same as those in the "operation example (1-2)" of the first embodiment.

[0097] --Operation Example (2-3)--Here, we will explain the operation when in=VSS changes to in=VDD and out=VDD changes to out=VDDIO, that is, the operation when the input signal in changes from 'L' to 'H' and the output signal out changes from 'L' to 'H'.

[0098] (Voltage Conversion Circuit) In the voltage conversion circuits 10 and 20, the on / off state of each transistor and the voltage of each node transition from the above-described "Operation Example (2-1)" to "Operation Example (2-2)."

[0099] As shown on the left side of Figure 5, the voltage at node n2 begins to drop from VDDIO toward VSS as the inverted input signal inb falls. During this drop, the voltage at node n10 drops from VDDIO until the Vgs of P-type transistor P16 (the voltage between VDD and n10) falls below the threshold and P-type transistor P16 turns off. Then, when the Vgs of P-type transistor P18 (the voltage between n2 and VDD) exceeds the threshold, P-type transistor P18 turns on and the voltage at node n10 drops to VDD. During this drop, when the Vgs of P-type transistor P1 (the voltage between n10 and VDDIO) exceeds the threshold, P-type transistor P1 turns on.

[0100] Here, in this embodiment, since the cross-coupled connection is not used, the voltage at node n10 drops faster than the voltage at the inverting output node outb. As a result, the P-type transistor P1 turns on earlier than in the first embodiment, and the voltage at the output node out also rises faster. Furthermore, as the voltage at the output node out rises, the P-type transistor P3 turns on and the voltage at node n1 rises earlier than in the first embodiment, and accordingly the P-type transistor P5 turns off earlier. Furthermore, during the process of the rise in the voltage at node n1, if the Vgs (voltage between VDD and n1) of the P-type transistor P15 exceeds the threshold, the P-type transistor P15 turns on. If the Vgs (voltage between n1 and VDD) of the P-type transistor P17 falls below the threshold, the P-type transistor P17 turns off, and the voltage at node n9, together with the node n1 and the output signal out, rises to VDDIO. As a result, the voltage of the output signal out rises to VDDIO earlier than in the first embodiment.

[0101] Although the pull-up circuits 30 and 40 are connected differently from those in the first embodiment, the operations of the pull-up circuits 30 and 40 and the pull-down circuits 50 and 60 are the same as those in the "Operation Example (1-3)" of the first embodiment. That is, as in the first embodiment, the pull-up circuit 30 and the pull-down circuit 60 act to assist the operation of raising the voltage of the output signal out to VDDIO.

[0102] --Operation example (2-4)--Here, we will explain the operation when in=VDD changes to in=VSS and out=VDDIO changes to out=VDD, that is, the operation when the input signal in changes from 'H' to 'L' and the output signal out changes from 'H' to 'L'.

[0103] (Voltage Conversion Circuit) In the voltage conversion circuits 10 and 20, the on / off state of each transistor and the voltage of each node transition from the above-described "Operation Example (2-2)" to the "Operation Example (2-1)" state.

[0104] As shown on the right side of Figure 5, the voltage at node n1 begins to drop from VDDIO toward VSS as the input signal in falls. During this drop, the voltage at node n9 drops from VDDIO until the Vgs of P-type transistor P15 (the voltage between VDD and n9) falls below the threshold and P-type transistor P15 turns off. Then, when the Vgs of P-type transistor P17 (the voltage between n1 and VDD) exceeds the threshold, P-type transistor P17 turns on and the voltage at node n9 drops to VDD. During this process, when the Vgs of P-type transistor P2 (the voltage between n9 and VDDIO) exceeds the threshold, P-type transistor P2 turns on.

[0105] In this embodiment, since the cross-coupled connection is not used, the voltage at node n9 drops faster than the voltage at output node out. As a result, P-type transistor P2 turns on earlier than in the first embodiment, and the voltage at inverted output node outb also rises faster. Furthermore, as the voltage at inverted output node outb rises, P-type transistor P4 turns on and the voltage at node n2 rises faster than in the first embodiment, and accordingly P-type transistor P6 also turns off earlier. Furthermore, during the process of the voltage rise of node n2, when Vgs (voltage between VDD and n2) of P-type transistor P16 exceeds the threshold, P-type transistor P16 turns on, when Vgs (voltage between n2 and VDD) of P-type transistor P18 falls below the threshold, P-type transistor P18 turns off, the voltage of node n10 rises to VDDIO together with node n2 and the inverted output signal outb, and when Vgs of P-type transistor P1 falls below the threshold, P-type transistor P1 turns off. As a result, the voltage of the output signal out drops to VDD more quickly than in the first embodiment.

[0106] Although the pull-up circuits 30 and 40 are connected differently from those in the first embodiment, the operations of the pull-up circuits 30 and 40 and the pull-down circuits 50 and 60 are the same as those in the "Operation Example (1-4)" of the first embodiment. That is, as in the first embodiment, the pull-up circuit 40 and the pull-down circuit 50 act to assist the operation of dropping the voltage of the output signal out to VDD.

[0107] [Effects of the Second Embodiment] As described above, the configuration of this embodiment provides the same effects as those of the first embodiment. Specifically, for example, compared to a case in which the pull-up circuits 30, 40 and the pull-down circuits 50, 60 are not provided, the output signal out is not delayed, and the circuit can be operated at a higher speed.

[0108] Furthermore, in the first embodiment, the P-type transistors P1 and P2 are cross-coupled, so when the inverted output signal outb starts to drop, and the P-type transistor P1 turns on during this process, the output signal out rises, and the P-type transistor P2 turns off, accelerating the drop of the inverted output signal outb. In contrast, in the present embodiment, the cross-coupled connection is not used, so node n10 is not connected to the drain of the P-type transistor P2, and therefore falls faster than the inverted output node outb, regardless of whether the P-type transistor P2 is turned off. Similarly, node n9 is not connected to the drain of the P-type transistor P1, and therefore falls faster than the output node out, regardless of whether the P-type transistor P1 is turned off. As a result, the rise time and fall time of the output signal out can be further shortened, thereby achieving high-speed operation of the level shift circuit 1.

[0109] <Modification> Fig. 6 shows a modification of the level shift circuit 1 according to the second embodiment. In Fig. 6, components corresponding to those in Fig. 4 are assigned the same reference numerals as in Fig. 4. The following description will focus on the differences from the second embodiment.

[0110] The level shift circuit 1 of this embodiment is configured in addition to the configuration of the second embodiment, with additional capacitors C1 to C4. Capacitor C1 (corresponding to a first capacitor) is provided between the output node out and node n1, and capacitor C3 (corresponding to a first capacitor and a third capacitor) is provided between node n1 and node n9. Capacitor C2 (corresponding to a second capacitor) is provided between the inverting output node outb and node n2, and capacitor C4 (corresponding to a second capacitor and a fourth capacitor) is provided between node n2 and node n10.

[0111] [Operation of Level Shift Circuit] Next, the operation of the level shift circuit 1 according to this modification will be described. Here, the operations of the voltage conversion circuits 10 and 20, the pull-up circuits 30 and 40, and the pull-down circuits 50 and 60 will be described together. In addition, the differences from the second embodiment will be mainly described, and the description of the operation examples (2-1) and (2-2) common to the second embodiment will be omitted.

[0112] --Operation Example (2-3)-- Here, an operation when in changes from VSS to VDD and out changes from VDD to VDDIO will be described.

[0113] As in the second embodiment, in the voltage conversion circuits 10 and 20, the on / off state of each transistor and the voltage of each node transition from the state of "Operation Example (2-1)" described above to the state of "Operation Example (2-2)." Here, the provision of capacitors C1 to C4 results in differences in the transition of voltages at some nodes compared to the second embodiment. Note that the transition of voltages due to capacitors C1 and C2 is the same as in the modified example of the first embodiment, so the transition of voltages due to capacitors C3 and C4 will be described here.

[0114] Due to AC coupling between node n1 and node n9 by capacitor C3, the voltage of node n9 rises in conjunction with the rise of the voltage of node n1, regardless of the on-state of P-type transistor P15. As a result, the voltage of node n9 rises faster than in the second embodiment, and P-type transistor P2 turns off earlier than in the second embodiment. Due to AC coupling between node n2 and node n10 by capacitor C4, the voltage of node n10 drops in conjunction with the fall of the voltage of node n2, regardless of the on-state of P-type transistor P18. As a result, the voltage of node n10 drops faster than in the second embodiment, and P-type transistor P1 turns on earlier than in the second embodiment. As a result, the output signal out rises from VDD to VDDIO earlier than in the second embodiment.

[0115] --Operation Example (2-4)-- Here, the operation when in changes from in=VDD to in=VSS and out changes from out=VDDIO to out=VDD will be described.

[0116] As in the second embodiment, in the voltage conversion circuits 10 and 20, the on / off states of each transistor and the voltages of each node transition from the aforementioned "Operation Example (2-2)" to the "Operation Example (2-1)" state. The provision of capacitors C1 to C4 results in differences in the voltage transitions of some nodes compared to the second embodiment. Since the voltage conversion circuits 10 and 20 have symmetrical configurations, the operation is opposite to that of "Operation Example (2-3)." The voltage transitions caused by the capacitors C1 and C2 are the same as those in the modified example of the first embodiment, and therefore, the voltage transitions caused by the capacitors C3 and C4 will be described here.

[0117] Due to AC coupling between node n2 and node n10 by capacitor C4, the voltage of node n10 rises in conjunction with the rise of the voltage of node n2, regardless of the on-state of P-type transistor P16. As a result, the voltage of node n10 rises faster than in the second embodiment, and P-type transistor P1 turns off earlier than in the second embodiment. Due to AC coupling between node n1 and node n9 by capacitor C3, the voltage of node n9 drops in conjunction with the fall of the voltage of node n1, regardless of the on-state of P-type transistor P17. As a result, the voltage of node n9 drops faster than in the second embodiment, and P-type transistor P2 turns on earlier than in the second embodiment. As a result, the output signal out drops from VDDIIO to VDD earlier than in the second embodiment.

[0118] As described above, according to this modification, the output signal out rises from VDD to VDDIO earlier than in the second embodiment. Also, the output signal out falls from VDDIO to VDD earlier than in the second embodiment. This enables the circuit operation of the level shift circuit 1 to be speeded up.

[0119] The level shift circuit of the present disclosure is extremely useful because it is compatible with lower operating voltages and / or higher speed circuit operations.

[0120] 1 Level shift circuit 30 Pull-up circuit (first pull-up circuit) 40 Pull-up circuit (second pull-up circuit) 50 Pull-down circuit (first pull-down circuit) 60 Pull-down circuit (second pull-down circuit) 70 Delay circuit N1 N-type transistor (first N-type transistor) N2 N-type transistor (second N-type transistor) N3 N-type transistor (third N-type transistor) N4 N-type transistor (fourth N-type transistor) P1 P-type transistor (fifth P-type transistor) P2 P-type transistor (sixth P-type transistor) P3 P-type transistor (first P-type transistor) P4 P-type transistor (third P-type transistor) P5 P-type transistor (second P-type transistor) P6 P-type transistor (fourth P-type transistor) P7 P-type transistor (5th P-type transistor, 7th P-type transistor, 11th P-type transistor) P8 P-type transistor (6th P-type transistor, 8th P-type transistor, 12th P-type transistor) P9 P-type transistor (7th P-type transistor, 9th P-type transistor, 13th P-type transistor) P10 P-type transistor (8th P-type transistor, 10th P-type transistor, 14th P-type transistor) P11 P-type transistor (5th P-type transistor, 11th P-type transistor, 15th P-type transistor) P12 P-type transistor (6th P-type transistor, 12th P-type transistor) P15 P-type transistor (7th P-type transistor) P16 P-type transistor (9th P-type transistor) P17 P-type transistor (8th P-type transistor) P18 P-type transistor (10th P-type transistor) n1 Node (first node) n2 Node (second node) n3 Node (third node, fifth node) n5 Node (fourth node, sixth node) n7 Node (third node, fifth node, seventh node) n8 Node (fourth node, sixth node, eighth node) n9 Node (fourth node) n10 Node (third node) in Input node inb Inverting input node out Output nodeoutb Inverting output node VDD First power supply VDDIO Third power supply VSS Ground (second power supply) C1 Capacitance (first capacitance) C2 Capacitance (second capacitance) C3 Capacitance (first capacitance, third capacitance) C4 Capacitance (second capacitance, fourth capacitance)

Claims

1. An input node receiving an input signal that transitions between a first power supply and a second power supply having a potential lower than the first power supply; a first N-type transistor provided between the input node and the first node, the gate of which is connected to the first power supply; a first P-type transistor provided between the first node and an output node that outputs an output signal, the gate of which is connected to the first power supply; a second P-type transistor provided between the output node and the first power supply, the gate of which is connected to the first node; an inverting input node receiving an inverted input signal obtained by inverting the input signal; a second N-type transistor provided between the inverting input node and a second node, the gate of which is connected to the first power supply; a third P-type transistor provided between the second node and an inverting output node, the gate of which is connected to the first power supply; a fourth P-type transistor provided between the inverting output node and the first power supply, the gate of which is connected to the second node; and a first pull-up circuit provided between a third power supply and the output node, that supplies the voltage of the third power supply to the output node when an inverted signal of the output signal transitions from a high level to a low level. a second pull-up circuit provided between the third power supply and the inverting output node, the second pull-up circuit supplying the voltage of the third power supply to the inverting output node when the output signal transitions from a high level to a low level.

2. A level shift circuit according to claim 1, comprising: a fifth P-type transistor provided between said third power supply and said output node, the gate of which is connected to said inverted output node; and a sixth P-type transistor provided between said third power supply and said inverted output node, the gate of which is connected to said output node.

3. A level shift circuit as claimed in claim 1, wherein the first pull-up circuit comprises: a fifth P-type transistor provided between the third power supply and the third node, the gate of which is supplied with a delayed version of the output signal; and a sixth P-type transistor provided between the third node and the output node, the gate of which is connected to the inverted output node; and the second pull-up circuit comprises: a seventh P-type transistor provided between the third power supply and a fourth node, the gate of which is supplied with a delayed version of the inverted signal; and an eighth P-type transistor provided between the fourth node and the inverted output node, the gate of which is connected to the output node.

4. A level shift circuit as claimed in claim 1, comprising: a first pull-down circuit provided between said output node and said first power supply, for supplying the voltage of said first power supply to said output node when said output signal transitions from high level to low level; and a second pull-down circuit provided between said inverted output node and said first power supply, for supplying the voltage of said first power supply to said inverted output node when said inverted signal transitions from high level to low level.

5. A level shift circuit as claimed in claim 4, wherein the first pull-down circuit comprises: a fifth P-type transistor provided between the output node and a third node, the first node being connected to its gate; and a third N-type transistor provided between the third node and the first power supply, the delay signal of the output signal being applied to its gate; and the second pull-down circuit comprises: a sixth P-type transistor provided between the inverted output node and a fourth node, the second node being connected to its gate; and a fourth N-type transistor provided between the fourth node and the first power supply, the delay signal of the inverted signal being applied to its gate.

6. A level shift circuit according to claim 1, comprising: a first capacitance provided between said output node and said first node; and a second capacitance provided between said inverting output node and said second node.

7. A level shift circuit as claimed in claim 1, comprising: a fifth P-type transistor provided between the third power supply and the output node, the gate of which is connected to the third node; a sixth P-type transistor provided between the third power supply and the inverting output node, the gate of which is connected to the fourth node; a seventh P-type transistor provided between the fourth node and the first node, the gate of which is connected to the first power supply; an eighth P-type transistor provided between the first power supply and the fourth node, the gate of which is connected to the first node; a ninth P-type transistor provided between the third node and the second node, the gate of which is connected to the first power supply; and a tenth P-type transistor provided between the first power supply and the third node, the gate of which is connected to the second node.

8. A level shift circuit as defined in claim 7, wherein the first pull-up circuit comprises: an eleventh P-type transistor provided between the third power supply and a fifth node, the gate of which is supplied with a delayed signal of the output signal; and a twelfth P-type transistor provided between the fifth node and the output node, the gate of which is connected to the third node; and the second pull-up circuit comprises: a thirteenth P-type transistor provided between the third power supply and a sixth node, the gate of which is supplied with a delayed signal of the inverted signal; and a fourteenth P-type transistor provided between the sixth node and the inverted output node, the gate of which is connected to the fourth node.

9. A level shift circuit according to claim 7, comprising: a first capacitance provided between said first node and said fourth node; and a second capacitance provided between said second node and said third node.

10. An input node receiving an input signal that transitions between a first power supply and a second power supply having a potential lower than the first power supply; a first N-type transistor provided between the input node and the first node, the gate of which is connected to the first power supply; a first P-type transistor provided between the first node and an output node, the gate of which is connected to the first power supply; a second P-type transistor provided between the output node and the first power supply, the gate of which is connected to the first node; an inverting input node receiving an inverted input signal obtained by inverting the input signal; a second N-type transistor provided between the inverting input node and a second node, the gate of which is connected to the first power supply; a third P-type transistor provided between the second node and an inverting output node, the gate of which is connected to the first power supply; a fourth P-type transistor provided between the inverting output node and the first power supply, the gate of which is connected to the second node; a fifth P-type transistor provided between a third power supply and the output node, the gate of which is connected to the inverting output node; and a sixth P-type transistor provided between the third power supply and the inverting output node, the gate of which is connected to the output node. a delay circuit that generates a first delayed signal obtained by delaying an output signal of the output node and a second delayed signal obtained by delaying an inverted signal of the inverted output node; a first pull-up circuit having a seventh P-type transistor that is provided between the third power supply and the third node and has a gate to which the first delayed signal is applied, and an eighth P-type transistor that is provided between the third node and the output node and has a gate to which the inverted output node is connected; a second pull-up circuit having a ninth P-type transistor that is provided between the third power supply and a fourth node and has a gate to which the second delayed signal is applied, and a tenth P-type transistor that is provided between the fourth node and the inverted output node and has a gate to which the output node is connected; a first pull-down circuit having an eleventh P-type transistor that is provided between the output node and a fifth node and has a gate to which the first node is applied, and a third N-type transistor that is provided between the fifth node and the first power supply and has a gate to which the first delayed signal is applied;a second pull-down circuit having a twelfth P-type transistor provided between the inverting output node and a sixth node, the twelfth P-type transistor having a gate connected to the second node, and a fourth N-type transistor provided between the sixth node and the first power supply, the gate of which is supplied with the second delay signal.

11. A level shift circuit according to claim 10, comprising: a first capacitance provided between said output node and said first node; and a second capacitance provided between said inverting output node and said second node.

12. An input node receiving an input signal that transitions between a first power supply and a second power supply having a potential lower than the first power supply; a first N-type transistor provided between the input node and the first node, the gate of which is connected to the first power supply; a first P-type transistor provided between the first node and an output node, the gate of which is connected to the first power supply; a second P-type transistor provided between the output node and the first power supply, the gate of which is connected to the first node; an inverting input node receiving an inverted input signal obtained by inverting the input signal; a second N-type transistor provided between the inverting input node and a second node, the gate of which is connected to the first power supply; a third P-type transistor provided between the second node and an inverting output node, the gate of which is connected to the first power supply; a fourth P-type transistor provided between the inverting output node and the first power supply, the gate of which is connected to the second node; a fifth P-type transistor provided between a third power supply and the output node, the gate of which is connected to the third node; and a sixth P-type transistor provided between the third power supply and the inverting output node, the gate of which is connected to the fourth node. a seventh P-type transistor provided between the fourth node and the first node, the gate of which is connected to the first power supply; an eighth P-type transistor provided between the first power supply and the fourth node, the gate of which is connected to the first node; a ninth P-type transistor provided between the third node and the second node, the gate of which is connected to the first power supply; a tenth P-type transistor provided between the first power supply and the third node, the gate of which is connected to the second node; a delay circuit that generates a first delayed signal obtained by delaying an output signal of the output node and a second delayed signal obtained by delaying an inverted signal of the inverted output node; an eleventh P-type transistor provided between the third power supply and a fifth node, the gate of which is given the first delayed signal; and a twelfth P-type transistor provided between the fifth node and the output node, the gate of which is connected to the third node;a second pull-up circuit having a thirteenth P-type transistor provided between the third power supply and a sixth node, the thirteenth P-type transistor having a gate to which the second delay signal is applied, and a fourteenth P-type transistor provided between the sixth node and the inverting output node, the fourteenth P-type transistor having a gate connected to the fourth node; a first pull-down circuit having a fifteenth P-type transistor provided between the output node and a seventh node, the fifteenth P-type transistor having a gate connected to the first node, and a third N-type transistor provided between the seventh node and the first power supply, the third N-type transistor having a gate to which the first delay signal is applied; and a second pull-down circuit having a sixteenth P-type transistor provided between the inverting output node and an eighth node, the sixteenth P-type transistor having a gate connected to the second node, and a fourth N-type transistor provided between the first power supply and the eighth node, the fourth N-type transistor having a gate to which the second delay signal is applied.

13. A level shift circuit according to claim 12, comprising: a first capacitance provided between the output node and the first node; a second capacitance provided between the inverting output node and the second node; a third capacitance provided between the first node and the fourth node; and a fourth capacitance provided between the second node and the third node.

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