Multi-level inverter

Abstract

This multi-level inverter (30, 130) comprises: a plurality of capacitor parts (21, 22, 121-124) that are connected in series; a plurality of switch parts (Su1-Su8, Sv1-Sv4, Sw1-Sw4) that are controlled so as to select and output any voltage among a plurality of voltages which can be output from a series connector of the capacitor parts; a plurality of rectification parts (Du1-Du6, Dv1, Dv2, Dw1, Dw2) that rectify the current flowing through the switch parts when a voltage at an intermediate level is selected from among the plurality of voltages; and a substrate (50, 150, 250, 350). The substrate has, as the plate surfaces thereof, an arrangement surface on which the capacitor parts, the switch parts, and the rectification parts are arranged and a connection surface which is a different plate surface from the arrangement surface and on which is formed connection wiring (43U, 43V, 43W, 143U, 146U, 149U) for electrically connecting the capacitor parts and the rectification parts.

Description

Multilevel Inverter CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Application No. 2024-044610, filed on March 21, 2024, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a multilevel inverter.

[0003] 2. Description of the Related Art Multilevel inverters are known in the art that convert DC power into AC power and output the AC power. The multilevel inverters include switches that are controlled to be turned on or off to output multiple voltage levels.

[0004] When the switching control of the switches is performed, the current path of the current flowing through the inverter is switched. In this case, a voltage is induced by the inductance of the commutation path, which is the path through which the current changes, and a surge voltage may occur. In view of this, there is a technology for reducing the surge voltage by, for example, arranging the switches so as to shorten the path length of the commutation path (see Patent Document 1).

[0005] JP 2023-24081 A

[0006] In a multilevel inverter, there is still room for improvement in reducing surge voltages that occur due to the implementation of switching control.

[0007] An object of the present disclosure is to provide a multilevel inverter capable of reducing surge voltages that occur due to the implementation of switching control.

[0008] The present disclosure provides a multilevel inverter including a plurality of capacitor units connected in series, a plurality of switch units controlled to select and output one of a plurality of voltages that can be output from the series connection of the capacitor units, and a plurality of rectifier units that rectify a current flowing through the switch units when an intermediate level voltage is selected from the plurality of voltages, the multilevel inverter including a substrate on which the capacitor units, the switch units, and the rectifier units are mounted, the substrate having as its board surfaces: an arrangement surface on which the capacitor units, the switch units, and the rectifier units are arranged, and a connection surface that is different from the arrangement surface and on which connection wiring is formed to electrically connect the capacitor units and the rectifier units.

[0009] In a multilevel inverter, a commutation path where the current changes occurs as a result of switching control of the switch section. Here, there is a concern that the inductance of the commutation path will increase due to the large loop area of ​​the commutation path. In this case, there is a concern that the voltage induced by the inductance of the commutation path will increase, and that this will result in a high surge voltage.

[0010] In a multilevel inverter, it is possible to select and output an intermediate-level voltage from among multiple voltages that can be output from the series-connected capacitor units. When switching control is performed to output the intermediate-level voltage, a current flows between the switch unit and the capacitor unit via the rectifier unit and the connecting wiring. Therefore, when switching control is performed to switch between a state in which an intermediate-level voltage is selected from among the multiple voltages and a state in which a voltage other than the intermediate level is selected, the current flowing through the connecting wiring may change. In this case, a path including the connecting wiring becomes a commutation path.

[0011] Therefore, in the present disclosure, the connection surface on which the connection wiring is formed is a plate surface different from the arrangement surfaces of the capacitor units, switch units, and rectifier units. In this case, the degree of freedom in arranging the connection paths is increased. This makes it possible to arrange the connection paths so that the loop area of ​​the commutation path including the connection wiring is small. Therefore, the inductance of the commutation path can be reduced, and the surge voltage generated by the implementation of switching control can be reduced.

[0012] The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which Fig. 1 is an overall configuration diagram of a control system according to a first embodiment, Fig. 2 is a diagram illustrating a commutation path that occurs with the implementation of switching control, Fig. 3 is a diagram illustrating a commutation path that occurs with the implementation of switching control, Fig. 4 is a diagram illustrating a commutation path that occurs with the implementation of switching control, Fig. 5 is a diagram illustrating a commutation path that occurs with the implementation of switching control, Fig. 6 is a plan view of an arrangement layer in a circuit board, Fig. 7 is a plan view of a connection layer in the circuit board, Fig. 8 is a cross-sectional view of a multilayer board, and Fig. 9 is a diagram illustrating an example of a commutation path that occurs with the implementation of switching control. FIG. 10 is a diagram showing the range of a commutation path that occurs when switching control is performed, FIG. 11 is a diagram showing the range of a commutation path that occurs when switching control is performed, FIG. 12 is a diagram showing the range of a commutation path that occurs when switching control is performed, FIG. 13 is a plan view of an arrangement layer in a circuit board according to a second embodiment, FIG. 14 is a plan view of an arrangement layer in a circuit board according to a modified example of the second embodiment, FIG. 15 is a circuit diagram of a five-level inverter according to a third embodiment, FIG. 16 is a diagram showing an example in which components of a five-level inverter are mounted on a circuit board, and FIG. 17 is a cross-sectional view of a multilayer board.

[0013] Several embodiments will be described with reference to the drawings. In several embodiments, functionally and / or structurally corresponding and / or associated parts may be designated by the same reference numerals or reference numerals that differ in the hundredth or more digit. For corresponding and / or associated parts, reference may be made to the descriptions of other embodiments.

[0014] A first embodiment of a multilevel inverter according to the present disclosure will be described below with reference to the drawings. In this embodiment, the multilevel inverter is a three-level inverter capable of outputting three voltage levels, and constitutes a control system mounted on an electric vehicle, a hybrid vehicle, or other electrically powered vehicle.

[0015] As shown in FIG. 1 , the control system 100 includes a rotating electric machine 10, a storage battery 15, and a three-level inverter 30. The rotating electric machine 10 is an on-vehicle main motor. A rotor of the rotating electric machine 10 is capable of transmitting power to drive wheels of the vehicle. In this embodiment, the rotating electric machine 10 is a three-phase synchronous machine and includes U-, V-, and W-phase windings 11U, 11V, and 11W as stator windings. The phase windings 11U, 11V, and 11W are arranged with a 120° electrical angle offset. The rotating electric machine 10 is, for example, a permanent magnet synchronous machine.

[0016] The storage battery 15 is electrically connected to the rotating electric machine 10 via a three-level inverter 30. The storage battery 15 is a power source that supplies driving power to the rotating electric machine 10. In this embodiment, the storage battery 15 is, for example, a battery pack configured as a series connection of battery cells serving as single cells. The battery cells may be, for example, secondary batteries such as lithium-ion batteries. The terminal voltage of the storage battery 15 is, for example, 600 to 800 V.

[0017] The three-level inverter 30 is a power conversion circuit that converts DC power supplied from the storage battery 15 into three-phase AC power by switching control and supplies the converted AC power to the rotating electric machine 10. A positive terminal 20H on the DC side of the three-level inverter 30 is connected to the positive side of the storage battery 15. A negative terminal 20L on the DC side of the three-level inverter 30 is connected to the negative side of the storage battery 15.

[0018] In this embodiment, the three-level inverter 30 is a neutral-point clamped three-level inverter. Specifically, the three-level inverter 30 is a three-phase inverter and includes a U-phase circuit section 31U, a V-phase circuit section 31V, a W-phase circuit section 31W, a first capacitor 21, and a second capacitor 22. For example, the capacitance of the first capacitor 21 and the capacitance of the second capacitor 22 are set to the same value.

[0019] The first and second capacitors 21, 22 are connected in series. Specifically, a first end of the first capacitor 21 is connected to the positive terminal 20H via the positive wiring 40H. A second end of the first capacitor 21 and a first end of the second capacitor 22 are connected to the intermediate terminal 23. A second end of the second capacitor 22 is connected to the negative terminal 20L via the negative wiring 40L. In this embodiment, each of the capacitors 21, 22 corresponds to a "capacitor section."

[0020] First, the circuit configuration of the three-level inverter 30 will be described below using the U-phase circuit section 31U as an example.

[0021] The U-phase circuit unit 31U includes U-phase first to fourth switches Su1 to Su4 and U-phase first and second diodes Du1 and Du2. The U-phase first to fourth switches Su1 to Su4 are voltage-controlled semiconductor switching elements, more specifically, GaN semiconductor switching devices. GaN semiconductor switching devices are also called GaN-HEMTs. GaN stands for gallium nitride, and HEMT stands for high electron mobility transistor.

[0022] The high-potential terminals of the U-phase first to fourth switches Su1 to Su4 are drains, and the low-potential terminals are sources. The U-phase first to fourth switches Su1 to Su4 are connected in series with their sources and drains connected. Specifically, the source of the U-phase first switch Su1 is connected to the drain of the U-phase second switch Su2. The source of the U-phase second switch Su2 is connected to the drain of the U-phase third switch Su3. The source of the U-phase third switch Su3 is connected to the drain of the U-phase fourth switch Su4.

[0023] The source of the U-phase first switch Su1, the drain of the U-phase second switch Su2, and the cathode of the U-phase first diode Du1 are connected via a U-phase first wiring 41U. The source of the U-phase third switch Su3, the drain of the U-phase fourth switch Su4, and the anode of the U-phase second diode Du2 are connected via a U-phase second wiring 42U. The anode of the U-phase first diode Du1, the cathode of the U-phase second diode Du2, and the intermediate terminal 23 are connected via a U-phase third wiring 43U.

[0024] Similar to the U-phase circuit unit 31U, the V- and W-phase circuit units 31V and 31W include V- and W-phase first to fourth switches Sv1 to Sv4 and Sw1 to Sw4, V- and W-phase first and second diodes Dv1, Dv2, Dw1 and Dw2, and V- and W-phase first to third wirings 41V to 43V and 41W to 43W. In the present embodiment, the configurations of the phase circuit units 31U, 31V and 31W are basically the same, and therefore detailed description of the V- and W-phase circuit units 31V and 31W will be omitted.

[0025] In this embodiment, the switches Su1 to Su4, Sv1 to Sv4, and Sw1 to Sw4 correspond to the "switch unit," and the diodes Du1, Du2, Dv1, Dv2, Dw1, and Dw2 correspond to the "rectifier unit." The first wirings 41U, 41V, and 41W of each phase correspond to the "first intermediate wiring," the second wirings 42U, 42V, and 42W of each phase correspond to the "second intermediate wiring," and the third wirings 43U, 43V, and 43W of each phase correspond to the "connection wiring."

[0026] The drains of the first switches Su1, Sv1, and Sw1 of each phase are connected to a first end of the first capacitor 21 and the positive terminal 20H via positive side wiring 40H. The sources of the fourth switches Su4, Sv4, and Sw4 of each phase are connected to a second end of the second capacitor 22 and the negative terminal 20L via negative side wiring 40L. The third wirings 43U, 43V, and 43W of each phase are connected via an intermediate terminal 23. As will be described in detail later, the positive side wiring 40H, the negative side wiring 40L, and the first to third wirings 41U to 43U, 41V to 43V, and 41W to 43W of each phase are wirings formed on a substrate.

[0027] In each phase, the second and third switches Su2, Su3, Sv2, Sv3, Sw2, and Sw3 are connected to the windings 11U, 11V, and 11W of the rotating electric machine 10.

[0028] Specifically, the source of the U-phase second switch Su2 and the drain of the U-phase third switch Su3 are connected to a U-phase output terminal 12U via a U-phase output wiring 13U. The U-phase output terminal 12U is connected to a first end of the U-phase winding 11U. The source of the V-phase second switch Sv2 and the drain of the V-phase third switch Sv3 are connected to a V-phase output terminal 12V via a V-phase output wiring 13V. The V-phase output terminal 12V is connected to a first end of the V-phase winding 11V. The source of the W-phase second switch Sw2 and the drain of the W-phase third switch Sw3 are connected to a W-phase output terminal 12W via a W-phase output wiring 13W. The W-phase output terminal 12W is connected to a first end of the W-phase winding 11W. The second ends of the phase windings 11U, 11V, and 11W are connected to each other. In other words, the phase windings 11U, 11V, and 11W are Y-connected.

[0029] In this embodiment, the sign of the phase current flowing from output terminals 12U, 12V, and 12W to windings 11U, 11V, and 11W in each phase is defined as positive, and the sign of the phase current flowing from first ends of windings 11U, 11V, and 11W to output terminals 12U, 12V, and 12W in each phase is defined as negative.

[0030] The three-level inverter 30 includes a control device 32. The control device 32 is an ECU (electronic control unit) that is mainly composed of a microcomputer equipped with a CPU and various memories. The functions provided by the microcomputer can be provided by software recorded in a physical memory device and a computer that executes the software, software alone, hardware alone, or a combination of these.

[0031] The control device 32 performs switching control to turn on or off the first to fourth phase switches Su1 to Su4, Sv1 to Sv4, and Sw1 to Sw4. For example, the control device 32 performs switching control to control the control variable of the rotating electrical machine 10 to a command value. The control variable is, for example, torque.

[0032] In the switching control, the control device 32 selects and outputs one of three voltage levels (specifically, H level, M level, and L level) that can be output from the series connection of the capacitors 21 and 22 .

[0033] When switching control is performed, the current path through each of the phase circuit units 31U, 31V, and 31W is switched. In this case, a voltage is induced by the inductance of a commutation path, which is a path through which the current changes, and a surge voltage may occur.

[0034] Specifically, the U-phase will be described as an example. When outputting an H-level voltage, the control device 32 turns on the U-phase first and second switches Su1 and Su2 and turns off the U-phase third and fourth switches Su3 and Su4. In this case, a current flows through a path including the positive electrode side wiring 40H and the U-phase first and second switches Su1 and Su2.

[0035] When outputting an M-level voltage, the control device 32 turns on the U-phase second and third switches Su2 and Su3 and turns off the U-phase first and fourth switches Su1 and Su4. In this case, a current flows through a path including the U-phase third wiring 43U. Specifically, when a negative U-phase current flows, a current flows from the U-phase output wiring 13U to the U-phase third switch Su3, the U-phase second wiring 42U, the U-phase second diode Du2, and the U-phase third wiring 43U. When a positive U-phase current flows, a current flows from the U-phase third wiring 43U to the U-phase first diode Du1, the U-phase first wiring 41U, the U-phase second switch Su2, and the U-phase output wiring 13U.

[0036] When outputting an L-level voltage, the control device 32 turns on the U-phase third and fourth switches Su3 and Su4 and turns off the U-phase first and second switches Su1 and Su2. In this case, a current flows through a path including the negative electrode side wiring 40L and the U-phase third and fourth switches Su3 and Su4.

[0037] In addition, when the V and W phase first to fourth switches Sv1 to Sv4, Sw1 to Sw4 are controlled so as to output H, M, and L level voltages in the V and W phases as well, current flows through the V and W phase circuit sections 31V and 31W, as in the case of the U phase.

[0038] 2 to 5 show the commutation paths for each switching pattern in the U-phase circuit section 31U.

[0039] 2 shows a commutation path that occurs in the U-phase circuit unit 31U in a switching pattern in which the sign of the U-phase current is negative and the output voltage of the three-level inverter 30 is switched between H and M levels. In this case, the commutation path includes the first capacitor 21, the positive electrode side wiring 40H, the U-phase first to third switches Su1 to Su3, the U-phase second wiring 42U, the U-phase second diode Du2, and the U-phase third wiring 43U.

[0040] 3 shows a commutation path that occurs in the U-phase circuit unit 31U in a switching pattern in which the sign of the U-phase current is positive and the output voltage of the three-level inverter 30 is switched between H and M levels. In this case, the commutation path includes the first capacitor 21, the positive electrode side wiring 40H, the U-phase first switch Su1, the U-phase first wiring 41U, the U-phase first diode Du1, and the U-phase third wiring 43U.

[0041] 4 shows a commutation path that occurs in the U-phase circuit unit 31U in a switching pattern in which the sign of the U-phase current is negative and the output voltage of the three-level inverter 30 is switched between levels L and M. In this case, the path that includes the U-phase second diode Du2, the U-phase second wiring 42U, the U-phase fourth switch Su4, the negative electrode side wiring 40L, the second capacitor 22, and the U-phase third wiring 43U becomes the commutation path.

[0042] 5 shows a commutation path that occurs in the U-phase circuit unit 31U in a switching pattern in which the sign of the U-phase current is positive and the output voltage of the three-level inverter 30 is switched between levels L and M. In this case, the path that includes the U-phase first diode Du1, the U-phase first wiring 41U, the U-phase second to fourth switches Su2 to Su4, the negative electrode side wiring 40L, the second capacitor 22, and the U-phase third wiring 43U forms the commutation path.

[0043] 2 to 5, a voltage is induced by the inductance of the commutation path, which can cause a surge voltage. Here, if the loop area of ​​the commutation path is large, there is a concern that the inductance of the commutation path will be larger than when the loop area of ​​the commutation path is small. In this case, there is a concern that the surge voltage generated by the implementation of switching control will be higher.

[0044] Specifically, when the commutation path is compressed and the loop area of ​​the commutation path is small, the current flowing in the forward path of the commutation path and the current flowing in the return path of the commutation path flow in opposite directions. In this case, the magnetic flux generated by the current flowing in the forward path and the magnetic flux generated by the current flowing in the return path cancel each other out. This reduces the inductance of the commutation path. On the other hand, when the loop area of ​​the commutation path is large, the magnetic flux generated in the forward and return paths of the current path described above is less likely to cancel each other out than when the loop area of ​​the commutation path is small, and the inductance of the commutation path increases. In this case, the voltage induced by the inductance of the commutation path increases, raising concerns about an increase in surge voltage.

[0045] Therefore, in this embodiment, the three-level inverter 30 has the following characteristic configuration in order to reduce the surge voltage that occurs when switching control is performed.

[0046] The following describes the arrangement of components in the three-level inverter 30. The capacitors 21 and 22 and the phase circuit sections 31U, 31V, and 31W are mounted on a circuit board 50 included in the three-level inverter 30. First, the U phase will be described as an example below.

[0047] 6, 7, and 8 are diagrams showing an example in which the U-phase circuit section 31U and the capacitors 21 and 22 are mounted on a circuit board 50. For convenience, the same reference numerals are used in FIGS. 6 to 8 to designate the same components as those previously described in FIG.

[0048] The circuit board 50 is a multilayer board having an arrangement layer 50A and a connection layer 50B, and has a rectangular shape (specifically, a rectangular shape) when viewed from the front of the board surface of the circuit board 50.

[0049] 6 , U-phase first to fourth switches Su1 to Su4, U-phase first and second diodes Du1 and Du2, and first and second capacitors 21 and 22 are arranged on a layout layer 50A, which is one layer of the circuit board 50. Also formed on the layout layer 50A are a U-phase output wiring 13U, a positive side wiring 40H, a negative side wiring 40L, a U-phase first wiring 41U, and a U-phase second wiring 42U. In this embodiment, the U-phase first to fourth switches Su1 to Su4, the U-phase first and second diodes Du1 and Du2, the first and second capacitors 21 and 22, and the wiring 13U, 40H, 40L, 41U, and 42U are arranged symmetrically with respect to an axis that passes through the center of the layout layer 50A in the Y direction and extends in the X direction.

[0050] As shown in FIG. 7 , U-phase third wiring 43U is formed on connection layer 50B, which is one layer of circuit board 50. In this embodiment, U-phase third wiring 43U is a solid pattern formed in the region of connection layer 50B excluding signal transmission region RS. Signal transmission region RS is a region for transmitting signals to the gates of each switch Su1 to Su4 provided in placement layer 50A. Note that in this embodiment, the plate surface of placement layer 50A corresponds to the "placement surface," and the plate surface of connection layer 50B corresponds to the "connection surface."

[0051] 8 is a partial cross-sectional view taken along line 8-8 in Figures 6 and 7. Specifically, it is a cross-sectional view of the vicinity of U-phase output terminal 12U.

[0052] A connection layer 50B and an arrangement layer 50A are stacked in this order in the Z-axis direction (thickness direction) of the circuit board 50. Here, the arrangement layer 50A is the surface layer, and the connection layer 50B is the inner layer. More specifically, the arrangement layer 50A includes a first wiring pattern layer 51A and a first insulating layer 52A. The first wiring pattern layer 51A is a layer on which the U-phase output wiring 13U, the positive electrode side wiring 40H, the negative electrode side wiring 40L, the U-phase first wiring 41U, and the U-phase second wiring 42U are formed. The components 21, 22, Su1 to Su4, Du1, and Du2 of the three-level inverter 30 are arranged on the first wiring pattern layer 51A. The connection layer 50B includes a second wiring pattern layer 51B on which the U-phase third wiring 43U is formed, and a second insulating layer 52B. Each insulating layer 52A, 52B is formed of an insulator (e.g., insulating resin). In the Z-axis direction of the circuit board 50, the second insulating layer 52B, the second wiring pattern layer 51B, the first insulating layer 52A, and the first wiring pattern layer 51A are laminated in this order.

[0053] Although not shown in FIG. 8 , the first wiring pattern layer 51A and the second wiring pattern layer 51B are connected via vias that penetrate the first insulating layer 52A in the Z-axis direction. Specifically, the first and second wiring pattern layers 51A and 51B are connected by first to fifth via portions 61 to 65 shown in FIGS. 6 and 7 . The first via portion 61 connects the anode of the U-phase first diode Du1 provided on the arrangement layer 50A to the U-phase third wiring 43U formed on the connection layer 50B. The second via portion 62 connects the cathode of the U-phase second diode Du2 provided on the arrangement layer 50A to the U-phase third wiring 43U formed on the connection layer 50B. The third via portion 63 and the fourth via portion 64 connect the second end of the first capacitor 21 provided on the arrangement layer 50A to the U-phase third wiring 43U formed on the connection layer 50B. The fourth via portion 64 and the fifth via portion 65 connect the first end of the second capacitor 22 provided on the arrangement layer 50A and the U-phase third wiring 43U formed on the connection layer 50B.

[0054] As described above with reference to FIGS. 2 to 5 , when switching control is performed to switch between a state in which an M-level voltage is selected and a state in which H- and L-level voltages are selected in the U-phase, a path including the U-phase third wiring 43U becomes a commutation path. Therefore, in this embodiment, the connection layer 50B on which the U-phase third wiring 43U is formed is a layer different from the arrangement layer 50A on which the capacitors 21 and 22, the U-phase first to fourth switches Su1 to Su4, and the U-phase first and second diodes Du1 and Du2 are arranged. This increases the degree of freedom in the arrangement of the U-phase third wiring 43U. This allows the U-phase third wiring 43U to be arranged so as to reduce the loop area of ​​the commutation path including the U-phase third wiring 43U. Specifically, the first wiring pattern layer 51A of the arrangement layer 50A and the second wiring pattern layer 51B of the connection layer 50B are disposed adjacent to each other with the first insulating layer 52A sandwiched therebetween, and the arrangement layer 50A and the connection layer 50B are disposed adjacent to each other in the Z-axis direction. This compresses the commutation path formed in the arrangement layer 50A and the connection layer 50B in the Z-axis direction, thereby reducing the loop area of ​​the commutation path including the U-phase third wiring 43U. This reduces the inductance of the commutation path. As a result, the voltage induced by the inductance of the commutation path can be reduced, thereby reducing the surge voltage generated by the implementation of switching control.

[0055] Next, the arrangement of each component on the arrangement layer 50A will be described.

[0056] In the arrangement layer 50A, the U-phase first to fourth switches Su1 to Su4 are arranged in series connection order. In this embodiment, the direction in which the U-phase first to fourth switches Su1 to Su4 are arranged, that is, the direction from the U-phase fourth switch Su4 to the U-phase first switch Su1, is defined as the Y direction (corresponding to the "first direction"). The direction perpendicular to the Y direction, that is, the direction from the positive terminal 20H and negative terminal 20L side toward the U-phase output terminal 12U side, is defined as the X direction (corresponding to the "second direction"). In this embodiment, the Y direction is the direction in which the short sides of the circuit board 50 extend, and the X direction is the direction in which the long sides of the circuit board 50 extend.

[0057] By arranging the U-phase first to fourth switches Su1 to Su4 in series connection order, the U-phase first to fourth switches Su1 to Su4 can be connected so that the length of the path connecting two adjacent switches in series is short, thereby realizing a configuration suitable for reducing the inductance of the commutation path.

[0058] The U-phase output wiring 13U is formed on the arrangement layer 50A at a position sandwiched in the Y direction between the source of the U-phase second switch Su2 and the drain of the U-phase third switch Su3, and extends in the X direction. The U-phase output terminal 12U is provided at the end of the U-phase output wiring 13U in the X direction.

[0059] In the arrangement layer 50A, U-phase first and second diodes Du1 and Du2 are provided at positions offset in the X direction from the U-phase first to fourth switches Su1 to Su4. In addition, in the arrangement layer 50A, first and second capacitors 21 and 22 are provided at positions offset in the opposite direction from the U-phase first to fourth switches Su1 to Su4. In the arrangement layer 50A, a positive terminal 20H is provided at a position offset in the opposite direction from the first capacitor 21. In the arrangement layer 50A, a negative terminal 20L is provided at a position offset in the opposite direction from the second capacitor 22.

[0060] The positive electrode side wiring 40H is formed on the arrangement layer 50A and includes a positive electrode side main wiring 70H and a positive electrode side parallel wiring 71H. The positive electrode side main wiring 70H is formed on the arrangement layer 50A on the opposite side of the second capacitor 22 in the Y direction with respect to the U-phase first switch Su1 and the first capacitor 21. The positive electrode side main wiring 70H is formed extending in the X direction to a position facing the drain of the U-phase first switch Su1 in the Y direction. The positive electrode side main wiring 70H is formed extending on the opposite side of the X direction to a position facing the positive electrode terminal 20H in the Y direction.

[0061] The positive parallel wiring 71H has a positive first portion 71Ha, a positive second portion 71Hb, and a positive third portion 71Hc. The positive first portion 71Ha extends from the positive main wiring 70H in the opposite direction to the Y direction. The positive second portion 71Hb extends from the positive first portion 71Ha in the opposite direction to the X direction to a position facing the positive terminal 20H in the Y direction. The positive third portion 71Hc extends from the positive second portion 71Hb in the Y direction to the positive main wiring 70H. The positive terminal 20H is provided on the positive third portion 71Hc.

[0062] The negative side wiring 40L is formed on the arrangement layer 50A and includes a negative side main wiring 70L and a negative side parallel wiring 71L. The negative side main wiring 70L is formed on the arrangement layer 50A on the opposite side of the first capacitor 21 in the Y direction with respect to the U-phase fourth switch Su4 and the second capacitor 22. The negative side main wiring 70L is formed extending in the X direction on the arrangement layer 50A to a position facing the source of the U-phase fourth switch Su4 in the Y direction. The negative side main wiring 70L is formed extending on the arrangement layer 50A on the opposite side of the X direction to a position facing the negative terminal 20L in the Y direction.

[0063] The negative parallel wiring 71L has a negative first portion 71La, a negative second portion 71Lb, and a negative third portion 71Lc. The negative first portion 71La is a portion formed extending in the Y direction from the negative main wiring 70L. The negative second portion 71Lb is a portion formed extending in the opposite direction to the X direction from the negative first portion 71La to a position facing the negative terminal 20L in the Y direction. The negative third portion 71Lc is a portion formed extending in the Y direction from the negative main wiring 70L to the negative second portion 71Lb. The negative terminal 20L is provided on the negative third portion 71Lc.

[0064] The U-phase first wiring 41U is formed on the arrangement layer 50A and extends in the X direction. The U-phase first wiring 41U has a first intermediate portion 41Ua and a first wide portion 41Ub. The first intermediate portion 41Ua is formed in a position on the arrangement layer 50A sandwiched in the Y direction between the source of the U-phase first switch Su1 and the drain of the U-phase second switch Su2. The first wide portion 41Ub is formed and extends in the X direction from the first intermediate portion 41Ua. The first wide portion 41Ub is formed wider in the Y direction than the first intermediate portion 41Ua. In other words, the U-phase first wiring 41U is formed wider in the Y direction on the side where the U-phase first diode Du1 is installed than on the sides where the U-phase first and second switches Su1 and Su2 are installed. In this embodiment, the first wide portion 41Ub is formed on the arrangement layer 50A, extending in the Y direction from the first intermediate portion 41Ua.

[0065] The first wide portion 41Ub faces the first via portion 61 in the X direction via an insulating region. The U-phase first diode Du1 is provided on the arrangement layer 50A such that its anode faces the first via portion 61 and its cathode faces the first wide portion 41Ub.

[0066] The U-phase second wiring 42U is formed on the arrangement layer 50A and extends in the X direction. The U-phase second wiring 42U has a second intermediate portion 42Ua and a second wide portion 42Ub. The second intermediate portion 42Ua is formed in a position on the arrangement layer 50A sandwiched in the Y direction between the source of the U-phase third switch Su3 and the drain of the U-phase fourth switch Su4. The second wide portion 42Ub is formed and extends in the X direction from the second intermediate portion 42Ua. The second wide portion 42Ub is formed wider in the Y direction than the second intermediate portion 42Ua. In other words, the U-phase second wiring 42U is formed wider in the Y direction on the side where the U-phase second diode Du2 is installed than on the sides where the U-phase third and fourth switches Su3 and Su4 are installed. In this embodiment, the second wide portion 42Ub is formed on the arrangement layer 50A, extending from the second intermediate portion 42Ua in the opposite direction to the Y direction.

[0067] The second wide portion 42Ub faces the second via portion 62 in the X direction with an insulating region interposed therebetween. The U-phase second diode Du2 is provided on the arrangement layer 50A such that its anode faces the second wide portion 42Ub and its cathode faces the second via portion 62.

[0068] In this embodiment, in the arrangement layer 50A, the U-phase first and second diodes Du1 and Du2 are provided at positions offset in the X direction from the U-phase first to fourth switches Su1 to Su4, and the first and second capacitors 21 and 22 are provided at positions offset on the opposite side of the X direction. This makes it possible to shorten both the wiring lengths of the U-phase first and second wiring 41U and 42U and the wiring lengths of the positive electrode side wiring 40H and the negative electrode side wiring 40L. This makes it possible to realize a configuration that is suitable for reducing the inductance of the commutation path.

[0069] Each of the U-phase first to fourth switches Su1 to Su4 is a parallel connection of multiple switches, constituting a switch group. Specifically, the U-phase first switch group Su1G is a parallel connection of four U-phase first switches Su1. The U-phase second switch group Su2G is a parallel connection of four U-phase second switches Su2. The U-phase third switch group Su3G is a parallel connection of four U-phase third switches Su3. The U-phase fourth switch group Su4G is a parallel connection of four U-phase fourth switches Su4. The switches Su1, Su2, Su3, and Su4 constituting the U-phase first to fourth switch groups Su1G, Su2G, Su3G, and Su4G are arranged side by side in the X direction.

[0070] The series-connected U-phase first to fourth switches Su1 to Su4 are arranged side by side in the Y direction. In this case, current can flow in the Y direction through the U-phase first and second wirings 41U and 42U and the U-phase output wiring 13U. Therefore, by arranging the switches Su1 to Su4 side by side in the X direction, which is the width direction of the current path, it is possible to widen the wiring width of the portions of the wirings 13U, 41U, and 42U through which current can flow in the Y direction. This makes it possible to realize a configuration that is suitable for reducing the inductance of the commutation path.

[0071] Each of the U-phase first and second diodes Du1 and Du2 is a parallel connection of multiple diodes, constituting a diode group. Specifically, the U-phase first diode group Du1G is a parallel connection of three U-phase first diodes Du1. The U-phase second diode group Du2G is a parallel connection of three U-phase second diodes Du2. The diodes Du1 and Du2 constituting the U-phase first and second diode groups Du1G and Du2G are arranged side by side in the Y direction.

[0072] The U-phase first and second wirings 41U, 42U are formed to extend in the X direction. In this case, current flows in the X direction through the U-phase first and second wirings 41U, 42U. Therefore, by arranging the diodes Du1, Du2 side by side in the Y direction and forming wide portions 41Ub, 42Ub in the U-phase first and second wirings 41U, 42U, the wiring width of the U-phase first and second wirings 41U, 42U can be made wide. This makes it possible to realize a configuration suitable for reducing the inductance of the commutation path.

[0073] The third via portion 63 is provided in the arrangement layer 50A, sandwiched in the Y direction between the positive main wiring 70H and the positive second portion 71Hb with an insulating region interposed therebetween. The fourth via portion 64 is provided in the arrangement layer 50A, sandwiched in the Y direction between the positive second portion 71Hb and the negative second portion 71Lb with an insulating region interposed therebetween. The intermediate terminal 23 is provided in the arrangement layer 50A adjacent to the fourth via portion 64. The fifth via portion 65 is provided in the arrangement layer 50A, sandwiched in the Y direction between the negative main wiring 70L and the negative second portion 71Lb with an insulating region interposed therebetween.

[0074] Each of the first and second capacitors 21 and 22 is a parallel connection of a plurality of capacitors, and constitutes a capacitor group.

[0075] Specifically, the first capacitor group 21G is a parallel connection of six first capacitors 21. The three first capacitors 21a, 21b, and 21c are arranged side by side in the Y direction on the arrangement layer 50A. The first capacitor 21a is arranged on the arrangement layer 50A so that a first end faces the positive main wiring 70H and a second end faces the third via portion 63. The first capacitor 21b is arranged on the arrangement layer 50A so that a first end faces the positive second portion 71Hb and a second end faces the third via portion 63. The first capacitor 21c is arranged on the arrangement layer 50A so that a first end faces the positive second portion 71Hb and a second end faces the fourth via portion 64. Two of each of the first capacitors 21a, 21b, and 21c are arranged side by side in the X direction. The third and fourth via portions 63, 64 are connected to each other via the U-phase third wiring 43U in the connection layer 50B, whereby the six first capacitors 21 are connected in parallel to each other.

[0076] The three second capacitors 22a, 22b, and 22c are arranged side by side in the Y direction on the arrangement layer 50A. The second capacitor 22a is arranged on the arrangement layer 50A so that a first end faces the fifth via portion 65 and a second end faces the negative main wiring 70L. The second capacitor 22b is arranged on the arrangement layer 50A so that a first end faces the fifth via portion 65 and a second end faces the negative second portion 71Lb. The second capacitor 22c is arranged on the arrangement layer 50A so that a first end faces the fourth via portion 64 and a second end faces the negative second portion 71Lb. Two of each of the second capacitors 22a, 22b, and 22c are arranged side by side in the X direction. The fourth and fifth via portions 64 and 65 are connected via the U-phase third wiring 43U in the connection layer 50B. As a result, the six second capacitors 22 are connected in parallel with one another.

[0077] The positive electrode wiring 40H and the negative electrode wiring 40L are formed to extend in the X direction. In this case, current flows in the X direction through the positive electrode wiring 40H and the negative electrode wiring 40L. Therefore, in this embodiment, the capacitors 21a, 21b, 21c, 22a, 22b, and 22c are arranged in the Y direction. The main wiring 70H and 70L and the parallel wiring 71H and 71L are arranged in the Y direction, and the wiring 40H and 40L are formed wider in the Y direction on the side where the capacitors 21 and 22 are installed than on the side where the U-phase first and fourth switches Su1 and Su4 are installed. This allows the wiring width of the wiring 40H and 40L to be wider. As a result, a configuration suitable for reducing the inductance of the commutation path can be realized.

[0078] The fourth via portion 64 is provided in a position on the arrangement layer 50A that is shifted in the Y direction opposite to the X direction from the position where the U-phase output wiring 13U is formed. This allows the empty area on the arrangement layer 50A on the X direction opposite from the U-phase output wiring 13U to be used as arrangement space for the first and second capacitors 21, 22. This makes it possible to realize a configuration that is suitable for increasing the number of parallel connections of each of the first and second capacitors 21, 22.

[0079] Next, the surge voltage reduction effect of the three-level inverter 30 according to the present embodiment will be described more specifically with reference to FIGS.

[0080] 9 to 12 are diagrams showing the commutation paths for each switching pattern flowing through the U-phase circuit unit 31U on the arrangement layer 50A and the connection layer 50B. Figures 9, 10, 11, and 12 correspond to the commutation paths of the switching patterns described above in Figures 2, 3, 4, and 5. In Figures 9 to 12, the range of the commutation path for each wiring on the arrangement layer 50A and the connection layer 50B is schematically indicated by dot hatching.

[0081] In a front view of the circuit board 50, the area in which the U-phase third wiring 43U is formed in the connection layer 50B overlaps at least a portion of the area in which each of the wirings 40H, 40L, 41U to 43U is formed in the arrangement layer 50A. Therefore, as shown in Figures 9 to 12, the commutation path in the connection layer 50B overlaps with the commutation path in the arrangement layer 50A, thereby appropriately reducing the loop area of ​​the commutation path. Therefore, in the three-level inverter 30, the inductance of the commutation path can be appropriately reduced.

[0082] In the switching pattern shown in FIG. 9 , the commutation path includes the U-phase first wiring 41U between the U-phase first and second switches Su1 and Su2 and the U-phase output wiring 13U between the U-phase second and third switches Su2 and Su3. In the switching pattern shown in FIG. 12 , the commutation path includes the U-phase output wiring 13U between the U-phase second and third switches Su2 and Su3 and the U-phase second wiring 42U between the U-phase third and fourth switches Su3 and Su4. Therefore, the commutation path has short wiring lengths L12, L23, and L34, which further reduces the inductance of the commutation path. As already explained, by arranging the U-phase first through fourth switches Su1 through Su4 in the order in which they are connected in series, the wiring lengths L12, L23, and L34 of the wiring between any two of the U-phase first through fourth switches Su1 through Su4 can be shortened.

[0083] In the switching patterns shown in FIGS. 9 and 11 , a path including the U-phase second wiring 42U serves as the commutation path. In the switching patterns shown in FIGS. 10 and 12 , a path including the U-phase first wiring 41U serves as the commutation path. Therefore, the wiring length Lsd of each of the wirings 41U, 42U that constitute the commutation path is short, thereby further reducing the inductance of the commutation path. As already explained, the wiring length Lsd of the U-phase first and second wirings 41U, 42U can be shortened by disposing the U-phase first and second diodes Du1, Du2 at positions offset in the X direction from the U-phase first to fourth switches Su1 to Su4.

[0084] Furthermore, the wide wiring widths W1 and W2 of the U-phase first and second wirings 41U and 42U, which form the commutation paths, allow for a further reduction in the inductance of the commutation paths. As already explained, the wiring widths W1 and W2 of the U-phase first and second wirings 41U and 42U can be increased by arranging multiple diodes connected in parallel with each other in the width direction of the current path and providing wide portions 41Ub and 42Ub in the U-phase first and second wirings 41U and 42U.

[0085] In the switching patterns shown in Figures 9 and 10, the positive electrode side wiring 40H serves as the commutation path. In the switching patterns shown in Figures 11 and 12, the negative electrode side wiring 40L serves as the commutation path. Therefore, the wiring length Lsc of each of the wirings 40H, 40L, which are the commutation paths, is short, which further reduces the inductance of the commutation path. As already explained, the wiring length Lsc of each of the wirings 40H, 40L can be shortened by arranging each of the capacitors 21, 22 at positions offset from the U-phase first to fourth switches Su1 to Su4 on the opposite side of the X direction.

[0086] Furthermore, the widths WH and WL of the wirings 40H and 40L, which are the commutation paths, are wide, which further reduces the inductance of the commutation paths. As already explained, by arranging a plurality of capacitors connected in parallel with each other in the width direction of the current paths to form the positive-side main wiring 70H and the positive-side parallel wiring 71H, and the negative-side main wiring 70L and the negative-side parallel wiring 71L, it is possible to widen the widths WH and WL of the wirings 40H and 40L.

[0087] 9 to 12, the commutation path includes one of the U-phase first to fourth switches Su1 to Su4. Therefore, by widening the width Ws of each switch group Su1G to Su4G, the inductance of the commutation path can be further reduced. As already explained, the width Ws of each switch group Su1G to Su4G can be widened by arranging multiple switches connected in parallel in the width direction of the current path.

[0088] In the arrangement layer 50A, the capacitors 21 and 22, the first to fourth U-phase switches Su1 to Su4, and the first and second U-phase diodes Du1 and Du2 are arranged on the same plane. In this case, the number of connection points via vias can be reduced compared to when the surfaces on which the capacitors 21 and 22, the first to fourth U-phase switches Su1 to Su4, and the first and second U-phase diodes Du1 and Du2 are arranged are not on the same plane. This makes it possible to suppress an increase in inductance due to the arrangement of vias.

[0089] In this embodiment, the U-phase third wiring 43U is a solid pattern formed on the connection layer 50B so as to include the installation areas of the capacitors 21 and 22, the first to fourth U-phase switches Su1 to Su4, and the first and second U-phase diodes Du1 and Du2 arranged on the arrangement layer 50A. This ensures that the area in which the U-phase third wiring 43U is formed is wider than the installation areas of the components 21 and 22, Su1 to Su4, Du1, and Du2 arranged on the arrangement layer 50A. This allows the commutation paths in the connection layer 50B to overlap appropriately with the commutation paths in the arrangement layer 50A. As a result, a configuration suitable for reducing the inductance of the commutation paths can be realized.

[0090] In this embodiment, the V- and W-phase circuit units 31V and 31W have the same configuration as the U-phase circuit unit 31U, and therefore detailed description thereof will be omitted. The components of the V- and W-phase circuit units 31V and 31W are arranged, for example, on the layout layer 50A and the connection layer 50B, at positions offset from the U-phase circuit unit 31U on the opposite side in the Y direction. In this case, the V- and W-phase circuit units 31V and 31W can also achieve the effect of reducing surge voltage, similar to the case described for the U-phase circuit unit 31U.

[0091] In the three-level inverter 30, by adopting the above-described configuration that reduces the inductance of the commutation path, it is possible to reduce the withstand voltage required for components such as the switches Su1 to Su4, Sv1 to Sv4, Sw1 to Sw4, the diodes Du1, Du2, Dv1, Dv2, Dw1, Dw2, and the capacitors 21 and 22. As a result, the three-level inverter 30 can be made smaller.

[0092] Second Embodiment A second embodiment will be described below with reference to the drawings, focusing on differences from the first embodiment. In this embodiment, the arrangement of components in the three-level inverter 30 is changed.

[0093] 13 is a diagram showing an example in which the phase circuit units 131U, 131V, and 131W are mounted on a circuit board 150 (more specifically, a layout layer 150A). Note that the first and second capacitors 21 and 22 are not shown in FIG.

[0094] The phase circuit sections 131U, 131V, and 131W are arranged offset in the Y direction when viewed from the front of the plate surface of the arrangement layer 150A. Specifically, the W-phase circuit section 131W, the V-phase circuit section 131V, and the U-phase circuit section 131U are arranged in this order in the Y direction on the arrangement layer 150A. That is, the U- and V-phase circuit sections 131U and 131V are arranged adjacent to each other in the Y direction, and the V- and W-phase circuit sections 131V and 131W are arranged adjacent to each other. The U- and W-phase circuit sections 131U and 131W have the same configuration as that described in the first embodiment.

[0095] In the V-phase circuit section 131V, the V-phase first switch Sv1, the V-phase second switch Sv2, the V-phase third switch Sv3, and the V-phase fourth switch Sv4 are arranged in this order in the Y direction. That is, the arrangement order of the V-phase first to fourth switches Sv1 to Sv4 in the Y direction is the reverse of the arrangement order of the U- and W-phase first to fourth switches Su1 to Su4 and Sw1 to Sw4. Accordingly, the arrangement of the V-phase first and second diodes Dv1 and Dv2 is also changed.

[0096] The U-phase fourth switch Su4 and the V-phase fourth switch Sv4 are arranged adjacent to each other in the Y direction. The sources of the U- and V-phase fourth switches Su4 and Sv4 are connected to the negative electrode side wiring 40L. The V-phase first switch Sv1 and the W-phase first switch Sw1 are arranged adjacent to each other in the Y direction. The drains of the V- and W-phase first switches Sv1 and Sw1 are connected to the positive electrode side wiring 40H. This simplifies the wiring patterns of the positive electrode side wiring 40H and the negative electrode side wiring 40L compared to when the first to fourth switches Su1 to Su4, Sv1 to Sv4, and Sw1 to Sw4 are arranged in the same order for each phase.

[0097] According to the present embodiment described above, the wiring patterns of the positive electrode side wiring 40H and the negative electrode side wiring 40L can be simplified, thereby increasing the degree of freedom in artwork design. This allows for an appropriate circuit layout. For example, it is possible to realize a circuit layout that can accurately ensure insulation between the positive electrode side wiring 40H and the negative electrode side wiring 40L. By ensuring insulation between the positive electrode side wiring 40H and the negative electrode side wiring 40L, for example, it is possible to prevent short-circuit current from flowing through each of the capacitors 21 and 22.

[0098] Modification of Second Embodiment The U-, V-, and W-phase circuit units do not necessarily have to be arranged side by side in the Y direction.

[0099] FIG. 14 is a diagram showing an example in which the phase circuit sections 231U, 231V, and 231W are mounted on a circuit board 250 (more specifically, on a layout layer 250A).

[0100] The circuit board 250 has a fan-like shape (specifically, a semicircular shape) when viewed from the front of the board surface of the circuit board 250. The phase circuit units 231U, 231V, and 231W are arranged so as to be offset in a direction along the arc of the fan shape of the circuit board 250 (i.e., the circumferential direction). Specifically, the U-phase circuit unit 231U, the V-phase circuit unit 231V, and the W-phase circuit unit 231W are arranged side by side in counterclockwise order in the circumferential direction. In other words, the U- and V-phase circuit units 231U and 231V are arranged adjacent to each other in the circumferential direction, and the V- and W-phase circuit units 231V and 231W are arranged adjacent to each other in the circumferential direction.

[0101] In the arrangement layer 250A, the first to fourth phase switches Su1 to Su4, Sv1 to Sv4, and Sw1 to Sw4 are arranged in a circumferential direction. The first and second phase diodes Du1, Du2, Dv1, Dv2, Dw1, and Dw2 are arranged in a direction perpendicular to the circumferential direction and radially outwardly of the circuit board 250 from the first to fourth phase switches Su1 to Su4, Sv1 to Sv4, and Sw1 to Sw4. The capacitors 21 and 22 are arranged in a radially inwardly of the circuit board 250 from the first to fourth phase switches Su1 to Su4, Sv1 to Sv4, and Sw1 to Sw4. In this embodiment, the circumferential direction of the circuit board 250 corresponds to the "first direction," and the radial direction corresponds to the "second direction." In FIG. 14, the central portion of the sector-shaped arrangement layer 250A and the first and second capacitors 21 and 22 are not shown.

[0102] On the circuit board 250, the switches Su1 to Su4, Sv1 to Sv4, and Sw1 to Sw4 can be arranged so that the V-phase first to fourth switches Sv1 to Sv4 are arranged in the reverse order of the U- and W-phase first to fourth switches Su1 to Su4 and Sw1 to Sw4 in the circumferential direction. Therefore, in this embodiment as well, the wiring patterns of the positive electrode side wiring 40H and the negative electrode side wiring 40L can be simplified, increasing the degree of freedom in artwork design. As a result, an appropriate circuit layout can be achieved.

[0103] Third Embodiment The third embodiment will be described below with reference to the drawings, focusing on differences from the first embodiment. The multilevel inverter is not limited to a three-level inverter, but may be an inverter capable of selecting and outputting one of four or more voltage levels. In this embodiment, the multilevel inverter is a five-level inverter capable of selecting and outputting one of five voltage levels. The five-level inverter can include U-, V-, and W-phase circuit units, as described in the first embodiment. Here, the circuit configuration of the five-level inverter will be described using the U phase as an example.

[0104] 15, the five-level inverter 130 includes a U-phase circuit unit 331U and first to fourth capacitors 121 to 124. For example, the capacitances of the capacitors 121 to 124 are the same. In this embodiment, the first to fourth capacitors 121 to 124 correspond to a "capacitor unit."

[0105] The U-phase circuit unit 331U includes U-phase first to eighth switches Su1 to Su8 and U-phase first to sixth diodes Du1 to Du6. Voltage-controlled semiconductor switching elements, more specifically GaN semiconductor switching devices, are used as the U-phase first to eighth switches Su1 to Su8. In this embodiment, the U-phase first to eighth switches Su1 to Su8 correspond to the "switch unit," and the U-phase first to sixth diodes Du1 to Du6 correspond to the "rectifier unit."

[0106] The capacitors 121 to 124 are connected in series. Specifically, a first end of the first capacitor 121 is connected to the positive terminal 20H and the drain of the U-phase first switch Su1 via a positive side wiring 140H. A second end of the first capacitor 121 and a first end of the second capacitor 122 are connected to the first intermediate terminal 101. A second end of the second capacitor 122 and a first end of the third capacitor 123 are connected to the second intermediate terminal 102. A second end of the third capacitor 123 and a first end of the fourth capacitor 124 are connected to the third intermediate terminal 103. A second end of the fourth capacitor 124 is connected to the negative terminal 20L and the source of the U-phase eighth switch Su8 via a negative side wiring 140L.

[0107] The U-phase first to eighth switches Su1 to Su8 are connected in series with their sources and drains connected. Specifically, the source of the U-phase first switch Su1 is connected to the drain of the U-phase second switch Su2. The source of the U-phase second switch Su2 is connected to the drain of the U-phase third switch Su3. The source of the U-phase third switch Su3 is connected to the drain of the U-phase fourth switch Su4. The source of the U-phase fourth switch Su4 is connected to the drain of the U-phase fifth switch Su5. The source of the U-phase fifth switch Su5 is connected to the drain of the U-phase sixth switch Su6. The source of the U-phase sixth switch Su6 is connected to the drain of the U-phase seventh switch Su7. The source of the U-phase seventh switch Su7 is connected to the drain of the U-phase eighth switch Su8.

[0108] The source of the U-phase first switch Su1, the drain of the U-phase second switch Su2, and the cathode of the U-phase first diode Du1 are connected via a U-phase first wiring 141U. The source of the U-phase fifth switch Su5, the drain of the U-phase sixth switch Su6, and the anode of the U-phase second diode Du2 are connected via a U-phase second wiring 142U. The anode of the U-phase first diode Du1, the cathode of the U-phase second diode Du2, and the first intermediate terminal 101 are connected via a U-phase third wiring 143U.

[0109] The source of the U-phase second switch Su2, the drain of the U-phase third switch Su3, and the cathode of the U-phase third diode Du3 are connected via a U-phase fourth wire 144U. The source of the U-phase sixth switch Su6, the drain of the U-phase seventh switch Su7, and the anode of the U-phase fourth diode Du4 are connected via a U-phase fifth wire 145U. The anode of the U-phase third diode Du3, the cathode of the U-phase fourth diode Du4, and the second intermediate terminal 102 are connected via a U-phase sixth wire 146U.

[0110] The source of the U-phase third switch Su3, the drain of the U-phase fourth switch Su4, and the cathode of the U-phase fifth diode Du5 are connected via a U-phase seventh wire 147U. The source of the U-phase seventh switch Su7, the drain of the U-phase eighth switch Su8, and the anode of the U-phase sixth diode Du6 are connected via a U-phase eighth wire 148U. The anode of the U-phase fifth diode Du5, the cathode of the U-phase sixth diode Du6, and the third intermediate terminal 103 are connected via a U-phase ninth wire 149U.

[0111] The source of the U-phase fourth switch Su4 and the drain of the U-phase fifth switch Su5 are connected to a U-phase output terminal 12U via a U-phase output wiring 13U.

[0112] FIG. 16 is a diagram showing an example in which the U-phase first to eighth switches Su1 to Su8, the U-phase first to sixth diodes Du1 to Du6, and the capacitors 121 to 124 are mounted on a circuit board 350. In FIG.

[0113] The circuit board 350 is a multilayer board having a first layer 350A, a second layer 350B, a third layer 350C, and a fourth layer 350D, and has a rectangular shape when viewed from the front of the board surface of the circuit board 350. The first layer 350A is provided with the first to eighth U-phase switches Su1 to Su8, the first to sixth U-phase diodes Du1 to Du6, and the first to fourth capacitors 121 to 124. The first layer 350A is also provided with the positive electrode side wiring 140H, the negative electrode side wiring 140L, and the first, second, fourth, fifth, seventh, and eighth U-phase wiring 141U, 142U, 144U, 145U, 147U, and 148U.

[0114] U-phase third wiring 143U is formed on second layer 350B. U-phase sixth wiring 146U is formed on third layer 350C. U-phase ninth wiring 149U is formed on fourth layer 350D. In this embodiment, the plate surface of first layer 350A corresponds to the "placement surface," the plate surfaces of second to fourth layers 350B to 350D correspond to the "connection surfaces," and U-phase third, sixth, and ninth wiring 143U, 146U, and 149U correspond to the "connection wiring."

[0115] 16, for convenience, U-phase first to ninth wirings 141U to 149U formed on different layers are shown together to show the connection relationships of the respective components. However, in reality, wirings 140H, 140L, 141U, 142U, 144U, 145U, 147U, and 148U formed on first layer 350A, U-phase third wiring 143U formed on second layer 350B, U-phase sixth wiring 146U formed on third layer 350C, and U-phase ninth wiring 149U formed on fourth layer 350D are formed at positions offset in the Z direction. In a front view of the board surface of circuit board 350, the area in which U-phase third, sixth, and ninth wirings 143U, 146U, and 149U are formed is provided so as to overlap the area in which each of wirings 140H, 140L, 141U, 142U, 144U, 145U, 147U, and 148U is formed on first layer 350A. For example, U-phase third, sixth, and ninth wirings 143U, 146U, and 149U are solid patterns formed on corresponding layers 350B, 350C, and 350D.

[0116] Fig. 17 is a partial cross-sectional view taken along line 17-17 in Fig. 16. Specifically, it is a cross-sectional view of the vicinity of U-phase output terminal 12U.

[0117] The fourth layer 350D, the third layer 350C, the second layer 350B, and the first layer 350A are stacked in this order in the Z-axis direction (thickness direction) of the circuit board 350. In this case, the first layer 350A is the surface layer, and the second to fourth layers 350B to 350D are inner layers.

[0118] Specifically, each of the layers 350A, 350B, 350C, and 350D includes a wiring pattern layer 351A, 351B, 351C, or 351D on which a wiring pattern is formed, and an insulating layer 352A, 352B, 352C, or 352D. The wiring pattern layers and insulating layers of each of the layers 350A, 350B, 350C, and 350D are stacked in the Z-axis direction of the circuit board 350 in the order of "352D," "351D," "352C," "351C," "352B," "351B," "352A," and "351A."

[0119] Although not shown, the wiring pattern layer 351A of the first layer 350A and the wiring pattern layers 351B, 351C, and 351D of the second, third, and fourth layers 350B, 350C, and 350D are connected via vias that penetrate the insulating layers 352A to 352C of the layers 350A to 350C in the Z direction. The wiring pattern layer 351B of the second layer 350B and the wiring pattern layer 351C of the third layer 350C are connected via vias that penetrate the insulating layer 352B of the second layer 350B in the Z direction. The wiring pattern layer 351C of the third layer 350C and the wiring pattern layer 351D of the fourth layer 350D are connected via vias that penetrate the insulating layer 352C of the third layer 350C in the Z direction.

[0120] According to this embodiment, the second, third, and fourth layers 350B, 350C, and 350D, on which the U-phase third, sixth, and ninth wirings 143U, 146U, and 149U are formed, are different from the first layer 350A, on which the capacitors 121-124, the U-phase first to eighth switches Su1-Su8, and the U-phase first to sixth diodes Du1-Du6 are arranged. This increases the degree of freedom in the arrangement of the U-phase third, sixth, and ninth wirings 143U, 146U, and 149U. This allows the U-phase third, sixth, and ninth wirings 143U, 146U, and 149U to be arranged so as to reduce the loop area of ​​the commutation path including the U-phase third, sixth, and ninth wirings 143U, 146U, and 149U. This reduces surge voltages induced by the inductance of the commutation path in the five-level inverter 130.

[0121] Other Embodiments The above-described embodiments may be modified as follows.

[0122] The multilevel inverter may be a two-phase or four or more-phase inverter.

[0123] In a multi-phase three-level inverter, as described in the second embodiment, the fourth switches for two of the multiple phases may be arranged adjacent to each other in the Y direction, and the sources of the fourth switches for the two phases may be connected to the negative wiring. Also, the first switches for two of the multiple phases may be arranged adjacent to each other in the Y direction, and the drains of the first switches for the two phases may be connected to the positive wiring.

[0124] Each switch constituting each phase circuit unit may be an N-channel MOSFET made of SiC. In this case, each switch has a body diode.

[0125] Each switch constituting each phase circuit may be an IGBT made of silicon. In this case, the high-potential terminal of the switch is the collector, and the low-potential terminal is the emitter. A freewheel diode is connected in reverse parallel to each switch.

[0126] As the rectifying elements constituting each phase circuit section, switches such as GaN semiconductor switching devices, N-channel MOSFETs, and IGBTs can be used instead of diodes.

[0127] The circuit board may be a multi-layer board having an arrangement layer as an inner layer and a connection layer as a surface layer.

[0128] The placement surface and the connection surface do not necessarily have to be formed on different layers of a multilayer board. For example, the front surface of the board may be the placement surface, and the back surface of the placement surface may be the connection surface. In this case, the circuit board does not have to be a multilayer board.

[0129] The installation of a control system including a multilevel inverter and a rotating electric machine is not limited to a vehicle, but may be, for example, a moving body such as an aircraft or a ship. If the moving body is an aircraft, the rotating electric machine serves as a power source for the aircraft's flight, and if the moving body is a ship, the rotating electric machine serves as a power source for the ship's navigation. Furthermore, the installation of a control system is not limited to a moving body.

[0130] - The following describes characteristic configurations extracted from the above-described embodiments. [Configuration 1] A multilevel inverter (30, 130) including: a plurality of capacitor units (21, 22, 121-124) connected in series; a plurality of switch units (Su1-Su8, Sv1-Sv4, Sw1-Sw4) controlled to select and output one of a plurality of voltages that can be output from the series connection of the capacitor units; and a plurality of rectifier units (Du1-Du6, Dv1, Dv2, Dw1, Dw2) that rectify a current flowing through the switch units when an intermediate level voltage is selected from the plurality of voltages, wherein the multilevel inverter (30, 130) includes a substrate (50, 150, 250, 350) on which the capacitor units, the switch units, and the rectifier units are mounted, the substrate having as a plate surface: an arrangement surface on which the capacitor units, the switch units, and the rectifier units are arranged; a connection surface, which is a plate surface different from the arrangement surface, and on which connection wiring (43U, 43V, 43W, 143U, 146U, 149U) electrically connecting each of the capacitor units and each of the rectifier units is formed. [Configuration 2] The multilevel inverter according to Configuration 1, wherein the switch units are connected in series, and the switch units are arranged on the arrangement surface in the order of their series connection. [Configuration 3] The multilevel inverter according to Configuration 2, wherein the rectifier unit is provided on the arrangement surface at a position shifted from each of the switch units in a second direction orthogonal to a first direction in which the switch units are arranged, and each of the capacitor units is provided on the arrangement surface at a position opposite to the installation position of the rectifier unit with respect to each of the switch units in the second direction.[Configuration 4] The plurality of switch units include a first switch (Su1, Sv1, Sw1), a second switch (Su2, Sv2, Sw2), a third switch (Su3, Sv3, Sw3), and a fourth switch (Su4, Sv4, Sw4), The plurality of rectifier units include a first diode (Du1, Dv1, Dw1) and a second diode (Du2, Dv2, Dw2), The plurality of capacitor units include a first capacitor (21) and a second capacitor (22) connected in series, The first switch, the second switch, the third switch, and the fourth switch are connected in series in this order, A high potential side terminal of the first switch is connected to a first end of the first capacitor via a positive side wiring (40H) formed on the arrangement surface, A low potential side terminal of the fourth switch is connected to a second end of the second capacitor via a negative side wiring (40L) formed on the arrangement surface, a low-potential terminal of the first switch and a high-potential terminal of the second switch are connected to the cathode of the first diode via first intermediate wiring (41U, 41V, 41W) formed on the placement surface; a low-potential terminal of the third switch and a high-potential terminal of the fourth switch are connected to the anode of the second diode via second intermediate wiring (42U, 41V, 41W) formed on the placement surface; and an anode of the first diode and a cathode of the second diode are connected to the second end of the first capacitor and the first end of the second capacitor via the connection wiring (43U, 43V, 43W) formed on the connection surface.[Configuration 5] The multilevel inverter according to Configuration 4, wherein the positive side wiring extending in the second direction is formed on the arrangement surface on a side opposite the second capacitor in the first direction with respect to the first switch and the first capacitor; the negative side wiring extending in the second direction is formed on the arrangement surface on a side opposite the first capacitor in the first direction with respect to the fourth switch and the second capacitor; the first intermediate wiring extending in the second direction is formed on the arrangement surface between the first switch and the second switch in the first direction; the second intermediate wiring extending in the second direction is formed on the arrangement surface between the third switch and the fourth switch in the first direction; and the connection wiring overlaps with at least a part of each of the positive side wiring, the negative side wiring, the first intermediate wiring, and the second intermediate wiring in a front view of the plate surface of the substrate. [Configuration 6] The multilevel inverter according to Configuration 5, wherein each of the first diode and the second diode is configured by a parallel connection of a plurality of diodes, the plurality of diodes configuring the first diode and the second diode are arranged side by side in the first direction on the arrangement surface, the first intermediate wiring is formed wider in the first direction on the side of an installation position of the first diode than on the side of installation positions of the first switch and the second switch, and the second intermediate wiring is formed wider in the first direction on the side of an installation position of the second diode than on the side of installation positions of the third switch and the fourth switch.[Configuration 7] The multilevel inverter according to Configuration 5 or 6, wherein each of the first capacitor and the second capacitor is formed by a parallel connection of a plurality of capacitors, and the plurality of capacitors constituting the first capacitor and the second capacitor are arranged side by side in the first direction on the arrangement surface, and the first switch, the second switch, the third switch, and the fourth switch are arranged between the first capacitor and the second capacitor and the first diode and the second diode on the arrangement surface, and the positive side wiring is formed wider in the first direction on the side of an installation position of the first capacitor than on the side of an installation position of the first switch, and the negative side wiring is formed wider in the first direction on the side of an installation position of the second capacitor than on the side of an installation position of the fourth switch. [Configuration 8] The multilevel inverter according to any one of Configurations 3 to 7, wherein each of the switch units is formed by a parallel connection of a plurality of switches, and the plurality of switches constituting each switch unit are arranged side by side in the second direction on the arrangement surface. [Configuration 9] The multilevel inverter according to any one of Configurations 4 to 8, wherein the arrangement surface on which the first capacitor, the second capacitor, the first switch, the second switch, the third switch, the fourth switch, the first diode, and the second diode are provided is the same surface. [Configuration 10] The multilevel inverter according to any one of Configurations 4 to 9, wherein the connection wiring is a solid pattern formed on the connection surface so as to include installation positions of the first capacitor, the second capacitor, the first switch, the second switch, the third switch, the fourth switch, the first diode, and the second diode that are arranged on the arrangement surface.[Configuration 11] The multilevel inverter according to any one of configurations 4 to 10, wherein the first switch, the second switch, the third switch, the fourth switch, the first diode, and the second diode are provided for the number of phases, and in the arrangement plane, the fourth switches for two of the multiple phases are arranged adjacent to each other in the first direction, and low potential side terminals of the fourth switches for each of the two phases are connected to the negative side wiring, or the first switches for two of the multiple phases are arranged adjacent to each other in the first direction, and high potential side terminals of the first switches for each of the two phases are connected to the positive side wiring. [Configuration 12] The multilevel inverter according to any one of configurations 4 to 10, wherein the first switch, the second switch, the third switch, the fourth switch, the first diode, and the second diode are provided for three phases, and in the arrangement plane, the fourth switches for a U phase and a V phase of the three phases are arranged adjacent to each other in the first direction, and low potential side terminals of the fourth switches for the U phase and the V phase are connected to the negative side wiring, and the first switches for a V phase and a W phase of the three phases are arranged adjacent to each other in the first direction, and high potential side terminals of the first switches for the V phase and the W phase are connected to the positive side wiring.

[0131] Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

Claims

1. A multilevel inverter (30, 130) comprising: a plurality of capacitor units (21, 22, 121-124) connected in series; a plurality of switch units (Su1-Su8, Sv1-Sv4, Sw1-Sw4) controlled to select and output one of a plurality of voltages that can be output from the series connection of the capacitor units; and a plurality of rectifier units (Du1-Du6, Dv1, Dv2, Dw1, Dw2) that rectify a current flowing through the switch units when an intermediate level voltage is selected from the plurality of voltages, wherein the multilevel inverter (30, 130) comprises a substrate (50, 150, 250, 350) on which the capacitor units, the switch units, and the rectifier units are mounted, the substrate having as a plate surface: an arrangement surface on which the capacitor units, the switch units, and the rectifier units are arranged; a connection surface that is a plate surface different from the arrangement surface and on which connection wiring (43U, 43V, 43W, 143U, 146U, 149U) that electrically connects the capacitor units and the rectifier units is formed.

2. The multilevel inverter according to claim 1, wherein the switch units are connected in series, and the switch units are arranged side by side in the order of the series connection on the layout surface.

3. The multilevel inverter according to claim 2, wherein the rectifier section is provided at a position on the arrangement surface that is shifted from each of the switch sections in a second direction that is perpendicular to a first direction in which the switch sections are arranged, and wherein each of the capacitor sections is provided at a position on the arrangement surface that is opposite to the installation position of the rectifier section with respect to each of the switch sections in the second direction.

4. The plurality of switch sections include a first switch (Su1, Sv1, Sw1), a second switch (Su2, Sv2, Sw2), a third switch (Su3, Sv3, Sw3), and a fourth switch (Su4, Sv4, Sw4), the plurality of rectifier sections include a first diode (Du1, Dv1, Dw1) and a second diode (Du2, Dv2, Dw2), the plurality of capacitor sections include a first capacitor (21) and a second capacitor (22) connected in series, the first switch, the second switch, the third switch, and the fourth switch are connected in series in this order, a high potential side terminal of the first switch is connected to a first end of the first capacitor via a positive side wiring (40H) formed on the arrangement surface, and a low potential side terminal of the fourth switch is connected to a second end of the second capacitor via a negative side wiring (40L) formed on the arrangement surface, 4. The multilevel inverter according to claim 3, wherein a low potential side terminal of the first switch and a high potential side terminal of the second switch are connected to the cathode of the first diode via first intermediate wiring (41U, 41V, 41W) formed on the arrangement surface, a low potential side terminal of the third switch and a high potential side terminal of the fourth switch are connected to the anode of the second diode via second intermediate wiring (42U, 41V, 41W) formed on the arrangement surface, and an anode of the first diode and a cathode of the second diode are connected to the second end of the first capacitor and the first end of the second capacitor via the connection wiring (43U, 43V, 43W) formed on the connection surface.

5. The multilevel inverter according to claim 4, wherein the positive side wiring extending in the second direction is formed on the arrangement surface on a side opposite the second capacitor in the first direction with respect to the first switch and the first capacitor; the negative side wiring extending in the second direction is formed on the arrangement surface on a side opposite the first capacitor in the first direction with respect to the fourth switch and the second capacitor; the first intermediate wiring extending in the second direction is formed on the arrangement surface between the first switch and the second switch in the first direction; the second intermediate wiring extending in the second direction is formed on the arrangement surface between the third switch and the fourth switch in the first direction; and the connection wiring overlaps with at least a portion of each of the positive side wiring, the negative side wiring, the first intermediate wiring, and the second intermediate wiring when viewed from the front of the plate surface of the substrate.

6. The multilevel inverter according to claim 5, wherein each of the first diode and the second diode is composed of a parallel connection of a plurality of diodes, the plurality of diodes constituting the first diode and the second diode are arranged side by side in the first direction on the arrangement surface, the first intermediate wiring is formed wider in the first direction on the side of the installation position of the first diode than on the side of the installation positions of the first switch and the second switch, and the second intermediate wiring is formed wider in the first direction on the side of the installation position of the second diode than on the side of the installation positions of the third switch and the fourth switch.

7. The multilevel inverter according to claim 5, wherein each of the first capacitor and the second capacitor is composed of a parallel connection of a plurality of capacitors, the plurality of capacitors constituting the first capacitor and the second capacitor are arranged side by side in the first direction on the arrangement surface, the first switch, the second switch, the third switch and the fourth switch are provided between the first capacitor and the second capacitor and the first diode and the second diode on the arrangement surface, the positive side wiring is formed wider in the first direction on the installation position side of the first capacitor than on the installation position side of the first switch, and the negative side wiring is formed wider in the first direction on the installation position side of the second capacitor than on the installation position side of the fourth switch.

8. A multilevel inverter according to any one of claims 3 to 7, wherein each of the switch sections is composed of a parallel connection of a plurality of switches, and in the layout plane, the plurality of switches constituting each of the switch sections are arranged side by side in the second direction.

9. The multilevel inverter according to any one of claims 4 to 7, wherein the arrangement surface on which the first capacitor, the second capacitor, the first switch, the second switch, the third switch, the fourth switch, the first diode, and the second diode are provided is the same surface.

10. The multilevel inverter according to any one of claims 4 to 7, wherein the connection wiring is a solid pattern formed on the connection surface so as to include the installation positions of the first capacitor, the second capacitor, the first switch, the second switch, the third switch, the fourth switch, the first diode, and the second diode arranged on the arrangement surface.

11. The multilevel inverter according to any one of claims 4 to 7, wherein the first switch, the second switch, the third switch, the fourth switch, the first diode, and the second diode are provided for the same number of phases, and in the arrangement plane, the fourth switches for two of the multiple phases are arranged adjacent to each other in the first direction, and low potential side terminals of the fourth switches for each of the two phases are connected to the negative side wiring, or the first switches for two of the multiple phases are arranged adjacent to each other in the first direction, and high potential side terminals of the first switches for each of the two phases are connected to the positive side wiring.

12. The multilevel inverter according to any one of claims 4 to 7, wherein the first switch, the second switch, the third switch, the fourth switch, the first diode, and the second diode are provided for three phases, and in the arrangement plane, the fourth switches for U-phase and V-phase of the three phases are arranged adjacent to each other in the first direction, and low potential side terminals of the fourth switches for U-phase and V-phase are connected to the negative side wiring, and the first switches for V-phase and W-phase of the three phases are arranged adjacent to each other in the first direction, and high potential side terminals of the first switches for V-phase and W-phase are connected to the positive side wiring.

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