Region-based filtering of parasitic networks for circuit test simulations

Abstract

Systems and methods are presented for region-specific filtering of parasitic networks for circuit test simulations. A method may include performing a circuit test through a parasitic network extracted for a circuit design, including by defining a region of the circuit design based on test locations specified for the circuit test and performing a tile filtering to remove any tiles for the specific nets that do not intersect with the region. Performing the circuit test may also include, for remaining tiles after the tile filtering, performing a resistor-filtering to remove any parasitic resistors in the remaining tiles that do not intersect with the region, obtaining a filtered parasitic network by performing a network-filtering on the parasitic network to remove network portions that do correspond to remaining parasitic resistors in the remaining tiles after the resistor-filtering, and performing a simulation for the circuit test through the filtered parasitic network.

Description

REGION-BASED FILTERING OF PARASITIC NETWORKS FOR CIRCUIT TEST SIMULATIONSCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 568,723, filed on March 22, 2024, and titled “REGION-BASED FILTERING OF PARASITIC NETWORKS FOR CIRCUIT TEST SIMULATIONS,” the entirety of which is incorporated by reference herein.BACKGROUND

[0002] Electronic circuits, such as integrated circuits, are used in nearly every facet of modem society, from automobiles to microwaves to personal computers. Design of circuits may involve many steps, known as a "design flow." The particular steps of a design flow are often dependent upon the type of circuit being designed, its complexity, the design team, and the circuit fabricator or foundry that will manufacture the circuit. Electronic design automation (EDA) applications support the design and verification of circuits prior to fabrication. EDA applications may implement various EDA procedures, e.g., functions, tools, or features to analyze, test, or verify a circuit design at various stages of the design flow.BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Certain examples are described in the following detailed description and in reference to the drawings.

[0004] Figure 1 shows an example of a computing system that supports region-based filtering of parasitic networks for circuit test simulations according to the present disclosure.

[0005] Figure 2 shows an example region definition for a circuit test based on test locations specified for the circuit test according to the present disclosure.

[0006] Figure 3 shows an example tile-filtering of a tile set based on a defined region for a circuit test according to the present disclosure.

[0007] Figure 4 shows an example of resistor-filtering and network-filtering according to the present disclosure.

[0008] Figure 5 shows an example of logic that a system may implement to support region-based filtering of parasitic networks for circuit test simulations according to the present disclosure.

[0009] Figure 6 shows an example of a computing system that supports region-based filtering of parasitic networks for circuit test simulations according to the present disclosure.DETAILED DESCRIPTION

[0010] Electronic circuits, such as integrated circuits (ICs), are used in nearly every facet of modem society, from automobiles to microwaves to personal computers. The design, verification, and physical manufacture of circuit devices often involve several steps, sometimes referred to as a "design flow." The particular steps of a design flow are dependent upon various factors, such as the type of integrated circuit being designed, its complexity, the design team, and the integrated circuit fabricator (e.g., foundry) that will manufacture the physical circuit. Typically, software and hardware tools can verify the circuit designs at various stages of the design flow, for example through complex rule checks, software-based simulations, hardware-based emulation, and various other techniques supported by modem EDA technology. These steps of a design flow aid in the discovery of errors in circuit designs, and allow design teams and engineers to correct or otherwise improve the designs prior to, during, or after physical manufacture.

[0011] Several steps are common to most design flows of IC design. Initially, the specification for a new circuit can be transformed into or otherwise generated as a logical design. Logical designs are sometimes referred to as a register transfer level (RTL) description of a circuit. With logical designs, a circuit can be described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high-speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed to confirm that the design will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as "functional verification."

[0012] After the accuracy of the logical design is confirmed through functional verification, a logical design can be converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, can describe the specific electronic devices (e.g., transistors, resistors, and capacitors) that form the circuit design, along with the interconnections between these electronic devices. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. The relationships between the electronic devices are then analyzed to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as "formal verification." Additionally, preliminary timing estimates for portions of the circuit are often made at this stage, using an assumed characteristic speed for each device, and incorporated into the verification process.

[0013] Once the electronic devices components and their interconnections are established, the design can again be transformed in a design flow. In particular, the next transformation may be to a physical design that describes specific geometric elements that form the circuit design. This type of physical version of a circuit design is often referred to as a "layout" design or “physical layout” (and may simply be referred to as a “layout”). The geometric elements, which typically are polygons, define the shapes that will be created in various layers of material to physically manufacture the circuit. Automated place androute tools can be used to define or generate the physical layouts, especially for wires that will be used to interconnect the circuit devices in the physical representation of the circuit design. Each layer of a circuit can have a corresponding layer representation in the layout design, and the geometric shapes described in a layer representation will define the relative locations of the circuit elements that will make up the circuit device (e.g., of transistors, resistors, capacitors, etc.). For example, shapes in the layer representation of a metal layer will define the locations of the metal wires used to connect the circuit devices.

[0014] Integrated circuit layout descriptions can be provided in many different formats. The Graphic Data System II (GDSII) format is a popular format for transferring and archiving two-dimensional graphical IC layout data. Among other features, GDSII contains a hierarchy of structures, each structure containing layout elements (e.g., polygons, paths or poly-lines, circles and textboxes). Other layout formats include an open-source format named Open Access, Milkyway by Synopsys, Inc., EDDM by Siemens EDA (formerly Mentor Graphics Corporation), and the Open Artwork System Interchange Standard (OASIS) format proposed by Semiconductor Equipment and Materials International (SEMI). These various industry formats are used to define the geometrical information in IC layout designs that are employed to manufacture integrated circuits. Once the circuit design is finalized, the layout portion of the design can be used by fabrication tools to manufacture the device using a photolithographic process.

[0015] Typically, a designer will perform a number of verification processes on the layout design. For example, the layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships described in the device design. In this process, a layout-versus-schematic (LVS) tool can extract a netlist from the layout design and compare it with the netlist taken from the circuit schematic. LVS can be augmented by formal equivalence checking, which checks whether two circuits perform exactly the same function without demanding isomorphism.

[0016] The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements and minimum linewidths of geometric elements. Such checks may be part of a design rule checking (DRC) process performed on layout design. DRC tools can take, as an input, a physical layout (e.g., in the GDSII or OASIS standard format) as well as a rule deck which specifies the specific rule checks to perform on the layout design. As checks in a DRC process can be specific to a particular circuit fabrication process, rule decks are typically provided by a foundry or circuit manufacturer specifying the particular rules that circuit designs must adhere to for circuit fabrication via the foundry (e.g., at a specified technology node or specific fabrication process parameters). Put another way, foundry-provided rule decks can include a list of rules specific to the semiconductor fabrication process employed by the foundry or otherwise selected for use in circuit manufacture. As such, a set of rules for a particular fabrication process can be referred to as a run-set, rule deck, or just a deck. An example format used for implementation of rule decks is the Standard Verification Rule Format (SVRF) by Siemens EDA (formerly Mentor Graphics Corporation).

[0017] There are many different fabrication processes for manufacturing a circuit, but most processes include a series of steps that deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and then etch the exposed (or non-exposed) portions of the layer away. For example, a simple semiconductor device component could be manufactured by the following steps. First, a positive-type epitaxial layer is grown on a silicon substrate through chemical vapor deposition. Next, a nitride layer is deposited over the epitaxial layer. Then specific areas of the nitride layer are exposed to radiation, and the exposed areas are etched away, leaving behind exposed areas on the epitaxial layer, (i.e., areas no longer covered by the nitride layer). The exposed areas then are subjected to a diffusion or ion implantation process, causing dopants, for example phosphorus, to enter the exposed epitaxial layer and form charged wells. This process of depositing layers of material on the substrate or subsequentmaterial layers, and then exposing specific patterns to radiation, etching, and dopants or other diffusion materials, is repeated a number of times, allowing the different physical layers of the circuit to be manufactured.

[0018] Each time that a layer of material is exposed to radiation, a photomask (mask) must be created to expose only the desired areas to the radiation, and to protect the other areas from exposure. The mask is created from circuit layout data. That is, the geometric elements described in a physical layout define the relative locations or areas of the circuit wafer that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create the mask based upon the design layout, after which the mask can be used in a photolithographic process for fabrication of physical circuits. One or more resolution enhancement techniques (RETs) are often employed to improve the resolution of the image that the mask forms on the substrate during the photolithographic process. One of these techniques is optical proximity correction (OPC). OPC can be rule-based, model-based, or both. In rule-based OPC, the proximity effects are characterized, and specific solutions are devised for specific geometric configurations. The layout design is then searched using a DRC tool or a geometric-based software engine to find these geometric configurations. Once they are found, the specific solutions are applied. Through various steps of a design flow, the design, manufacture, and fabrication of circuits can be performed and supported through EDA technology.

[0019] While various steps of a design flow are described herein, circuit manufacture processes continue to evolve and may include any additional or alternative flow steps. Moreover, the intricacy of each step in a design flow is immense, especially as circuit designs continue to increase in complexity and the transistors and other devices that form a circuit are merely a few atoms wide. As such, accurate and effective design flow steps may increase the efficiency of circuit design and improvements at any given step in the design flow can yield significant benefits.

[0020] With increased circuit design complexity, appropriate analysis and verification of circuit designs may be necessary to ensure that IC reliability,functionality, and performance requirements are satisfied. Parasitic extractions are one form of verification that EDA design flows may employ, which can entail the calculation of parasitic effects in a circuit design. In some implementations, parasitic extractions support the calculation of various parasitic effects on a circuit design, such as parasitic resistances, capacitances, inductances, and the like. The output of such parasitic extraction processes may be a parasitic network, which may be in the form of resistors (an R-network), resistors and capacitors (an RC-network), or any other suitable form. Parasitic networks allow circuit designers to test the behavior of circuit designs and determine when possible issues may arise. Such tests may be in the form of point-to-point resistance simulations, current density experiments through a number of activated sources and sinks, voltage drop measurements (e.g., along branch points and victim devices), and more.

[0021] Analysis and simulation through extracted parasitic networks (e.g., R or RC-parasitic networks) has becoming increasingly challenging as the complexity of modem circuit designs continues to explode. Processing scaling, smaller technology nodes, and increased transistor counts have resulted in modem integrated circuits with billions of circuit devices, often times more. The hardware requirements or simulation latencies to test modem circuits (including extracted parasitic networks) has become a bottleneck in EDA design flows. Electrostatic discharge and reliability tests, simulations, or verifications can require simulation of chip-wide power or ground networks, which can require massive amounts of parasitic network data to be processed. Parasitic network (e.g., netlist) extractions for power and ground nets of a full-chip design may require immense amounts of hardware resources, and testing and simulations based on such networks may likewise require immense computational resources and time.

[0022] Some techniques have been developed to enhance performance and reduce the problem complexity of parasitic network simulations. Netlist reductions to reduce the extraction size of a parasitic network can result in an overall smaller netlist of a R or RC-network. However, such reductions may be performed on a global level, without regard to the actual point-to-point,voltage drop, or current density tests being performed. Thus, such optimizations can be limited in effectiveness. Another attempt to address simulation complexity is to increase the computational capability of EDA systems. With an increased number of compute nodes, processors, or machines that form a distributed EDA system, simulation latencies can be decreased through sheer computational power. However, such brute-force computational increases may be limited by an EDA system’s resources and become prohibitive in cost.

[0023] The disclosure herein may provide systems, methods, devices, and logic for region-based filtering of parasitic networks for circuit test simulations.

[0024] Figure 1 shows an example of a computing system that supports region-based filtering of parasitic networks for circuit test simulations according to the present disclosure. The computing system 100 may take the form of a single or multiple computing devices such as application servers, compute nodes, desktop or laptop computers, smart phones or other mobile devices, tablet devices, embedded controllers, and more. In some implementations, the computing system 100 hosts, instantiates, executes, supports, or implements an EDA application or EDA system that supports circuit design and analysis, and may accordingly provide or implement any of the region-based filtering technology described herein.

[0025] As an example implementation to support any combination of the region-based filtering technology described herein, the computing system 100 shown in Figure 1 includes an region-based filtering engine 110. The computing system 100 may implement the region-based filtering engine 110 (including components thereof) in various ways, for example as hardware and programming. The programming for the region-based filtering engine 110 may take the form of processor-executable instructions stored on a non- transitory machine-readable storage medium and the hardware for the regionbased filtering engine 110 may include a processor to execute those instructions. A processor may take the form of single processor or multiprocessor systems, and in some examples, the computing system 100 implements multiple engines using the same computing system features orhardware components (e.g., a common processor or a common storage medium).

[0026] In operation, the region-based filtering engine 110 may perform a circuit test through a parasitic network extracted for a circuit design. Any suitable parasitic network extraction technique, process, or feature may be supported, implemented, or otherwise used by the region-based filtering engine 110. In some implementations, the region-based filtering engine 110 may itself extract a parasitic network for a circuit design. In other implementations, the region-based filtering engine 110 may access or use a previously-extracted parasitic network, e.g., a parasitic network extracted at a prior or different step in an EDA flow.

[0027] The region-based filtering engine 110 may support performance of circuit tests of any type through the parasitic network. Example circuit tests include point-to-point tests, current density tests, voltage drop tests, or any other suitable circuit test can be performed through simulations of the parasitic network. In some implementations, parameters of circuit tests may be specified through a control file that the region-based filtering engine 110 can access. A control file may specify multiple tests to perform through a parasitic network, such as point-to-point tests at various different point pairs in the circuit design, current density tests with different sets of sources and sinks activated, electrostatic discharge tests, voltage drop tests along branch points and victim devices, reliability tests, and the like. Based on the parameters specified for a given circuit test, the region-based filtering engine 110 may filter the parasitic network to utilize only a relevant subset necessary to perform a given test, for example via the various region-based filtering features described herein.

[0028] In performing the circuit test, the region-based filtering engine 110 may defining a region of the circuit design based on the test locations specified for the circuit test and performing a tile filtering, from a tile set for specific nets applicable to the circuit test, to remove any tiles for the specific nets that do not intersect with the region. In performing the circuit test, the region-based filtering engine 110 may further, for remaining tiles in the tile set after the tilefiltering, perform a resistor-filtering to remove any parasitic resistors in the remaining tiles that do not intersect with the region and obtain a filtered parasitic network by performing a network-filtering on the parasitic network to remove network portions that do correspond to the remaining parasitic resistors in the remaining tiles after the resistor-filtering. Then, the regionbased filtering engine 110 may perform a simulation for the circuit test through the filtered parasitic network.

[0029] These and other technical features and technical benefits of the region-based filtering technology are described in greater detail next.

[0030] Figure 2 shows an example region definition for a circuit test based on test locations specified for the circuit test according to the present disclosure. In support of the region-based filtering technology described herein, the region-based filtering engine 110 may define a region of the circuit design for which a particular circuit test applies to. The defined region may be referred to, defined by, or represented as a bounding box. In some sense, the region defined by the region-based filtering engine 110 may delineate a specific circuit design sub-portion or extracted parasitic network sub-portion upon which to perform a given circuit test. Thus, the region-based filtering engine 110 may limit computations, simulations, solving or other R or RC- network processing to the specifically relevant sub-portion instead of an entire circuit design (or entire extracted parasitic network thereof). By flexibly partitioning the relevant circuit or network sub-portion on a per-test basis, the region-based filtering technology of the present disclosure may improve processing efficiency by filtering other portions of a circuit design that contribute minimally or negligibly to the simulation of the given circuit test.

[0031] In the example of Figure 2, the region-based filtering engine 110 defines a region for a given circuit test performed for a circuit design 210. The region-based filtering engine 110 may define a region for a given circuit test based on the test locations specified for the given circuit test, such as the test locations 220 shown in Figure 2. To do so, the region-based filtering engine 110 may analyze the test locations 220 specified for a circuit test to determine a bounded region of the circuit design 210 that includes all of the specifiedtest locations 220, but not an entirety of the circuit design 210. To do so, the region-based filtering engine 110 may parse through the test locations 220 to determine extrema vertices for the test locations. An extrema vertex may refer to any location determined among or based on the test locations 220 that comprises a maximum or minimum horizontal or vertical coordinate among the test locations 220. To explain in a 2-dimensional x-y coordinate system, the extrema vertices of the test locations 220 may comprise the test locations with the highest x-value coordinate, the lowest x-value coordinate, the highest y-value coordinate, and the lowest y-value coordinate. To explain in terms of directional terms, the extrema vertices may comprise a leftmost test location among the test locations, a rightmost test location among the test locations, an uppermost test location among the test locations, and a lowermost test location among the test locations 220.

[0032] For a point-to-point circuit test with two test locations (e.g., the two test locations 220 of Figure 2), then it can be understood that the two test locations form the extrema vertices. This may be the case as one of the two test locations may necessarily include a greatest or least x-coordinate and y- coordinate value and vice versa. For current density circuit tests with multiple source and sink locations or other circuit tests with multiple locations, then the region-based filtering engine 110 may determine the extrema vertices of a such a circuit test by a determining the minimum and maximum x- and y- coordinate values from among the test locations.

[0033] In some implementations, the region-based filtering engine 110 may determine extrema vertices relative to a circuit device located at the test locations. Circuit tests may specify test locations that correspond to or are positioned within specific test devices of a circuit design, such as pin-pairs, ports, internal nodes, circuit output pins, etc. The region-based filtering engine 110 may determine extrema vertices such that the circuit devices at which the test locations are specified are not partially split or otherwise cut-off by a defined region. Thus, in some implementations, the region-based filtering engine 110 may determine the extrema vertices to comprise (in directional terms) a leftmost location of a circuit device at a leftmost test location amongthe test locations, a rightmost location of a circuit device at a rightmost test location among the test locations, an uppermost location of a circuit device at an uppermost test location among the test locations, a lowermost location of a circuit device at a lowermost test location among the test locations, or combinations thereof.

[0034] To illustrate through the example of Figure 2, the region-based filtering engine 110 may determine extrema vertices for the test locations 220 based on the circuit devices in which the test locations 220 are positioned within. This can be seen in Figure 2 as the circuit devices 230. Thus, for the lower-left test location of the test locations 220 of Figure 2, the region-based filtering engine 110 may determine the extrema vertex 241 as the lower- leftmost corner, coordinate, or position of the corresponding circuit device that this lower-left test location is located within. For the upper-right test location of the test locations 220 of Figure 2, the region-based filtering engine 110 may determine the extrema vertex 242 as the upper-rightmost corner, coordinate, or position of the corresponding circuit device that this upper-right test location is located within. Thus, in the example of Figure 2, the region-based filtering engine 110 may determine the extrema vertices 241 and 242 based on the test locations 220 specified for a given circuit test for the circuit design 210.

[0035] As the extrema vertices may specify minimum or maximum coordinate values among or otherwise based on specified test locations, the region-based filtering engine 110 may define the region as a rectangular bounding box that passes through the extrema vertices (and thus encapsulates each of the test locations specified for a circuit test).

[0036] In some implementations, the region-based filtering engine 110 may define a region that extends past the determined extrema vertices. For example, the region-based filtering engine 110 may buffer the extrema vertices to form buffered extrema vertices by adding a buffer amount to each of the extrema vertices. The region-based filtering engine 110 may buffer any type of determined extrema vertex, whether as a test location itself or as a coordinate, location, or position of a circuit device a test location is located within.

[0037] Buffering the extrema vertices may include adding a predetermined or configured buffer value to the maximum x-value and y-value (thus increasing the upper and right boundaries of the defined region) of relevant extrema vertices. Buffering the extrema vertices may likewise include adding a predetermined or configured buffer value to the minimum x-value and y- value that increases lower and right boundaries of the defined region. In this sense, “adding” may refer to a decrease in the minimum x- and y-values of the relevant extrema vertices such that the minimum x-value and minimum y- value are lower by the buffer amount and these buffered extrema vertices extend the size of a defined region past these minima values. Thus, the buffered extrema vertices may define a larger region for which to partition the circuit design. The region-based filtering engine 110 may thus define a region based on buffered extrema vertices as described herein.

[0038] In the example of Figure 2, the region-based filtering engine 110 buffers each of the extrema vertices 241 and 242 by a buffer amount illustrated as the buffer 250. A buffer added by the region-based filtering engine 110 may improve the accuracy of circuit test simulations performed using the defined region of a circuit design. Neighboring devices extending past the extrema vertices may impact the test locations specified in the circuit test, but may be otherwise excluded by a region defined directly at the extrema vertices. While increasing the region size may result in increased processing latency (with a larger circuit sub-portion to simulate), the trade-offs between accuracy and performance may be worthwhile. In some examples, the buffer value applied by the region-based filtering engine 110 may be a preset or fixed value that is experimentally determined. Experimental determinations can involve defining regions with a set of differing buffer values and determining the impact on accuracy and performance for each varying buffer value. The buffer value may be configured, controlled, or set by the region-based filtering engine 110 based on such experiments based on desired trade-offs, performance goals, accuracy tolerances, and the like. In some implementations, the region-based filtering engine 110 may set the buffer 250 such that accuracy of the region-based filtering is within an accuracy threshold(e.g., 99.9%+) of conventional brute-force techniques without region-based filtering.

[0039] In the example of Figure 2, the defined region 260 is illustrated through a 2-dimensional bounding box that can partition a portion of a circuit design or parasitic network for which a circuit test can be applied to. However, it can be understood that a circuit design and its extracted parasitic network can be 3-dimensional with multiple different circuit layers in the circuit design. In some implementations, the region-based filtering engine 110 may define a constant, consistent, or otherwise identical region 260 for each of the different layers of a circuit design. In other implementations, the region-based filtering engine 110 may adapt the region 260 on a per-layer basis. For example, the region-based filtering engine 110 may apply a weight or adjustment factor to a region 260 for a particular layer based on a location, level, attributes, or any characteristic of the layer.

[0040] As an illustrative example, the region-based filtering engine 110 may narrow, shrink, or reduce the size of the defined region (e.g., through the adjustment factor) for lower-level layers of a circuit design, such as from the substrate layer to a metal 3 (M3) layer. The region-based filtering engine 110 may define a slightly wider region for metal 4 (M4) - metal 7 (M7) layers, and further define an even wider region for the top layers of the circuit design, e.g., metal 8 (M8) layer to the top layer. In such an example, the region-based filtering engine 110 may adjust exact dimensions or size of the region 260 for a given layer based on application of an adjustment factor (e.g., applying a 0.98 adjustment factor value to dimensions of a region in a substrate layer, a 1.0 adjustment factor for the region of the M4, and a 1.03 adjustment factor for the region of a top layer). Note that any adjustment factor applied by the region-based filtering engine 110 may vary based on which layer an initial region is defined for. Any consistent or suitable implementation is contemplated herein by which the region-based filtering engine 110 can define regions of differing size, dimension, width, length, or area on a per-layer or per-layer group basis.

[0041] Layer groups may be defined or configured by the region-based filtering engine 110 in any suitable manner, e.g., as pre-defined groups or user-specified groups. An example of group layers can be configured by the region-based filtering engine 110 as lower-level layers (e.g., substrate to M3), mid-level layers (e.g., M4-M7), and upper-level layers (e.g., M8 to top layer). The region-based filtering engine 110 may apply a different adjustment factor to each layer group, and thus a defined region 260 for each layer group may vary. Such an adjustment factor may be useful to vary the size or dimensions of a region for different layers of a circuit design, which can increase the accuracy of simulations and circuit tests. This may be the case as parasitic devices of top-level layers may contribute more than lower-level layers, and per-layer variations of a defined region 260 can capture these contribution levels through the region-based filtering technology described herein. As such, the region-based filtering engine 110 may define a region 260 with dimensions that vary on a per-layer basis.

[0042] Through any of the various features described herein, the regionbased filtering engine 110 may define a region that encapsulates the specified test locations of a circuit test. In the example of Figure 2, the region-based filtering engine 110 defines the region 260 for the circuit design 210 based on the specified test locations 220. The region 260 may thus form a sub-partition of the circuit design and extracted parasitic network upon which a circuit test through the test locations 220 can be simulated, solved, or otherwise performed. As a feature in support of such partitioned simulations or circuit test performances, the region-based filtering engine 110 may filter out the specific parasitics (e.g., parasitic resistors) of a parasitic network that are outside of the region defined for a given circuit test. As part of or in support such a process, the region-based filtering engine 110 may perform a tilefiltering, example features of which are described next with reference to Figure 3.

[0043] Figure 3 shows an example tile-filtering of a tile set based on a defined region for a circuit test according to the present disclosure. After defining a region 260 for a given circuit test, the region-based filtering engine110 may perform a tile filtering to remove any tiles that do not intersect with the region. Tiling of nets may be used to partition nets of a parasitic network into smaller sub-portions. For complex nets and very large nets, such as ground and power nets, tiling technologies may split such immense nets into smaller partitions to improve processing efficiency and reductions in problem complexities. Various net-tiling technologies have been developed, and the region-based filtering engine 110 may implement, apply, or utilize any suitable tiling features as part of the region-based filtering technology of the present disclosure. Tile sizes, distribution, and features may be defined by tiling technologies based on a net size, and can take into account the parasitic devices on each net, simulation inputs (e.g., probe locations), or combinations of both. Thus, tiles generated for different nets of the same parasitic network may vary (at times greatly) in size and distribution. Tiling may be performed as part of or in combination with parasitic extraction for a circuit design, any features of which the region-based filtering engine 110 may use or otherwise access.

[0044] The region-based filtering engine 110 may perform tile-filtering on a tile set, such as the tile set 310 shown in Figure 3. A tile set may be specific to a given circuit test, e.g. , comprising the tiles of the specific nets of a parasitic network applicable to a given circuit test. In some implementations, the region-based filtering engine 110 may obtain an extracted netlist of a parasitic network in separate net tiles, each of which cover a specific partition of the circuit design. These separate net files may together form a tile set. In the example of Figure 3, the tile set 310 comprises tiles from nets of a parasitic network labeled as neti, net2, nets, and so on.

[0045] The region-based filtering engine 110 may filter the tile set 310 to remove any tiles that do not intersect (e.g., at least partially overlap) with the defined region 260. For any tile of a net that does not overlap the defined region 260 at all, the region-based filtering engine 110 may remove such a tile from the tile set 310. As an illustrative example shown in Figure 3, the regionbased filtering engine 110 may filter the tiles of neti based on the defined region 260 by removing any tiles of neti that do not interest with the definedregion 260. The remaining tiles 311 after filtering of the neti tiles may thus be determined by the region-based filtering engine 110. In a consistent manner, the region-based filtering engine 110 may perform tile-filtering for the net2 tiles to determine the remaining tiles 312 for net2, perform tile-filtering for the nets tiles to determine the remaining tiles 313 for nets, and so forth for any other net tiles of the tile set 310.

[0046] After filtering (e.g., removing) non-overlapping tiles from the tile set 310, the region-based filtering engine 110 may obtain a filtered tile set 320. This filtered tile set 320 may represent the partitions of applicable nets for the circuit test that overlap with the defined region 260. As tile filtering may be a relatively quicker and computationally inexpensive operation, the regionbased filtering engine 110 may first perform the tile-filtering process to filter out larger chunks of a circuit design with increased efficiency and reduced computational requirements. Accordingly, the region-based filtering engine 110 may perform tile-filtering based on a defined region in any of the various ways described herein.

[0047] In support of the region-based filtering technology described herein, the region-based filtering engine 110 may also perform resistor-filtering and network-filtering, example features of which are described next with reference to Figure 4.

[0048] Figure 4 shows an example of resistor-filtering and network-filtering according to the present disclosure. Note that for tiles that partially-overlap the defined region among the remaining tiles, there may be some parasitic devices (e.g., parasitic resistors) that are located within a partially-overlapping tile but are located outside the defined region 260. Thus, for remaining tiles in the filtered tile set 320 after the tile filtering, the region-based filtering engine 110 may perform a resistor-filtering to remove any parasitic resistors in the remaining tiles that do not intersect with the region (e.g., that do not overlap or are otherwise included within the region). While many of the examples herein are described using parasitic resistors as an example, filtering of any type of parasitic device is contemplated herein and within the scope of any resistor-filtering performed by the region-based filtering engine 110.

[0049] For any tile that is completely located within the region 260 (which can be referred to as a totally-overlapping tile), the region-based filtering engine 110 need not perform resistor-filtering. This may be the case because each of the parasitic devices within such a totally-encompassed tile are located within the region 260. Thus, in some implementations, the regionbased filtering engine 110 may limit the resistor-filtering process to any partially-intersecting (e.g., partially-overlapping) tiles in the filtered tile set 320. Parasitic devices included in totally-overlapping tiles of the filtered tile set 320 may all be identified as remaining parasitic-resistors located within the defined region 260.

[0050] The region-based filtering engine 110 may filter individual parasitic- resistors from the partially-overlapping tiles of the filtered tile set 320. An example of such is shown in Figure 4 through the remaining tile 401 , which can be seen is a partially-overlapping tile in which a portion of the remaining tile 401 is within the defined region 260 and another portion of the remaining tile 401 is outside of the defined region 260. In this example, the region-based filtering engine 110 may filter (e.g., remove or discard) the parasitic resistors outside of the region 260. The parasitic resistors located within the defined region 260 are kept, marked, tracked, or otherwise identified by the regionbased filtering as remaining parasitic-resistors. As noted herein, any parasitic resistors in a completely-intersecting tile may be identified as remaining parasitic resistors.

[0051] The remaining parasitic-resistors after the resistor-filtering may comprise only those parasitic-resistors located within the region 260 defined for the circuit test. In Figure 4, the region-based filtering engine 110 may identify the remaining parasitic resistors 410 through the resistor-filtering performed for the tile set 320. Note that many of the examples presented herein are described with reference to parasitic-resistors, but the region-based filtering technology is not so limited. Region-based filtering may be consistently performed for parasitic networks that include parasitic devices of any type or any type combinations.

[0052] Next, the region-based filtering engine 110 may filter a parasitic network to include only the parasitic resistors (or devices) included in the defined region 260. In doing so, the region-based filtering engine 110 may exclude any parasitic devices from the parasitic network that are not located within defined region 260. The region-based filtering engine 110 may obtain a filtered parasitic network by performing a network-filtering on the parasitic network to remove network portions of the parasitic network that do correspond to the remaining parasitic resistors 410 in the remaining tiles after the resistor-filtering. In the example of Figure 4, the region-based filtering engine 110 obtains the filtered parasitic network 420.

[0053] In some implementations, the parasitic network may be represented as a graph structure in which edges of the graph structure represent parasitic resistors and nodes represent locations in the circuit design. In such implementations, the region-based filtering engine 110 may perform the network-filtering on the parasitic network by removing edges from the graph structure that do not represent any of the remaining parasitic resistors 410 after the resistor-filtering. Removal or filtering of the graph structure may involve any additional or alternative steps in order to properly represent the defined region 260. Any suitable filtering, partitioning, or processing of extracted parasitic networks is contemplated herein in order to remove any parasitic devices not identified through the resistor-filtering performed by the region-based filtering engine 110.

[0054] Note that a control file may include multiple different circuit tests for the region-based filtering engine 110 to perform. The region-based filtering engine 110 may construct or access a graph structure that represents the entire parasitic network and filter this graph structure based on the specific region defined for each of the different circuit tests. In other examples, the region-based filtering engine 110 may construct a given graph for each specific circuit test, and each constructed graph may be a sub-graph of the overall graph structure that represents the entire parasitic network. Various implementation options are possible.

[0055] The region-based filtering engine 110 may then perform a simulation for the circuit test through the filtered parasitic network. A simulation may include any sort of processing or solving operation performed for the circuit test. The region-based filtering engine 110 may implement or use any suitable simulation techniques in which to perform the circuit test, and do so with a filtered parasitic network instead of the entire parasitic network extracted for a circuit design upon which the circuit test is being performed. By filtering the parasitic network to include the determined parasitic-resistors and remove any parasitic-resistors that are determined as outside the defined region, the region-based filtering engine 110 may limit simulations or processing to only a selected subsection of the entire parasitic network.

[0056] As such a selected subsection has been defined as a relevant region for test locations of a specific circuit test, the region-based filtering engine 110 may reduce the problem complexity of the circuit test and include particularly relevant data for simulations. By doing so, the circuit test simulations may be performed with increased efficiency and speed. Various region-based filtering features are described herein, any of which can be implemented individually or in combination. For example, the various filtering features described herein may be implemented or used independently or in combination to reduce the amount of data used for simulations in circuit tests based on a defined-region, whether through tile-filtering, resistor-filtering, network-filtering, or combinations thereof. For example, the region-based filtering engine 110 may directly perform resistor-filtering based on a defined region without the use of tiles, e.g., in a flow in which tiles are not generated during or as part of parasitic extraction. In such examples, the region-based filtering engine 10 may perform resistor-filtering to remove any parasitic devices in a parasitic network that are not part of or located within the defined region.

[0057] As described herein, various technical benefits can be achieved through the region-based filtering technology of the present disclosure. Smart selection of circuit design regions to use in simulation may improve the efficiency and speed of EDA systems in performing simulations for circuit tests, and buffer control of regions may allow for flexible configurations basedon accuracy and run time. Through the region-based filtering technology described herein, performance improvements, runtime reductions, and reduced memory footprints can be achieved.

[0058] Figure 5 shows an example of logic 500 that a system may implement to support region-based filtering of parasitic networks for circuit test simulations according to the present disclosure. For example, the computing system 100 may implement the logic 500 as hardware, executable instructions stored on a machine-readable medium, or as a combination of both. The computing system 100 may implement the logic 500 via the region-based filtering engine 110, through which the computing system 100 may perform or execute the logic 500 as a method to support region-based filtering of parasitic networks according to the present disclosure. The following description of the logic 500 is provided using the region-based filtering engine 110 as an example implementation. However, other implementation options by computing systems are possible.

[0059] In implementing the logic 500, the region-based filtering engine 110 may perform a circuit test through a parasitic network extracted for a circuit design (502). The circuit test may specify test locations in the circuit design and specific nets of the parasitic network that the circuit test applies to. The region-based filtering engine 110 may perform the circuit test by defining a region of the circuit design based on the test locations specified for the circuit test (504), performing a tile filtering, from a tile set for the specific nets, to remove any tiles for the specific nets that do not intersect with the region (506), for remaining tiles in the tile set after the tile filtering, performing a resistorfiltering to remove any parasitic resistors in the remaining tiles that do not intersect with the region (508) obtaining a filtered parasitic network by performing a network-filtering on the parasitic network to remove network portions that do correspond to the remaining parasitic resistors in the remaining tiles after the resistor-filtering (510) and performing a simulation for the circuit test through the filtered parasitic network (512).

[0060] The logic 500 shown in Figure 5 provides an illustrative example by which a computing system 100 may support or implement various features ofthe region-based filtering technology described herein. Additional or alternative steps in the logic 500 are contemplated herein, including according to any of the various features described herein for the region-based filtering engine 110.

[0061] Figure 6 shows an example of a computing system 600 that supports region-based filtering of parasitic networks for circuit test simulations according to the present disclosure. The computing system 600 may include a processor 610, which may take the form of a single or multiple processors. The processor(s) 610 may include a central processing unit (CPU), microprocessor, or any hardware device suitable for executing instructions stored on a machine-readable medium. The computing system 600 may include a machine-readable medium 620. The machine-readable medium 620 may take the form of any non-transitory electronic, magnetic, optical, or other physical storage device that stores executable instructions, such as the region-based filtering instructions 622 shown in Figure 6. As such, the machine-readable medium 620 may be, for example, Random Access Memory (RAM) such as a dynamic RAM (DRAM), flash memory, spin-transfer torque memory, an Electrically-Erasable Programmable Read-Only Memory (EEPROM), a storage drive, an optical disk, and the like.

[0062] The computing system 600 may execute instructions stored on the machine-readable medium 620 through the processor 610. Executing the instructions (e.g., the region-based filtering instructions 622) may cause the computing system 600 to perform or implement any of the region-based filtering technology described herein, including according to any aspect of the region-based filtering engine 110.

[0063] For example, execution of the region-based filtering instructions 622 by the processor 610 may cause the computing system 600 to perform a circuit test through a parasitic network extracted for a circuit design including by defining a region of the circuit design based on test locations specified for the circuit test and performing a tile filtering, from a tile set for the specific nets to remove any tiles for the specific nets that do not intersect with the region. Execution of the region-based filtering instructions 622 may cause thecomputing system 600 to perform the circuit test by, for remaining tiles in the tile set after the tile filtering, performing a resistor-filtering to remove any parasitic resistors in the remaining tiles that do not intersect with the region, obtaining a filtered parasitic network by performing a network-filtering on the parasitic network to remove network portions that do correspond to the remaining parasitic resistors in the remaining tiles after the resistor-filtering, and performing a simulation for the circuit test through the filtered parasitic network.

[0064] Any combination of the region-based filtering technology as described herein may be implemented via the region-based filtering instructions 622.

[0065] The systems, methods, devices, and logic described above, including the region-based filtering engine 110, may be implemented in many different ways in many different combinations of hardware, logic, circuitry, and executable instructions stored on a machine-readable medium. For example, the region-based filtering engine 110, may include circuitry in a controller, a microprocessor, or an application specific integrated circuit (ASIC), or may be implemented with discrete logic or components, or a combination of other types of analog or digital circuitry, combined on a single integrated circuit or distributed among multiple integrated circuits. A product, such as a computer program product, may include a storage medium and machine-readable instructions stored on the medium, which when executed in an endpoint, computer system, or other device, cause the device to perform operations according to any of the description above, including according to any features of the region-based filtering engine 110.

[0066] The processing capability of the systems, devices, and engines described herein, including the region-based filtering engine 110, may be distributed among multiple system components, such as among multiple processors and memories, optionally including multiple distributed processing systems or cloud / network elements. Parameters, databases, and other data structures may be separately stored and managed, may be incorporated into a single memory or database, may be logically and physically organized inmany different ways, and may be implemented in many ways, including data structures such as linked lists, hash tables, or implicit storage mechanisms. Programs may be parts (e.g., subroutines) of a single program, separate programs, distributed across several memories and processors, or implemented in many different ways, such as in a library (e.g., a shared library).

[0067] While various examples and features have been described above, many more implementations are possible.

Claims

CLAIMS1 . A method comprising: performing, by a computing system (100, 600), a circuit test through a parasitic network extracted for a circuit design (210), wherein the circuit test is specified at test locations (220) in the circuit design (210) and applicable to specific nets of the parasitic network, including by: defining a region (260) of the circuit design based on the test locations (220) specified for the circuit test; performing a tile filtering, from a tile set (310) for the specific nets, to remove any tiles for the specific nets that do not intersect with the region (260); for remaining tiles (311 , 312, 313, 401 ) in the tile set after the tile filtering, performing a resistor-filtering to remove any parasitic resistors in the remaining tiles (311 , 312, 313, 401 ) that do not intersect with the region (260); obtaining a filtered parasitic network (420) by performing a network-filtering on the parasitic network to remove network portions that do correspond to remaining parasitic resistors (410) in the remaining tiles after the resistor-filtering; and performing a simulation for the circuit test through the filtered parasitic network (420).

2. The method of claim 1 , comprising defining the region (260) of the circuit design (210) to include each of the test locations (220) specified for the circuit test, but not an entirety of the circuit design (210).

3. The method of claim 1 or 2, wherein defining the region (260) of the circuit design based on the test locations (220) comprises: identifying extrema vertices (241 , 242) in the circuit design (210) based on the test locations (220) specified for the circuit test;buffering extrema vertices (241 , 242) to form buffered extrema vertices by adding a buffer (250) amount to each of the extrema vertices (241 , 242); and forming the region (260) with the buffered extrema vertices as comers of the region (260).

4. The method of claim 3, wherein the extrema vertices (241 , 242) comprise: a leftmost location of a circuit device at a leftmost test location among the test locations (220), and a rightmost location of a circuit device at a rightmost test location among the test locations (220).

5. The method of claim 3, wherein the extrema vertices (241 , 242) comprise: an uppermost location of a circuit device at an uppermost test location among the test locations (220), and a lowermost location of a circuit device at a lowermost test location among the test locations (220).

6. The method of any of claims 1-5, wherein the parasitic network is represented as a graph structure in which edges of the graph structure represent parasitic resistors and nodes represent locations in the circuit design (210); and wherein performing the network-filtering on the parasitic network comprises removing edges from the graph structure that do not represent any of the remaining parasitic resistors (410) after the resistor-filtering.

7. The method of any of claims 1-6, wherein the circuit test comprises a point-to-point resistance test, a current density test, or combinations of both.

8. A system comprising: a processor (610); and a non-transitory machine-readable medium (620) comprising instructions (622) that, when executed by the processor (610), cause a computing system (100, 600) to perform a circuit test through a parasitic network extracted for a circuit design (210), wherein the circuit test is specified at test locations (220) in the circuit design (210) and applicable to specific nets of the parasitic network, including by: defining a region (260) of the circuit design based on the test locations (220) specified for the circuit test; performing a tile filtering, from a tile set (310) for the specific nets, to remove any tiles for the specific nets that do not intersect with the region (260); for remaining tiles (311 , 312, 313, 401 ) in the tile set after the tile filtering, performing a resistor-filtering to remove any parasitic resistors in the remaining tiles (311 , 312, 313, 401 ) that do not intersect with the region (260); obtaining a filtered parasitic network (420) by performing a network-filtering on the parasitic network to remove network portions that do correspond to remaining parasitic resistors (410) in the remaining tiles after the resistor-filtering; and performing a simulation for the circuit test through the filtered parasitic network (420).

9. The system of claim 9, wherein the instructions (622), when executed, cause the computing system (100, 600) to define the region (260) of the circuit design (210) to include each of the test locations (220) specified for the circuit test, but not an entirety of the circuit design (210).

10. The system of claim 8 or 9, wherein the instructions (622), when executed, cause the computing system (100, 600) to define the region (260) of the circuit design based on the test locations (220) comprises:identifying extrema vertices (241 , 242) in the circuit design (210) based on the test locations (220) specified for the circuit test; buffering extrema vertices (241 , 242) to form buffered extrema vertices by adding a buffer (250) amount to each of the extrema vertices (241 , 242); and forming the region (260) with the buffered extrema vertices as comers of the region (260).11 . The system of claim 10, wherein the extrema vertices (241 , 242) comprise: an upper-left location of a circuit device at an uppermost-leftmost test location among the test locations (220), and a lower-right location of a circuit device at a lowermost-rightmost test location among the test locations (220).

12. The system of claim 10, wherein the extrema vertices (241 , 242) comprise: an upper-right location of a circuit device at an uppermost-rightmost test location among the test locations (220), and a lower-left location of a circuit device at a lowermost-leftmost test location among the test locations (220).

13. The system of any of claims 8-12, wherein the parasitic network is represented as a graph structure in which edges of the graph structure represent parasitic resistors and nodes represent locations in the circuit design (210); and wherein the instructions (622), when executed, cause the computing system (100, 600) to perform the network-filtering on the parasitic network by removing edges from the graph structure that do not represent any of the remaining parasitic resistors (410) after the resistor-filtering.

14. The system of any of claims 8-13 wherein the circuit test comprises a point-to-point resistance test, a current density test, or combinations of both.

15. A non-transitory machine-readable medium (620) comprising instructions (622) that, when executed by a processor (610), cause a computing system (100, 600) to perform a method according to any of claims 1-7.

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