Printed circuit board power source structure and manufacturing method therefor

Abstract

Provided in the present application are a printed circuit board (PCB) power source structure and a manufacturing method therefor. The PCB power source structure comprises power source traces arranged on the surface of a PCB, wherein the power source traces comprise a copper-plated region and a laminated region, the laminated region is superimposed on the surface of the copper-plated region to form an integral conductor, and the respective cross-sectional areas of the copper-plated region and laminated region in the integral conductor are determined on the basis of the current-carrying capacity required by power source signals. In the present application, power source traces are formed by superimposing other metals on conventional copper traces for electrical conduction, such that the routing space of a power source network is greatly reduced while current conduction requirement of the power source network is met, thus facilitating the trace design of other signals, and avoiding the addition of layers of a PCB, thereby facilitating the miniaturization design of the PCB and reducing the manufacturing cost of the PCB.

Description

Circuit board power supply structure and manufacturing method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to a Chinese patent application filed with the Patent Office of China on March 29, 2024, with application number 202410382948.1 and entitled “A Circuit Board Power Supply Structure and Manufacturing Method,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of circuit board manufacturing, and in particular to a circuit board power supply structure and a manufacturing method. Background Art

[0004] With the rapid development of electronic information, electronic products are becoming increasingly versatile, and the power consumption of corresponding electronic components is gradually increasing, with a trend towards low voltage and high current. Power supply design is both a key and challenging aspect of PCB (Printed Circuit Board) design, especially for low-voltage, high-current circuits. During PCB design, efforts are often made to reduce the number of PCB layers or the size of the PCB in order to lower board costs. This approach, whether reducing the number of layers or reducing the size, increases the difficulty of PCB design, potentially leading to issues such as signal integrity and insufficient power flow.

[0005] In the related art, in order to make the PCB design meet the flow rate of the power signal line, the PCB is made to meet the large power flow rate by widening the power signal line width and increasing the PCB stacking.

[0006] The above design method results in an increase in the size of the PCB board and may result in no routing space for other signal networks, while also increasing the cost. Summary of the Invention

[0007] In view of the above problems, the embodiments of the present application are proposed to provide a circuit board power supply structure and a manufacturing method that overcome the above problems or at least partially solve the above problems.

[0008] In a first aspect, an embodiment of the present application discloses a circuit board power supply structure, comprising: a power supply trace including a copper-plated area and a laminated area; the laminated area is superimposed on the surface of the copper-plated area to form an integral conductor;

[0009] The cross-sectional areas of the copper-plated region and the laminated region in the overall conductor are determined by the current carrying capacity required by the power signal.

[0010] Optionally, isolation holes are provided in the copper-plated area at preset intervals along the current flow direction of the copper-plated area;

[0011] The area where the isolation hole is located is not covered with metal copper.

[0012] Optionally, the preset interval is greater than or equal to 5 mm and less than or equal to 10 mm;

[0013] The larger the width of the copper plated area, the smaller the preset interval between the isolation holes.

[0014] Optionally, the isolation hole is a circular isolation hole;

[0015] The diameter of the isolation hole is greater than or equal to 0.3 mm and less than or equal to 0.4 mm.

[0016] Optionally, the stacked region is formed of any one or more of gold, silver, aluminum, tin, and iron.

[0017] Optionally, the trace width of the stacked area is less than or equal to the trace width of the copper plating area.

[0018] Optionally, the laminate region has a thickness of 0.5OZ to 1.5OZ.

[0019] Optionally, the width of the copper plated area is one third to one half of the width of the copper plated area when current is passed through the copper plated area alone, which is determined by the required current carrying capacity.

[0020] Optionally, the wirings on the surface of the circuit board except the power wiring are covered with a protective film.

[0021] Optionally, metal burrs are formed on the surface of the copper-plated area by micro-etching.

[0022] In a second aspect, an embodiment of the present application discloses a method for manufacturing a circuit board power supply structure, the method comprising:

[0023] Determine the width and thickness of the copper plating area and the width and thickness of the laminate area based on the current carrying capacity required by the power signal;

[0024] Etching the inner layers of the circuit board and laminating the various layers of the circuit board to form a circuit board;

[0025] A copper-plated area is formed by electroplating on the surface of the circuit board body based on the width and thickness of the copper-plated area, and the laminated area is superimposed on the copper-plated area based on the width and thickness of the laminated area to form a power supply line on the surface of the circuit board.

[0026] Optionally, before pressing the laminate region onto the copper plated region based on the width and thickness of the laminate region, the method further comprises:

[0027] Isolation holes are formed by etching the copper-plated area at preset intervals along the current flow direction of the copper-plated area; the area where the isolation holes are located is not covered with metal copper.

[0028] Optionally, before pressing the laminate region onto the copper plated region based on the width and thickness of the laminate region, the method further comprises:

[0029] Cover all traces on the circuit board surface except the power traces with a protective film.

[0030] Optionally, after covering the protective film on the surface of the circuit board except for the power supply lines, the method further includes:

[0031] The copper-plated area is micro-etched to form metal burrs on the surface of the copper-plated area.

[0032] Optionally, after micro-etching the copper-plated area so that metal burrs are formed on the surface of the copper-plated area, the method further includes:

[0033] The laminated area is superimposed on the copper plated area by electroplating or lamination.

[0034] Optionally, after forming the power traces on the surface of the circuit board, the method further includes:

[0035] Cover the power traces on the surface of the circuit board with a protective film.

[0036] Optionally, the method further comprises:

[0037] When metal tin is selected for the laminated region, the metal tin is mixed with any one or more of metal silver, metal gold, metal aluminum and metal iron to form a laminated region, and then the laminated region is superimposed on the copper-plated region.

[0038] The present application discloses a circuit board power supply structure, comprising: a power supply trace arranged on the surface of the circuit board; the power supply trace comprising a copper-plated region and a laminated region; the laminated region superimposed on the surface of the copper-plated region to form a single conductor; wherein the cross-sectional area of ​​each of the copper-plated region and the laminated region in the single conductor is determined by the current carrying capacity required by the power signal. The power supply trace of the present application, by superimposing other metals on top of conventional copper traces for electrical conduction, significantly reduces the wiring space for the power supply network while ensuring current flow through the power supply network, thereby facilitating the routing design of other signals, while avoiding the need to increase PCB board layers, facilitating the miniaturization of PCB board design, and reducing PCB board manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG1 is a front view of a PCB board surface power routing design provided by an embodiment of the present application;

[0040] FIG2 is a front view of a metal overlay design for power traces on a PCB board provided by an embodiment of the present application;

[0041] FIG3 is a top view of a PCB board surface power routing design provided by an embodiment of the present application;

[0042] FIG4 is a top view of a metal overlay design for power traces on a PCB board provided by an embodiment of the present application;

[0043] FIG5 is a design diagram of a server central processing unit power supply PCB board provided in an embodiment of the present application;

[0044] FIG6 is a metal overlay design of the power supply wiring on the surface and inner layer of a PCB board provided by an embodiment of the present application;

[0045] FIG7 is a flow chart of a method for manufacturing a circuit board surface structure provided in an embodiment of the present application.

[0046] Reference numerals

[0047] 10-circuit board; 11-surface trace; 12-power trace; 121-isolation hole; 122-copper-plated area; 123-stacked area; 13-inner layer trace; 14-bottom layer trace; 15-low-current power trace; 21-normal signal trace; 22-power module; 23-central processing unit; 24-surface high-current power plane. DETAILED DESCRIPTION

[0048] The following describes exemplary embodiments of the present application in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0049] The concepts and background involved in this application are explained below.

[0050] In conventional PCB design, increasing the current carrying capacity of power signal traces requires widening the trace width. Based on a 1oz (ounce) copper thickness, a 1mm wide copper trace can carry 1A of current. With the development of core processors in current electronic products, core power supplies are increasingly moving towards low voltage and high current. For example, the core power supplies of central processing units and graphics processing units require current carrying capacity of 200-300A. The core power supply design for these processors requires increasing the lateral width of the power network plane and adding more PCB layers to accommodate the high current carrying capacity, which increases PCB manufacturing costs. In other words, in conventional PCB design, increasing the power network plane to increase current carrying capacity requires increasing the PCB size or leaving space for other signal networks. Alternatively, if increasing the power network plane is not feasible, the PCB stackup must be increased, such as adding two or four power layers dedicated to the power network. Conventional PCB design hinders PCB miniaturization and increases PCB manufacturing costs.

[0051] In the PCB design process, in order to reduce the cost of PCB boards, it is usually achieved by reducing the number of PCB board layers or reducing the size of PCB boards. However, whether reducing the number of board layers or reducing the size, it increases the difficulty of PCB board design, which in turn causes problems such as signal integrity problems or insufficient power flow. This application mainly proposes a design method for increasing the flow capacity of PCB board surface routing from the perspective of PCB design and its production. Mainly from the perspective of PCB design and production, without increasing the number of board layers or reducing the number of board layers or reducing the size of the board to reduce costs, the flow capacity of the power signal routing on the surface of the PCB board is increased, thereby reducing the cost of the PCB board while ensuring the electrical performance of the electronic product. The details are as follows.

[0052] Referring to Figures 1 and 2, Figure 1 is a front view of a PCB board surface power trace design provided by an embodiment of the present application, and Figure 2 is a front view of a PCB board surface power trace metal overlay design provided by an embodiment of the present application. It shows a circuit board power structure provided by an embodiment of the present application, comprising: a power trace 12 arranged on the surface of a circuit board 10; the power trace 12 includes a copper-plated area 122 and a laminated area 123; the laminated area 123 is superimposed on the surface of the copper-plated area 122, and the laminated area 123 and the copper-plated area 122 together form a single conductor; wherein the cross-sectional area of ​​each of the copper-plated area 122 and the laminated area 123 in the single conductor is determined by the current carrying capacity required by the power signal and the metal conductivity of the laminated area.

[0053] Specifically, an embodiment of the present application provides a circuit board surface structure, including: power traces arranged on the surface of the circuit board, the power traces are used for power network signal transmission, and constitute the power plane of the circuit board. During the PCB design process, when encountering a high-current power network, the required trace width can be determined based on the current carrying capacity required by the power network signal. For example, if the current of the power network signal is 50A, the power trace width required in the conventional design is 50mm. In order to reduce the width of the power trace in the conventional design, so as to reduce the surface area of ​​the circuit board occupied by the power trace. In this application, the conventional power trace formed by copper foil is optimized into a power trace formed by a copper-plated area and a laminated area. Among them, the copper-plated area is a conventional copper trace, and the laminated area can be a conductive area formed by other metals, such as aluminum, tin, etc. The superposition of the two areas can meet the large current flow requirements while reducing the width of the copper-plated area.

[0054] Specifically, if the power network signal is routed on the surface of the PCB (i.e., the top or bottom surface), the width of the power network signal can be shortened. For example, if the current of the power network signal is 50A, the surface power trace plane can be designed to be 20mm to 30mm wide. The actual width needs to be calculated based on the conductivity of the subsequently superimposed metal and the thickness of the superimposed metal. The calculation method can be: if the copper thickness on the actual PCB board is 1OZ, if the superimposed metal is aluminum and the thickness is also 1OZ, then a 50A power trace plane width of 30mm can meet the required current carrying capacity. That is, under the premise of meeting the current carrying capacity requirements of the high-current power network, in order to reduce the number of PCB board layers or reduce the size of the PCB board, thereby reducing the production cost of the PCB board; the local area of ​​the high-current power network trace is improved, and the laminated area formed by other metals is superimposed on the copper-plated area formed by the copper trace by electroplating or pressing to meet the power current. The other metals can be selected according to actual needs and costs, and the embodiments of the present application are not limited here.

[0055] In summary, the present application discloses a circuit board power supply structure, comprising: power supply lines arranged on the surface of the circuit board; the power supply lines comprising a copper-plated region and a laminated region; the laminated region superimposed on the surface of the copper-plated region to form an integral conductor; wherein the cross-sectional area of ​​each of the copper-plated region and the laminated region in the integral conductor is determined by the current carrying capacity required by the power signal. The power supply lines of the present application are conductive by superimposing other metals on top of conventional copper lines. While ensuring the current flow of the power network, the wiring space of the power network is greatly reduced, thereby facilitating the routing design of other signals. At the same time, the addition of PCB board layers is avoided, facilitating the miniaturization of PCB board design and reducing the manufacturing cost of PCB board.

[0056] Optionally, refer to Figure 3, which is a top view of a power routing design on the surface of a PCB board provided in an embodiment of the present application; isolation holes 121 are set in the copper-plated area at preset intervals along the current flow direction of the copper-plated area 122; the area where the isolation holes 121 are located is not covered with metal copper.

[0057] Specifically, to enhance the overall conductivity of the conductor formed by stacking the laminated area over the copper-plated area, further detailed design is performed during the PCB design process, provided that the width of the power trace on the PCB surface needs to be reduced. This can be achieved by designing isolation holes in the copper-plated areas of the power traces. This isolation hole design allows copper metal in this area to be removed during PCB fabrication, sized to the isolation hole size. Furthermore, when other metals are added, the added metals can be inserted into the holes, thereby increasing the connection strength and conductivity between the different metals.

[0058] Specifically, the design and production method of the isolation hole can be: in the PCB design process, on the power wiring plane on the surface, an isolation hole is added at a preset distance according to the current flow direction. Adding the isolation hole can avoid the metal copper in the area where the isolation hole is located on the power wiring plane. That is, there is no metal copper in the isolation hole area. As shown in Figure 2, there is no metal copper in the isolation hole 121 area on the power wiring plane. In addition, when setting the isolation hole, the isolation hole does not need to be completely in a straight line. As long as the isolation hole is added along the power current flow direction, the isolation hole can have position deviations left and right, up and down, according to actual conditions. The position deviation has no effect on the technical effect to be achieved by this application. During the PCB processing and production process, the isolation hole area is directly etched with a solution in the isolation hole area to remove the metal copper in the isolation hole area, so that when the laminated area is subsequently superimposed, the metal in the laminated area is in better contact with the copper-plated area.

[0059] Furthermore, when setting the isolation hole, the distance between the isolation hole and the edge of the nearest copper-plated area can be greater than or equal to 1 mm. When the distance between the isolation hole and the edge of the nearest copper-plated area is greater than or equal to 1 mm, if the metal of the laminated area enters the isolation hole during the pressing process, the connection strength between the laminated area and the copper-plated area can be better guaranteed.

[0060] Optionally, the preset interval is greater than or equal to 5 mm and less than or equal to 10 mm; the larger the width of the copper-plated area, the smaller the preset interval between the isolation holes.

[0061] Specifically, the preset interval between the two isolation holes can be greater than or equal to 5 mm and less than or equal to 10 mm. For example, the preset interval can be selected from: 5 mm, 6 mm, 7 mm, 8 mm, 9 mm, 10 mm, etc., which is not limited in the embodiment of the present application. When the preset interval selects a distance within this interval, the connection strength and conductivity requirements between the metals in the copper-plated area and the laminated area can be met. In addition, the isolation holes can be arranged in a single row or in multiple rows. In actual use, the size of the isolation holes, the distance between the isolation holes, and the specific arrangement of the isolation holes can all be designed according to actual needs, which is not limited in the embodiment of the present application.

[0062] Furthermore, due to process limitations, the thickness of the copper-plated region is within a certain range. Therefore, if the current carrying capacity required is greater, the copper-plated region will be correspondingly wider. In this case, to ensure the connection strength between the laminated region and the copper-plated region, when isolation holes are provided in the copper-plated region, the preset distance between the isolation holes can be reduced accordingly. That is, the greater the width of the copper-plated region along a first direction, the smaller the preset spacing between the isolation holes. The first direction is along the copper-plated region and perpendicular to the direction of current flow. For example, if the width of the copper-plated region is 50 mm, the distance between adjacent isolation holes can be 10 mm. If the width of the copper-plated region is 200 mm, the distance between adjacent isolation holes can be set to 5 mm to meet the connection strength requirements.

[0063] Optionally, referring to FIG3 , the isolation hole is a circular isolation hole; the diameter of the isolation hole is greater than or equal to 0.3 mm and less than or equal to 0.4 mm.

[0064] Specifically, the isolation holes can be designed to be circular, but can also be square, rectangular, triangular, or any other polygonal or irregular shape, all of which can achieve the technical effect of the isolation holes of this application. This application does not limit the specific shape of the isolation holes. Preferably, the circular design can simplify the manufacturing process.

[0065] In addition, when the isolation hole is circular, the diameter of the isolation hole can be designed to be greater than or equal to 0.3 mm and less than or equal to 0.4 mm. For example, the diameter of the isolation hole can be 0.3 mm, 0.32 mm, 0.34 mm, 0.36 mm, 0.38 mm, 0.4 mm, etc. When the size of the isolation hole is within the above range, the connection strength and conductivity requirements between the metal of the copper-plated area and the laminated area can be met. The specific size design can be selected according to actual conditions. In addition to the circular shape, the size design of the isolation hole of other shapes can refer to the circular shape, and the embodiment of the present application is not limited here.

[0066] Optionally, referring to Figure 4, Figure 4 is a top view of a metal overlay design for power traces on the surface of a PCB board provided in an embodiment of the present application; the stacking area 123 is formed by any one or more of gold, silver, aluminum, tin, and iron.

[0067] Specifically, the order of metal conductivity is: silver > copper > gold > aluminum > iron > tin. When designing using this application, the metals used in the stacking area can be selected based on conductivity and manufacturing cost, taking into account the other metals to be laminated or plated and the current carrying capacity required for the power network. Detailed calculations are performed to optimize the power network trace width and the thickness of the metal to be laminated, thereby reducing the wiring density on the PCB board surface, facilitating miniaturization and cost reduction.

[0068] For example, the laminated area is formed by any one or more of gold, silver, aluminum, tin, and iron. For example, it can be aluminum, or a mixture of aluminum and tin. If metallic tin is used, it is necessary to add other metals to the mixture to increase its melting point. For example, metallic tin is mixed with any one or more of metallic silver, metallic gold, metallic aluminum, and metallic iron to form a laminated area. This avoids the surrounding temperature rising during subsequent PCB board soldering, causing the superimposed metallic tin to melt and cause a short circuit risk. The embodiments of the present application are not limited here. The method of the present application effectively reduces the surface area occupied by the PCB board of the power supply line by superimposing the copper-plated area and the laminated area, saves the surface space of the PCB board, and reduces the production cost.

[0069] Optionally, the width of the traces in the laminated area is less than or equal to the width of the traces in the copper-plated area. Optionally, the thickness of the laminated area is 0.5 oz to 1.5 oz. The specific thickness can be determined based on the process level and current carrying capacity requirements, and is not limited in this embodiment of the present application.

[0070] For example, if the current of the power network signal is 50A, the surface power trace plane can be designed with a width of 20mm to 30mm. The actual width needs to be calculated based on the conductivity and thickness of the subsequently superimposed metal. The calculation method can be: if the actual copper on the PCB board is 1OZ, and the added metal is aluminum and the thickness is also 1OZ, then the 50A power trace plane width is 30mm to meet the required current carrying capacity.

[0071] Specifically, the routing width of the laminated area can be less than or equal to the routing width of the copper-plated area. For example, the thickness of the laminated area can be 0.5OZ to 1.5OZ. For example, it can be: 0.5OZ, 0.7OZ, 0.9OZ, 1.0OZ, 1.2OZ, 1.3OZ, 1.4OZ, 1.5OZ. The power routing of the present application is superimposed with other metals on top of the conventional copper routing for conduction. Under the condition that the power network is passed through, the wiring space of the power network is greatly reduced, thereby facilitating the routing design of other signals, while avoiding the addition of PCB board layers, facilitating the miniaturization design of PCB boards, and reducing the production cost of PCB boards.

[0072] Optionally, the width of the copper plated area is one third to one half of the width of the copper plated area when current is passed through the copper plated area alone, which is determined by the required current carrying capacity.

[0073] Specifically, the width of the copper-plated area can be one-third to one-half of the width required when the power supply routing is performed solely on the copper layer. For example, if the current of the power network signal is 50A, a conventional design using only copper routing would require a routing width of 50mm. However, using the method of this application, the surface power routing plane can be designed to be approximately 16mm to 30mm wide. This embodiment of the application is not limited here.

[0074] The design method of this application can reduce the power network wiring area by about 1 / 3 to 1 / 2 compared with the conventional design. While meeting the condition of power network flow, the power network wiring space is greatly reduced, which is beneficial to the routing design of other signals. At the same time, it avoids adding PCB board layers, is beneficial to the miniaturization design of PCB boards, and reduces the production cost of PCB boards.

[0075] Optionally, the wirings on the surface of the circuit board except the power wiring are covered with a protective film.

[0076] Optionally, metal burrs are formed on the surface of the copper-plated area by micro-etching.

[0077] Specifically, in the embodiment of the present application, the signal transmission rate in the current PCB board is constantly increasing. In order to avoid the attenuation of signal transmission quality due to the skin effect during high-speed signal transmission, the metal copper on the surface of the PCB board is usually treated with RTF (Reverse Treat Foil). The metal copper surface formed by this process is smooth. Therefore, during the processing of the PCB board, after the metal copper of other signal networks is covered with ink, in order to strengthen the bonding between the copper-plated area and the laminated area, the present application further performs micro-etching on the metal copper of the exposed power supply network to form burrs on the metal copper surface, and then electroplates or presses other metals on it. This can greatly increase the bonding force between different metals and the current transmission efficiency, reduce the transmission impedance, and thus improve the overall conductivity; while ensuring that other high-speed signal lines are not affected.

[0078] Furthermore, during the PCB manufacturing process, after the inner layers of the PCB are etched and formed, the entire PCB is laminated. Drilling and copper plating are then performed to complete the initial version. Metal overlay is then performed. First, except for the power network plane window that requires optimization, other conventional network traces are covered with ink to ensure that no copper metal is leaking. Second, the exposed copper metal on the power network plane on the PCB is micro-etched to create more burrs on the metal surface. More burrs facilitate good contact with the laminated metal and current transmission, reducing transmission impedance. Third, other metals (such as silver, aluminum, etc.) that require overlay are electroplated or laminated onto the optimized copper power network trace plane. The width can be smaller than the underlying copper trace and the thickness can be 0.5 oz to 1.5 oz. Since the metal in other areas is already covered with ink, plating or laminating the additional metal will not cause short circuits with other networks. Finally, the optimized power network traces on the entire PCB are covered with ink, completing the PCB manufacturing process.

[0079] In addition, refer to Figure 5, which is a design diagram of a server central processing unit power PCB board provided by an embodiment of the present application, including: ordinary signal traces 21, power modules 22, central processing units 23, and surface high current power planes 24. The layout of each area on the circuit board is shown in the figure. Since the size of the central processing unit power PCB board is certain, the area occupied by ordinary signal traces 21, power modules 22, and central processing units 23 on the circuit board is relatively fixed. Therefore, due to the existence of these limitations, the area left for the power plane is within a relatively fixed range. This results in that when the current flow demand is large, the circuit board can currently arrange the power traces. The area of ​​the line is difficult to meet the actual current demand. Referring to Figure 5, for the design of the server CPU power PCB board, the surface high current power plane 24 can generally be set between the power module 22 and the CPU 23. The surface high current power plane 24 provides the current generated by the power module 22 to the CPU 23. Among them, the narrowest part of the surface high current power plane 24, that is, the length of d1 in Figure 5, determines the actual current carrying capacity of the power plane, that is, the narrowest part of the surface high current power plane 24 is the width of the actual connection between the power plane and the CPU. Since the CPU 23 also needs to reserve pins for connecting signals of other components such as memory, Therefore, the actual width of the power supply line that can be left by the CPU 23 is limited. For example, for a CPU with a width of 75 mm, the width that can be connected to the power supply line is generally 12-15 mm (d1 in Figure 5). For a CPU with a width of 60 mm, the width that can be connected to the power supply line is generally around 13 mm, that is, the actual power supply line width is only about one-fifth of the width of the CPU. In the related art, the high current flow requirement is met by increasing the circuit board stacking method. If the power supply line design of the present application is adopted, the required width of the original copper line is reduced when a high current flows, and the same current is achieved by superimposing the stacking area. The current carrying capacity of the original copper trace width is the same, so that without increasing the size of the PCB board or adding PCB board stacking, it is possible to realize the research and development design of server products, for example, for a central processing unit with a width of 75 mm, the original power trace width is 12-15 mm, and using the solution of the present application, it is possible to superimpose a laminated area formed by other metals on the basis of the 12-15 mm original copper trace, so that the cross-sectional area of ​​the power trace is increased. For example, adding a laminated area formed by metal aluminum with the same width and thickness as the original copper trace can make the actual current carrying capacity of the power trace twice the original current carrying capacity, meeting the current flow requirements of the central processing unit. The present application realizes the current carrying requirements of large currents without increasing costs for the current flow requirements of central processing units with core power supplies exceeding 100A. Therefore, this technical solution can be applied to the research and development design of all PCB boards with large current power supply networks, especially server product PCB design, saving production costs.

[0080] Refer to Figure 6, which illustrates a metal overlay design for the surface and inner power routing of a PCB board, provided by an embodiment of the present application. Figure 6 also illustrates another application scenario of the present PCB design, provided by an embodiment of the present application. This design can also be used to overlay other metals on the copper metal for inner-layer power network routing on a PCB board. However, this will increase the number of process steps required during PCB manufacturing, resulting in higher PCB board costs and lower PCB board production yields. If used for metal overlay of inner-layer power network routing, the design is the same as the surface overlay method described above and will not be further described here.

[0081] That is, this application mainly proposes a design method for increasing the flow capacity of the surface routing of PCB boards from the perspective of PCB design and its production. Without increasing the number of board layers or reducing the number of board layers or the size of the board to reduce costs, the flow capacity of the power signal routing on the surface of the PCB board is increased, thereby reducing the cost of the PCB board while ensuring the electrical performance of the electronic product. Specifically, by reducing the width of the high-current power network routing in the PCB board; other metals (silver, aluminum, tin) are superimposed on the metal copper by electroplating or pressing for power transmission; during the PCB board design process, isolation holes are required for the high-current power network routing to increase the bonding between different metals; during the PCB board processing process, other network routings are first covered with ink, and then the power plane is micro-etched to increase the surface roughness of the metal copper, and then the power network routing metal is superimposed to avoid short circuits; at the same time, if metal tin is used for superposition, other metals need to be added to the metal tin to increase its melting point to avoid the superimposed metal tin melting during the later soldering of the PCB board. In specific operations, the trace width of the high-current power network and the thickness of the superimposed metal are calculated in detail based on the conductivity of the superimposed metal. By superimposing other metals above the high-current power network traces, the problem of ensuring power flow can be effectively solved without increasing the trace width or the stacking layer. Furthermore, compared with conventional designs, this application facilitates the miniaturization of PCB board designs, reduces PCB board manufacturing costs, and promotes the miniaturization of electronic products.

[0082] In summary, the present application discloses a circuit board surface structure comprising: a power supply line arranged on the surface of the circuit board; the power supply line comprising a copper-plated region and a laminated region; the laminated region superimposed on the surface of the copper-plated region to form an integral conductor; wherein the cross-sectional area of ​​each of the copper-plated region and the laminated region in the integral conductor is determined by the current carrying capacity required by the power supply signal. The power supply line of the present application is conductive by superimposing other metals on top of conventional copper lines. While satisfying the current flow requirements of the power supply network, the power supply network wiring space is greatly reduced, thereby facilitating the routing design of other signals, while avoiding the need to increase PCB board layers, facilitating the miniaturization of PCB board design, and reducing the cost of PCB board manufacturing.

[0083] In the second aspect, referring to FIG7 , FIG7 is a flow chart of a method for manufacturing a circuit board surface structure provided by an embodiment of the present application. The embodiment of the present application discloses a method for manufacturing a circuit board surface structure, the method comprising:

[0084] Step 101, determining the width and thickness of the copper plating area and the width and thickness of the laminated area based on the current carrying capacity required by the power signal;

[0085] Step 102: etching the inner layer of the circuit board and laminating the layers of the circuit board to form a circuit board;

[0086] Step 103: Electroplating a copper-plated area on the surface of the circuit board body based on the width and thickness of the copper-plated area, and superimposing the laminated area on the copper-plated area based on the width and thickness of the laminated area to form a power supply line on the surface of the circuit board.

[0087] In the embodiments of the present application, in the PCB design process, in order to reduce the cost of the PCB board, it is usually achieved by reducing the number of PCB board layers or reducing the size of the PCB board. However, whether it is reducing the number of board layers or reducing the size, it increases the difficulty of PCB board design, thereby causing problems such as signal integrity problems or insufficient power flow. This application mainly proposes a design method for increasing the flow capacity of the surface routing of the PCB board from the perspective of PCB design and its production. Mainly from the perspective of PCB design and production, without increasing the number of board layers or reducing the number of board layers or reducing the size of the board in order to reduce costs, the flow capacity of the power signal routing on the surface of the PCB board is increased, thereby reducing the cost of the PCB board while ensuring the electrical performance of the electronic product. The details are as follows.

[0088] A method for fabricating a circuit board surface structure may include: first, determining the width and thickness of the copper-plated area and the width and thickness of the laminated area based on the required current carrying capacity of the power signal. Specifically, the width of the metal copper trace is reduced through calculation based on the current carrying capacity of the power network. For example, if the current of the power network signal is 50A, the surface power trace plane can be designed to have a width of 20mm to 30mm. The actual width needs to be calculated based on the conductivity and thickness of the subsequently superimposed metal. For example, if the actual copper on the PCB is 1oz, and if the superimposed metal is aluminum and also 1oz thick, then a 50A power trace plane width of 30mm can meet the required current carrying capacity. Specifically, while meeting the current carrying capacity of the high-current power network, in order to reduce the number of PCB board layers or reduce the size of the PCB board, thereby reducing the cost of PCB board manufacturing, a localized area of ​​the high-current power network trace is electroplated or pressed together to form a laminated area formed by other metals and the copper-plated area formed by the copper traces to meet the power carrying capacity. The other metals can be selected based on actual needs and cost. During the PCB manufacturing process, the inner layers of the circuit board are etched and the various layers are laminated to form the circuit board. Specifically, after the inner layers of the PCB board are etched and formed, the entire PCB board is laminated. Then, holes are drilled and copper is electroplated based on the width of the copper-plated area determined above to complete the initial version. The metal in the laminated area is further stacked to form the power supply lines on the surface of the circuit board.

[0089] In summary, the present application discloses a circuit board surface structure comprising: a power supply line arranged on the surface of the circuit board; the power supply line comprising a copper-plated region and a laminated region; the laminated region superimposed on the surface of the copper-plated region to form an integral conductor; wherein the cross-sectional area of ​​each of the copper-plated region and the laminated region in the integral conductor is determined by the current carrying capacity required by the power supply signal. The power supply line of the present application is conductive by superimposing other metals on top of conventional copper lines. While satisfying the current flow requirements of the power supply network, the power supply network wiring space is greatly reduced, thereby facilitating the routing design of other signals, while avoiding the need to increase PCB board layers, facilitating the miniaturization of PCB board design, and reducing the cost of PCB board manufacturing.

[0090] Optionally, before step 103, the method further includes:

[0091] Step 104 , etching isolation holes in the copper-plated area at preset intervals along the current flow direction of the copper-plated area; the area where the isolation holes are located is not covered with metal copper.

[0092] In the embodiments of the present application, to enhance the conductivity of the overall conductor formed by stacking the laminated area over the copper-plated area, further detailed design is performed during the PCB design process, provided that the width of the power trace on the PCB surface needs to be reduced. Isolation holes can be designed in the copper-plated area of ​​the power trace. This isolation hole design allows copper metal in this area to be removed during PCB processing, sized to the isolation hole size. Furthermore, when other metal is stacked, the added metal can be inserted into the hole, thereby increasing the connection strength and conductivity between the different metals.

[0093] During the PCB design process, circular isolation holes with a diameter of 0.3-0.4 mm are added every 5-10 mm on the power routing plane, according to the current flow direction. These isolation holes are designed to keep the copper metal in this area of ​​the power routing plane out of the way. The preset spacing between two isolation holes can be greater than or equal to 5 mm and less than or equal to 10 mm. For example, the preset spacing can be selected from 5 mm, 6 mm, 7 mm, 8 mm, 9 mm, 10 mm, etc., and this embodiment of the present application does not limit this. When the preset spacing is within this range, the connection strength and conductivity requirements between the copper-plated area and the metal in the laminated area can be met. Furthermore, the isolation holes can be arranged in a single row or multiple rows. In actual use, the size of the isolation holes, the distance between the isolation holes, and the specific arrangement of the isolation holes can all be designed according to actual needs and are not limited in this embodiment of the present application. There is no copper metal in the isolation hole area. As shown in Figure 3, there is no copper metal in the circular hole area on the power routing plane. In addition, the isolation holes do not need to be completely in a straight line. As long as the isolation holes are added along the direction of the power current flow, the isolation holes can have position deviations to the left, right, top, and bottom according to actual conditions, which has no effect on the functions to be achieved by this patent. During the PCB processing and manufacturing process, the isolation hole area is directly etched with a solution to remove the metal copper in the isolation hole area. During the PCB board design process, the size and spacing of the isolation holes on the power network traces can be optimized and adjusted according to the PCB board area, the power network trace width, and the metal to be pressed or electroplated, thereby increasing the bonding strength between copper and other metals.

[0094] In addition, when making the isolation hole, the isolation hole can be designed to be circular, and of course it can also be square, rectangular, triangular, and any polygonal or irregular shape, which can all achieve the technical effect of the isolation hole of the present application. The present application does not limit the specific shape of the isolation hole. Preferably, the circular design can simplify the manufacturing process. In the case where the isolation hole is circular, the diameter of the isolation hole can be designed to be greater than or equal to 0.3 mm and less than or equal to 0.4 mm. For example, the diameter of the isolation hole can be 0.3 mm, 0.32 mm, 0.34 mm, 0.36 mm, 0.38 mm, 0.4 mm, etc. When the size of the isolation hole is within the above range, the connection strength and conductivity requirements between the metals of the copper-plated area and the laminated area can be met. The specific size design can be selected according to the actual situation. In addition to the circle, the size design of the isolation hole of other shapes can refer to the circle. The embodiment of the present application is not limited here.

[0095] Optionally, before step 103, the method further includes:

[0096] Step 105 : Covering the other traces on the surface of the circuit board except the power traces with a protective film.

[0097] In the embodiment of the present application, after the inner layer of the PCB board is etched and formed, the entire PCB board is pressed together, and then holes are drilled and copper is electroplated to complete the initial version; the metal is further superimposed. At this time, except for the power network plane window that needs to be optimized, other conventional network lines are covered with ink to ensure that the metal copper is not leaked. Other metals that need to be superimposed (such as silver, aluminum, etc.) are electroplated or pressed on the optimized power network line plane copper. The width should not be greater than the width of the metal copper line below it, and the thickness can be 0.5OZ to 1.5OZ; because the metal in other areas has been covered with ink, electroplating or pressing other metals will not cause short circuits with other networks, thereby improving the yield rate of the finished product.

[0098] Optionally, after step 105, the method further includes:

[0099] Step 106 : Micro-etching the copper-plated area to form metal burrs on the surface of the copper-plated area.

[0100] In the embodiment of the present application, the signal transmission rate in the current PCB board is constantly increasing. In order to avoid the attenuation of signal transmission quality due to the skin effect during high-speed signal transmission, the metal copper on the surface of the PCB board is usually treated with RTF (Reverse Treat Foil). The metal copper surface formed by this process is smooth. Therefore, during the processing of the PCB board, after the metal copper of other signal networks is covered with ink, in order to strengthen the bonding between the copper-plated area and the laminated area, the present application further performs micro-etching on the metal copper of the exposed power supply network to form burrs on the metal copper surface, and then electroplates or presses other metals on it. This can greatly increase the bonding force between different metals and the current transmission efficiency, reduce the transmission impedance, and thus improve the overall conductivity; while ensuring that other high-speed signal lines are not affected.

[0101] The exposed power network plane metal copper on the surface of the PCB board is micro-etched to make its metal surface have more burrs. More metal burrs are conducive to good contact with the pressed metal and current transmission, reducing transmission impedance.

[0102] Optionally, after step 106, the method further includes:

[0103] Step 107 : Overlaying the laminated area on the copper-plated area by electroplating or lamination.

[0104] In an embodiment of the present application, other metals (such as silver, aluminum, etc.) that need to be superimposed on the stacking area can be electroplated or pressed onto the optimized power network routing plane copper. The specific method can be determined according to the metal type of the selected stacking area, and the embodiment of the present application is not limited here.

[0105] For example, iron is very hard and difficult to press-fit. If iron is used, electroplating is required. Aluminum, tin, etc. can be pressed.

[0106] Optionally, after step 103, the method further includes:

[0107] Step 108: Cover the power traces on the surface of the circuit board with a protective film.

[0108] In this embodiment, during the PCB fabrication process, before the stacking areas are added, the metal in other areas is already covered with ink. This prevents short circuits with other networks during electroplating or lamination of the other metals. Finally, the optimized power network traces on the entire PCB are covered with ink, completing the PCB fabrication process.

[0109] Optionally, the method further comprises:

[0110] Step 109 , when metal tin is selected as the laminated area, the metal tin is mixed with any one or more of metal silver, metal gold, metal aluminum and metal iron to form a laminated area, and then the laminated area is superimposed on the copper-plated area.

[0111] In the embodiments of the present application, iron is relatively hard and difficult to press together. If iron is used, an electroplating process is required. Silver and gold are relatively expensive and are not recommended. If tin is used, it is necessary to add other metals to the mixture to increase its melting point. For example, tin can be mixed with any one or more of silver, gold, aluminum, and iron to form a laminated area to avoid the surrounding temperature rising during subsequent PCB board soldering, causing the superimposed tin to melt and create a short circuit risk.

[0112] That is, this application mainly proposes a design method for increasing the flow capacity of the surface routing of PCB boards from the perspective of PCB design and its production. Without increasing the number of board layers or reducing the number of board layers or the size of the board to reduce costs, the flow capacity of the power signal routing on the surface of the PCB board is increased, thereby reducing the cost of the PCB board while ensuring the electrical performance of the electronic product. Specifically, by reducing the width of the high-current power network routing in the PCB board; other metals (silver, aluminum, tin) are superimposed on the metal copper by electroplating or pressing for power transmission; during the PCB board design process, isolation holes are designed for the high-current power network routing to increase the bonding between different metals; during the PCB board processing process, other network routings are first covered with ink, and then the power plane is micro-etched to increase the surface roughness of the metal copper, and then the power network routing metal is superimposed to avoid short circuits; at the same time, if metal tin is superimposed, other metals need to be added to the metal tin to increase its melting point to avoid the superimposed metal tin melting during the later soldering of the PCB board. In specific operations, the trace width of the high-current power network and the thickness of the superimposed metal are calculated in detail based on the conductivity of the superimposed metal. By superimposing other metals above the high-current power network traces, the problem of ensuring power flow can be effectively solved without increasing the trace width or the stacking layer. Furthermore, compared with conventional designs, this application facilitates the miniaturization of PCB board designs, reduces PCB board manufacturing costs, and promotes the miniaturization of electronic products.

[0113] Under the premise of meeting the current carrying requirements of the high-current power supply network, this application proposes to reduce the PCB board stacking or reduce the PCB board size, thereby reducing the PCB board production cost; it proposes to perform localized treatment on the high-current power supply network routing, and to superimpose other metals on the copper routing by electroplating or pressing to meet the power flow. Other metals can be selected according to actual needs and costs. This application solves the technical problem of meeting the current carrying design of the high-current power supply network without increasing the stacking and size of the PCB board. It can be especially used in the design of PCB boards for server products that require hundreds of amperes of nuclear power.

[0114] In summary, the present application discloses a circuit board surface structure comprising: a power supply line arranged on the surface of the circuit board; the power supply line comprising a copper-plated region and a laminated region; the laminated region superimposed on the surface of the copper-plated region to form an integral conductor; wherein the cross-sectional area of ​​each of the copper-plated region and the laminated region in the integral conductor is determined by the current carrying capacity required by the power supply signal. The power supply line of the present application is conductive by superimposing other metals on top of conventional copper lines. While satisfying the current flow requirements of the power supply network, the power supply network wiring space is greatly reduced, thereby facilitating the routing design of other signals, while avoiding the need to increase PCB board layers, facilitating the miniaturization of PCB board design, and reducing the cost of PCB board manufacturing.

[0115] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0116] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0117] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are protected by this application.

Claims

1. A circuit board power supply structure, characterized in that: include: Power traces arranged on the surface of the circuit board; The power trace includes a copper-plated area and a laminated area; the laminated area is superimposed on the surface of the copper-plated area; the copper-plated area and the laminated area together form an integral conductor; The cross-sectional areas of the copper-plated region and the laminated region in the overall conductor are determined by the current carrying capacity required by the power signal and the metal conductivity of the laminated region.

2. The circuit board power supply structure according to claim 1, characterized in that: Disposing isolation holes in the copper-plated area at preset intervals along the current flow direction of the copper-plated area; The area where the isolation hole is located is not covered with metal copper.

3. The circuit board power supply structure according to claim 2, characterized in that: The preset interval is greater than or equal to 5 mm and less than or equal to 10 mm; The greater the width of the copper-plated area along a first direction, the smaller the preset interval between the isolation holes, and the first direction is perpendicular to the current flow direction.

4. The circuit board power supply structure according to claim 2 or 3, characterized in that: The isolation hole is a circular isolation hole; The diameter of the isolation hole is greater than or equal to 0.3 mm and less than or equal to 0.4 mm.

5. The circuit board power supply structure according to claim 1, characterized in that: The stacked region is formed of any one or more of gold, silver, aluminum, tin, and iron.

6. The circuit board power supply structure according to claim 1, characterized in that: The routing width of the stacked area is less than or equal to the routing width of the copper-plated area.

7. The circuit board power supply structure according to claim 6, characterized in that: The thickness of the laminated region is 0.5OZ to 1.5OZ.

8. The circuit board power supply structure according to claim 1, characterized in that: The width of the copper-plated area is one third to one half of the width of the copper-plated area when only the copper-plated area is used for current flow, which is determined by the required current-carrying capacity.

9. The circuit board power supply structure according to claim 1, characterized in that: The other wirings on the surface of the circuit board except the power wiring are covered with a protective film.

10. The circuit board power supply structure according to claim 1, characterized in that: Metal burrs are formed on the surface of the copper-plated area by micro-etching.

11. The circuit board power supply structure according to claim 1, characterized in that: The distance between the isolation hole and the closest edge of the copper-plated area is greater than or equal to 1 mm.

12. The circuit board power supply structure according to claim 1, characterized in that: The isolation holes are arranged in a single row or in multiple rows.

13. The circuit board power supply structure according to claim 5, characterized in that: The metal of the stacked layer region is a mixed metal formed by metal tin and any one or more of metal silver, metal gold, metal aluminum and metal iron.

14. A method for manufacturing a circuit board power supply structure, characterized in that: The method comprises: Determining the width and thickness of the copper plated area and the width and thickness of the stacking area based on the current carrying capacity required by the power signal and the metal conductivity of the stacking area; Etching the inner layers of the circuit board and laminating the various layers of the circuit board to form a circuit board; Based on the width and thickness of the copper-plated area, a copper-plated area is electroplated on the surface of the circuit board body, and based on the width and thickness of the laminated area, the laminated area is superimposed on the copper-plated area to form a power supply line on the surface of the circuit board.

15. The method according to claim 14, characterized in that Before pressing the laminated area onto the copper plated area based on the width and thickness of the laminated area, the method further includes: Isolation holes are formed by etching in the copper-plated area at preset intervals along the current flow direction of the copper-plated area; the area where the isolation holes are located is not covered with metal copper.

16. The method according to claim 14, characterized in that Before pressing the laminated area onto the copper plated area based on the width and thickness of the laminated area, the method further includes: The other wirings on the surface of the circuit board except the power wiring are covered with a protective film.

17. The method according to claim 16, characterized in that After covering the other areas of the circuit board surface except the power supply wiring with a protective film, the method further includes: The copper-plated area is micro-etched to form metal burrs on the surface of the copper-plated area.

18. The method according to claim 17, characterized in that After micro-etching the copper-plated area so that metal burrs are formed on the surface of the copper-plated area, the method further includes: The laminated area is superimposed on the copper-plated area by electroplating or lamination.

19. The method according to claim 14, wherein After forming the power supply traces on the circuit board surface, the method further includes: A protective film is covered on the power supply traces on the surface of the circuit board.

20. The method according to claim 14, wherein The method further comprises: When metal tin is selected as the laminated area, the metal tin is mixed with any one or more of metal silver, metal gold, metal aluminum and metal iron to form a laminated area, and then the laminated area is superimposed on the copper-plated area.

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