Clock detection method and system, device, medium, and server

Abstract

The present application relates to the field of data processing, and discloses a clock detection method and system, a device, a medium, and a server, for use in solving the problem of inaccurate data transmission caused by an inaccurate clock during one-wire communication. According to the solution a clock signal of a hard disk and a data signal are encoded to obtain a communication signal; and the communication signal is sent to a baseboard management controller, so that the baseboard management controller parses the communication signal, and on the basis of the clock signal obtained by parsing, determines whether a clock of the hard disk is accurate. According to the present application, hard disk log data, a hard disk state signal, and a clock signal can be transmitted via a hard disk state pin, the clock of a hard disk can be calibrated by encoding the clock signal and a data signal and parsing a communication signal, and then whether the data signal is transmitted on the basis of an accurate clock can determined, so as to find a problem in time to ensure the accuracy of data signal transmission, thereby ensuring the reliability of monitoring the hard disk.

Description

Clock detection method, system, device, medium and server

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on March 29, 2024, with application number 202410382840.2, and application name “A clock detection method, system, device, medium and server”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of data processing, and in particular to a clock detection method, system, device, medium and server. Background Art

[0004] The hard disk is one of the most important storage devices in the computer. Therefore, the healthy operation of the hard disk is one of the key factors to ensure the reliability of the device server.

[0005] In order to ensure accurate control of the operating status of the hard disk, the device needs to monitor the hard disk during operation to obtain the hard disk status information. The current main hard disk monitoring solutions are divided into hard disk in-band monitoring and hard disk out-of-band monitoring. Hard disk in-band monitoring is to obtain the hard disk status information after the monitoring software running on the central processing unit (CPU) communicates data with the hard disk. This monitoring solution often makes it difficult to present the monitoring data to the operation and maintenance personnel. Hard disk out-of-band monitoring is to monitor the hard disk status after obtaining the hard disk status information through the baseboard management controller (Baseboard Management Controller, BMC). If the communication between the hard disk and the baseboard management controller is single-line, the hard disk can only transmit monitoring data to the baseboard management controller and cannot perform clock calibration through additional lines. Therefore, the baseboard management controller cannot detect whether the monitoring data sent by the hard disk is based on the correct clock, which may cause the transmitted monitoring data to be inaccurate, and the reliability of hard disk monitoring is low. Summary of the Invention

[0006] In a first aspect, the present application provides a clock detection method, which is applied to a baseboard management controller, wherein the baseboard management controller communicates with a hard disk via a single line. The clock detection method includes:

[0007] Receives the communication signal sent by the hard disk through the hard disk status pin. The communication signal is a signal obtained by encoding the hard disk data signal and its own clock signal. The data signal is a signal modulated by the hard disk based on the hard disk log data and the hard disk status signal corresponding to the hard disk status pin.

[0008] Analyze the communication signal to obtain a clock signal and a data signal; and

[0009] Determine whether the hard disk clock is accurate based on the clock signal.

[0010] In one embodiment, parsing a communication signal to obtain a clock signal and a data signal includes:

[0011] Parse the communication signal to obtain at least two flag signals and data to be transmitted; the data signal includes the data to be transmitted and a flag signal with a fixed pulse width. The flag signal is used to represent the current transmission progress of the data signal. The hard disk encodes its current clock frequency into the flag signal;

[0012] Determine whether the hard drive's clock is accurate based on the clock signal, including:

[0013] The accuracy of the hard disk clock is determined based on the pulse width corresponding to the two flag signals.

[0014] In one embodiment, determining whether the hard disk clock is accurate based on the pulse widths corresponding to the two flag signals includes:

[0015] Determining whether the pulse widths corresponding to the two flag signals are within a preset range of the standard pulse width, or determining whether the difference between the pulse widths corresponding to the two flag signals is within an error range;

[0016] In response to the pulse widths corresponding to the two flag signals being within a preset range of the standard pulse width, or the difference being within an error range, determining that the hard disk clock is accurate; and

[0017] In response to the pulse widths corresponding to the two flag signals not being within a preset range of the standard pulse width, or the difference being not within an error range, it is determined that the hard disk clock is inaccurate.

[0018] In one embodiment, the hard disk status pin outputs a control signal of a first level when the hard disk is in a preset state, inserts a plurality of pulse signals of a second level with a preset width into the control signal, and uses the pulse signals to divide the control signal to obtain a pulse width of the first level corresponding to each data bit, encodes the current clock frequency of the hard disk into a pulse signal of the second level with a preset width, and obtains a communication signal based on the pulse signal of the second level with the preset width and the plurality of pulse widths of the first level, wherein the data signal includes a plurality of data bits, and the second level is opposite to the first level;

[0019] Analyze the communication signal to obtain the clock signal and data signal, including:

[0020] parsing the communication signal to obtain at least two second-level pulse signals and a plurality of first-level pulse widths;

[0021] Determine whether the hard drive's clock is accurate based on the clock signal, including:

[0022] Whether the clock of the hard disk is accurate is determined based on at least two pulse signals of the second level.

[0023] In one embodiment, determining whether the hard disk clock is accurate based on at least two pulse signals of the second level includes:

[0024] Determining whether a width difference between two second-level pulse signals is within an error range;

[0025] In response to being within the error range, determining that the clock of the hard disk is accurate; and

[0026] In response to not being within the error range, it is determined that the clock of the hard disk is inaccurate.

[0027] In one embodiment, parsing a communication signal to obtain a clock signal and a data signal includes:

[0028] The communication signal is parsed to obtain a square wave signal and a data signal, wherein a square wave frequency of the square wave signal and a clock frequency of the hard disk are in a second mapping relationship;

[0029] Determine whether the hard drive's clock is accurate based on the clock signal, including:

[0030] Determines whether the hard disk clock is accurate based on the square wave signal.

[0031] In one embodiment, determining whether the hard disk clock is accurate based on the square wave signal includes:

[0032] Determine whether the frequency difference between the two square wave signals is within a preset frequency range;

[0033] In response to the frequency difference being within a preset frequency range, determining that the clock of the hard disk is accurate; and

[0034] In response to the frequency difference not being within the preset frequency range, it is determined that the clock of the hard disk is inaccurate.

[0035] In one embodiment, it further includes:

[0036] In response to determining that the clock of the hard disk is inaccurate, a feedback signal is sent to the hard disk and / or hard disk controller via the hard disk status pin to cause the hard disk to retransmit the data signal or communication signal.

[0037] In a second aspect, the present application provides a clock detection method, which is applied to a hard disk, wherein the hard disk communicates with a baseboard management controller via a single line. The clock detection method includes:

[0038] Encode its own clock signal and data signal to obtain a communication signal, where the data signal is a signal modulated by the hard disk according to the hard disk log data and the hard disk status signal corresponding to the hard disk status pin; and

[0039] The communication signal is sent to the baseboard management controller through the hard disk status pin, so that the baseboard management controller analyzes the communication signal, obtains the clock signal and the data signal, and determines whether the hard disk clock is accurate based on the clock signal.

[0040] In one embodiment, the data signal includes data to be transmitted and a flag signal of a fixed pulse width. The flag signal is used to indicate the current transmission progress of the data signal. The communication signal is obtained by encoding its own clock signal and data signal, including:

[0041] Encode its current clock frequency into the flag signal; and

[0042] Integrate the flag signal and the data to be transmitted to obtain a communication signal;

[0043] The baseboard management controller analyzes the communication signal to obtain the clock signal and data signal, and determines whether the hard disk clock is accurate based on the clock signal, including:

[0044] The baseboard management controller analyzes the communication signal to obtain at least two flag signals and data to be transmitted; and

[0045] The accuracy of the hard disk clock is determined based on the pulse width corresponding to the two flag signals.

[0046] In one embodiment, the hard disk status pin outputs a control signal of a first level when the hard disk is in a preset state; and encodes its own clock signal and data signal to obtain a communication signal, including:

[0047] Inserting a plurality of pulse signals of a second level with a preset width into the control signal to divide the control signal using the pulse signals to obtain a pulse width of the first level corresponding to each data bit one by one; the data signal includes a plurality of data bits, and the second level is opposite to the first level; and

[0048] The clock signal thereof is encoded with a plurality of second-level pulse signals and a plurality of first-level pulse widths to obtain a communication signal.

[0049] In one embodiment, encoding the clock signal thereof with a plurality of second-level pulse signals and a plurality of first-level pulse widths to obtain a communication signal includes:

[0050] Encoding its current clock frequency into a pulse signal of a second level with a preset width, wherein a first mapping relationship exists between the clock frequency and the preset width, and the communication signal includes a plurality of pulse signals of the second level with the preset width and a plurality of pulse widths of the first level;

[0051] The baseboard management controller analyzes the communication signal to obtain the clock signal and data signal, and determines whether the hard disk clock is accurate based on the clock signal, including:

[0052] The baseboard management controller analyzes the communication signal to obtain at least two second-level pulse signals and a plurality of first-level pulse widths;

[0053] Determining whether a width difference between two second-level pulse signals is within an error range;

[0054] In response to being within the error range, determining that the clock of the hard disk is accurate; and

[0055] In response to not being within the error range, it is determined that the clock of the hard disk is inaccurate.

[0056] In one embodiment, encoding its own clock signal and data signal to obtain a communication signal includes:

[0057] Encoding its current clock frequency into a square wave signal, wherein the frequency of the square wave signal and the clock frequency form a second mapping relationship; and

[0058] Inserting the square wave signal into the data signal to obtain a communication signal;

[0059] The baseboard management controller analyzes the communication signal to obtain the clock signal and data signal, and determines whether the hard disk clock is accurate based on the clock signal, including:

[0060] The baseboard management controller analyzes the communication signal to obtain a square wave signal and a data signal, and determines whether the hard disk clock is accurate based on the square wave signal.

[0061] In one embodiment, encoding its own clock signal and data signal to obtain a communication signal includes:

[0062] Encoding its current clock frequency into a square wave signal, wherein the frequency of the square wave signal and the clock frequency form a second mapping relationship;

[0063] Encoding each data bit into a pulse width corresponding to the data bit to obtain a first pulse width signal, wherein the data signal includes multiple data bits, and the first pulse width signal includes pulse widths corresponding to the multiple data bits; and

[0064] Encoding the square wave signal and the first pulse width signal to obtain a communication signal;

[0065] The baseboard management controller analyzes the communication signal to obtain the clock signal and data signal, and determines whether the hard disk clock is accurate based on the clock signal, including:

[0066] The baseboard management controller analyzes the communication signal to obtain a square wave signal and a first pulse width signal, and determines whether the hard disk clock is accurate based on the square wave signal.

[0067] In one embodiment, encoding the square wave signal and the first pulse width signal to obtain a communication signal includes:

[0068] At least two square wave signals are respectively inserted before the pulse width corresponding to the first data bit and / or after the pulse width corresponding to the last data bit and / or between the pulse widths corresponding to any two data bits to obtain a communication signal.

[0069] In one embodiment, encoding each data bit into a pulse width corresponding to the data bit to obtain a first pulse width signal includes:

[0070] Each data bit is encoded into a pulse width with a duty cycle corresponding to the data bit one by one to obtain a first pulse width signal, and a third mapping relationship is formed between the duty cycle and the data bit.

[0071] In one embodiment, encoding each data bit into a pulse width corresponding to the data bit to obtain a first pulse width signal includes:

[0072] Each data bit is encoded into a pulse width of a preset level corresponding to the data bit to obtain a first pulse width signal, and a fourth mapping relationship exists between the pulse width of the preset level and the data bit.

[0073] In one embodiment, it further includes:

[0074] After the baseboard management controller determines that the clock of the hard disk is inaccurate, receiving a feedback signal sent by the baseboard management controller; and

[0075] The data signal or the communication signal is resent based on the feedback signal.

[0076] In a third aspect, the present application further provides a clock detection system, which is applied to a baseboard management controller, wherein the baseboard management controller communicates with a hard disk via a single line. The clock detection system includes:

[0077] The receiving unit is used to receive the communication signal sent by the hard disk through the hard disk status pin. The communication signal is a signal obtained by the hard disk based on the data signal and its own clock signal encoding;

[0078] A parsing unit, configured to parse the communication signal to obtain a clock signal and a data signal; and

[0079] The judgment unit is used to judge whether the clock of the hard disk is accurate based on the clock signal.

[0080] In a fourth aspect, the present application further provides a clock detection system, wherein a hard disk and a baseboard management controller communicate via a single line, and the clock detection system comprises:

[0081] An encoding unit, configured to encode its own clock signal and data signal to obtain a communication signal, wherein the data signal is a signal modulated by the hard disk according to the hard disk log data and the hard disk status signal corresponding to the hard disk status pin; and

[0082] The sending unit is used to send the communication signal to the baseboard management controller through the hard disk status pin, so that the baseboard management controller analyzes the communication signal, obtains the clock signal and the data signal, and determines whether the hard disk clock is accurate based on the clock signal.

[0083] In a fifth aspect, the present application further provides an electronic device, comprising:

[0084] a memory for storing computer-readable instructions;

[0085] The processor is configured to implement the steps of the clock detection method described above when executing computer-readable instructions.

[0086] In a sixth aspect, the present application also provides one or more non-volatile computer-readable storage media storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, the one or more processors implement the steps of the clock detection method as described above.

[0087] In a seventh aspect, the present application further provides a server, comprising a hard disk and a baseboard management controller, wherein the hard disk and the baseboard management controller are connected by a single line, and there is only one transmission channel between the hard disk and the baseboard management controller via the single line;

[0088] The baseboard management controller is used to implement the steps of the clock detection method applied to the baseboard management controller; the hard disk is used to implement the steps of the clock detection method applied to the hard disk. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0090] FIG1 is a schematic diagram showing a connection between a hard disk and a baseboard management controller according to one or more embodiments of the present application;

[0091] FIG2 is a flow chart of a clock detection method applied to a baseboard management controller according to one or more embodiments of the present application;

[0092] FIG3 is a schematic diagram of a data signal provided by one or more embodiments of the present application;

[0093] FIG4 is a schematic diagram of a combination of a square wave signal and a data signal provided by one or more embodiments of the present application;

[0094] FIG5 is a schematic diagram of a square wave signal provided by one or more embodiments of the present application;

[0095] FIG6 is a flowchart of a clock detection method applied to a hard disk according to one or more embodiments of the present application;

[0096] FIG7 is a specific flow chart of a clock detection method applied to a hard disk provided by one or more embodiments of the present application;

[0097] FIG8 is a specific flow chart of a clock detection method applied to a baseboard management controller according to one or more embodiments of the present application;

[0098] FIG9 is a schematic diagram of a clock detection system applied to a hard disk according to one or more embodiments of the present application;

[0099] FIG10 is a schematic diagram of a clock detection system applied to a baseboard management controller according to one or more embodiments of the present application;

[0100] FIG11 is a schematic diagram of an electronic device provided by one or more embodiments of the present application. DETAILED DESCRIPTION

[0101] The core of this application is to provide a clock detection method, system, device, medium and server, which can realize the transmission of hard disk log data, hard disk status signal and clock signal through the hard disk status pin, and calibrate the hard disk clock by encoding the clock signal and data signal, and analyzing the communication signal, so as to determine whether the data signal is based on the correct clock transmission, and timely discover problems to ensure the accuracy of data signal transmission, thereby ensuring the reliability of monitoring the hard disk.

[0102] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0103] To facilitate understanding, let's first introduce the aspects of out-of-band hard drive monitoring. Out-of-band management refers to managing the network through a dedicated network management channel, separating network management data from business data. This independent channel transmits only management data, separating network management data from business data. This improves network management efficiency and reliability, while also enhancing the security of network management data.

[0104] Because in-band monitoring cannot meet maintenance requirements, after server deployment, out-of-band management and monitoring capabilities are provided through a baseboard management controller (BMC). A BMC is a dedicated service processor that uses sensors to monitor the status of a computer, network server, or other hardware device and communicates with the device's system administrator via independent connections. In practice, the BMC is typically installed on the motherboard or main circuit board of the monitored device. The BMC uses sensors to measure internal physical variables such as temperature, humidity, power supply voltage, fan speed, communication parameters, and operating system (OS) functions. If any of these variables exceeds specified limits, the BMC notifies the system administrator. The BMC also provides web services, including network communication capabilities and a webpage displaying a monitoring interface. Maintenance personnel can access BMC monitoring data by connecting to the BMC of the monitored device via a network cable at the facility site or by connecting the BMCs of multiple monitored devices via a network in a data center.

[0105] Due to the limited performance and pin count of the BMC chip in a BMC system, as the number of components and items requiring monitoring increases, complex programmable logic devices (CPLDs) are often included in BMC systems to offload performance pressure from the BMC chip and provide more pins for connecting sensors or monitored components. A CPLD primarily consists of three components: logic blocks, programmable interconnects, and input / output (I / O) blocks. A logic block in a CPLD typically includes 4 to 20 macrocells, each of which typically consists of a product term array, a product term allocation, and programmable registers. Each macrocell has multiple configurations and can be cascaded, enabling the implementation of complex combinational and sequential logic functions. CPLDs with higher integration densities often also include embedded array blocks with on-chip random access memory (RAM) / read-only memory (ROM). The programmable interconnects primarily provide the interconnect network between the logic blocks, macrocells, and I / O pins. Input / output blocks (I / O blocks) provide the interface between internal logic and the device's I / O pins.

[0106] As an important component of the server, the hard disk is an important target for out-of-band monitoring and management. According to the type of communication interface, it is mainly divided into Serial Attached SCSI (SAS) / Serial Advanced Technology Attachment (SATA) interface hard disks and Non-Volatile Memory Host Controller Interface Specification (NVMHCIS or NVM Express, NVMe) interface hard disks. Among them, the SAS interface is compatible with the SATA interface. According to the type of storage medium, hard disks are mainly divided into mechanical hard disks (HDD) and solid-state drives (SSD). Among them, mechanical hard disks mainly have SAS or SATA interfaces. Solid-state drives include SAS, SATA, and NVMe interface hard disks.

[0107] It should be noted that, in an embodiment of the present invention, the baseboard management controller may include only a baseboard management controller chip, or it may be a system including a baseboard management controller chip and a complex programmable logic device. The complex programmable logic device may be a complex programmable logic device only provided on the hard disk backplane or a complex programmable logic device provided on the server mainboard.

[0108] Furthermore, in this application, the hard disk selects the hard disk status pin to send data to the baseboard management controller because:

[0109] Hard drive pins are primarily categorized into three types: data pins, power pins, and hard drive status pins. The hard drive's data pins connect to the in-band system, while the hard drive's power pins are used to connect power and ground signals. Therefore, the baseboard management controller can only directly access the hard drive's status pins.

[0110] The hard disk status pins of the hard disk mainly include the hard disk status indication pin, the hard disk production debugging pin and the hard disk idle pin.

[0111] Among them, the hard disk status indication pins include the hard disk in-place status indication pin and the hard disk read / write status indication pin. The hard disk status indication pins are pins used by the hard disk to output hard disk status indication signals. For example, the hard disk in-place status indication pin is used to output the hard disk in-place status signal, and the hard disk read / write status indication pin is used to output the hard disk read / write status signal.

[0112] When a hard drive is connected to the hard drive backplane, the hard drive status indicator pins can be connected in two main ways: one to the baseboard management controller (BMC) to transmit the corresponding hard drive status data, and the other to the control circuit on the hard drive backplane to control the status of the corresponding controlled components, thereby informing the user of the corresponding hard drive status. For example, the hard drive backplane is equipped with a hard drive status indicator to indicate the hard drive's operating status. For example, when the hard drive is in the read / write state, the hard drive status indicator pins can be controlled to output a square wave signal to the amplifying and driving circuit of the hard drive status indicator to illuminate the hard drive status indicator. When the hard drive is not in the read / write state (idle state), the hard drive status indicator pins can be controlled to output a constant level signal (e.g., a constant high level signal) to turn off the hard drive status indicator, indicating that the hard drive is in the idle state. The user can then determine whether the hard drive is in the read / write state by observing the on / off status of the hard drive status indicator. The same principle applies to the hard drive status display based on the hard drive presence status indicator pins. Alternatively, the hard drive can also output two different constant level signals (one high, one low) through these hard drive status indicator pins to indicate different states. These signals can be input to the baseboard management controller to trigger corresponding recording, processing, or control.

[0113] The production debug pins of hard drives are mainly the pins (debug pins) next to the SAS or SATA interface of hard drives. These pins are usually used during the production debug phase of the hard drive. In actual use of the hard drive, the production debug pins can be used to output boot information during the hard drive initialization phase.

[0114] On the NVMe interface hard drive, in addition to the above-mentioned hard drive status indication pin, there is also a hard drive idle pin.

[0115] The above-mentioned hard disk status pins are not the pins used by the hard disk to output data, and there is no risk of leaking user data stored in the hard disk. Currently, after the hard disk is inserted into the hard disk backplane, these hard disk status pins are directly connected to the baseboard management controller or have the permission to connect to the baseboard management controller.

[0116] In an embodiment of the present application, the hard disk status pin of the hard disk may include at least one of a hard disk status indication pin, a hard disk production debugging pin, and a hard disk idle pin.

[0117] In an embodiment of the present invention, if hard disk status indication pins such as a hard disk in-place status indication pin and a hard disk read / write status indication pin are used, since these hard disk status pins are usually already connected to the general-purpose input / output (GPIO) pins of the baseboard management controller chip in the baseboard management controller or the input / output (I / O) pins of the complex programmable logic device, this hardware architecture can be directly adopted without making changes to the hardware architecture of the server, which is simple and convenient to implement.

[0118] Currently, the hard drive production debug pins on devices are typically left floating, typically consisting of four pins. If the embodiments of the present invention utilize the hard drive production debug pins as the hard drive status pins for outputting hard drive log data, a connector with a corresponding number of pins can be used to connect the hard drive production debug pins to the GPIO pins of the baseboard management controller chip or the I / O pins of a complex programmable logic device.

[0119] Since the hard disk idle pin is usually only available in the interface of NVMe interface hard drives, high-speed signals cannot be left floating. Currently, the hard disk idle pin in the NVMe interface is grounded through the resistor and capacitor circuit on the hard disk backplane after the hard disk is connected to the hard disk backplane. If the embodiment of the present invention uses the hard disk idle pin as the hard disk status pin for outputting hard disk log data, the connection relationship between the hard disk idle pin and the hard disk backplane is changed to connect to the GPIO pin of the baseboard management controller chip or the I / O pin of the complex programmable logic device.

[0120] In an out-of-band system, if the hard drive expansion card has an integrated circuit bus connected to the baseboard management controller chip, the baseboard management controller chip can access the hard drive expansion card via the integrated circuit bus and forward commands or hard drive log data to the hard drive through the hard drive expansion card. Furthermore, within the baseboard management controller, the baseboard management controller chip can also connect to a complex programmable logic device (CPLD) via the IC bus, and then connect to the hard drive status pin via the CPLD. Alternatively, the baseboard management controller chip can directly connect to the hard drive status pin.

[0121] In a first aspect, the present application provides a clock detection method applied to a hard disk, as shown in FIG1 , where the hard disk communicates with a baseboard management controller via a single line.

[0122] Single-line communication refers to the existence of only one transmission channel between the hard drive and the baseboard management controller. Single-line communication can be achieved through, but is not limited to, a single-wire connection. A single-wire connection refers to a single transmission line (DATA) between the hard drive and the baseboard management controller. This line can only provide a single transmission channel for transmitting hard drive status signals (GND in Figure 1 is the ground line, not a transmission line). Unlike a bus that includes a clock line, data line, etc., the single-wire connection in this application has only one line for transmitting hard drive status signals and does not include any other lines.

[0123] As shown in FIG2 , the clock detection method includes:

[0124] S11: Receive a communication signal sent by the hard disk through the hard disk status pin. The communication signal is a signal encoded by the hard disk based on the data signal and its own clock signal. The data signal is a signal modulated by the hard disk based on the hard disk log data and the hard disk status signal corresponding to the hard disk status pin.

[0125] Specifically, the clock signal corresponds to the clock source within the hard drive, used to synchronize data transmission and processing. The data signal is a signal modulated based on the hard drive log data and the hard drive status signal corresponding to the hard drive status pin. It contains hard drive status information and the data content corresponding to the current log. The clock signal and data signal are then encoded to convert the original clock and data signals into communication signals suitable for transmission over a single-wire transmission channel.

[0126] The reason the hard drive encodes the clock and data signals before transmission is that, in single-wire communication, clock calibration cannot be performed between the sender and receiver (that is, between the hard drive status pin and the baseboard management controller), making it impossible to determine whether the data signal is transmitted based on the correct clock. By encoding the clock and data signals, they can be combined into a single communication signal for transmission, meeting the requirements of signal transmission in single-wire communication scenarios.

[0127] S12: Analyze the communication signal to obtain a clock signal and a data signal;

[0128] S13: Determine whether the hard disk clock is accurate based on the clock signal.

[0129] Specifically, at the baseboard management controller end, after receiving the communication signal, the clock signal and data signal are obtained by parsing the communication signal, and whether the hard disk clock is accurate is judged based on the clock signal. In this way, the clock signal can be detected in a single-line communication mode to ensure the accuracy of data transmission.

[0130] Among them, the following methods can be used to determine whether the hard disk clock is accurate based on the clock signal: First, the baseboard management controller stores a standard clock signal, and compares the frequency of the received clock signal with the standard clock signal stored in itself. If the two clock frequencies are similar and stable, it can be determined that the hard disk clock is accurate; second, it can also be: the baseboard management controller performs a stability assessment on the received clock signal, and determines whether the hard disk clock is stable by counting the fluctuations of the clock signal within a certain period of time, thereby indirectly determining the accuracy of the clock.

[0131] In one embodiment, parsing a communication signal to obtain a clock signal and a data signal includes:

[0132] Parse the communication signal to obtain at least two flag signals and data to be transmitted; the data signal includes the data to be transmitted and a flag signal with a fixed pulse width. The flag signal is used to represent the current transmission progress of the data signal. The hard disk encodes its current clock frequency into the flag signal;

[0133] Determine whether the hard drive's clock is accurate based on the clock signal, including:

[0134] The accuracy of the hard disk clock is determined based on the pulse width corresponding to the two flag signals.

[0135] Specifically, when transmitting a data signal, along with the valid data to be transmitted, there are usually several flag signals that are transmitted together with the data to be transmitted, such as a flag signal that indicates the start of data transmission, a flag that indicates the end of data transmission, a data check bit, etc., which are interspersed in the transmission process of the data to be transmitted, and these flag signals are usually given a fixed pulse width in the communication protocol. At this time, the present application uses these fixed pulse width flag signals to carry the clock signal to realize the function of transmitting both the data to be transmitted and the clock signal during the single-line communication process. As shown in Figure 3, in Figure 3, the data signal indicates the start flag bit for the start of data transmission and the end flag bit for the end of data transmission. The data to be transmitted (including multiple data bits) is between the start flag bit and the end flag bit, and the start flag bit and the end flag bit can be used to encode the clock signal.

[0136] Accordingly, the baseboard management controller's process for parsing the communication signal includes extracting a flag signal from the communication signal. The flag signal should have a fixed pulse width when the hard drive's clock is functioning normally. Therefore, the baseboard management controller determines whether the hard drive's clock is accurate by determining whether the flag signal's pulse width is fixed. If not, indicating a change in the pulse width, the baseboard management controller then determines whether the change in the pulse width is greater than a threshold. If the change is greater than the threshold, the hard drive's clock is considered inaccurate. If the pulse width remains fixed, or the change is within the threshold, the hard drive's clock is considered accurate.

[0137] Compared to generating the clock signal separately, encoding the clock signal and the flag signal can not only more accurately evaluate the accuracy of the hard disk clock, which helps to promptly detect and correct clock inaccuracies, but also simplify the system design, so that more information can be transmitted within a limited channel under single-line communication mode, reducing the need for additional lines and lowering system complexity and cost.

[0138] In one embodiment, determining whether the hard disk clock is accurate based on the pulse widths corresponding to the two flag signals includes:

[0139] Determining whether the pulse widths corresponding to the two flag signals are within a preset range of the standard pulse width, or determining whether the difference between the pulse widths corresponding to the two flag signals is within an error range;

[0140] If the pulse widths corresponding to the two marker signals are within the preset range of the standard pulse width, or the difference is within the error range, the hard disk clock is determined to be accurate;

[0141] If the pulse widths corresponding to the two flag signals are not within the preset range of the standard pulse width, or the difference is not within the error range, it is determined that the hard disk clock is inaccurate.

[0142] In this embodiment, the accuracy of the hard disk clock is determined based on the pulse widths corresponding to the two flag signals. Specifically, the determination can be made as to whether the pulse widths corresponding to the two flag signals are within a preset range. If both pulse widths are within the preset range, the hard disk clock is determined to be accurate. Conversely, if the pulse widths corresponding to the two flag signals are not within the preset range, the hard disk clock is determined to be inaccurate. Alternatively, the determination can be made as to whether the difference between the pulse widths corresponding to the two flag signals is within an error range. If so, the hard disk clock is determined to be accurate. If not, the hard disk clock is determined to be inaccurate.

[0143] Furthermore, the above-described method for determining the clock based on two marker signals provides a method for determining whether the clock has drifted during this time interval by determining whether the difference between the two marker signals is within an error range. By determining whether the pulse widths of the two marker signals are within a preset range of a standard pulse width, it is possible to determine whether the clock has drifted from the standard clock. In another embodiment, the baseboard management controller can determine whether the clock is accurate based on a marker signal. In this case, the baseboard management controller stores a standard pulse width for a marker signal corresponding to a standard clock, and directly determines whether the clock is accurate by comparing the pulse width of the marker signal in the collected transmitted communication signal with the standard pulse width. This method of determining whether the hard disk clock is accurate by collecting whether the difference between the pulse widths corresponding to the two marker signals is within an error range is more suitable for scenarios where the baseboard management controller does not store a standard pulse width. By collecting two pulse widths, it is possible to directly determine whether the clock has drifted during the transmission of the data to be transmitted.

[0144] In a specific embodiment, two flag bits located before and after the data to be transmitted are usually selected as two flag signals for determining whether the hard disk clock is accurate, or the time interval between the two flag signals for determining whether the hard disk clock is accurate is limited to be no less than a preset time interval, thereby determining whether the clock drift occurs within this time interval, etc.

[0145] In summary, this method effectively checks the hard drive's clock accuracy, ensuring the accuracy and stability of data transmission. By analyzing the pulse width of the marker signal, inaccurate hard drive clocks can be promptly detected, providing a reliable clock signal reference for subsequent data processing and transmission. This prevents data transmission errors caused by clock inaccuracies and improves system reliability and stability.

[0146] In one embodiment, the hard disk status pin outputs a control signal of a first level when the hard disk is in a preset state, inserts a plurality of pulse signals of a second level with a preset width into the control signal, and uses the pulse signals to divide the control signal to obtain a pulse width of the first level corresponding to each data bit, encodes the current clock frequency of the hard disk into a pulse signal of the second level with a preset width, and obtains a communication signal based on the pulse signal of the second level with the preset width and the plurality of pulse widths of the first level, wherein the data signal includes a plurality of data bits, and the second level is opposite to the first level;

[0147] Analyze the communication signal to obtain the clock signal and data signal, including:

[0148] parsing the communication signal to obtain at least two second-level pulse signals and a plurality of first-level pulse widths;

[0149] Determine whether the hard drive's clock is accurate based on the clock signal, including:

[0150] Whether the clock of the hard disk is accurate is determined based on at least two pulse signals of the second level.

[0151] In one embodiment, determining whether the hard disk clock is accurate based on at least two pulse signals of the second level includes:

[0152] Determining whether a width difference between two second-level pulse signals is within an error range;

[0153] If it is within the error range, the hard disk clock is determined to be accurate;

[0154] If it is not within the error range, it is determined that the hard disk clock is inaccurate.

[0155] Specifically, when the hard disk status pin outputs a first-level control signal when the hard disk is in a preset state, the hard disk modulates the hard disk status signal and hard disk status data to obtain the first signal. The process may include: in the preset state, inserting a plurality of second-level pulse signals of preset width into the control signal, so as to divide the control signal using the pulse signals to obtain a first-level pulse width corresponding to each data bit, wherein the data signal includes multiple data bits and the second level is opposite to the first level. That is, by inserting a second-level pulse signal of opposite width into a constant first level to obtain a plurality of first-level pulse width signals, the hard disk log data is modulated.

[0156] In this case, the clock signal itself can be encoded with multiple second-level pulse signals and multiple first-level pulse widths to obtain a communication signal. This communication signal includes not only the clock signal, but also the hard disk log data and the corresponding hard disk status data, ensuring the accurate transmission of the clock signal and the data signal. In addition, the transmission of the hard disk status signal, the hard disk log data and the clock signal can be achieved through the hard disk status pin. Specifically, the clock signal is transmitted using this pulse signal, and the second-level pulse signal of the preset width is used as a segmentation signal to obtain the first-level pulse width corresponding to each data bit. When the hard disk clock is accurate, the width of each pulse signal output by the hard disk should be the preset width, or within the range of the preset width. If the hard disk clock is inaccurate, the width of each pulse signal output will deviate from the range of this preset width.

[0157] Therefore, the steps for the baseboard management controller to determine whether the hard disk clock is accurate based on the clock signal may include: first parsing the communication signal to obtain at least two second-level pulse signals, and judging whether the corresponding pulse width is within the error range based on the two pulse signals; if it is within the error range, it is determined that the clock has not drifted during the data transmission process, and the hard disk clock is accurate; otherwise, it is determined that the clock has drifted during the data transmission process, the hard disk clock is inaccurate, and correspondingly, the transmitted data signal is also inaccurate.

[0158] In one embodiment, parsing a communication signal to obtain a clock signal and a data signal includes:

[0159] The communication signal is parsed to obtain a square wave signal and a data signal, wherein a square wave frequency of the square wave signal and a clock frequency of the hard disk are in a second mapping relationship;

[0160] Determine whether the hard disk clock is accurate based on the clock signal;

[0161] Determines whether the hard disk clock is accurate based on the square wave signal.

[0162] In this embodiment, a square wave signal corresponding to the clock signal is regenerated, encoded with the data signal, and transmitted together to the baseboard management controller end (the combination of the square wave and the data signal is shown in Figure 4, the data signal includes a start flag indicating the start of data transmission, an end flag indicating the end of data transmission, and the data to be transmitted (including multiple data bits). The square wave signal can be inserted before the first data bit and after the last data bit of the data to be transmitted).

[0163] After receiving the communication signal, the BMC analyzes it in the following steps: It parses the received communication signal and separates it into a square wave signal and a data signal. This process allows the BMC to obtain the encoded clock and data signals. Based on the parsed square wave signal, the BMC determines whether the hard drive's clock is accurate. By analyzing the frequency and characteristics of the square wave signal, the BMC assesses the hard drive's clock accuracy and promptly corrects any clock errors or drift, ensuring accurate and stable data transmission.

[0164] In this embodiment, the shape of the square wave signal is shown in Figure 5. Since the square wave signal is a signal with obvious high and low level changes, it is easy to parse in the baseboard management controller. It can restore the clock signal by detecting the frequency and characteristics of the square wave signal, thereby ensuring the accuracy of the clock information. In addition, compared with other signal encoding methods, the frequency of the square wave signal changes relatively quickly, and it can transmit information of multiple clock cycles in a shorter time, thereby improving data transmission efficiency and effectively saving communication bandwidth. Furthermore, due to the obvious high and low level changes of the square wave signal, it can better resist the influence of noise and interference, reduce the bit error rate, and improve the reliability of data transmission.

[0165] In one embodiment, determining whether the hard disk clock is accurate based on the square wave signal includes:

[0166] Determine whether the frequency difference between the two square wave signals is within a preset frequency range;

[0167] If the frequency difference is within the preset frequency range, the hard drive clock is determined to be accurate;

[0168] If the frequency difference is not within the preset frequency range, it is determined that the hard disk clock is inaccurate.

[0169] This embodiment describes the specific steps for a baseboard management controller (BMC) to parse a communication signal and the conditions for determining the hard drive clock accuracy. First, the BMC parses the communication signal to obtain at least two square wave signals and a first pulse width signal. The BMC needs to parse the communication signal and extract the square wave signal and pulse width signal contained therein for subsequent clock accuracy determination. Second, the BMC needs to determine whether the frequency difference between the two square wave signals is within a preset frequency range. This step is to determine whether the hard drive clock frequency is stable. By comparing the frequency difference of the square wave signals, it can determine whether the hard drive clock frequency is within the expected range. Finally, if the frequency difference is within the preset frequency range, the BMC determines that the hard drive clock is accurate. If the frequency difference is not within the preset frequency range, the BMC determines that the hard drive clock is inaccurate. This step makes the final clock accuracy determination based on the previous frequency difference determination results. If the frequency difference is within the preset range, the hard drive clock is considered accurate; otherwise, it is considered inaccurate.

[0170] Furthermore, after the baseboard management controller parses the square wave signal, the methods for determining whether the hard disk clock is accurate based on the square wave signal may include the following: first, comparing the square wave frequency of the parsed square wave signal with a square wave reference frequency pre-stored in the baseboard management controller to determine whether the difference between the two is within a preset range; second, determining the clock frequency based on the square wave frequency of the parsed square wave signal and a second mapping relationship, comparing the clock frequency with a clock reference frequency pre-stored in the baseboard management controller to determine whether the difference between the two is within a preset range; third, parsing at least two square wave signals, determining the square wave frequencies of the two square wave signals, determining whether the difference between the two square wave frequencies is within a preset range, and determining whether the clock drift occurs in the time period between the two square wave signals; fourth, parsing at least two square wave signals, determining the square wave frequencies of the two square wave signals, determining two clock frequencies based on the square wave frequencies of the parsed square wave signals and the second mapping relationship, and determining whether the difference between the two clock frequencies is within a preset range, and determining whether the clock drift occurs in the time period between the two square wave signals.

[0171] In summary, this embodiment describes how a baseboard management controller (BMC) analyzes square wave signals within communication signals to assess the hard drive's clock accuracy and make judgments based on pre-set standards. This design effectively monitors and maintains the hard drive's clock status, ensuring proper system operation and reliable data transmission.

[0172] In one embodiment, it further includes:

[0173] When it is determined that the hard disk clock is inaccurate, a feedback signal is sent to the hard disk and / or hard disk controller via the hard disk status pin, so that the hard disk retransmits the data signal or communication signal.

[0174] In this embodiment, when the hard drive clock is determined to be inaccurate, the baseboard management controller sends a feedback signal to the hard drive via the hard drive status pin to trigger the hard drive to retransmit the data signal or communication signal. Since there is only a single-line connection between the hard drive and the baseboard management controller, a strict agreement on the data transmission time is required to ensure the accuracy and timeliness of communication. One method of agreeing on time is to pre-set a time window in the system, within which the hard drive sends the data signal or communication signal. After receiving the data signal or communication signal, the baseboard management controller sends a feedback signal within the preset time window. Through this agreed-on time method, the hard drive and the baseboard management controller can communicate within the agreed time, ensuring the accuracy and timeliness of data transmission. This method can effectively improve the reliability and stability of data transmission and ensure the normal operation of the system.

[0175] Furthermore, in one embodiment, after the baseboard management controller determines that the hard disk clock is inaccurate, it also includes: generating an error report and feeding it back to the hard disk controller, so that the hard disk controller switches the hard disk or adjusts the hard disk clock source based on the error report.

[0176] Specifically, after the baseboard management controller determines that the hard disk clock is inaccurate, it will also generate a detailed error report, which may include the specific clock deviation value and time, etc. This error report will be promptly fed back to the hard disk controller for reference.

[0177] The hard disk controller can choose to switch hard disks based on the information in the error report, such as switching to a spare hard disk, to ensure data security and reliability; specifically, before switching hard disks, it is necessary to first completely back up the data on the current hard disk to the spare hard disk, then connect the spare hard disk to the baseboard management controller, and re-transmit the data signal.

[0178] The hard drive controller can also adjust the hard drive's clock source based on the information in the error report, such as by changing the hard drive's clock source control parameters or synchronizing the hard drive's internal clock with an external clock signal. Adjusting the clock source when the clock is inaccurate ensures proper hard drive operation and prevents data loss or corruption, effectively improving the hard drive's stability and reliability.

[0179] In a second aspect, as shown in FIG6 , the present application further provides a clock detection method, which is applied to a hard disk, and single-line communication between the hard disk and the baseboard management controller. The clock detection method includes:

[0180] S21: Encode its own clock signal and data signal to obtain a communication signal. The data signal is a signal modulated by the hard disk according to the hard disk log data and the hard disk status signal corresponding to the hard disk status pin;

[0181] In the hard drive, the first step is to obtain the drive's clock signal and data signal. The clock signal corresponds to the clock source within the hard drive, used to synchronize data transmission and processing. The data signal is modulated based on the hard drive's log data and the hard drive status signal corresponding to the hard drive status pin. It contains the hard drive status information and the data content corresponding to the current log. The clock and data signals are then encoded. The purpose of encoding is to convert the original clock and data signals into communication signals suitable for transmission over a single-wire transmission channel.

[0182] Specifically, the clock and data signals need to be encoded before transmission because, in single-wire communication, clock calibration cannot be performed between the transmitter and receiver (that is, between the hard drive's hard drive status pin and the baseboard management controller), making it impossible to determine whether the data signal is transmitted based on the correct clock. By encoding the clock and data signals, they can be combined into a single communication signal for transmission. The baseboard management controller can then parse this communication signal to obtain the clock and data signals and, based on the clock signal, determine whether the hard drive's clock is accurate. This allows clock signal detection in single-wire communication, ensuring the accuracy of data transmission.

[0183] S22: Sending the communication signal to the baseboard management controller through the hard disk status pin, so that the baseboard management controller analyzes the communication signal to obtain a clock signal and a data signal, and determines whether the hard disk clock is accurate based on the clock signal.

[0184] Specifically, at the baseboard management controller end, after receiving the communication signal, the communication signal is parsed to obtain the clock signal and data signal, and then the hard disk clock is judged based on the clock signal to determine whether the hard disk clock is accurate. If the hard disk clock is accurate, the data signal transmitted by the hard disk is also determined to be accurate, otherwise the data signal transmitted by the hard disk is determined to be inaccurate.

[0185] In summary, the clock detection method of the present application can realize the transmission of hard disk log data, hard disk status signal and clock signal through the hard disk status pin, and can calibrate the hard disk clock by encoding the clock signal and data signal, and parsing the communication signal, and then determine whether the data signal is based on the correct clock transmission, so as to detect problems in time and ensure the accuracy of data signal transmission.

[0186] In one embodiment, the data signal includes data to be transmitted and a flag signal of a fixed pulse width. The flag signal is used to indicate the current transmission progress of the data signal. The communication signal is obtained by encoding its own clock signal and data signal, including:

[0187] Encode its current clock frequency into the flag signal;

[0188] Integrate the flag signal and the data to be transmitted to obtain a communication signal;

[0189] The baseboard management controller analyzes the communication signal to obtain the clock signal and data signal, and determines whether the hard disk clock is accurate based on the clock signal, including:

[0190] The baseboard management controller analyzes the communication signal to obtain at least two flag signals and data to be transmitted;

[0191] The accuracy of the hard disk clock is determined based on the pulse width corresponding to the two flag signals.

[0192] This embodiment further describes in detail the composition and processing method of the data signal, as well as the analysis and clock accuracy judgment method of the communication signal by the baseboard management controller. Specifically, when transmitting a data signal, along with the valid data to be transmitted, several flag signals are usually transmitted together with the data to be transmitted, such as a flag signal that indicates the start of data transmission, a flag signal that indicates the end of data transmission, a data check bit, etc., which are interspersed in the transmission process of the data to be transmitted. These flag signals are usually assigned a fixed pulse width in the communication protocol. At this time, the present application uses these fixed pulse width flag signals to carry the clock signal to achieve the function of transmitting both the data to be transmitted and the clock signal during the single-line communication process.

[0193] As shown in Figure 3, the data signal indicates the start flag bit that indicates the start of data transmission and the end flag bit that indicates the end of data transmission. Between the start flag bit and the end flag bit is the data to be transmitted (including multiple data bits). The start flag bit and the end flag bit can be used to encode the clock signal.

[0194] Specifically, if the data signal in the present application includes data to be transmitted and a flag signal of a fixed pulse width, a communication signal containing a clock frequency, a flag signal and data to be transmitted can be generated by encoding its own clock signal and the flag signal in the data signal. Encoding the current clock frequency into the flag signal can ensure that the clock information can be synchronized during the data transmission process. The flag signal and the data to be transmitted are integrated to form a complete communication signal so that it can be transmitted to the baseboard management controller on a single-line transmission channel. The baseboard management controller parses the received communication signal, obtains at least two flag signals and the data to be transmitted, and determines whether the hard disk clock is accurate based on the pulse width corresponding to the two flag signals. By comparing the changes in the pulse width, the accuracy of the hard disk clock can be evaluated, thereby ensuring the correctness and reliability of data transmission.

[0195] In other words, the present application multiplexes a flag signal, which is used not only to indicate the progress of data transmission or for verification purposes, but also to determine the accuracy of the clock. Specifically, the flag signal should have a fixed pulse width when the clock is normal. If the pulse width changes, and the degree of change is greater than a threshold, the hard drive clock is considered inaccurate. If the pulse width remains unchanged, or the degree of change is within the threshold, the hard drive clock is considered accurate.

[0196] Compared to generating the clock signal separately, encoding the clock signal and the flag signal can not only more accurately evaluate the accuracy of the hard disk clock, which helps to promptly detect and correct clock inaccuracies, but also simplify the system design, so that more information can be transmitted within a limited channel under single-line communication mode, reducing the need for additional lines and lowering system complexity and cost.

[0197] In one embodiment, the hard disk status pin outputs a control signal of a first level when the hard disk is in a preset state; and encodes its own clock signal and data signal to obtain a communication signal, including:

[0198] Inserting a plurality of pulse signals of a second level with a preset width into the control signal to divide the control signal using the pulse signals to obtain pulse widths of the first level corresponding to respective data bits, wherein the data signal includes a plurality of data bits and the second level is opposite to the first level;

[0199] The clock signal thereof is encoded with a plurality of second-level pulse signals and a plurality of first-level pulse widths to obtain a communication signal.

[0200] Specifically, when the hard disk status pin outputs a first-level control signal when the hard disk is in a preset state, the hard disk modulates the hard disk status signal and hard disk status data to obtain the first signal. The process may include: in the preset state, inserting a plurality of second-level pulse signals of preset width into the control signal, so as to divide the control signal using the pulse signals to obtain a first-level pulse width corresponding to each data bit, wherein the data signal includes multiple data bits and the second level is opposite to the first level. That is, by inserting a second-level pulse signal of opposite width into a constant first level to obtain a plurality of first-level pulse width signals, the hard disk log data is modulated.

[0201] In this case, its own clock signal can be encoded with multiple second-level pulse signals and multiple first-level pulse widths to obtain a communication signal. This communication signal not only includes the clock signal, but also the hard disk log data and the corresponding hard disk status data, ensuring the accurate transmission of the clock signal and data signal, and the transmission of the hard disk status signal, hard disk log data and clock signal can be realized through the hard disk status pin.

[0202] Similarly, the process of the baseboard management controller parsing the communication signal includes: parsing the hard disk clock signal and multiple second-level pulse signals and multiple first-level pulse widths from the communication signal, and judging the hard disk clock based on the clock signal.

[0203] In addition, the preset state can also be the hard disk in-place state or out-of-place state, and this method can also be used when the first level signal is continuously output in the preset state. Since the implementation method is the same, this application will not elaborate on it here.

[0204] In summary, in this embodiment, the hard disk status pin of the hard disk is utilized to realize the transmission of the hard disk status signal and the hard disk log data through modulation at the hard disk end, so that the baseboard management controller can monitor the hard disk by parsing the hard disk log data according to the data signal; further, the clock signal is modulated into the pulse signal in the hard disk log data, and the clock signal is parsed without using a clock line, so that the baseboard management controller can determine whether the hard disk clock is accurate according to the clock signal.

[0205] In one embodiment, encoding the clock signal thereof with a plurality of second-level pulse signals and a plurality of first-level pulse widths to obtain a communication signal includes:

[0206] Encoding its current clock frequency into a pulse signal of a second level with a preset width, wherein a first mapping relationship exists between the clock frequency and the preset width, and the communication signal includes a plurality of pulse signals of the second level with the preset width and a plurality of pulse widths of the first level;

[0207] The baseboard management controller analyzes the communication signal to obtain the clock signal and data signal, and determines whether the hard disk clock is accurate based on the clock signal, including:

[0208] The baseboard management controller analyzes the communication signal to obtain at least two second-level pulse signals and a plurality of first-level pulse widths;

[0209] Determining whether a width difference between two second-level pulse signals is within an error range;

[0210] If it is within the error range, the hard disk clock is determined to be accurate;

[0211] If it is not within the error range, it is determined that the hard disk clock is inaccurate.

[0212] In this embodiment, the flag signal with a fixed pulse width is a pulse signal of a second level with a preset width. Encoding the clock signal and the data signal is to encode the clock signal with this pulse signal. That is, the clock signal is transmitted using this pulse signal. Specifically, a pulse signal of a second level with a preset width is used as a segmentation signal to obtain a pulse width of the first level corresponding to each data bit. When the hard disk clock is accurate, the width of each pulse signal output by the hard disk should be the preset width, or within the range of the preset width. If the hard disk clock is inaccurate, the width of each pulse signal output will deviate from the range of the preset width.

[0213] Therefore, the steps for the baseboard management controller to determine whether the hard disk clock is accurate based on the clock signal may include: first parsing the communication signal to obtain at least two second-level pulse signals, and judging whether the corresponding pulse width is within the error range based on the two pulse signals; if it is within the error range, it is determined that the clock has not drifted during the data transmission process, and the hard disk clock is accurate; otherwise, it is determined that the clock has drifted during the data transmission process, the hard disk clock is inaccurate, and correspondingly, the transmitted data signal is also inaccurate.

[0214] In summary, this application provides a specific implementation method for transmitting hard disk log data using the hard disk status pin of the hard disk. This method can realize the transmission of hard disk log data using the original pins of the hard disk, and then the baseboard management controller can monitor the hard disk based on this hard disk log data. Furthermore, this application also utilizes the modulation of the hard disk log data and the hard disk status signal and incorporates the clock signal. Therefore, the hard disk status pin of the hard disk can realize both the transmission of hard disk log data and the judgment of the clock, thereby improving the accuracy of the transmitted hard disk log data.

[0215] In one embodiment, encoding its own clock signal and data signal to obtain a communication signal includes:

[0216] Encoding its current clock frequency into a square wave signal, wherein the frequency of the square wave signal and the clock frequency form a second mapping relationship;

[0217] Inserting the square wave signal into the data signal to obtain a communication signal;

[0218] The baseboard management controller analyzes the communication signal to obtain the clock signal and data signal, and determines whether the hard disk clock is accurate based on the clock signal, including:

[0219] The baseboard management controller analyzes the communication signal to obtain a square wave signal and a data signal, and determines whether the hard disk clock is accurate based on the square wave signal.

[0220] In the above embodiment, the clock signal and the existing fixed pulse width flag signal are encoded so that the flag signal carries the clock signal, and then whether the hard disk clock is accurate can be determined based on the flag signal.

[0221] This embodiment aims to provide a specific step of regenerating a square wave signal corresponding to a clock signal, encoding it with a data signal, and transmitting it together to the baseboard management controller end. Specifically, in this embodiment, the specific steps of encoding its own clock signal and data signal to obtain a communication signal include: encoding its own current clock frequency into a square wave signal, and the frequency of the square wave signal and the clock frequency are in a second mapping relationship. This means that the frequency change of the square wave signal and the change of the clock frequency are in a second mapping relationship, so that the clock signal can be accurately restored at the baseboard management controller end based on the square wave signal and the second mapping relationship. The encoded square wave signal is inserted into the data signal, and together with the data signal, it constitutes a complete communication signal; in this way, the clock signal and the data signal are combined and transmitted together, ensuring the synchronization of the clock information and the data information.

[0222] After receiving the communication signal, the BMC analyzes it in the following steps: It parses the received communication signal and separates it into a square wave signal and a data signal. This process allows the BMC to obtain the encoded clock and data signals. Based on the parsed square wave signal, the BMC determines whether the hard drive's clock is accurate. By analyzing the frequency and characteristics of the square wave signal, the BMC assesses the hard drive's clock accuracy and promptly corrects any clock errors or drift, ensuring accurate and stable data transmission.

[0223] In this embodiment, since the square wave signal exhibits significant high and low level variations, it is easily parsed by the baseboard management controller. The baseboard management controller can recover the clock signal by detecting the frequency and characteristics of the square wave signal, thereby ensuring the accuracy of the clock information. Furthermore, compared to other signal encoding methods, the frequency of the square wave signal varies relatively quickly, allowing the transmission of information spanning multiple clock cycles in a relatively short period of time. This improves data transmission efficiency and effectively conserves communication bandwidth. Furthermore, since the square wave signal exhibits significant high and low level variations, it can better resist the effects of noise and interference, reducing bit error rates and improving data transmission reliability.

[0224] Among them, after the baseboard management controller parses the square wave signal, the method of determining whether the hard disk clock is accurate based on the square wave signal may include the following: first, comparing the square wave frequency of the parsed square wave signal with the square wave reference frequency pre-stored in the baseboard management controller to determine whether the difference between the two is within a preset range; second, determining the clock frequency based on the square wave frequency of the parsed square wave signal and the second mapping relationship, comparing the clock frequency with the clock reference frequency pre-stored in the baseboard management controller to determine whether the difference between the two is within a preset range; third, parsing at least two square wave signals, determining the square wave frequencies of the two square wave signals, determining whether the difference between the two square wave frequencies is within a preset range, and determining whether the clock drift occurs in the time period between the two square wave signals; fourth, parsing at least two square wave signals, determining the square wave frequencies of the two square wave signals, determining two clock frequencies based on the square wave frequencies of the parsed square wave signals and the second mapping relationship, and determining whether the difference between the two clock frequencies is within a preset range, and determining whether the clock drift occurs in the time period between the two square wave signals.

[0225] The square wave reference frequency may be set to a preset multiple of the single-wire communication protocol rate, such as f=100×F, where f is the square wave reference frequency and F is the single-wire communication protocol rate.

[0226] The above are just several methods provided in this embodiment to determine whether the hard disk clock is accurate based on the square wave signal, and the implementation is not limited to these.

[0227] In one embodiment, encoding its own clock signal and data signal to obtain a communication signal includes:

[0228] Encoding its current clock frequency into a square wave signal, wherein the frequency of the square wave signal and the clock frequency form a second mapping relationship;

[0229] Encoding each data bit into a pulse width corresponding to the data bit one by one to obtain a first pulse width signal, wherein the data signal includes multiple data bits, and the first pulse width signal includes pulse widths corresponding to the multiple data bits;

[0230] Encoding the square wave signal and the first pulse width signal to obtain a communication signal;

[0231] The baseboard management controller analyzes the communication signal to obtain the clock signal and data signal, and determines whether the hard disk clock is accurate based on the clock signal, including:

[0232] The baseboard management controller analyzes the communication signal to obtain a square wave signal and a first pulse width signal, and determines whether the hard disk clock is accurate based on the square wave signal.

[0233] This embodiment provides a specific implementation method for encoding the clock signal and data signal of the hard disk to obtain a communication signal. Specifically, the data signal is a signal obtained by modulating the hard disk log data and the hard disk status signal, while the clock signal is encoded as a square wave signal. The frequency of the square wave signal and the clock frequency have a second mapping relationship. This encoding method helps to retain the clock frequency information during the transmission process, so that the baseboard management controller can restore the accurate clock signal. The communication signal is sent to the baseboard management controller through the hard disk status pin, so that the baseboard management controller parses the communication signal to obtain the clock signal and data signal, and determines whether the hard disk clock is accurate based on the clock signal.

[0234] Furthermore, the data signal is encoded as follows: each data bit is encoded into a pulse width corresponding to the data bit, and a first pulse width signal is obtained; wherein, the data signal includes multiple data bits, and the first pulse width signal includes pulse widths corresponding to the multiple data bits; such an encoding method can effectively convert the data bits into pulse width information, which is convenient for parsing and identifying during the transmission process. Then the square wave signal and the data signal are encoded as follows: the square wave signal and the first pulse width signal are encoded to obtain a final communication signal. This step integrates the clock signal and the data signal into a unified communication signal for transmission on a single-line transmission channel. The baseboard management controller parses the received communication signal to obtain a square wave signal and a first pulse width signal, and judges whether the hard disk clock is accurate based on the square wave signal (and / or parses the data signal based on the first pulse width signal). Through parsing and judging, the baseboard management controller can accurately evaluate the accuracy of the hard disk clock, thereby ensuring the reliability and accuracy of data transmission.

[0235] In summary, this embodiment determines the accuracy of the hard drive's clock by encoding the hard drive's clock and data signals and parsing them at the receiving end. This solves the problem of clock calibration being impossible in single-wire communication. Furthermore, this method can be effectively applied to single-wire connections between hard drives and baseboard management controllers, improving communication reliability and accuracy.

[0236] In one embodiment, encoding the square wave signal and the first pulse width signal to obtain a communication signal includes:

[0237] At least two square wave signals are respectively inserted before the pulse width corresponding to the first data bit and / or after the pulse width corresponding to the last data bit and / or between the pulse widths corresponding to any two data bits to obtain a communication signal.

[0238] In this embodiment, when encoding the square wave signal and the first pulse width signal to obtain a communication signal, at least two square wave signals are specifically inserted into specific positions in the communication signal, such as before the pulse width corresponding to the first data bit, after the pulse width corresponding to the last data bit, and between the pulse widths corresponding to any two data bits.

[0239] The square wave signal is combined with the first pulse width signal to form an optimized communication signal structure. The optimized communication signal not only contains the original square wave signal and the first pulse width signal information, but also contains the additional inserted square wave signal, making the transmitted data richer and more complete.

[0240] As shown in Figure 4, the data signal includes a start flag indicating the start of data transmission, an end flag indicating the end of data transmission, and the data to be transmitted (including multiple data bits). A square wave signal can be inserted before the first data bit and after the last data bit of the data to be transmitted. By determining whether the square wave signal drifts, the accuracy of the clock signal throughout the entire transmission process of the data to be transmitted can be determined. The shape of the square wave signal is shown in Figure 5.

[0241] After receiving the communication signal, the baseboard management controller effectively analyzes the square wave signal and the first pulse width signal and uses this information to determine the hard drive clock accuracy. This allows the baseboard management controller to more accurately assess the hard drive clock accuracy, thereby improving the overall stability and reliability of the system.

[0242] In a preferred embodiment, the time interval between the insertion positions of the two square wave signals is not less than a preset time interval, or the number of data bits between the insertion positions of the two square wave signals is not less than a preset number, so as to facilitate the determination of whether the clock signal drifts in the time period between the two square wave signals.

[0243] In summary, this embodiment further improves the encoding and parsing process of the communication signal in the hard disk clock detection method, improves the system's ability to evaluate clock accuracy, and also enhances the reliability and stability of data transmission.

[0244] In one embodiment, encoding each data bit into a pulse width corresponding to the data bit to obtain a first pulse width signal includes:

[0245] Each data bit is encoded into a pulse width with a duty cycle corresponding to the data bit one by one to obtain a first pulse width signal, and a third mapping relationship is formed between the duty cycle and the data bit.

[0246] The present embodiment describes the step of encoding each data bit into a pulse width corresponding to a data bit. Specifically, if each data bit is digitized into hexadecimal, 16 different pulse widths are set, which can correspond to 16 digits in the hexadecimal systems such as 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F. Then, each hexadecimal encoding is corresponding to the pulse width of a specific duty cycle, i.e., 0 corresponds to the pulse width of a specific duty cycle, 1 corresponds to another duty cycle pulse width, and so on (the pulse width of different duty cycles corresponds to different data bits in hexadecimal), and the combination of all pulse widths is the first pulse width signal. By the above encoding step, it is achieved that each data bit is encoded into a pulse width signal corresponding to a data bit, and the transmission of data is achieved by the change of duty cycle. The baseboard management controller end can obtain corresponding data bits by resolving duty cycle, and then can obtain hard disk log data, realizes the monitoring of hard disk.

[0247] For example, the hard disk status pin is the indicator light pin of the hard disk. When it is in a non-preset state and outputs an indication signal to make the indicator light flash, the encoding method in this embodiment can be used. This encoding method still presents a pulse width signal with a duty cycle, thereby also realizing the function of making the indicator light flash.

[0248] In summary, in this application, through this encoding method, the hard disk log data and hard disk status signal can be encoded and output to the baseboard management controller through the hard disk status pin, so that the baseboard management controller can parse the data and obtain the hard disk log data and hard disk status signal through the hard disk status pin.

[0249] In one embodiment, encoding each data bit into a pulse width corresponding to the data bit to obtain a first pulse width signal includes:

[0250] Each data bit is encoded into a pulse width of a preset level corresponding to the data bit to obtain a first pulse width signal, and a fourth mapping relationship exists between the pulse width of the preset level and the data bit.

[0251] Specifically, in this embodiment, each data bit is encoded into a pulse width of a preset level corresponding to the data bit, thereby obtaining a first pulse width signal. Specific steps may include: first determining the number of data bits to be encoded, for example, by converting each data bit of the hard disk log data into hexadecimal, i.e., setting 16 different pulse widths corresponding to the sixteen hexadecimal digits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F. For example, in a rectangular wave signal with a period of 100 milliseconds, the pulse width can be designed to be 42 milliseconds to 49 milliseconds and 51 milliseconds to 58 milliseconds, and every 1 millisecond corresponds to a hexadecimal data, that is, a total of 16 pulse widths correspond to the sixteen digits in hexadecimal; according to specific needs, the pulse width encoding method corresponding to each data bit is determined, and each data bit is encoded one by one. It can be a method in which high-level or low-level pulse width signals appear alternately, for example, data 0 is encoded as a high level of the first width, data 1 is encoded as a low level of the second width, and so on; each encoded data bit is combined to form a complete pulse width signal for subsequent transmission or processing.

[0252] Alternatively, all data bits may be encoded as high levels of corresponding widths or low levels of corresponding widths, and the data bits may be spaced by inserting opposite levels between two adjacent data bits; for example, 0 is encoded as the first pulse width, 1 is encoded as the second pulse width, 2 is encoded as the third pulse width, and 3 is encoded as the fourth pulse width. If the first to fourth pulse widths are high levels, a low level of a certain width is inserted between the two adjacent data bits (to space the two data bits); if the first to fourth pulse widths are low levels, a high level of a certain width is inserted between the two adjacent data bits (to space the two data bits). The combination of data bits is not limited to the above, and the encoding method is not limited to the above examples.

[0253] For example, if the hard drive status pin is used as the hard drive indicator pin and outputs an indication signal to flash the indicator in a non-preset state, the encoding method of this embodiment can be used. This encoding method still presents a pulse width signal composed of a combination of high and low levels, thereby also achieving the function of flashing the indicator. In this case, the square wave reference frequency is set to f = 1 / |t1-t2|, where t1 and t2 are the pulse widths of two adjacent data bits, and f is the square wave reference frequency.

[0254] In summary, through the above encoding steps, each data bit can be encoded into a corresponding pulse width signal to achieve data transmission and processing.

[0255] In one embodiment, it further includes:

[0256] After the baseboard management controller determines that the clock of the hard disk is inaccurate, receiving a feedback signal sent by the baseboard management controller;

[0257] The data signal or the communication signal is resent based on the feedback signal.

[0258] In this embodiment, if the baseboard management controller determines that the hard drive clock is inaccurate, it sends a feedback signal. Then, based on this feedback signal, it resends the data signal or communication signal. This process ensures that the hard drive clock is calibrated in a timely manner, thereby ensuring the accuracy and stability of data transmission. In this example, the baseboard management controller plays a vital role by promptly detecting the accuracy of the hard drive clock and issuing the corresponding feedback signal. After receiving the feedback signal, the system can resend the data signal or communication signal as appropriate to ensure the accuracy of the hard drive clock. This way, even if the hard drive clock deviates, the baseboard management controller can promptly calibrate and correct it, ensuring the accuracy and stability of data transmission.

[0259] Because the hard drive and baseboard management controller (BMC) are connected via a single cable, the data transmission time can be pre-arranged, and the BMC will send a feedback signal within the preset time. One method for pre-arranging the time is to pre-set a time window in the system within which the hard drive sends data or communication signals. After receiving the data or communication signal, the BMC sends a feedback signal within the preset time window. This allows the hard drive and BMC to communicate within the agreed timeframe, ensuring accurate and timely data transmission.

[0260] In summary, the method of this embodiment can effectively ensure the accuracy of the hard disk clock and the stability of data transmission.

[0261] In a specific embodiment, the process at the sending end (hard disk end) is shown in FIG7 :

[0262] S71: Start; S72: Send communication request; S73: Send clock signal; S74: Send data signal; S75: Send clock signal; S76: Send data end mark; S77: Wait for the verification pass signal fed back by the baseboard management controller; S78: Whether the verification pass signal is received; if so, enter S710, otherwise enter S79; S79: Resend the data signal; S710: End.

[0263] The process at the receiving end (baseboard management controller end) is shown in Figure 8:

[0264] S81: Start; S82: Detect communication request signal; S83: Record clock signal; S84: Receive data signal and perform data analysis; S85: Record clock signal; S86: Receive data end mark; S87: Compare the error between the two clock signals; S88: Is the error within the preset range? If so, enter S89, otherwise enter S810; S89: Send verification pass signal; S810: Send verification fail signal.

[0265] In a third aspect, the present application further provides a clock detection system, as shown in FIG9 , wherein a single-line communication is performed between the hard disk and the baseboard management controller. The clock detection system includes:

[0266] The encoding unit 91 is used to encode its own clock signal and data signal to obtain a communication signal. The data signal is a signal modulated by the hard disk based on the hard disk log data and the hard disk status signal corresponding to the hard disk status pin;

[0267] The sending unit 92 is used to send the communication signal to the baseboard management controller through the hard disk status pin, so that the baseboard management controller analyzes the communication signal, obtains the clock signal and the data signal, and determines whether the hard disk clock is accurate based on the clock signal.

[0268] In one embodiment, the data signal includes data to be transmitted and a flag signal with a fixed pulse width, and the flag signal is used to indicate the current transmission progress of the data signal. The encoding unit 91 includes:

[0269] A first encoding unit, configured to encode its current clock frequency into a flag signal;

[0270] An integration unit, used for integrating the flag signal and the data to be transmitted to obtain a communication signal;

[0271] The baseboard management controller analyzes the communication signal to obtain the clock signal and data signal, and determines whether the hard disk clock is accurate based on the clock signal, including:

[0272] The baseboard management controller analyzes the communication signal to obtain at least two flag signals and data to be transmitted;

[0273] The accuracy of the hard disk clock is determined based on the pulse width corresponding to the two flag signals.

[0274] In one embodiment, the hard disk status pin outputs a control signal of a first level when the hard disk is in a preset state; the encoding unit 91 includes:

[0275] a pulse inserting unit, configured to insert a plurality of pulse signals of a second level with a preset width into the control signal, so as to divide the control signal using the pulse signals to obtain pulse widths of the first level corresponding to respective data bits, wherein the data signal includes a plurality of data bits, and the second level is opposite to the first level;

[0276] The second encoding unit is used to encode its own clock signal, a plurality of second-level pulse signals, and a plurality of first-level pulse widths to obtain a communication signal.

[0277] In one embodiment, the second encoding unit is specifically configured to encode its current clock frequency into a pulse signal of a second level with a preset width, wherein the clock frequency and the preset width are in a first mapping relationship, and the communication signal includes a plurality of pulse signals of the second level with a preset width and a plurality of pulse widths of the first level;

[0278] The baseboard management controller analyzes the communication signal to obtain the clock signal and data signal, and determines whether the hard disk clock is accurate based on the clock signal, including:

[0279] The baseboard management controller analyzes the communication signal to obtain at least two second-level pulse signals and a plurality of first-level pulse widths;

[0280] Determining whether a width difference between two second-level pulse signals is within an error range;

[0281] If it is within the error range, the hard disk clock is determined to be accurate;

[0282] If it is not within the error range, it is determined that the hard disk clock is inaccurate.

[0283] In one embodiment, the encoding unit 91 includes:

[0284] A third encoding unit is configured to encode its current clock frequency into a square wave signal, wherein the frequency of the square wave signal and the clock frequency are in a second mapping relationship;

[0285] A square wave insertion unit, used for inserting a square wave signal into a data signal to obtain a communication signal;

[0286] The baseboard management controller analyzes the communication signal to obtain the clock signal and data signal, and determines whether the hard disk clock is accurate based on the clock signal, including:

[0287] The baseboard management controller analyzes the communication signal to obtain a square wave signal and a data signal, and determines whether the hard disk clock is accurate based on the square wave signal.

[0288] In one embodiment, the encoding unit 91 includes:

[0289] A third encoding unit is configured to encode its current clock frequency into a square wave signal, wherein the frequency of the square wave signal and the clock frequency are in a second mapping relationship;

[0290] a fourth encoding unit, configured to encode each data bit into a pulse width corresponding to the data bit one by one, to obtain a first pulse width signal, wherein the data signal includes a plurality of data bits, and the first pulse width signal includes pulse widths corresponding to the plurality of data bits;

[0291] a fifth encoding unit, configured to encode the square wave signal and the first pulse width signal to obtain a communication signal;

[0292] The baseboard management controller analyzes the communication signal to obtain the clock signal and data signal, and determines whether the hard disk clock is accurate based on the clock signal, including:

[0293] The baseboard management controller analyzes the communication signal to obtain a square wave signal and a first pulse width signal, and determines whether the hard disk clock is accurate based on the square wave signal.

[0294] In one embodiment, the fifth encoding unit is specifically used to insert at least two square wave signals before the pulse width corresponding to the first data bit and / or after the pulse width corresponding to the last data bit and / or between the pulse widths corresponding to any two data bits to obtain a communication signal.

[0295] In one embodiment, the fourth encoding unit is specifically configured to encode each data bit into a pulse width with a duty cycle corresponding to the data bit one by one to obtain a first pulse width signal, and a third mapping relationship exists between the duty cycle and the data bit.

[0296] In one embodiment, the fourth encoding unit is specifically configured to encode each data bit into a pulse width of a preset level corresponding to the data bit to obtain a first pulse width signal, and a fourth mapping relationship exists between the pulse width of the preset level and the data bit.

[0297] In one embodiment, it further includes:

[0298] A feedback unit, configured to receive a feedback signal sent by the baseboard management controller after the baseboard management controller determines that the clock of the hard disk is inaccurate;

[0299] The data signal or the communication signal is resent based on the feedback signal.

[0300] For an introduction to the clock detection system, please refer to the above embodiments, which will not be described in detail in this application.

[0301] In a fourth aspect, the present application further provides a clock detection system, as shown in FIG10 , which is applied to a baseboard management controller, wherein the baseboard management controller communicates with the hard disk via a single line. The clock detection system includes:

[0302] The receiving unit 101 is used to receive the communication signal sent by the hard disk through the hard disk status pin. The communication signal is a signal obtained by the hard disk according to the data signal and its own clock signal encoding;

[0303] The parsing unit 102 is used to parse the communication signal to obtain a clock signal and a data signal;

[0304] The judgment unit 103 is configured to judge whether the hard disk clock is accurate based on the clock signal.

[0305] In one embodiment, the parsing unit 102 is specifically configured to parse the communication signal to obtain at least two flag signals and data to be transmitted; the data signal includes the data to be transmitted and a flag signal with a fixed pulse width, the flag signal is used to represent the current transmission progress of the data signal, and the hard disk encodes its current clock frequency into the flag signal;

[0306] The judgment unit 103 is specifically configured to judge whether the hard disk clock is accurate according to the pulse widths corresponding to the two flag signals.

[0307] In one embodiment, the judgment unit 103 is specifically used to judge whether the pulse widths corresponding to the two flag signals are within a preset range of the standard pulse width, or whether the difference between the pulse widths corresponding to the two flag signals is within an error range; if the pulse widths corresponding to the two flag signals are within the preset range of the standard pulse width, or the difference is within the error range, it is determined that the hard disk clock is accurate; if the pulse widths corresponding to the two flag signals are not within the preset range of the standard pulse width, or the difference is not within the error range, it is determined that the hard disk clock is inaccurate.

[0308] In one embodiment, the hard disk status pin outputs a control signal of a first level when the hard disk is in a preset state, inserts a plurality of pulse signals of a second level with a preset width into the control signal, and uses the pulse signals to divide the control signal to obtain a pulse width of the first level corresponding to each data bit, encodes the current clock frequency of the hard disk into a pulse signal of the second level with a preset width, and obtains a communication signal based on the pulse signal of the second level with the preset width and the plurality of pulse widths of the first level, wherein the data signal includes a plurality of data bits, and the second level is opposite to the first level;

[0309] The analyzing unit 102 is specifically configured to analyze the communication signal to obtain at least two second-level pulse signals and a plurality of first-level pulse widths;

[0310] The judging unit 103 is specifically configured to judge whether the clock of the hard disk is accurate based on at least two pulse signals of the second level.

[0311] In one embodiment, the judgment unit 103 is specifically used to judge whether the width difference between the two second-level pulse signals is within an error range; if it is within the error range, it is determined that the hard disk clock is accurate; if it is not within the error range, it is determined that the hard disk clock is inaccurate.

[0312] In one embodiment, the parsing unit 102 is specifically configured to parse the communication signal to obtain a square wave signal and a data signal, wherein a square wave frequency of the square wave signal and a clock frequency of the hard disk are in a second mapping relationship;

[0313] The judgment unit 103 is specifically configured to judge whether the hard disk clock is accurate based on the square wave signal.

[0314] In one embodiment, the judgment unit 103 is specifically used to determine whether the frequency difference between the two square wave signals is within a preset frequency range; if the frequency difference is within the preset frequency range, it is determined that the hard disk clock is accurate; if the frequency difference is not within the preset frequency range, it is determined that the hard disk clock is inaccurate.

[0315] In one embodiment, it further includes:

[0316] The feedback sending unit is used to send a feedback signal to the hard disk through the hard disk status pin when it is determined that the hard disk clock is inaccurate, so as to trigger the hard disk to retransmit the data signal or communication signal.

[0317] For an introduction to the clock detection system, please refer to the above embodiments, which will not be described in detail in this application.

[0318] In a fifth aspect, the present application further provides an electronic device, as shown in FIG11 , comprising:

[0319] Memory 111, for storing computer-readable instructions;

[0320] The processor 112 is configured to implement the steps of the above-mentioned clock detection method when executing computer-readable instructions.

[0321] For an introduction to the electronic device, please refer to the above embodiments, and this application will not go into details here.

[0322] In a sixth aspect, the present application also provides one or more non-volatile computer-readable storage media storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, the one or more processors implement the steps of the clock detection method as described above.

[0323] For an introduction to computer-readable storage media, please refer to the above embodiments, and this application will not go into details here.

[0324] In a seventh aspect, the present application further provides a server, comprising a hard disk and a baseboard management controller, wherein the hard disk and the baseboard management controller are connected by a single line, and there is only one transmission channel between the hard disk and the baseboard management controller via the single line;

[0325] The hard disk is used to implement the steps of the above-mentioned clock detection method applied to the hard disk;

[0326] The baseboard management controller is used to implement the steps of the above-mentioned clock detection method applied to the baseboard management controller.

[0327] For an introduction to the server, please refer to the above embodiment, and this application will not go into details here.

[0328] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0329] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A clock detection method, characterized in that: Applied to a baseboard management controller, wherein the baseboard management controller communicates with a hard disk via a single line, the clock detection method includes: Receive a communication signal sent by the hard disk through the hard disk status pin, wherein the communication signal is a signal obtained by encoding the hard disk according to the data signal and its own clock signal, and the data signal is a signal obtained by modulating the hard disk according to the hard disk log data and the hard disk status signal corresponding to the hard disk status pin; parsing the communication signal to obtain the clock signal and the data signal; and It is determined whether the clock of the hard disk is accurate based on the clock signal.

2. The clock detection method according to claim 1, wherein: Parsing the communication signal to obtain the clock signal and the data signal includes: parsing the communication signal to obtain at least two flag signals and data to be transmitted; the data signal includes the data to be transmitted and a flag signal with a fixed pulse width, the flag signal is used to represent the current transmission progress of the data signal, and the hard disk encodes its current clock frequency into the flag signal; Determining whether the clock of the hard disk is accurate based on the clock signal includes: Whether the clock of the hard disk is accurate is determined according to the pulse widths corresponding to the two flag signals.

3. The clock detection method according to claim 2, wherein: Determining whether the hard disk clock is accurate according to the pulse widths corresponding to the two flag signals includes: Determining whether the pulse widths corresponding to the two flag signals are within a preset range of a standard pulse width, or determining whether a difference between the pulse widths corresponding to the two flag signals is within an error range; In response to the pulse widths corresponding to the two flag signals being within a preset range of the standard pulse width, or the difference being within an error range, determining that the clock of the hard disk is accurate; and In response to the pulse widths corresponding to the two flag signals not being within the preset range of the standard pulse width, or the difference not being within the error range, it is determined that the clock of the hard disk is inaccurate.

4. The clock detection method according to claim 2, wherein: The hard disk status pin outputs a control signal of a first level when the hard disk is in a preset state, inserts a plurality of pulse signals of a second level with a preset width into the control signal, and uses the pulse signals to divide the control signal to obtain a pulse width of the first level corresponding to each data bit, encodes its own current clock frequency into a pulse signal of the second level with the preset width, and obtains the communication signal based on the pulse signal of the second level with the preset width and the plurality of pulse widths of the first level, wherein the data signal includes the plurality of data bits, and the second level is opposite to the first level; Parsing the communication signal to obtain the clock signal and the data signal includes: parsing the communication signal to obtain at least two pulse signals of the second level and a plurality of pulse widths of the first level; Determining whether the clock of the hard disk is accurate based on the clock signal includes: Whether the clock of the hard disk is accurate is determined based on at least two pulse signals of the second level.

5. The clock detection method according to claim 4, wherein: Determining whether the hard disk clock is accurate based on at least two pulse signals of the second level includes: Determining whether a width difference between two pulse signals of the second level is within an error range; In response to being within the error range, determining that the clock of the hard disk is accurate; and In response to the error not being within the error range, it is determined that the clock of the hard disk is inaccurate.

6. The clock detection method according to claim 1, wherein: Parsing the communication signal to obtain the clock signal and the data signal includes: parsing the communication signal to obtain a square wave signal and the data signal, wherein a square wave frequency of the square wave signal and a clock frequency of the hard disk are in a second mapping relationship; Determining whether the clock of the hard disk is accurate based on the clock signal includes: Whether the clock of the hard disk is accurate is determined based on the square wave signal.

7. The clock detection method according to claim 6, wherein: Determining whether the clock of the hard disk is accurate based on the square wave signal includes: Determining whether a frequency difference between the two square wave signals is within a preset frequency range; In response to the frequency difference being within the preset frequency range, determining that the clock of the hard disk is accurate; and In response to the frequency difference not being within the preset frequency range, it is determined that the clock of the hard disk is inaccurate.

8. The clock detection method according to any one of claims 1 to 7, wherein: Also includes: In response to determining that the clock of the hard disk is inaccurate, a feedback signal is sent to the hard disk and / or hard disk controller via the hard disk status pin to enable the hard disk to retransmit the data signal or the communication signal.

9. A clock detection method, characterized in that: Applied to a hard disk, wherein the hard disk communicates with a baseboard management controller via a single line, the clock detection method includes: Encoding its own clock signal and data signal to obtain a communication signal, wherein the data signal is a signal modulated by the hard disk according to the hard disk log data and the hard disk status signal corresponding to the hard disk status pin; and The communication signal is sent to the baseboard management controller through the hard disk status pin, so that the baseboard management controller parses the communication signal to obtain the clock signal and the data signal, and determines whether the hard disk clock is accurate based on the clock signal.

10. The clock detection method according to claim 9, wherein: The data signal includes data to be transmitted and a flag signal of a fixed pulse width, wherein the flag signal is used to indicate the current transmission progress of the data signal. The clock signal and the data signal are encoded to obtain a communication signal, including: Encoding its current clock frequency into the flag signal; and Integrating the flag signal and the data to be transmitted to obtain the communication signal; The baseboard management controller analyzes the communication signal to obtain the clock signal and the data signal, and determines whether the clock of the hard disk is accurate based on the clock signal, including: The baseboard management controller parses the communication signal to obtain at least two of the flag signals and the data to be transmitted; and Whether the clock of the hard disk is accurate is determined according to the pulse widths corresponding to the two flag signals.

11. The clock detection method according to claim 10, wherein: The hard disk status pin outputs a control signal of a first level when the hard disk is in a preset state; and encodes its own clock signal and data signal to obtain a communication signal, including: In the preset state, a plurality of pulse signals of a second level with a preset width are inserted into the control signal, so as to divide the control signal by using the pulse signals to obtain pulse widths of the first level corresponding to respective data bits; the data signal includes the plurality of data bits, and the second level is opposite to the first level; and The communication signal is obtained by encoding its own clock signal, a plurality of pulse signals of the second level, and a plurality of pulse widths of the first level.

12. The clock detection method according to claim 11, wherein: Encoding its own clock signal with a plurality of pulse signals of the second level and a plurality of pulse widths of the first level to obtain the communication signal includes: Encoding its current clock frequency into a pulse signal of a second level of the preset width, wherein a first mapping relationship exists between the clock frequency and the preset width, and the communication signal includes a plurality of pulse signals of the second level of the preset width and a plurality of pulse widths of the first level; The baseboard management controller analyzes the communication signal to obtain the clock signal and the data signal, and determines whether the clock of the hard disk is accurate based on the clock signal, including: The baseboard management controller analyzes the communication signal to obtain at least two pulse signals of the second level and a plurality of pulse widths of the first level; Determining whether a width difference between two pulse signals of the second level is within an error range; In response to being within the error range, determining that the clock of the hard disk is accurate; and In response to the error not being within the error range, it is determined that the clock of the hard disk is inaccurate.

13. The clock detection method according to claim 9, wherein: Encode its own clock signal and data signal to obtain a communication signal, including: Encoding its current clock frequency into a square wave signal, wherein a second mapping relationship exists between the frequency of the square wave signal and the clock frequency; and inserting the square wave signal into the data signal to obtain the communication signal; The baseboard management controller analyzes the communication signal to obtain the clock signal and the data signal, and determines whether the clock of the hard disk is accurate based on the clock signal, including: The baseboard management controller analyzes the communication signal to obtain the square wave signal and the data signal, and determines whether the clock of the hard disk is accurate based on the square wave signal.

14. The clock detection method according to claim 9, wherein: Encode its own clock signal and data signal to obtain a communication signal, including: Encoding its current clock frequency into a square wave signal, wherein a second mapping relationship exists between the frequency of the square wave signal and the clock frequency; Encoding each data bit into a pulse width corresponding to the data bit one by one to obtain a first pulse width signal, wherein the data signal includes a plurality of the data bits, and the first pulse width signal includes pulse widths corresponding to the plurality of the data bits; and Encoding the square wave signal and the first pulse width signal to obtain the communication signal; The baseboard management controller analyzes the communication signal to obtain the clock signal and the data signal, and determines whether the clock of the hard disk is accurate based on the clock signal, including: The baseboard management controller analyzes the communication signal to obtain the square wave signal and the first pulse width signal, and determines whether the clock of the hard disk is accurate based on the square wave signal.

15. The clock detection method according to claim 14, wherein: Encoding the square wave signal and the first pulse width signal to obtain the communication signal includes: The communication signal is obtained by inserting at least two of the square wave signals before the pulse width corresponding to the first data bit and / or after the pulse width corresponding to the last data bit and / or between the pulse widths corresponding to any two data bits.

16. The clock detection method according to claim 14, wherein: Encoding each data bit into a pulse width corresponding to the data bit to obtain a first pulse width signal includes: Each data bit is encoded into a pulse width with a duty cycle corresponding to the data bit one by one to obtain the first pulse width signal, and a third mapping relationship is formed between the duty cycle and the data bit.

17. The clock detection method according to claim 14, wherein: Encoding each data bit into a pulse width corresponding to the data bit to obtain a first pulse width signal includes: Each of the data bits is encoded into a pulse width of a preset level corresponding to the data bit to obtain the first pulse width signal, and a fourth mapping relationship is formed between the pulse width of the preset level and the data bit.

18. The clock detection method according to any one of claims 9 to 17, wherein: Also includes: After the baseboard management controller determines that the clock of the hard disk is inaccurate, receiving a feedback signal sent by the baseboard management controller; and The data signal or the communication signal is resent based on the feedback signal.

19. A clock detection system, characterized in that: Applied to a baseboard management controller, wherein the baseboard management controller communicates with a hard disk via a single line, the clock detection system includes: a receiving unit, configured to receive a communication signal sent by the hard disk through a hard disk status pin, wherein the communication signal is a signal obtained by encoding the hard disk according to the data signal and its own clock signal; a parsing unit, configured to parse the communication signal to obtain the clock signal and the data signal; and A judging unit is configured to judge whether the clock of the hard disk is accurate based on the clock signal.

20. A clock detection system, characterized in that: Single-line communication between the hard disk and the baseboard management controller, the clock detection system includes: An encoding unit, configured to encode its own clock signal and data signal to obtain a communication signal, wherein the data signal is a signal modulated by the hard disk according to the hard disk log data and the hard disk status signal corresponding to the hard disk status pin; and The sending unit is used to send the communication signal to the baseboard management controller through the hard disk status pin, so that the baseboard management controller parses the communication signal, obtains the clock signal and the data signal, and determines whether the hard disk clock is accurate based on the clock signal.

21. An electronic device, characterized in that: include: a memory for storing computer-readable instructions; A processor, configured to implement the steps of the clock detection method according to any one of claims 1 to 8 or the steps of the clock detection method according to any one of claims 9 to 18 when executing the computer-readable instructions.

22. One or more non-volatile computer-readable storage media storing computer-readable instructions, wherein when the computer-readable instructions are executed by one or more processors, the one or more processors implement the steps of the clock detection method according to any one of claims 1 to 8 or the steps of the clock detection method according to any one of claims 9 to 18.

23. A server, characterized in that: It includes a hard disk and a baseboard management controller, wherein the hard disk is connected to the baseboard management controller via a single line, and there is only one transmission channel between the hard disk and the baseboard management controller via the single line; The baseboard management controller is used to implement the steps of the clock detection method according to any one of claims 1 to 8, and the hard disk is used to implement the steps of the clock detection method according to any one of claims 9 to 18.

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