Pixel circuit and driving method, and display panel and display apparatus

Abstract

A pixel circuit and a driving method, and a display panel and a display apparatus. The pixel circuit comprises a driving sub-circuit, a first light-emitting sub-circuit, a second light-emitting sub-circuit, a first reset sub-circuit, a compensation sub-circuit and a first storage sub-circuit, wherein the driving sub-circuit is coupled to a first node, a second node and a third node; the first light-emitting sub-circuit is coupled to a first voltage signal end, a first light-emitting signal end and the second node; the second light-emitting sub-circuit is coupled to the third node, a second light-emitting signal end and an anode of a light-emitting device; the first reset sub-circuit is coupled to a reset signal end, the first node and a first initialization signal end; the compensation sub-circuit is coupled to the first node, the third node and a first scanning signal end; and the first storage sub-circuit is coupled to the first voltage signal end and the second node. The pixel circuit is used for the display panel.

Description

Pixel circuit and driving method, display panel and display device

[0001] This application claims priority to Chinese patent application No. 202410371350.2, filed on March 28, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and driving method, a display panel, and a display device. Background Art

[0003] With the development of display technology, display devices (such as mobile phones, laptops, and tablets) are increasingly used in people's lives. Among them, organic light-emitting diode (OLED) displays have attracted widespread attention due to their advantages such as active illumination, wide viewing angle, high contrast, fast response, low power consumption, and ultra-thinness. Summary of the Invention

[0004] In one aspect, a pixel circuit is provided. The pixel circuit includes a driver subcircuit, a first light-emitting subcircuit, a second light-emitting subcircuit, a first reset subcircuit, a compensation subcircuit, and a first storage subcircuit. The driver subcircuit is coupled to a first node, a second node, and a third node. The driver subcircuit is configured to control the conduction and cutoff of the second node and the third node under the control of the potential of the first node, and to generate a drive current based on the potentials of the first node and the second node. The first light-emitting subcircuit is coupled to a first voltage signal terminal, a first light-emitting signal terminal, and the second node. The first light-emitting subcircuit is configured to control the conduction and cutoff of the first voltage signal terminal and the second node in response to a first light-emitting signal received at the first light-emitting signal terminal. The second light-emitting subcircuit is coupled to the third node, the second light-emitting signal terminal, and an anode of a light-emitting device. The second light-emitting subcircuit is configured to control the conduction and cutoff of the third node and the anode of the light-emitting device in response to a second light-emitting signal received at the second light-emitting signal terminal. The first reset sub-circuit is coupled to a reset signal terminal, the first node, and the first initialization signal terminal; the first reset sub-circuit is configured to control the first initialization signal terminal and the first node to be conductive and cutoff in response to a reset signal received at the reset signal terminal. The compensation sub-circuit is coupled to the first node, the third node, and a first scan signal terminal; the compensation sub-circuit is configured to control the first node and the third node to be conductive and cutoff in response to a first scan signal received at the first scan signal terminal. The first storage sub-circuit is coupled to the first voltage signal terminal and the second node; the first storage sub-circuit is configured to store the potential of the second node.

[0005] In some embodiments, within a display frame period, the moment when the first voltage signal terminal and the second node start to conduct is earlier than the moment when the third node and the anode of the light-emitting device start to conduct; the moment when the first voltage signal terminal and the second node start to turn off is earlier than the moment when the third node and the anode of the light-emitting device start to turn off.

[0006] In some embodiments, the first storage sub-circuit includes a first storage capacitor, a first plate of the first storage capacitor is connected to the first voltage signal terminal, and a second plate of the first storage capacitor is connected to the second node.

[0007] In some embodiments, the pixel circuit further includes a second reset subcircuit and a data write subcircuit. The second reset subcircuit is coupled to a second initialization signal terminal, the anode of the light-emitting device, and a second scan signal terminal; the second reset subcircuit is configured to control the conduction and cutoff of the anode of the light-emitting device and the second initialization signal terminal in response to a second scan signal received at the second scan signal terminal; the data write subcircuit is coupled to the second node, the third scan signal terminal, and the data signal terminal; the data write subcircuit is configured to control the conduction and cutoff of the data signal terminal and the second node in response to a third scan signal received at the third scan signal terminal.

[0008] In some embodiments, the second scanning signal terminal and the third scanning signal terminal receive the same signal.

[0009] In some embodiments, the first light-emitting sub-circuit includes a second transistor, the second light-emitting sub-circuit includes a third transistor, the first electrode of the second transistor is coupled to the first plate of the first storage capacitor, the second electrode is coupled to the second plate of the first storage capacitor, and the control electrode is coupled to the first light-emitting signal terminal; the first electrode of the third transistor is coupled to the third node, the second electrode is coupled to the anode of the light-emitting device, and the control electrode is coupled to the second light-emitting signal terminal EM2.

[0010] On the other hand, a driving method for a pixel circuit is provided, which is used to drive the pixel circuit as described in any of the above embodiments, and a display frame period includes a reset phase; the driving method includes: in the reset phase, the first reset subcircuit transmits the first initialization signal received at the first initialization signal terminal to the first node in response to the reset signal received at the reset signal terminal; the compensation subcircuit transmits the potential at the first node to the third node in response to the first scan signal received at the first scan signal terminal, the second light-emitting subcircuit transmits the potential at the third node to the anode of the light-emitting device in response to the second light-emitting signal received at the second light-emitting signal terminal, and the first storage subcircuit stores the potential of the second node after the end of the previous frame.

[0011] In some embodiments, the reset phase includes a first reset phase and a second reset phase; in the first reset phase, the second light-emitting sub-circuit transmits the potential at the third node to the anode of the light-emitting device in response to the second light-emitting signal received at the second light-emitting signal terminal; the first reset sub-circuit transmits the first initialization signal received at the first initialization signal terminal to the first node in response to the reset signal received at the reset signal terminal; in the second reset phase, the compensation sub-circuit transmits the potential at the first node to the third node in response to the first scan signal received at the first scan signal terminal; the second light-emitting sub-circuit transmits the potential at the third node to the anode of the light-emitting device in response to the second light-emitting signal received at the second light-emitting signal terminal.

[0012] In some embodiments, the pixel circuit further includes a second reset subcircuit and a write subcircuit; after the reset stage, a display frame cycle further includes a data write compensation stage; in the data write compensation stage, the data write subcircuit transmits the data signal received at the data signal terminal to the second node in response to the second scan number received at the second scan signal terminal; the compensation subcircuit transmits the potential at the second node to the first node in response to the first scan signal received at the first scan signal terminal; the second reset subcircuit transmits the second initialization signal received at the second initialization signal terminal to the anode of the light-emitting device in response to the second scan number received at the second scan signal terminal.

[0013] In another aspect, a display panel is provided. The display panel includes a plurality of pixel circuits, each of which includes a second transistor; the second transistor is coupled to a first voltage signal terminal. The display panel includes a substrate, a semiconductor layer, a first conductive layer, and a second conductive layer. The semiconductor layer is disposed on the substrate and includes a second active portion of the second transistor, the second active portion including a second source region, a second drain region, and a second channel region, the second channel region being disposed between the second source region and the second drain region. The first conductive layer is disposed on a side of the semiconductor layer away from the substrate and includes a plurality of first conductive blocks; the orthographic projections of the first conductive blocks on the substrate overlap with the orthographic projections of one of the second source region and the second drain region on the substrate, and the overlapping portion forms a first storage capacitor; the first conductive blocks are connected to the other of the second source region and the second drain region. The second conductive layer is disposed on a side of the first conductive layer away from the substrate and includes a first power signal line, which is connected to the first conductive block and coupled to the first voltage signal terminal.

[0014] In some embodiments, the pixel circuit further includes a first transistor, the semiconductor layer further includes a first active portion of the first transistor, the first active portion includes a first source region, a first drain region, and a first channel region, the first channel region being disposed between the first source region and the first drain region. The display panel further includes a third conductive layer, the third conductive layer being disposed between the semiconductor layer and the first conductive layer and including a second conductive block, the orthographic projection of the second conductive block on the substrate overlapping the orthographic projection of the first channel region on the substrate. The second conductive layer further includes a third conductive block, the orthographic projection of the third conductive block on the substrate overlapping the orthographic projection of the second conductive block on the substrate, and the overlapping portion of the third conductive block and the second conductive block forming a second storage capacitor.

[0015] In some embodiments, the first conductive block and the third conductive block are integrally provided.

[0016] In some embodiments, the pixel circuit further includes a third transistor connected to the anode of the light-emitting device. The semiconductor layer further includes a third active portion of the third transistor, the third active portion including a third source region, a third drain region, and a third channel region, wherein the third channel region is disposed between the third source region and the third drain region. The third conductive layer further includes a fourth conductive block and a fifth conductive block; the orthographic projection of the fourth conductive block on the substrate overlaps with the orthographic projection of the second channel region on the substrate, and the orthographic projection of the fifth conductive block on the substrate overlaps with the orthographic projection of the third channel region on the substrate; the orthographic projection of the fourth conductive block on the substrate and the orthographic projection of the fifth conductive block on the substrate are staggered.

[0017] In some embodiments, the display panel further includes a fourth conductive layer; the fourth conductive layer is disposed on a side of the first conductive layer away from the third conductive layer, and the fourth conductive layer includes a first luminous signal line. The first luminous signal line is coupled to the first luminous signal terminal; the first luminous signal line includes alternating first straight segments and first bent segments; the first straight segments extend along a first direction, the first bent segments bend toward a side of the first straight segment along a second direction, the orthographic projection of the first bent segment on the substrate overlaps with the orthographic projection of the fourth conductive block on the substrate, and the first bent segment is connected to the fourth conductive block.

[0018] In some embodiments, the display panel further comprises a fourth conductive layer; the fourth conductive layer is disposed on a side of the first conductive layer away from the third conductive layer, and the fourth conductive layer further comprises a second light-emitting signal line. The second light-emitting signal line is coupled to the second light-emitting signal terminal; the second light-emitting signal line comprises a first straight portion and a second straight portion connected to each other; the first straight portion extends along the first direction, the second straight portion extends along the second direction, and an orthographic projection of the second straight portion on the substrate overlaps with an orthographic projection of the fifth conductive block on the substrate and is connected to the fifth conductive block.

[0019] In some embodiments, the active layer patterns are arranged into multiple rows and columns, each row of active layer patterns includes at least two active layer patterns arranged at intervals along a first direction, and along the first direction, the intervals between any two adjacent active layer patterns are approximately equal; each column of active layer patterns includes at least two active layer patterns arranged at intervals along a second direction; and the orthographic projection of one of the fifth conductive blocks on the substrate overlaps with the orthographic projection of a third channel region on the substrate.

[0020] In some embodiments, along the first direction, in the orthographic projection onto the substrate, a second straight line portion is provided between any two adjacent active layer pattern groups, and the first channel region includes a second straight line segment and a second bending segment; the second straight line segment extends along the first direction, and the second bending segment bends toward one side of the second straight line segment along the second direction.

[0021] In some embodiments, the multiple active layer patterns include multiple first active layer patterns and multiple second active layer patterns; the multiple active layer patterns are arranged into multiple rows and columns, a row of active layer patterns is divided into multiple active layer pattern groups, and an active layer pattern group includes an adjacent first active layer pattern and a second active layer pattern; in the same active layer pattern group, the first active layer pattern and the second active layer pattern are roughly symmetrical about the first axis, the first axis extends along the second direction, and the second direction intersects with the first direction; in the orthographic projection onto the substrate, the orthographic projection of one of the fifth conductive blocks on the substrate overlaps with the third channel region in the adjacent first active layer pattern in two adjacent active layer pattern groups, and the third channel region in the second active layer pattern.

[0022] In some embodiments, in an orthographic projection onto the substrate, a second straight line portion is provided between any two adjacent active layer pattern groups; and an extension direction of the first channel region is parallel to the first direction.

[0023] In another aspect, a display device is provided, comprising: a display panel as described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0025] FIG1 is a structural diagram of a display device according to some embodiments;

[0026] FIG2 is another structural diagram of a display device according to some embodiments;

[0027] FIG3 is a structural diagram of a display device including a display panel according to some embodiments;

[0028] FIG4 is a structural diagram of a display panel including a substrate and a pixel circuit according to some embodiments;

[0029] FIG5 is a cross-sectional view along section line AA in FIG4 ;

[0030] FIG6A is a structural diagram of a pixel circuit according to some embodiments;

[0031] FIG6B is another structural diagram of a pixel circuit according to some embodiments;

[0032] FIG7 is a structural diagram of a pixel circuit including a transistor and a capacitor according to some embodiments;

[0033] FIG8 is a timing diagram of a pixel circuit according to some embodiments;

[0034] FIG9 is another timing diagram of a pixel circuit according to some embodiments;

[0035] FIG10 is a structural diagram of a transistor included in a pixel circuit according to some embodiments, wherein the transistor is turned on or off;

[0036] FIG11 is another structural diagram of a transistor included in a pixel circuit according to some embodiments being turned on or off;

[0037] FIG12 is another structural diagram of a transistor included in a pixel circuit according to some embodiments, wherein the transistor is turned on or off;

[0038] FIG13 is another structural diagram of a transistor included in a pixel circuit according to some embodiments, wherein the transistor is turned on or off;

[0039] FIG14 is another structural diagram of a transistor included in a pixel circuit according to some embodiments, wherein the transistor is turned on or off;

[0040] FIG15A is a structural diagram of a display panel including a film layer structure according to some embodiments;

[0041] FIG15B is another structural diagram of a display panel including a film layer structure according to some embodiments;

[0042] FIG16A is a structural diagram of a semiconductor layer and a first conductive layer stacked according to some embodiments;

[0043] FIG16B is another structural diagram of a semiconductor layer and a first conductive layer stacked according to some embodiments;

[0044] FIG17A is a diagram showing another structure of a display panel including a film layer structure according to some embodiments;

[0045] FIG17B is a diagram showing another structure of a display panel including a film layer structure according to some embodiments;

[0046] FIG18A is a partial enlarged view of B in FIG17A;

[0047] FIG18B is a partial enlarged view of C in FIG17B . DETAILED DESCRIPTION

[0048] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0049] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0050] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0051] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0052] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0053] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0054] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0055] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0056] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0057] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0058] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0059] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0060] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0061] In the embodiments of the present disclosure, the capacitor can be a capacitive device independently manufactured through a process, for example, by manufacturing dedicated capacitive electrodes, each of which can be implemented by a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. The capacitor can also be a parasitic capacitor between transistors, or implemented by the transistor itself and other devices or circuits, or by utilizing the parasitic capacitance between the circuits within the circuit itself.

[0062] In the circuit provided in the embodiments of the present disclosure, the first node, the second node, and the third node do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by equivalent junction points of related electrical connections in the circuit diagram.

[0063] The "low level" of the pixel circuit provided in the embodiment of the present disclosure refers to a level that can turn on the operated transistor included therein, and accordingly, the "high level" refers to a level that cannot turn on the operated transistor included therein (i.e., the transistor is turned off).

[0064] As shown in FIG. 1 and FIG. 2 , some embodiments of the present disclosure provide a display device 1000 , which may be any device that displays either moving (eg, video) or fixed (eg, still image) content and either text or images.

[0065] Exemplarily, the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a vehicle display, or an aircraft display.

[0066] In some examples, as shown in FIG1 , the display device 1000 may be a portable display product, such as the mobile phone shown in FIG1 .

[0067] In some other examples, as shown in FIG2 , the display device 1000 may be a wearable device. For example, the display device 1000 may be a watch as shown in FIG2 .

[0068] In some embodiments, as shown in FIG. 3 , a display device 1000 includes a display panel 100 , a driving circuit board 200 , a housing 300 , and a cover plate 400 .

[0069] Among them, the display panel 100 has a relative light-emitting side 100A and a non-light-emitting side 100B. The light-emitting side 100A refers to the side of the display panel 100 that can emit light (the upper side of the display panel 100 in Figure 3), and the non-light-emitting side 100B refers to the other side opposite to the light-emitting side 100A (the lower side of the display panel 100 in Figure 3).

[0070] The driving circuit board 200 is disposed on the non-luminous side of the display panel 100 and is connected to the display panel 100 to provide a luminous signal to the display panel 100 .

[0071] The housing 300 may be a box-shaped structure with an opening. The display panel 100 and the driver circuit board 200 may be disposed in the housing 300 . The cover plate 400 is disposed on the light-emitting side of the display panel 100 and located at the opening of the housing 300 .

[0072] As shown in FIG. 3 , the longitudinal section of the housing 300 may be, for example, U-shaped. The display panel 100 and the driving circuit board 200 are disposed in the housing 300 , and the cover plate 400 is disposed at the opening of the housing 300 .

[0073] The display panel 100 may be of various types and may be selected according to actual needs.

[0074] Exemplarily, the display panel 100 may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, an active matrix organic light-emitting diode (AMOLED) display panel, a liquid crystal display (LCD) display panel, or a mini / micro light-emitting display (MLED) display panel, etc. The embodiments of the present disclosure are not specifically limited herein.

[0075] In the following, some embodiments of the present disclosure are schematically described by taking the display panel 100 as an OLED display panel as an example.

[0076] In some embodiments, as shown in FIG. 4 and FIG. 5 , the display panel 100 includes a substrate 10 and a plurality of sub-pixels 20 .

[0077] The material used for the substrate 10 may include a polymer resin or glass. For example, the substrate 10 may be flexible and may be made of a polymer resin, such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate two formal acid glycol ester (PEN), polyethylene terephthalate (PET), polyphenylene sulfide granula (PPS), polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). Illustratively, the substrate 10 may be rigid and include a glass material containing SiO 2 as a main component.

[0078] As shown in FIG4 , a plurality of sub-pixels 20 are disposed on a substrate 10. The plurality of sub-pixels 20 may be arranged, for example, in multiple rows and columns. Each row of sub-pixels 20 includes at least two sub-pixels 20 arranged along a first direction X, and each column of sub-pixels 20 includes at least two sub-pixels 20 arranged along a second direction Y. The first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y.

[0079] The plurality of sub-pixels 20 may include a first sub-pixel emitting a first color, a second sub-pixel emitting a second color, and a third sub-pixel emitting a third color. The first, second, and third colors are three primary colors. For example, the first color is red, the second color is blue, and the third color is green. This is not specifically limited in the present embodiment.

[0080] 4 and 5 , each sub-pixel 20 includes a pixel circuit 21 and a light-emitting device 22 disposed on a substrate 10. The pixel circuit 21 includes a plurality of transistors 211 and a storage capacitor 212 (Capacitor, C for short).

[0081] The transistors used in the circuits provided in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as an example.

[0082] Exemplarily, the transistor 211 is, for example, an oxide thin film transistor. The oxide thin film transistor has a high carrier mobility, which can improve the response speed of the transistor 211 .

[0083] 5 , the transistor 211 includes an active portion 2111, a source 2112, a drain 2113, and a gate 2114. The source 2112 and the drain 2113 are respectively in contact with the active portion 2111. The storage capacitor 212 includes two plates disposed opposite to each other.

[0084] It should be noted that the source 2112 and the drain 2113 can be interchanged, that is, 2112 in FIG. 5 represents the drain, and 2113 represents the source.

[0085] The pixel circuit 21 may have various structures, which can be selected based on actual needs. For example, the pixel circuit 21 may have a structure such as "2T1C," "3T1C," "6T1C," "7T1C," "6T2C," or "7T2C." "T" represents the transistor 211, and the number preceding "T" represents the number of transistors 211. "C" represents the storage capacitor 212, and the number preceding "C" represents the number of storage capacitors 212.

[0086] As shown in FIG5 , the light-emitting device 22 includes a first electrode 221, a light-emitting functional layer 222, and a second electrode 223. The first electrode 221 can be electrically connected to the source 2112 or drain 2113 of the driving transistor in the plurality of transistors 211, for example. FIG5 illustrates the electrical connection between the first electrode 221 and the drain 2113 of the transistor 211. The material of the first electrode 221 includes indium tin oxide (ITO) or silver (Ag). The material of the second electrode includes aluminum (Al), Ag, or magnesium (Mg).

[0087] It should be noted that the first electrode 221 is the anode of the light-emitting device 22, and the second electrode 223 is the cathode of the light-emitting device 22; alternatively, the first electrode 221 is the cathode of the light-emitting device 22, and the second electrode 223 is the anode of the light-emitting device 22. The following uses the example of the first electrode 221 being the anode of the light-emitting device 22 and the second electrode 223 being the cathode of the light-emitting device 22 as an example to illustrate the embodiments of the present disclosure.

[0088] Exemplarily, as shown in FIG5 , the second electrode 223 (cathode) is a whole-layer structure.

[0089] The light-emitting functional layer 222 may include only a light-emitting layer, or, in addition to the light-emitting layer, may also include at least one of an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL).

[0090] In some embodiments, as shown in FIG5 , the display panel 100 further includes an encapsulation layer 30. The encapsulation layer 30 is disposed on a side of the plurality of sub-pixels 20 away from the substrate 10. The encapsulation layer 30 is used to encapsulate the light-emitting devices 22 to increase the service life of the light-emitting devices 22. The encapsulation layer 30 may be an encapsulation film or an encapsulation substrate, which is not specifically limited in the present embodiment.

[0091] Exemplarily, the encapsulation layer 30 may include a single encapsulation film, or may include two or more stacked encapsulation films. For example, as shown in FIG5 , the encapsulation layer 30 includes a first inorganic encapsulation layer 31, a first organic encapsulation layer 32, and a second inorganic encapsulation layer 33 stacked in a direction perpendicular to and away from the substrate 10. The materials of the first inorganic encapsulation layer 31 and the second inorganic encapsulation layer 33 include any one or more of silicon nitride, silicon oxynitride, or silicon oxide. The material of the first organic encapsulation layer 32 includes a polymer resin, such as polyimide.

[0092] In the related art, during the process of the display panel emitting light, the brightness of the display panel is uneven, resulting in poor display effect of the display panel.

[0093] In order to solve the above technical problems, some embodiments of the present disclosure provide a pixel circuit 21, as shown in Figures 6A and 6B, the pixel circuit 21 includes a driving sub-circuit 201, a first light-emitting sub-circuit 202, a second light-emitting sub-circuit 203, a first reset sub-circuit 204, a compensation sub-circuit 205 and a first storage sub-circuit 206.

[0094] In some examples, as shown in Figures 6A and 6B, the driver sub-circuit 201 is coupled to the first node N1, the second node N2, and the third node N3. The driver sub-circuit 201 is configured to control the conduction and cutoff of the second node N2 and the third node under the control of the potential of the first node N1; and generate a driving current according to the potential of the first node N1 and the potential of the second node N2.

[0095] Exemplarily, as shown in FIG7 , the driving sub-circuit 201 includes a first transistor (driving transistor) T1 , wherein the first electrode of the first transistor T1 is coupled to the second node N2 , the second electrode is coupled to the third node N3 , and the control electrode (gate) is coupled to the first node N1 .

[0096] In some examples, as shown in Figures 6A and 6B, the first light-emitting sub-circuit 202 is coupled to the first voltage signal terminal VDD, the first light-emitting signal terminal EM1 and the second node N2; the first light-emitting sub-circuit 202 is configured to control the conduction and cutoff of the first voltage signal terminal VDD and the second node N2 in response to the first light-emitting signal received at the first light-emitting signal terminal EM1.

[0097] Exemplarily, as shown in FIG7 , the first light-emitting sub-circuit 202 includes a second transistor T2 , a first electrode of the second transistor T2 coupled to the first voltage signal terminal VDD, a second electrode coupled to the second node N2 , and a control electrode coupled to the first light-emitting signal terminal EM1 .

[0098] In some examples, as shown in Figures 6A and 6B, the second light-emitting sub-circuit 203 is coupled to the third node N3, the second light-emitting signal terminal EM2 and the anode of the light-emitting device 22; the second light-emitting sub-circuit 203 is configured to control the conduction and cutoff of the third node N3 and the anode of the light-emitting device 22 in response to the second light-emitting signal received at the second light-emitting signal terminal EM2.

[0099] The waveform of the first light-emitting signal is different from the waveform of the second light-emitting signal. For example, the first light-emitting signal controls the first voltage signal terminal VDD and the second node N2 to begin conducting earlier than the second light-emitting signal controls the third node N3 and the anode of the light-emitting device 22 to begin conducting. The first light-emitting signal controls the first voltage signal terminal VDD and the second node N2 to begin turning off earlier than the second light-emitting signal controls the third node N3 and the anode of the light-emitting device 22 to begin turning off.

[0100] 7 , the second light-emitting sub-circuit 203 includes a third transistor T3 , a first electrode of the third transistor T3 coupled to the third node N3 , a second electrode coupled to the anode of the light-emitting device 22 , and a control electrode coupled to the second light-emitting signal terminal EM2 .

[0101] 6A, 6B and 7, the cathode of the light emitting device 22 is coupled to the second voltage signal terminal VSS, wherein the level output by the second voltage signal terminal VSS is lower than the high level output by the first voltage signal terminal VDD.

[0102] 6A and 6B , the first reset sub-circuit 204 is coupled to the reset signal terminal RESET, the first node N1, and the first initialization signal terminal VINIT1. The first reset sub-circuit 204 is configured to control the conduction and cutoff of the first initialization signal terminal VINIT1 and the first node N1 in response to the reset signal received at the reset signal terminal RESET.

[0103] Exemplarily, as shown in FIG7 , the first reset subcircuit 204 includes a fourth transistor T4 , a first electrode of the fourth transistor T4 coupled to the first initialization signal terminal VINIT1 , a second electrode coupled to the first node N1 , and a control electrode coupled to the reset signal terminal RESET.

[0104] Alternatively, illustratively, the first reset sub-circuit 204 includes a plurality of fourth transistors T4 connected in series, one end of the plurality of fourth transistors T4 connected in series is coupled to the first initialization signal terminal VINIT1, the other end is coupled to the first node N1, and the control electrode of each fourth transistor T4 is coupled to the reset signal terminal RESET.

[0105] For example, the first reset sub-circuit 204 includes two fourth transistors T4 connected in series, and the two fourth transistors T4 form a dual-gate transistor to reduce leakage current, but the embodiments of the present disclosure are not limited to this, and it can also be considered that the first reset sub-circuit 204 includes three, four or more fourth transistors T4 connected in series, as long as the same technical concept is applied.

[0106] In this manner, under the control of the reset signal terminal RESET, the first initialization signal received by the first initialization signal terminal VINIT1 can be transmitted to the first node N1 through the first reset sub-circuit 204, thereby initializing the first node N1. This can improve the problem that the potential remaining in the first node N1 of the previous image frame affects the displayed image of the next image frame, thereby improving the brightness uniformity of the display panel 100.

[0107] In some examples, as shown in Figures 6A and 6B, the compensation sub-circuit 205 is coupled to the first node N1, the third node N3 and the first scan signal terminal GATE1; the compensation sub-circuit 205 is configured to control the conduction and cutoff of the first node N1 and the third node N3 in response to the first scan signal received at the first scan signal terminal GATE1.

[0108] Exemplarily, as shown in FIG7 , the compensation sub-circuit 205 includes a fifth transistor T5 , a first electrode of the fifth transistor T5 coupled to the third node N3 , a second electrode coupled to the first node N1 , and a control electrode coupled to the first scan signal terminal GATE1 .

[0109] Alternatively, illustratively, the compensation sub-circuit 205 includes a plurality of fifth transistors T5 connected in series, one end of the plurality of fifth transistors T5 connected in series is coupled to the third node N3, the other end is coupled to the first node N1, and the control electrode of each fifth transistor T5 is coupled to the first scan signal terminal GATE1.

[0110] For example, the compensation sub-circuit 205 includes two fifth transistors T5 connected in series, and the two fifth transistors T5 form a dual-gate transistor to reduce leakage current, but the embodiments of the present disclosure are not limited to this, and it can also be considered that the compensation sub-circuit 205 includes three, four or more fourth transistors T4 connected in series, as long as the same technical idea is applied.

[0111] In some embodiments, as shown in FIG. 6A and FIG. 6B , the first storage sub-circuit 206 is coupled to the first voltage signal terminal VDD and the second node N2 ; the first storage sub-circuit 206 is configured to store the potential of the second node N2 .

[0112] Exemplarily, as shown in FIG7 , the first storage sub-circuit 206 includes a first storage capacitor C1, wherein the first plate of the first storage capacitor C1 is connected to the first voltage signal terminal VDD, that is, the first plate of the first storage capacitor C1 is connected to the first electrode of the second transistor T2, and the second plate is connected to the second node N2, that is, the second plate is connected to the second electrode of the second transistor T2.

[0113] In this manner, before the data writing compensation stage, the first storage capacitor C1 can store the potential at the second node N2 after the previous frame display is completed to charge the second node N2, thereby reducing the risk of unstable potential of the second node N2 due to leakage of the second node N2, which is beneficial for the second node N2 to maintain a relatively stable potential corresponding to the first voltage signal terminal VDD, thereby reducing the potential difference of the second node N2 of multiple pixel circuits 21 and improving the brightness uniformity of the display panel 100.

[0114] It should be noted that in the circuits provided in the embodiments of the present disclosure, transistors are described using P-type transistors as an example. It should be noted that the embodiments of the present disclosure include but are not limited to this. For example, one or more transistors in the circuits provided in the embodiments of the present disclosure may also be N-type transistors. It is only necessary to connect the respective poles of the selected type of transistor accordingly with reference to the respective poles of the corresponding transistors in the embodiments of the present disclosure, and to provide corresponding high or low potentials at the corresponding potential terminals.

[0115] In some embodiments, as shown in Figures 6A and 6B, the pixel circuit 21 also includes a second reset sub-circuit 207, which is coupled to the second initialization signal terminal VINIT2, the anode of the light-emitting device 22 and the second scan signal terminal GATE2; the second reset sub-circuit 207 is configured to control the conduction and cutoff of the anode of the light-emitting device 22 and the second initialization signal terminal VINIT2 in response to the second scan signal received at the second scan signal terminal GATE2.

[0116] 7 , the second reset sub-circuit 207 includes a sixth transistor T6 , a first electrode of the sixth transistor T6 being connected to the second initialization signal terminal VINIT2 , a second electrode being coupled to the anode of the light emitting device 22 , and a control electrode being coupled to the second scan signal terminal GATE2 .

[0117] In this manner, under the control of the second scanning signal terminal GATE2, the second initialization signal received by the second initialization signal terminal VINIT2 can be transmitted to the anode of the light-emitting device 22 through the second reset sub-circuit 207, thereby initializing the anode of the light-emitting device 22, and improving the problem that the potential remaining in the anode of the light-emitting device 22 in the previous image frame affects the display image of the next image frame, thereby improving the brightness uniformity of the display panel 100.

[0118] In some embodiments, as shown in Figure 6A, the pixel circuit 21 also includes a data writing sub-circuit 208, which is coupled to the second node N2, the third scan signal terminal GATE3 and the data signal terminal DATA; the data writing sub-circuit 208 is configured to control the conduction and cutoff of the data signal terminal DATA and the second node N2 in response to the second scan number received at the third scan signal terminal GATE3.

[0119] Exemplarily, the data writing sub-circuit 208 includes a seventh transistor T7 , a first electrode of the seventh transistor T7 is connected to the data signal terminal DATA, a second electrode is coupled to the second node N2 , and a control electrode is coupled to the third scan signal terminal GATE3 .

[0120] Based on the above embodiment, as shown in FIG6B , the second scan signal terminal GATE2 and the third scan signal terminal GATE3 receive the same signal. In this way, the control electrode of the sixth transistor T6 and the control electrode of the seventh transistor T7, which reset the anode of the light-emitting device 22, can both be controlled by the second scan signal terminal GATE2. This allows the anode of the light-emitting device 22 to be reset simultaneously during the data write compensation process, simplifying the circuit structure.

[0121] The following uses the example of the second scan signal terminal GATE2 and the third scan signal terminal GATE3 receiving the same signal as an example to schematically illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure is not limited to this, and it can also be considered that the second scan signal terminal GATE2 and the third scan signal terminal GATE3 receive different signals, as long as the same technical concept is applied.

[0122] In some embodiments, as shown in FIG6A and FIG6B , the pixel circuit 21 further includes a second storage subcircuit 209 , which is coupled to the first voltage signal terminal VDD and the first node N1 ; the first storage subcircuit 206 is configured to store the potential of the first node N1 .

[0123] Exemplarily, as shown in FIG7 , the second storage sub-circuit 209 includes a second storage capacitor C2 , a first plate of the second storage capacitor C2 is connected to the first voltage signal terminal VDD, and a second plate is connected to the first node N1 .

[0124] The following describes in detail the operation of the pixel circuit 21 within a display frame period, in conjunction with a timing diagram. The following embodiments utilize a case where all of the transistors are P-type. As shown in Figures 8 and 9 , a display frame period includes a reset phase P1, a data write compensation phase P2, and a light-emitting phase P3.

[0125] Among them, in the reset phase P1:

[0126] In response to the reset signal received at the reset signal terminal RESET, the first reset sub-circuit 204 transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1 to reset the first node N1. That is, the potential of the first node N1 is Vin1.

[0127] The compensation sub-circuit 205 transmits the potential at the first node N1 to the third node N3 in response to the first scan signal received at the first scan signal terminal GATE1. In this way, the first initialization signal can be transmitted from the first node N1 to the third node N3 to reset the third node N3, that is, the potential of the third node N3 is Vin1.

[0128] In response to the second light-emitting signal received at the second light-emitting signal terminal EM2, the second light-emitting sub-circuit 203 transmits the potential at the third node N3 to the anode of the light-emitting device 22. In this way, the first initialization signal can be transmitted from the third node N3 to the anode of the light-emitting device 22 to reset the anode of the light-emitting device 22. That is, the potential of the anode of the light-emitting device 22 is Vin1. At this time, the difference between the potential Vin1 of the anode of the light-emitting device 22 and the potential Vss of the cathode of the light-emitting device 22 is Vin1-Vss, and is less than the threshold voltage of the light-emitting device 22. In this way, the risk of the light-emitting device 22 emitting light during the reset phase P1 can be reduced.

[0129] The first storage sub-circuit 206 stores the potential of the second node N2 after the previous frame ends. The potential of the second node N2 can maintain a relatively stable potential corresponding to the first voltage signal terminal VDD, that is, the potential of the second node N2 is Vdd.

[0130] In some examples, the sub-pixels 20 are arranged in an array with multiple rows and columns, and the first scan signal terminal GATE1 in the pixel circuit 21 of a row of sub-pixels 20 and the reset signal terminal RESET in the pixel circuit 21 of the upper N (N is greater than or equal to 1, for example, N is equal to 7) rows of sub-pixels 20 are connected to the same signal.

[0131] In this case, the reset phase P1 includes a first reset phase P11 and a second reset phase P12 .

[0132] As shown in Figure 10, in the first reset phase P11:

[0133] The second light emitting sub-circuit 203 transmits the potential at the third node N3 to the anode of the light emitting device 22 in response to the second light emitting signal received at the second light emitting signal terminal EM2 .

[0134] In response to the reset signal received at the reset signal terminal RESET, the first reset sub-circuit 204 transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1 to reset the first node N1.

[0135] As shown in Figure 11, in the second reset phase P12:

[0136] The first reset sub-circuit 204 maintains the state, and the compensation sub-circuit 205 transmits the potential at the first node N1 to the third node N3 in response to the first scan signal received at the first scan signal terminal GATE1. In this way, the first initialization signal can be transmitted from the first node N1 to the third node N3 to reset the third node N3.

[0137] The second light-emitting sub-circuit 203 maintains a state, and thus the first initialization signal can be transmitted from the third node N3 to the anode of the light-emitting device 22 to reset the anode of the light-emitting device 22 .

[0138] Exemplarily, each sub-circuit in the pixel circuit 21 includes a transistor 211 or a storage capacitor 212. As shown in Figures 8 and 10, in the first reset phase P11, the reset signal is 0, the second light-emitting signal is 0, the first scanning signal is 1, the second light-emitting signal is 1, and the second scanning signal is 1. "0" represents a low level, and "1" represents a high level.

[0139] In this case, the reset signal terminal RESET and the second light-emitting signal terminal EM2 input a low level, the third transistor T3 and the fourth transistor T4 are turned on, the first scan signal terminal GATE1, the second light-emitting signal terminal EM2 and the second scan signal terminal GATE2 input a high level, and the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all turned off.

[0140] At this time, the first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the first node N1 via the fourth transistor T4, and the potential of the first node N1 is Vin1. The potential of the third node N3 is transmitted to the anode of the light-emitting device 22 via the fourth transistor T4. The first storage capacitor C1 can maintain a relatively stable potential corresponding to the first voltage signal terminal VDD, that is, the potential of the second node N2 is Vdd. The potential difference between the first node N1 and the second node N2 is Vin1-Vdd, thereby keeping the first transistor T1 in a fixed on state.

[0141] As shown in FIG11 , in the second reset phase P12 , the reset signal is 0, the second light emitting signal is 0, the first scanning signal is 0, the second light emitting signal is 1, and the second scanning signal is 1. “0” represents a low level and “1” represents a high level.

[0142] In this case, the reset signal terminal RESET, the second light-emitting signal terminal EM2 and the input low level, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are turned on, the first scan signal terminal GATE1, the second light-emitting signal terminal EM2 and the second scan signal terminal GATE2 are input high level, and the second transistor T2, the sixth transistor T6 and the seventh transistor T7 are all turned off.

[0143] The potential at the first node N1 is transmitted to the third node N3 via the fifth transistor T5, causing the potential at the third node N3 to also be Vin1, thereby resetting the third node N3. The potential at the third node N3 is transmitted to the anode of the light-emitting device 22 via the third transistor T3, causing the potential at the anode of the light-emitting device 22 to be Vin1, thereby resetting the anode of the light-emitting device 22. The potential difference between the first node N1 and the second node N2 is also Vin1-VDD, thereby maintaining the first transistor T1 in a fixed on state.

[0144] In summary, throughout the reset phase P1, the potential difference between the first node N1 and the second node N2 remains at VINIT - VDD, keeping the first transistor T1 in a fixed on state. Consequently, regardless of whether the data signal in the previous image display frame was a high-grayscale signal or a low-grayscale signal, the first transistor T1 remains in a fixed on state during the data write compensation phase. This alleviates the short-term image retention problem caused by hysteresis.

[0145] In other examples, as shown in Figures 9 and 11, each sub-circuit in the pixel circuit 21 includes a transistor 211 or a capacitor 212. In the reset phase P1, the reset signal is 0, the second light-emitting signal is 0, the first scanning signal is 0, the second light-emitting signal is 1, and the second scanning signal is 1. "0" represents a low level, and "1" represents a high level.

[0146] In this case, the reset signal terminal RESET, the second light-emitting signal terminal EM2 and the input low level, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are turned on, the first scan signal terminal GATE1, the second light-emitting signal terminal EM2 and the second scan signal terminal GATE2 are input high level, and the second transistor T2, the sixth transistor T6 and the seventh transistor T7 are all turned off.

[0147] At this time, the first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the first node N1 via the fourth transistor T4, causing the potential of the first node N1 to be Vin1. The potential at the first node N1 is transmitted to the third node N3 via the fifth transistor T5, causing the potential at the third node N3 to also be Vin1, thereby resetting the third node N3. The potential at the third node N3 is transmitted to the anode of the light-emitting device 22 via the third transistor T3, causing the potential of the anode of the light-emitting device 22 to be Vin1, thereby resetting the anode of the light-emitting device 22. In this way, the potential difference between the first node N1 and the second node N2 is also Vin1-VDD, causing the first transistor T1 to be in a fixed on state. In this way, regardless of whether the data signal in the previous image display frame is a high grayscale signal or a low grayscale signal, the first transistor T1 enters the data write compensation phase in this display frame in a fixed on state. This can improve the short-term afterimage problem caused by the hysteresis effect.

[0148] As shown in FIG8, FIG9 and FIG12, in the data writing compensation phase P2,

[0149] The data writing sub-circuit 208 transmits the data signal received at the data signal terminal DATA to the second node N2 in response to the second scan signal received at the second scan signal terminal GATE2.

[0150] The compensation sub-circuit 205 transmits the potential at the second node N2 to the first node N1 in response to the first scan signal received at the first scan signal terminal GATE1 .

[0151] The second storage sub-circuit 209 is used to maintain the potential of the first node N1.

[0152] In response to the second scan signal received at the second scan signal terminal GATE2 , the second reset sub-circuit 207 transmits the second initialization signal received at the second initialization signal terminal VINIT2 to the anode of the light emitting device 22 to reset the anode of the light emitting device 22 .

[0153] For example, as shown in FIG12 , each sub-circuit in the pixel circuit 21 includes a transistor 211 or a storage capacitor 212. In the data writing compensation phase P2, the first scanning signal is 0, the second scanning signal is 0, the reset signal is 1, the second light-emitting signal is 1, and the first light-emitting signal is 1. Here, "0" represents a low level, and "1" represents a high level.

[0154] In this case, the first scan signal terminal GATE1 and the second scan signal terminal GATE2 are input low level, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all turned on, the reset signal terminal RESET, the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are input high level, and the second transistor T2, the third transistor T3 and the fourth transistor T4 are all turned off.

[0155] At this time, the second initialization signal at the second initialization signal terminal VINIT2 is transmitted to the anode of the light-emitting device 22 through the sixth transistor T6 to reset the anode of the light-emitting device 22. At this time, the difference between the potential Vin2 of the anode of the light-emitting device 22 and the potential Vss of the cathode of the light-emitting device 22 is Vin1-Vss, and is less than the threshold voltage of the light-emitting device 22. In this way, the risk of the light-emitting device 22 emitting light during the data writing compensation phase P2 can be reduced.

[0156] The data signal received at the data signal terminal DATA is transmitted to the second node N2 through the seventh transistor T7, that is, the potential of the second node N2 is Vdata. As can be seen from the above, the potential of the first node N1 is Vint1. The potential difference between the gate (first node N1) and the source (second node N2) of the first transistor T1 is Vint1-Vdata. The gate-source potential difference of the first transistor T1 is greater than its own threshold voltage Vth, the first transistor T1 is turned on, and the data signal is transmitted from the third node N3 to the second node N2. The data signal at the second node N2 is transmitted to the first node N1 through the fifth transistor T5. The potential of the first node N1 gradually increases from Vin1. When the potential of the first node N1 increases to Vdata+Vth, the first transistor T1 is turned off, and the data write compensation phase P2 ends. As a result, the data signal Vdata and the threshold voltage Vth are written to the second storage capacitor C2.

[0157] As shown in FIG8, FIG9 and FIG13, in the light-emitting stage P3,

[0158] In response to the first lighting signal received at the first lighting signal terminal EM1 , the first lighting sub-circuit 202 transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2 , ie, the potential of the second node is Vdd.

[0159] The driving sub-circuit 201 generates a driving current under the control of the potentials of the first node N1 and the second node N2, and outputs the driving current to the third node N3.

[0160] The second light emitting sub-circuit 203 transmits the driving current received at the third node N3 to the anode of the light emitting device 22 in response to the second light emitting signal received at the second light emitting signal terminal EM2, so that the light emitting device 22 emits light under the control of the driving current.

[0161] 13 , each subcircuit in the pixel circuit 21 includes a transistor 211 or a storage capacitor 212. In the light emitting phase P3, the first light emitting signal is 0, the second light emitting signal is 0, the reset signal is 1, the first scanning signal is 1, and the second scanning signal is 1.

[0162] In this case, a low level is input to the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2, turning on the second transistor T2 and the third transistor T3. A high level is input to the reset signal terminal RESET, the first scan signal terminal GATE1, and the second scan signal terminal GATE2, turning off the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0163] At this time, the first voltage signal at the first voltage signal terminal VDD is transmitted to the second node N2 through the second transistor T2, that is, the potential of the second node is Vdd. As can be seen from the above, the potential of the first node N1 is Vdata+Vth. The first transistor T1 generates a driving current under the control of the potentials of the first node N1 and the third node N3, and the first transistor T1 operates in the saturation region. According to the saturation current formula, the driving current generated by the first transistor T1 (the current input to the light-emitting device 22) is:

[0164] Wherein, W / L is the channel width-to-length ratio of the first transistor T1; μ is the carrier mobility; Cox is the channel capacitance per unit area of ​​the first transistor T1; Vgs is the gate-source voltage difference of the first transistor T1; and Vth is the threshold voltage of the first transistor T1.

[0165] It can be seen that the magnitude of the current Ioled input to the light-emitting device 22 is related to the potential Vdata of the written data signal and the first voltage signal, and is not related to the threshold voltage Vth of the first transistor T1. This avoids the problem that the difference in the threshold voltage of the first transistor T1 of each pixel circuit 21 caused by the manufacturing process affects the magnitude of the driving current, thereby affecting the display effect.

[0166] In some embodiments, as shown in FIG8 and FIG9 , between the data writing compensation phase P2 and the light emitting phase P3 , a display frame period further includes a pre-light emitting phase P4 .

[0167] As shown in FIG14 , in the pre-lighting stage P4:

[0168] In response to the reset signal received at the first light emitting signal terminal EM1 , the first light emitting sub-circuit 202 transmits the first voltage signal received at the first voltage signal terminal VDD to the first node N1 , so that the potential of the first node N1 is Vdd.

[0169] 14 , each subcircuit in the pixel circuit 21 includes a transistor 211 or a storage capacitor 212. In the pre-emission stage, the first emission signal is 0, the second emission signal is 1, the first scanning signal is 1, the second scanning signal is 1, and the reset signal is 1.

[0170] In this case, a low level is input to the first light-emitting signal terminal EM1, and the second transistor T2 is turned on. A high level is input to the second light-emitting signal terminal EM2, the first scan signal terminal GATE1, the second scan signal terminal GATE2, and the fifth signal terminal, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all turned off.

[0171] At this time, the first voltage signal received at the first voltage signal terminal VDD is transmitted to the second node N2 through the second transistor T2, thereby charging the second node N2, and the potential of the second node N2 changes from Vdata to Vdd. Since the fifth transistor T5 is turned off at this stage, the light-emitting device 22 does not emit light in the pre-light-emitting stage P4 and prepares for the next stage of light-emitting.

[0172] In some embodiments, as shown in FIG4 , the following uses an example in which all pixel circuits 21 are arranged in multiple rows and columns to illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto. Furthermore, a plurality of pixel circuits 21 arranged along a first direction X is referred to as a row of pixel circuits 21 , and a plurality of pixel circuits 21 arranged along a second direction Y is referred to as a column of pixel circuits 21 .

[0173] On this basis, the display panel 100 further includes a plurality of gate lines GL, a plurality of data lines DL, a plurality of first power signal lines VDL, a plurality of first initialization signal lines VL1 and a plurality of second initialization signal lines VL2.

[0174] As shown in FIG4 , each gate line GL extends substantially along a first direction X and is configured to transmit any one of a first scan signal, a second scan signal, a reset signal, a first light-emitting signal, and a second light-emitting signal. For example, a gate line GL may be connected to any one of a first scan signal terminal GATE1, a second scan signal terminal GATE2, a reset signal terminal RESET, a first light-emitting signal terminal EM1, and a second light-emitting signal terminal EM2 of a row of pixel circuits 21.

[0175] 4 , the data lines DL extend substantially along the second direction Y and are configured to transmit data signals. For example, one data line DL may be connected to a data signal terminal DATA of a column of pixel circuits 21 .

[0176] 4 , the first power signal line VDL extends substantially along the second direction Y and is configured to transmit a first power potential signal. For example, one first power signal line VDL may be connected to the first voltage signal terminal VDD of a column of pixel circuits 21 .

[0177] 4 , the first initialization signal line VL1 extends substantially along the first direction X and is configured to transmit a first initialization signal. One first initialization signal line VL1 may be connected to the first initialization signal terminal VINIT1 of a row of pixel circuits 21 , for example.

[0178] 4 , the second initialization signal line VL2 extends substantially along the first direction X and is configured to transmit a second initialization signal. One second initialization signal line VL2 can be connected to the second initialization signal terminal VINIT2 of a row of pixel circuits 21 , for example.

[0179] The pixel circuit 21 provided in some embodiments of the present disclosure is exemplarily described below in conjunction with the film layer of the display panel 100 .

[0180] 15A and 15B , the display panel 100 further includes a semiconductor layer 101, a first conductive layer 102, and a second conductive layer 103. For example, the first conductive layer 102 is a second gate conductive layer, and the second conductive layer 103 is a second source and drain conductive layer.

[0181] The semiconductor layer 101 is disposed on the substrate 10. As shown in Figures 16A and 16B, the semiconductor layer 101 includes a plurality of active layer patterns 1011. Each active layer pattern 1011 includes an active portion of each transistor 211 in each pixel circuit 21. As shown in Figures 16A and 16B, the active layer pattern 1011 includes a first active portion t1 of a first transistor T1, a first active portion t2 of a second transistor T2, a third active portion t3 of a third transistor T3, a fourth active portion t4 of a fourth transistor T4, a fifth active portion t5 of a fifth transistor T5, a sixth active portion t6 of a sixth transistor T6, and a seventh active portion of a seventh transistor T7. The active portion of each transistor includes a source region, a drain region, and a channel region, with the channel region being located between the source and drain regions. As shown in Figures 16A and 16B, the first channel region t13 is located between the first source region t11 and the first drain region t12, the second channel region t23 is located between the second source region t21 and the second drain region t22, the third channel region t33 is located between the third source region t31 and the third drain region t32, the fourth channel region t43 is located between the fourth source region t41 and the fourth drain region t42, the fifth channel region t53 is located between the fifth source region t51 and the fifth drain region t52, the sixth channel region t63 is located between the sixth source region t61 and the sixth drain region t62, and the seventh channel region t73 is located between the seventh source region t71 and the seventh drain region t72.

[0182] Exemplarily, the active portion of each transistor 211 included in the active layer pattern 1011 is integrally arranged.

[0183] For example, the semiconductor layer 101 can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the source region and drain region can be regions doped with n-type impurities or p-type impurities. The semiconductor layer 101 can be prepared, for example, by depositing a semiconductor material on the surface of the substrate 10 and performing an etching process to form the semiconductor layer 101, so that the semiconductor layer 101 has an active layer pattern 1011.

[0184] As shown in Figures 17A, 17B, 18A, and 18B, the first conductive layer 102 is disposed on a side of the semiconductor layer 101 away from the substrate 10 and includes a plurality of first conductive blocks 1021. The orthographic projections of the first conductive blocks 1021 on the substrate 10 overlap with the orthographic projections of one of the second source region t21 and the second drain region t22 on the substrate 10. The overlapping portion of the first conductive blocks 1021 and the second drain region t22 on the substrate 10 form the first storage capacitor C1. This simplifies the film structure and reduces manufacturing costs.

[0185] The first conductive block 1021 is connected to the other of the second source region t21 and the second drain region t22 , thereby coupling the first storage capacitor C1 and the second transistor T2 .

[0186] Exemplarily, the first conductive block 1021 is connected to the second drain region t22, and the orthographic projection of the first conductive block 1021 on the substrate overlaps with the orthographic projection of the second source region t21 on the substrate 10. The shape of the orthographic projection of the first conductive block 1021 on the substrate 10 is substantially equal to the orthographic projection of the second drain region t22 on the substrate 10.

[0187] In some examples, as shown in Figures 17A, 17B, 18A and 18B, the display panel 100 further includes a sixth block 40, which is connected to one of the second source region t21 and the second drain region t22 through a via, and is connected to the first conductive block 1021 through a via.

[0188] As shown in Figures 15A and 15B, the second conductive layer 103 is disposed on a side of the first conductive layer 102 away from the substrate 10. The second conductive layer 103 includes a first power signal line VDL, which is connected to the first conductive block 1021 and is configured to be coupled to the first voltage signal terminal VDD. In this way, the first storage capacitor C1 and the second transistor T2 can be coupled to the first voltage signal terminal VDD.

[0189] 15A and 15B , the first power signal line VDL includes alternately connected third straight segments VDL1 and third bending segments VDL2 . The third straight segments VDL1 extend along the second direction, and the third bending segments VDL2 bend toward a side along the first direction X away from the third straight segment VDL1 .

[0190] The second conductive layer 103 further includes a data line DL configured to be coupled to the data signal terminal DATA. The data line DL is coupled to the fourth source region t41 , so that the fourth transistor T4 is coupled to the data signal terminal DATA.

[0191] In some embodiments, as shown in Figures 15A and 15B , the display panel 100 further includes a third conductive layer 104. For example, the third conductive layer 104 is a first gate conductive layer. As shown in Figures 16A and 16B , the third conductive layer 104 is disposed between the semiconductor layer 101 and the first conductive layer 102. The third conductive layer 104 includes a second conductive block 1041. The orthographic projection of the second conductive block 1041 on the substrate 10 overlaps with the orthographic projection of the first channel region t13 on the substrate 10. That is, the portion of the second conductive block 1041 that overlaps with the first channel region t13 forms the gate of the first transistor T1.

[0192] In addition, as shown in Figures 17A, 17B, 18A, and 18B, the first conductive layer 102 also includes a third conductive block 1022. The orthographic projection of the third conductive block 1022 on the substrate 10 overlaps with the orthographic projection of the second conductive block 1041 on the substrate 10, and the overlapping portion forms the second storage capacitor C2. As can be seen above, the first conductive layer 102 also includes the first conductive block 1021. In other words, the first conductive block 1021 and the third conductive block 1022 are made of the same material and are disposed in the same layer. In this case, the first conductive block 1021 and the third conductive block 1022 can be formed through a single patterning process, thereby reducing manufacturing costs.

[0193] In some embodiments, as shown in Figures 17A, 17B, 18A, and 18B, the first conductive block 1021 is directly connected to the third conductive block 1022. The direct connection between the first conductive block 1021 and the third conductive block 1022 means that the first conductive block 1021 and the third conductive block 1022 are not connected via other connection structures (e.g., connection lines and connection holes).

[0194] In this way, one of the first conductive block 1021 and the third conductive block 1022 is coupled to the first power signal line through a via, so that both the first conductive block 1021 and the third conductive block 1022 can be coupled to the first power signal line, thereby reducing the number of through holes and simplifying the film layer structure of the display panel 100.

[0195] In some embodiments, as shown in FIG. 16A and FIG. 16B , the third conductive layer 104 further includes a fourth conductive block 1042 and a fifth conductive block 1043 .

[0196] The orthographic projection of the fourth conductive block 1042 on the substrate 10 overlaps with the orthographic projection of the second channel region t23 on the substrate 10. That is, the portion of the fourth conductive block 1042 overlapping with the second channel region t23 forms the gate of the second transistor T2. The orthographic projection of the fifth conductive block 1043 on the substrate 10 overlaps with the orthographic projection of the third channel region t33 on the substrate 10. That is, the portion of the fifth conductive block 1043 overlapping with the third channel region t33 forms the gate of the third transistor T3. The orthographic projection of the fourth conductive block 1042 on the substrate 10 and the orthographic projection of the fifth conductive block 1043 on the substrate 10 are staggered.

[0197] In addition, as shown in Figures 16A and 16B, the third conductive layer 104 also includes a first scan signal line GL1, a second scan signal line GL2 and a reset signal line RL. The first scan signal line GL1 is configured to be coupled to the first scan signal terminal GATE1. The positive projection of the first scan signal line GL1 on the substrate 10 overlaps with the fifth channel region t53. The portion of the first scan signal line GL1 that overlaps with the fifth channel region t53 forms the gate of the fifth transistor T5.

[0198] As shown in Figures 16A and 16B, the second scan signal line GL2 is configured to be coupled to the second scan signal terminal GATE2. The orthographic projection of the second scan signal line GL2 on the substrate 10 overlaps with the orthographic projection of the sixth channel region t63 on the substrate 10, and overlaps with the orthographic projection of the seventh channel region t73 on the substrate 10. The portion of the second scan signal line GL2 that overlaps with the sixth channel region t63 forms the gate of the sixth transistor T6, and the portion that overlaps with the seventh channel region t73 forms the gate of the seventh transistor T7.

[0199] As shown in Figures 16A and 16B, the reset signal line RL is configured to be coupled to the reset signal terminal, the orthographic projection of the reset signal line RL on the substrate 10 overlaps with the orthographic projection of the fourth channel region t43 on the substrate 10, and the portion of the reset signal line RL overlapping with the fourth channel region t43 forms the gate of the fourth transistor T4.

[0200] On this basis, as shown in Figures 15A, 15B, 17A, 17B, 18A, and 18B, the display panel 100 further includes a fourth conductive layer 105. For example, the fourth conductive layer 105 is a first source-drain conductive layer. The fourth conductive layer 105 is disposed on a side of the first conductive layer 102 away from the third conductive layer 104. The fourth conductive layer 105 includes a first light-emitting signal line EL1 and a second light-emitting signal line EL2. The first light-emitting signal line EL1 is configured to be coupled to the first light-emitting signal terminal EM1, and the second light-emitting signal line EL2 is configured to be coupled to the second light-emitting signal terminal EM2.

[0201] As shown in Figures 17A and 17B, the first light-emitting signal line EL1 includes alternating first straight segments EL11 and first curved segments EL12. The first straight segment EL11 extends along a first direction X, while the first curved segment EL12 bends toward one side of the first straight segment EL11 along a second direction Y. The orthographic projection of the first curved segment EL11 on the substrate 10 overlaps with the orthographic projection of the fourth conductive block 1042 on the substrate 10 and is connected to the fourth conductive block 1042. This arrangement couples the second transistor T2 to the first light-emitting signal terminal EM1.

[0202] 17A , 17B , 18A and 18B , in the orthographic projection onto the substrate 10 , the first straight line segment EL11 is disposed between the third conductive block 1022 and the fourth conductive block 1042 , and the first bending segment EL12 bends toward the side of the third conductive block 1022 close to the fourth conductive block 1042 .

[0203] As shown in Figures 17A, 17B, 18A, and 18B, the second light-emitting signal line EL2 includes a first straight portion EL21 and a second straight portion EL22 that are connected. The first straight portion EL21 extends along a first direction X, and the second straight portion EL22 extends along a second direction Y. The orthographic projection of the second straight portion EL22 on the substrate 10 overlaps with the orthographic projection of the fifth conductive block 1043 on the substrate 10 and is connected to the fifth conductive block 1043. This arrangement couples the third transistor T3 to the second light-emitting signal terminal EM2.

[0204] In some embodiments, as shown in FIG17A and FIG18A , the active layer patterns 1011 are arranged in multiple rows and columns. Each row of active layer patterns 1011 includes at least two active layer patterns 1011 spaced apart along the first direction X. The interval between any two adjacent active layer patterns 1011 along the first direction X is substantially equal. The orthographic projection of one fifth conductive block 1043 on the substrate 10 overlaps with the orthographic projection of one third channel region t33 on the substrate 10.

[0205] On this basis, as shown in Figures 17A and 18A, multiple second straight line portions EL22 are arranged at intervals along the first direction X. In the orthographic projection onto the substrate 10, a second straight line portion EL22 is provided between any two adjacent active layer patterns 1011. In this case, the number of second straight line portions EL22 is large, and the area occupied is large, resulting in a shorter channel region extending along the first direction X in the active layer pattern 1011, which in turn reduces the performance (e.g., carrier mobility) of the transistor including the channel region. Generally, the first channel region in the active layer pattern 1011 extends along the first direction X.

[0206] Based on this, the first channel region t13 includes a second straight segment t131 and a second curved segment t132. The second straight segment t131 extends along the first direction X, and the second curved segment t132 bends toward a side of the second straight segment t131 along the second direction Y. This increases the length of the first channel region t13, thereby improving the performance of the first transistor T1.

[0207] As shown in FIG. 15A , a plurality of first power signal lines VDL and data lines DL are arranged along a first direction X and overlap each other.

[0208] In other embodiments, as shown in Figures 16B, 17B, and 18B, the plurality of active layer patterns 1011 include a plurality of first active layer patterns 1111 and a plurality of second active layer patterns 1112. The plurality of active layer patterns 1011 are arranged in multiple rows and columns, and a row of active layer patterns 1011 is divided into multiple active layer pattern 1011 groups, each active layer pattern 1011 group including a first active layer pattern 1111 and a second active layer pattern 1112 adjacent to each other; within the same active layer pattern 1011 group, the first active layer pattern 1111 and the second active layer pattern 1112 are substantially symmetrical about a first axis S1, and the first axis S1 extends along the second direction Y.

[0209] As shown in Figures 17B and 18B, in an orthographic projection onto the substrate 10, the orthographic projection of one fifth conductive block 1043 on the substrate 10 overlaps with both the third channel region t33 in the first active layer pattern 1111 and the third channel region t33 in the second active layer pattern 1112 of two adjacent active layer pattern groups. When the fifth conductive block 1043 is coupled to the second light-emitting signal line EL2 through a via, the number of vias can be reduced, simplifying the film structure.

[0210] On this basis, the second straight line portions EL22 are arranged at intervals along the first direction X. In an orthographic projection onto the substrate 10, a second straight line portion EL22 is provided between any two adjacent active layer pattern groups. In this manner, the number of second straight line portions EL22 is small, and the area they occupy is small, thereby ensuring that the length of the channel region extending along the first direction X in the active layer pattern 1011 is appropriate, thereby improving the performance of the transistor including this channel region.

[0211] Based on this, the extension direction of the first channel region t13 is parallel to the first direction X. In this case, the performance of the first transistor T1 is better.

[0212] As shown in FIG. 17B and FIG. 18B , the sixth block 40 is coupled to one of the second source region and the second drain region in the first active layer pattern 1111 through a via hole, and is coupled to the second drain region t22 through a via hole.

[0213] The first conductive block 1021 overlapping the first active layer pattern 1111 is directly connected to the first conductive block 1021 overlapping the second active layer pattern 1112 belonging to the same group as the first active layer pattern 1111. The first conductive block 1021 is coupled to the sixth block 40 through a via.

[0214] As shown in FIG15B , among the plurality of first power signal lines VDL, two first power signal lines VDL respectively connected to two pixel circuits 21 in the same pixel circuit group are grouped together. The two first power signal lines VDL in a first power signal line group are symmetrical about the first axis S1. In this case, the third bending segment VDL2 bends away from the other first power signal lines VDL in the same group.

[0215] Among the multiple data lines DL, two data lines DL connected to two pixel circuits 21 in the same pixel circuit group constitute a data line group. The two data lines DL in a data line group are symmetrical about the first axis S1. A data line group is located between two first power signal lines VDL in a first power signal line group.

[0216] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0217] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A pixel circuit comprising: a driving subcircuit coupled to the first node, the second node, and the third node; The driving sub-circuit is configured to control the conduction and cutoff of the second node and the third node under the control of the potential of the first node; and, generating a driving current according to the potential of the first node and the potential of the second node; a first light-emitting subcircuit coupled to the first voltage signal terminal, the first light-emitting signal terminal, and the second node; the first light-emitting subcircuit configured to control conduction and cutoff of the first voltage signal terminal and the second node in response to a first light-emitting signal received at the first light-emitting signal terminal; a second light-emitting subcircuit coupled to the third node, the second light-emitting signal terminal, and the anode of the light-emitting device; the second light-emitting subcircuit configured to control the conduction and cutoff of the third node and the anode of the light-emitting device in response to a second light-emitting signal received at the second light-emitting signal terminal; a first reset sub-circuit coupled to a reset signal terminal, the first node, and the first initialization signal terminal; the first reset sub-circuit being configured to control conduction and cutoff of the first initialization signal terminal and the first node in response to a reset signal received at the reset signal terminal; a compensation sub-circuit coupled to the first node, the third node, and a first scan signal terminal; the compensation sub-circuit configured to control the conduction and cutoff of the first node and the third node in response to a first scan signal received at the first scan signal terminal; The first storage sub-circuit is coupled to the first voltage signal terminal and the second node; the first storage sub-circuit is configured to store the potential of the second node.

2. The pixel circuit according to claim 1, wherein: In a display frame period, the first voltage signal terminal and the second node start to conduct earlier than the third node and the anode of the light-emitting device start to conduct; The first voltage signal terminal and the second node start to be cut off earlier than the third node and the anode of the light emitting device start to be cut off.

3. The pixel circuit according to claim 1, wherein: The first storage sub-circuit includes: A first storage capacitor, wherein a first plate of the first storage capacitor is connected to the first voltage signal terminal, and a second plate of the first storage capacitor is connected to the second node.

4. The pixel circuit according to any one of claims 1 to 3, further comprising: a second reset subcircuit coupled to the second initialization signal terminal, the anode of the light-emitting device, and the second scan signal terminal; the second reset subcircuit configured to control the conduction and cutoff of the anode of the light-emitting device and the second initialization signal terminal in response to a second scan signal received at the second scan signal terminal; A data writing sub-circuit is coupled to the second node, the third scanning signal terminal and the data signal terminal; the data writing sub-circuit is configured to control the conduction and cutoff of the data signal terminal and the second node in response to a third scanning number received at the third scanning signal terminal.

5. The pixel circuit according to claim 3, wherein: The second scanning signal terminal and the third scanning signal terminal receive the same signal. The pixel circuit according to claim 2 , wherein: The first light-emitting sub-circuit includes a second transistor, and the second light-emitting sub-circuit includes a third transistor. The first electrode of the second transistor is coupled to the first plate of the first storage capacitor, the second electrode is coupled to the second plate of the first storage capacitor, and the control electrode is coupled to the first light-emitting signal terminal; the first electrode of the third transistor is coupled to the third node, the second electrode is coupled to the anode of the light-emitting device, and the control electrode is coupled to the second light-emitting signal terminal EM2.

7. A method for driving a pixel circuit, for driving the pixel circuit according to any one of claims 1 to 6, wherein a display frame period includes a reset phase; The driving method includes: In the reset phase, the first reset sub-circuit transmits the first initialization signal received at the first initialization signal terminal to the first node in response to the reset signal received at the reset signal terminal; The compensation subcircuit transmits the potential at the first node to the third node in response to the first scanning signal received at the first scanning signal terminal, the second light-emitting subcircuit transmits the potential at the third node to the anode of the light-emitting device in response to the second light-emitting signal received at the second light-emitting signal terminal, and the first storage subcircuit stores the potential of the second node after the end of the previous frame.

8. The driving method of the pixel circuit according to claim 7, wherein the reset phase comprises a first reset phase and a second reset phase; In the first reset phase, the first reset sub-circuit transmits the first initialization signal received at the first initialization signal terminal to the first node in response to the reset signal received at the reset signal terminal; The second light emitting sub-circuit transmits the potential at the third node to the anode of the light emitting device in response to the second light emitting signal received at the second light emitting signal terminal; In the second reset phase, the compensation sub-circuit transmits the potential at the first node to the third node in response to the first scan signal received at the first scan signal terminal; The second light emitting sub-circuit transmits the potential at the third node to the anode of the light emitting device in response to the second light emitting signal received at the second light emitting signal terminal.

9. The driving method of a pixel circuit according to claim 7 or 8, wherein the pixel circuit further comprises a second reset subcircuit and a write subcircuit; and after the reset phase, a display frame period further comprises a data write compensation phase; During the data writing compensation phase, the data writing sub-circuit transmits the data signal received at the data signal terminal to the second node in response to the third scanning number received at the third scanning signal terminal; the compensation sub-circuit transmits the potential at the second node to the first node in response to the first scanning signal received at the first scanning signal terminal; the second reset sub-circuit transmits the second initialization signal received at the second initialization signal terminal to the anode of the light-emitting device in response to the second scanning number received at the second scanning signal terminal.

10. A display panel comprising a plurality of pixel circuits, each of the pixel circuits comprising a second transistor; the second transistor being coupled to a first voltage signal terminal; The display panel includes: substrate; a semiconductor layer disposed on the substrate and comprising a second active portion of the second transistor, the second active portion comprising a second source region, a second drain region, and a second channel region, the second channel region being disposed between the second source region and the second drain region; a first conductive layer, disposed on a side of the semiconductor layer away from the substrate, and comprising a plurality of first conductive blocks; An orthographic projection of the first conductive block on the substrate overlaps with an orthographic projection of one of the second source region and the second drain region on the substrate, and the overlapping portion of the two forms a first storage capacitor; the first conductive block is connected to the other of the second source region and the second drain region; The second conductive layer is disposed on a side of the first conductive layer away from the substrate and includes a first power signal line connected to the first conductive block and coupled to the first voltage signal terminal.

11. The display panel according to claim 10, wherein: The pixel circuit further includes a first transistor, the semiconductor layer further includes a first active portion of the first transistor, the first active portion includes a first source region, a first drain region, and a first channel region, and the first channel region is disposed between the first source region and the first drain region; The display panel further includes: a third conductive layer, disposed between the semiconductor layer and the first conductive layer, and comprising a second conductive block, wherein an orthographic projection of the second conductive block on the substrate overlaps with an orthographic projection of the first channel region on the substrate; The first conductive layer further includes a third conductive block, the orthographic projection of the third conductive block on the substrate overlaps with the orthographic projection of the second conductive block on the substrate, and the overlapping portion of the third conductive block and the second storage capacitor is formed.

12. The display panel according to claim 11, wherein: The first conductive block and the third conductive block are directly connected.

13. The display panel according to claim 11 or 12, wherein the pixel circuit further comprises a third transistor, wherein the third transistor is connected to an anode of the light emitting device; in, The semiconductor layer further includes a third active portion of the third transistor, the third active portion including a third source region, a third drain region, and a third channel region, and the third channel region is disposed between the third source region and the third drain region; The third conductive layer further includes a fourth conductive block and a fifth conductive block; The orthographic projection of the fourth conductive block on the substrate overlaps with the orthographic projection of the second channel region on the substrate, and the orthographic projection of the fifth conductive block on the substrate overlaps with the orthographic projection of the third channel region on the substrate; wherein, the orthographic projection of the fourth conductive block on the substrate and the orthographic projection of the fifth conductive block on the substrate are staggered.

14. The display panel according to claim 13, further comprising a fourth conductive layer; The fourth conductive layer is disposed on a side of the first conductive layer away from the third conductive layer, and includes: A first light-emitting signal line is coupled to the first light-emitting signal end; the first light-emitting signal line includes a first straight line segment and a first bent segment that are alternately connected; the first straight line segment extends along a first direction, and the first bent segment bends toward one side of the first straight line segment along the second direction, and the orthographic projection of the first bent segment on the substrate overlaps with the orthographic projection of the fourth conductive block on the substrate, and is connected to the fourth conductive block.

15. The display panel according to claim 13, further comprising a fourth conductive layer; The fourth conductive layer is disposed on a side of the first conductive layer away from the third conductive layer, and includes: A second light-emitting signal line is coupled to the second light-emitting signal end; the second light-emitting signal line includes a first straight portion and a second straight portion connected to each other; the first straight portion extends along the first direction, and the second straight portion extends along the second direction; the orthographic projection of the second straight portion on the substrate overlaps with the orthographic projection of the fifth conductive block on the substrate, and is connected to the fifth conductive block.

16. The display panel according to claim 15, wherein: The active layer patterns are arranged in multiple rows and columns, each row of active layer patterns includes at least two active layer patterns arranged at intervals along the first direction, and along the first direction, the intervals between any two adjacent active layer patterns are substantially equal; each column of active layer patterns includes at least two active layer patterns arranged at intervals along the second direction; An orthographic projection of the fifth conductive block on the substrate overlaps with an orthographic projection of the third channel region on the substrate.

17. The display panel according to claim 16, wherein: Along the first direction, in the orthographic projection onto the substrate, a second straight line portion is arranged between any two adjacent active layer patterns, and the first channel region includes a second straight line segment and a second bending segment; the second straight line segment extends along the first direction, and the second bending segment bends toward one side of the second straight line segment along the second direction.

18. The display panel according to claim 15, wherein: The plurality of active layer patterns include a plurality of first active layer patterns and a plurality of second active layer patterns; The plurality of active layer patterns are arranged into a plurality of rows and columns, a row of active layer patterns is divided into a plurality of active layer pattern groups, and an active layer pattern group includes a first active layer pattern and a second active layer pattern that are adjacent to each other; In the same active layer pattern group, the first active layer pattern and the second active layer pattern are substantially symmetrical about a first axis, the first axis extends along a second direction, and the second direction intersects the first direction; In an orthographic projection onto the substrate, an orthographic projection of one of the fifth conductive blocks on the substrate overlaps with the third channel region in the first active layer pattern and the third channel region in the second active layer pattern of two adjacent active layer pattern groups.

19. The display panel according to claim 18, wherein: In an orthographic projection onto the substrate, a second straight line portion is provided between any two adjacent active layer pattern groups; and an extension direction of the first channel region is parallel to the first direction.

20. A display device comprising the display panel according to any one of claims 10 to 19.

Images