Central processing unit and accelerator interaction method and apparatus, and electronic device

Abstract

The present disclosure provides a central processing unit and accelerator interaction method and apparatus, and an electronic device. The method comprises: when it is determined that there is a data transmission requirement, sending a command to a register of an accelerator by means of a command interface, so that the accelerator executes the command, wherein the register is a local random access memory in the accelerator; and receiving an execution result of the accelerator executing the command. Thus, the central processing unit can directly send a command to the accelerator by means of the command interface, and receives an execution result fed back by the accelerator, so as to complete data transmission, so that the data transmission speed and efficiency can be improved.

Description

Method, device and electronic device for interaction between central processing unit and accelerator

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on and claims the priority of Chinese patent application with application number 202410365390.6 and application date March 28, 2024. The entire content of the Chinese patent application is hereby incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the technical field of computer processors, and in particular to a method, device, and electronic device for interaction between a central processing unit and an accelerator. Background Art

[0004] With the rapid development of highly compute-intensive applications such as artificial intelligence, scientific computing, video processing, network transmission, and signal processing, the demand for chip data processing capabilities is increasing. In addition to leveraging radical superscalar, multi-core, and multi-threading technologies to fully exploit instruction set and thread-level parallelism, many chips are using AI (artificial intelligence) processors, graphics processing units (GPUs), digital signal processing units (DSPs), data processing units (DPUs), cryptographic accelerators, and stream processors as accelerators, along with general-purpose CPUs (central processing units) as heterogeneous cores in multi-core processors, further developing data-level parallelism (DLP).

[0005] Among them, data transmission between the central processing unit and the accelerator is achieved through DDR (Double Data Rate SDRAM, double-rate synchronous dynamic random access memory, i.e. memory). The transmission speed is slow, affecting the efficiency of data transmission, which is an urgent problem that needs to be solved. Summary of the Invention

[0006] The present disclosure provides a method, device, and electronic device for interaction between a central processing unit and an accelerator, aiming to solve at least one of the technical problems in the related art to a certain extent.

[0007] In a first aspect, an embodiment of the present disclosure provides a method for interaction between a central processing unit and an accelerator, the method comprising:

[0008] When it is determined that there is a data transmission demand, a command is sent to a register of the accelerator through a command interface so that the accelerator executes the command, wherein the register is a local random access memory inside the accelerator;

[0009] Receive the execution result of the accelerator execution command.

[0010] In one possible implementation, in the method provided in the embodiment of the present disclosure, the command includes a blocking mode and a non-blocking mode.

[0011] In one possible implementation, the method provided in the embodiment of the present disclosure further includes:

[0012] A consistent access channel is set between the central processing unit and the accelerator, so that the accelerator can directly access the memory of the central processing unit through the consistent access channel.

[0013] In one possible implementation, in the method provided in an embodiment of the present disclosure, when it is determined that there is a data transmission requirement, sending a command to a register of the accelerator through a command interface includes:

[0014] In response to the first control instruction, a first command is sent to the register through the command interface, where the first command is used to instruct to store the first data into the accelerator.

[0015] In one possible implementation, in the method provided in an embodiment of the present disclosure, when it is determined that there is a data transmission requirement, sending a command to a register of the accelerator through a command interface includes:

[0016] In response to the second control instruction, a second command is sent to the register through the command interface, where the second command is used to instruct to obtain second data from the accelerator.

[0017] In one possible implementation, in the method provided in an embodiment of the present disclosure, a specific address space and a command queue are set in the register. When it is determined that there is a data transmission requirement, a command is sent to the register of the accelerator through the command interface, including:

[0018] In response to the third control instruction, storing the command in a specific address space of the accelerator; or

[0019] In response to the third control instruction, storing the command in the command queue; or

[0020] In response to the fourth control instruction, if it is determined that the accelerator has completed executing the current command, a command is sent to the accelerator.

[0021] In one possible implementation, in the method provided by the embodiment of the present disclosure, after storing the command in the command queue in response to the third control instruction, the method further includes:

[0022] When there are no empty items in the command queue, it is determined that the command queue is full;

[0023] Stop sending commands and continue monitoring the command queue until there is an empty item in the command queue, then store the command in the command queue.

[0024] In one possible implementation, in the method provided in the embodiment of the present disclosure, when there is no empty item in the command queue, determining that the command queue is full includes:

[0025] Upon receiving an abnormal instruction fed back by the accelerator, determining that the command queue is full; / or

[0026] receiving a return value of the command, and determining that the command queue is full if the return value is a first preset value indicating that the command was not successfully executed; / or

[0027] If the judgment instruction configured to check whether the queue has an empty item indicates that there is no empty item, it is determined that the command queue is full; or

[0028] If the execution time of the command is greater than or equal to the preset first command timeout, it is determined that the command queue is full. In one possible implementation, the method provided by the embodiment of the present disclosure continuously monitors the command queue until there is an empty item in the command queue, and then stores the command in the command queue, including:

[0029] When receiving an abnormal instruction, if it is determined that there is an empty item in the command queue, the command is stored in the command queue; / or

[0030] receiving a return value, and if the return value is a second preset value indicating successful command execution, determining that there is an empty item in the command queue, then storing the command in the command queue; / or

[0031] If the judgment instruction set for checking whether there is an empty item in the queue indicates that there is an empty item, it is determined that there is an empty item in the command queue, and the command is stored in the command queue; / or

[0032] If the execution time of the command is less than the first command timeout time, it is determined that there is an empty item in the command queue, and the command is stored in the command queue.

[0033] In one possible implementation, in the method provided in the embodiment of the present disclosure, in response to the fourth control instruction, when it is determined that the accelerator has completed executing the current command, sending a command to the accelerator includes:

[0034] If the execution time of the command is greater than or equal to the preset second command timeout time, stop sending the command; / or receive the return value of the command, if the return value is a third preset value indicating that the command was not executed successfully, stop sending the command.

[0035] In one possible implementation, the method provided in the embodiment of the present disclosure further includes:

[0036] If the command execution time is less than the second command timeout period, resume sending the command; / or

[0037] A return value of the command is received, and if the return value is a fourth preset value indicating successful execution of the command, sending the command is resumed.

[0038] In a second aspect, an embodiment of the present disclosure provides a central processing unit and an accelerator interaction device, comprising:

[0039] A sending unit, configured to send a command to a register of the accelerator through a command interface when determining that there is a data transmission demand, so that the accelerator executes the command, wherein the register is a local random access memory inside the accelerator;

[0040] The receiving unit is used to receive the execution result of the accelerator execution command.

[0041] In one possible implementation, in the apparatus provided by the embodiment of the present disclosure, the command includes a blocking mode and a non-blocking mode.

[0042] In one possible implementation, in the apparatus provided by the embodiment of the present disclosure, the sending unit is specifically configured to:

[0043] A consistent access channel is set between the central processing unit and the accelerator, so that the accelerator can directly access the memory of the central processing unit through the consistent access channel.

[0044] In one possible implementation, in the apparatus provided by the embodiment of the present disclosure, the sending unit is specifically configured to:

[0045] In response to the first control instruction, a first command is sent to the register through the command interface, where the first command is used to instruct to store the first data into the accelerator.

[0046] In one possible implementation, in the apparatus provided by the embodiment of the present disclosure, the sending unit is specifically configured to:

[0047] In response to the second control instruction, a second command is sent to the register through the command interface, where the second command is used to instruct to obtain second data from the accelerator.

[0048] In one possible implementation, in the apparatus provided by the embodiment of the present disclosure, a specific address space and a command queue are set in the register, and the sending unit is specifically configured to:

[0049] In response to the third control instruction, storing the command in a specific address space of the accelerator; or

[0050] In response to the third control instruction, storing the command in the command queue; or

[0051] In response to the fourth control instruction, if it is determined that the accelerator has completed executing the current command, a command is sent to the accelerator.

[0052] In one possible implementation, in the apparatus provided by the embodiment of the present disclosure, the sending unit is specifically configured to:

[0053] When there are no empty items in the command queue, it is determined that the command queue is full;

[0054] Stop sending commands and continue monitoring the command queue until there is an empty item in the command queue, then store the command in the command queue.

[0055] In one possible implementation, in the apparatus provided in the embodiment of the present disclosure, the sending unit is specifically configured to:

[0056] Upon receiving an abnormal instruction fed back by the accelerator, determining that the command queue is full; / or

[0057] receiving a return value of the command, and determining that the command queue is full if the return value is a first preset value indicating that the command was not successfully executed; / or

[0058] If the judgment instruction configured to check whether the queue has an empty item indicates that there is no empty item, it is determined that the command queue is full; or

[0059] If the execution time of the command is greater than or equal to the preset first command timeout time, it is determined that the command queue is full.

[0060] In one possible implementation, in the apparatus provided by the embodiment of the present disclosure, the sending unit is specifically configured to:

[0061] When receiving an abnormal instruction, if it is determined that there is an empty item in the command queue, the command is stored in the command queue; / or

[0062] receiving a return value, and if the return value is a second preset value indicating successful command execution, determining that there is an empty item in the command queue, then storing the command in the command queue; / or

[0063] If the judgment instruction set for checking whether there is an empty item in the queue indicates that there is an empty item, it is determined that there is an empty item in the command queue, and the command is stored in the command queue; / or

[0064] If the execution time of the command is less than the first command timeout time, it is determined that there is an empty item in the command queue, and the command is stored in the command queue.

[0065] In one possible implementation, in the apparatus provided by the embodiment of the present disclosure, the sending unit is specifically configured to:

[0066] If the execution time of the command is greater than or equal to the preset second command timeout time, stop sending the command; / or receive the return value of the command, if the return value is a third preset value indicating that the command was not executed successfully, stop sending the command.

[0067] In one possible implementation, in the apparatus provided by the embodiment of the present disclosure, the sending unit is specifically configured to:

[0068] If the command execution time is less than the second command timeout period, resume sending the command; / or

[0069] A return value of the command is received, and if the return value is a fourth preset value indicating successful execution of the command, sending the command is resumed.

[0070] In a third aspect, an embodiment of the present disclosure provides an electronic device comprising: at least one processor, at least one memory, and computer program instructions stored in the memory, which, when executed by the processor, implement the method provided in the first aspect of the embodiment of the present disclosure.

[0071] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having computer program instructions stored thereon, which implements the method provided in the first aspect of the embodiment of the present disclosure when the computer program instructions are executed by a processor.

[0072] In the disclosed embodiments, when data transmission is required between the central processing unit and the accelerator, the central processing unit sends a command to the accelerator via a command interface and receives the result of the accelerator's execution of the command. Thus, the central processing unit can directly send a command to the accelerator via the command interface and receive the result of the execution fed back by the accelerator, completing the data transmission, thereby improving data transmission speed and efficiency.

[0073] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] The above and / or additional aspects and advantages of the present disclosure will become apparent and readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0075] FIG1 is a flow chart of a method for interaction between a central processing unit and an accelerator provided by an embodiment of the present disclosure;

[0076] FIG2 is a schematic diagram of an interaction between a central processing unit and an accelerator provided by an embodiment of the present disclosure;

[0077] FIG3 is a structural diagram of a central processing unit and accelerator interaction device provided by an embodiment of the present disclosure;

[0078] FIG4 illustrates a block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure. DETAILED DESCRIPTION

[0079] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other in the absence of conflict.

[0080] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0081] The rapid advancement of semiconductor technology has led to ever-increasing microprocessor speeds and integration densities. This has resulted in a continuous increase in the number and variety of transistor resources available to processor designers. From an architectural perspective, more processor designs are moving towards on-chip multiprocessors, with an increasing number of integrated processor cores. From an application perspective, the rapid development of computationally intensive applications such as artificial intelligence, scientific computing, video processing, network transmission, and signal processing is placing increasing demands on chip data processing capabilities. In addition to leveraging aggressive superscalar, multi-core, and multi-threading technologies to fully exploit instruction set and thread-level parallelism, many chips are integrating accelerators alongside general-purpose processors (CPUs) as heterogeneous cores within multicore processors, further exploiting data-level parallelism (DLP). Accelerators typically utilize multifunctional components and wide datapath architectures to enhance their computational capabilities and exploit data-level parallelism, requiring CPU control. A challenge with heterogeneous architectures is that the interaction between control flow and data flow can become a bottleneck for the overall architecture.

[0082] Accelerators include domain processors, function accelerators, and application scenario accelerators. Examples include AI processors, graphics processors (GPUs), digital signal processors (DSPs), data processors (DPUs), stream processors, network processors, image signal processors (ISPs), display processors, encryption and decryption accelerators, audio accelerators, video codec accelerators, various mathematical operation accelerators, convolution operation accelerators, and matrix operation accelerators.

[0083] Memory, also known as internal storage or main memory, is a crucial component of a computer. It temporarily stores data processed by the CPU (Central Processing Unit) and exchanges data with external storage devices such as hard drives. Memory serves as the bridge between the CPU and peripherals, and all computer programs run in memory. As soon as the computer starts running, the operating system transfers the required data from memory to the CPU for computation. Once the computation is complete, the CPU transmits the result.

[0084] The CPU (Central Processing Unit), Accelerator, DDR (Double Data Rate SDRAM), and PCIe (Peripheral Component Interconnect express) are connected through a bus, and the SSD (Solid State Disk) is connected to the PCIe.

[0085] For example, when the CPU and GPU work together to process data, they first read the data from the SSD via PCIe and store it in the DDR. The GPU then reads the required data from the DDR for processing and returns the processed data to the DDR. The CPU then reads the GPU-processed data from the DDR and returns it to the DDR. Once the data is processed, it is transferred back to the SSD via PCIe.

[0086] Since the data transmission between the CPU and the accelerator is achieved through DDR transit, which is data interaction at the memory level, the transmission speed is slow, which affects the efficiency of data transmission.

[0087] Based on this, embodiments of the present disclosure provide a method, apparatus, and electronic device for interaction between a central processing unit (CPU) and an accelerator. In response to a data transmission requirement between the CPU and the accelerator, the CPU sends a command to the accelerator via a command interface and receives feedback from the accelerator regarding the execution result of the command. This allows the CPU to directly send commands to the accelerator via the command interface and receive feedback from the accelerator regarding the execution result, completing data transmission and improving data transmission speed and efficiency.

[0088] It should be noted that the execution entity of the central processing unit and accelerator interaction method of this embodiment can be a central processing unit and accelerator interaction device, which can be implemented by software and / or hardware. The device can be configured in an electronic device, and the electronic device can include but is not limited to a terminal, a server, etc.

[0089] FIG1 is a flow chart of a method for interaction between a central processing unit and an accelerator according to an embodiment of the present disclosure. As shown in FIG1 , the method includes:

[0090] S101: When it is determined that there is a data transmission requirement, a command is sent to a register of the accelerator through a command interface.

[0091] In the embodiment of the present disclosure, when there is a need for data transmission between the central processing unit and the accelerator, the central processing unit can directly send commands to the register inside the accelerator through the command interface.

[0092] Among them, there is a data transmission demand between the central processing unit and the accelerator. The central processing unit may need to store data in the accelerator, or the central processing unit may need to read data from the accelerator, or the central processing unit may need to store data in the accelerator and read data from the accelerator at the same time, etc. The embodiments of the present disclosure do not impose specific restrictions on this.

[0093] Exemplarily, the central processing unit can execute a first control instruction, which is a custm_load instruction. At this time, the command sent by the central processing unit can instruct to fetch data from the local random access memory (SRAM) of the accelerator to the vector / fixed-point / floating-point register. The address space corresponding to the instruction is exclusive, and the CPU can only access the corresponding accelerator.

[0094] Exemplarily, the central processing unit can execute the second control instruction, which is the custm_store instruction. At this time, the command sent by the central processing unit can instruct to store the data in the vector / fixed-point / floating-point register into the SRAM of the accelerator. The address space corresponding to the instruction is exclusive, and the CPU can only access the corresponding accelerator.

[0095] Exemplarily, the central processing unit may execute a third control instruction, which is a custm_sendcmd instruction. At this time, the central processing unit may send a command to the accelerator without waiting for the command in the accelerator to be executed.

[0096] For example, the central processing unit may execute a fourth control instruction, which is a custm_sendcmdwaitfinish instruction. At this time, the central processing unit sends a command to the accelerator and must wait for the accelerator to finish executing the command (a timeout exception may also be set).

[0097] In some embodiments, a command interface is provided on the central processing unit, and the central processing unit can directly send commands to the accelerator through the command interface.

[0098] In the disclosed embodiment, the central processing unit can directly send commands to the accelerator through a command interface provided on the central processing unit, thereby establishing an efficient data path and control path between the central processing unit and the accelerator, realizing data transmission, and improving data transmission speed and efficiency.

[0099] For example, the control path: The CPU can control the accelerator through commands, and some instructions are reserved for custom functions, supporting blocking mode and / or non-blocking mode. In blocking mode, the CPU waits for the accelerator to complete the previous command before sending the next command to the accelerator for execution. In non-blocking mode, the CPU does not need to wait for the accelerator to complete the previous command before sending the next command to the accelerator for execution.

[0100] For example, the data path: The CPU can support direct data interaction with inter-accelerator registers and SPM (scratchpad memory) levels. A customized CPU interface for accessing DSA memory is provided. A consistent access channel is provided: This allows accelerators to access consistent memory areas.

[0101] S102: Receive the execution result of the accelerator execution command.

[0102] In the embodiment of the present disclosure, when data transmission is required between the central processing unit and the accelerator, the central processing unit can send commands to the register of the accelerator through the command interface, and can also receive the execution results fed back by the accelerator when executing the commands.

[0103] In some embodiments, the central processing unit executes a first control instruction, and the command sent by the central processing unit is used to instruct the first data to be stored in the accelerator, and the execution result fed back by the accelerator execution command is received, including: receiving the execution result of the first data stored fed back by the accelerator execution command; or receiving the execution result of the first data storage failure fed back by the accelerator execution command; or receiving the execution result of the failure to store the first data due to insufficient accelerator storage space fed back by the accelerator execution command.

[0104] The first control instruction may be a custm_store instruction.

[0105] In an embodiment of the present disclosure, the central processing unit executes a first control instruction, and the command sent by the central processing unit to the accelerator can be used to instruct the first data to be stored in the accelerator. In this case, after receiving the command, the accelerator can execute the command and store the first data.

[0106] The accelerator may successfully store the first data, or the accelerator may fail to store the first data when the storage space of the accelerator is insufficient to store the first data.

[0107] It can be understood that when the first data is successfully stored, the accelerator feeds back the execution result to the central processor, and can feed back the execution result of the stored first data to the central processor, thereby, the central processor can receive the execution result of the stored first data fed back by the accelerator execution command.

[0108] It can also be understood that in the event of a first data storage failure, the accelerator feeds back the execution result to the central processor, and can feed back the execution result of the first data storage failure to the central processor, thereby the central processor can receive the execution result of the first data storage failure fed back by the accelerator execution command.

[0109] It can also be understood that when the size of the remaining storage space in the accelerator is smaller than the data size of the first data, the storage space of the accelerator is insufficient to store the first data. The accelerator feeds back the execution result to the central processing unit, and can feed back to the central processing unit the execution result that the storage of the first data failed due to insufficient storage space of the accelerator. Thus, the central processing unit can receive the execution result fed back by the accelerator execution command that the storage of the first data failed due to insufficient storage space of the accelerator.

[0110] For example, when the central processing unit executes a first control instruction, which is a custm_store instruction, the command sent by the central processing unit to the accelerator may instruct to store specific data in a vector / fixed-point / floating-point register into the accelerator. When the accelerator receives the command, it may feedback to the central processing unit that the specific data has been stored, or feedback that the storage of the specific data has failed, or feedback that the accelerator storage space is insufficient to store the specific data, and so on.

[0111] In some embodiments, the central processing unit executes a second control instruction, and the command sent by the central processing unit is used to instruct the acquisition of second data from the accelerator, and receives the execution result feedback from the accelerator execution command, including: receiving the execution result including the second data fed back by the accelerator execution command; or receiving the execution result of the failure to obtain the second data fed back by the accelerator execution command; or receiving the execution result of the failure to read the second data fed back by the accelerator execution command.

[0112] The second control instruction may be a custm_load instruction.

[0113] In the embodiment of the present disclosure, the command sent by the central processing unit to the accelerator may be used to instruct the accelerator to obtain the second data. In this case, after receiving the command, the accelerator may execute the command and read the second data.

[0114] If the second data is stored in the accelerator, the accelerator can read the second data by executing the command. If the second data is not stored in the accelerator, the accelerator may fail to read the second data by executing the command.

[0115] It can be understood that when the second data is successfully read, the accelerator feeds back the execution result to the central processor, and can feed back the execution result including the second data to the central processor, thereby, the central processor can receive the execution result including the second data fed back by the accelerator execution command.

[0116] It can also be understood that when the first data reading fails, the accelerator feeds back the execution result to the central processing unit, and can feed back the execution result of the failure to obtain the second data to the central processing unit. Thus, the central processing unit can receive the execution result of the failure to obtain the second data fed back by the accelerator execution command.

[0117] It can also be understood that when the second data is not read, the accelerator feeds back the execution result to the central processing unit, and can feed back the execution result of not reading the second data to the central processing unit. Thus, the central processing unit can receive the execution result of not reading the second data fed back by the accelerator execution command.

[0118] Exemplarily, when the central processing unit executes the second control instruction, and the second control instruction is the custm_load instruction, the command sent by the central processing unit to the accelerator can instruct to read specific data from the accelerator. When the accelerator receives the command, it can feedback the specific data to the central processing unit, or feedback that the specific data acquisition failed, or feedback that the specific data was not read, and so on.

[0119] By implementing the disclosed embodiments, in response to a data transmission requirement between the central processing unit and the accelerator, the central processing unit sends a command to the accelerator via a command interface; the central processing unit receives the execution result fed back by the accelerator after executing the command. Thus, the central processing unit can directly send a command to the accelerator via the command interface and receive the execution result fed back by the accelerator, completing the data transmission, thereby improving data transmission speed and efficiency.

[0120] In some embodiments, in order to transmit data between the central processing unit and the accelerator, a command queue can be set up in the register of the accelerator, or a space can be allocated in the register of the accelerator to store commands, so that the central processing unit can send multiple commands to the accelerator without having to wait for the accelerator to complete execution after sending a command before sending the next command, which can improve processing efficiency.

[0121] In some embodiments, sending a command to the accelerator includes:

[0122] The central processing unit executes the third control instruction and stores the command in a specific address space; or

[0123] The central processing unit executes the third control instruction and stores the command in the command queue; or

[0124] The central processing unit executes the fourth control instruction, and sends a command to the accelerator when it is determined that the accelerator has completed executing the current command.

[0125] In the embodiment of the present disclosure, the central processing unit sends a command to the accelerator through the command interface. When the central processing unit executes the third control instruction, which is the custm_sendcmd instruction, the central processing unit can store the command in a specific address space.

[0126] In some embodiments, the specific address space may be a space in a dedicated address space of the accelerator, and may store commands.

[0127] In some embodiments, the accelerator executes commands stored in a specific address space, and can execute them in the order in which the commands are stored, or can execute them in order from high to low priority based on the priority of the commands, or can execute them in order from high to low priority based on the priority of the commands and the order in which they are stored, and from early to late storage order, and so on.

[0128] In the embodiment of the present disclosure, the central processing unit sends a command to the accelerator through the command interface. When the central processing unit executes the third control instruction, which is the custm_sendcmd instruction, the central processing unit may store the command in the command queue.

[0129] In some embodiments, as shown in FIG2 , a command queue is set between the central processing unit and the accelerator, and the commands sent by the central processing unit to the accelerator can be stored in the command queue.

[0130] In an embodiment of the present disclosure, the central processing unit sends a command to the accelerator through the command interface. When the central processing unit executes the fourth control instruction and the third control instruction is the custm_sendcmdwaitfinish instruction, the central processing unit can send a command to the accelerator when it determines that the accelerator has completed executing the current command.

[0131] In some embodiments, the central processing unit executes the third control instruction to store the command in the specific address space, including: the central processing unit determines that the specific address space is not full; and the central processing unit stores the command in the specific address space.

[0132] In the embodiment of the present disclosure, the central processing unit stores the command in the specific address space, and may store the command in the specific address space when it is determined that the specific address space is not full.

[0133] It is understandable that the size of the specific address space is limited and can only store a limited number of commands. If it is determined that the specific address space is not full, the commands can be stored in the specific address space.

[0134] In some embodiments, the specific address space is not full, which may mean that there is still space in the specific address space, or that the remaining space in the specific address space is sufficient to store the command.

[0135] In some embodiments, the central processing unit executes the third control instruction to store the command in the command queue, including: the central processing unit determines that the command queue is not full; and the central processing unit stores the command in the command queue.

[0136] In the embodiment of the present disclosure, the central processing unit stores the command in the command queue, and may store the command in the command queue when it is determined that the command queue is not full.

[0137] It is understandable that the number of commands that can be stored in the command queue is limited. It can only store a limited number of commands. If it is determined that the command queue is not full, the command can be stored in the command queue.

[0138] In some embodiments, the central processing unit determines that the command queue is not full, including: the central processing unit determines that there is an empty item in the command queue, and determines that the command queue is not full.

[0139] In the embodiment of the present disclosure, the central processing unit determines that the command queue is not full. It can determine that the command queue is not full when it determines that there are empty items in the command queue, or it can determine that the command queue is not full when it determines that the empty items in the command queue are sufficient to store commands.

[0140] In some embodiments, the above method further includes: the central processing unit determines that the command queue is full, and determines to stop sending commands.

[0141] In the embodiment of the present disclosure, the central processing unit may determine to stop sending commands when determining that the command queue is full.

[0142] In some embodiments, the central processing unit determines that the command queue is full, including: the central processing unit determines that there are no empty items in the command queue, and determines that the command queue is full; or determines that the command queue is full because there are no empty items in the command queue and the command waiting to be stored in the command queue reaches a preset time.

[0143] In the embodiment of the present disclosure, the central processing unit determines that the command queue is full. This may be determined when it is determined that there is no empty item in the command queue.

[0144] In the embodiment of the present disclosure, the central processing unit determines that the command queue is full. This may be determined because there is no empty item in the command queue and the command waiting to be stored in the command queue reaches a preset time.

[0145] For example, a command queue (command FIFO) is provided between the central processing unit and the accelerator, and the instruction defaults to sending commands to the command queue. There is no need to wait for the command in the accelerator to complete execution. The CPU sends the command to the command queue until the command queue is full.

[0146] The CPU determines whether the command queue is full. The judgment conditions are: if the command queue has no empty items, or the number of commands stored in the command queue is greater than the number of empty items in the command queue, the command queue is determined to be full.

[0147] When the command queue is not full, the command is sent to the command queue.

[0148] When the command queue is full, you can use the following processing methods:

[0149] A. The command reports an exception. The command returns an exception to the CPU, and the CPU stops sending commands until there is an empty item in the command queue.

[0150] B. This command is designed with a return value given point register, and the return value is the first return value and the second return value. Specifically, 0 and 1 can be used to indicate whether the command is set successfully, or other values ​​can be used to indicate it. The embodiment of the present disclosure does not limit this. In one example, if the command queue is full, the command returns a return value of 0 to the central processing unit, indicating that the command is not set successfully. If the command queue is not full, the command returns a return value of 1 to the central processing unit, indicating that the command is set successfully.

[0151] C. Design a judgment instruction to check whether there is an empty item in the command queue. If there is an empty item, the CPU will send the command to the command queue. If there is no empty item, the CPU will stop sending commands until the command queue has an empty item.

[0152] D. The command is set to execute the first timeout period. This command waits until it is sent to the command queue. If the waiting time exceeds the first timeout period, an exception is reported and returned to the CPU. The CPU stops sending commands until there is an empty item in the command queue.

[0153] In some embodiments, the method further includes: the central processing unit determines that a feedback instruction of the accelerator executing the current command is received, and the feedback instruction indicates that the current command has been executed, and determines that the accelerator has completed executing the current command.

[0154] In an embodiment of the present disclosure, the central processing unit sends a command to the accelerator when it determines that the accelerator has completed executing the current command. Specifically, when it determines that a feedback instruction of the accelerator executing the current command is received and the feedback instruction indicates that the current command has been executed, it can be determined that the accelerator has completed executing the current command.

[0155] In some embodiments, the method further includes: the central processing unit determines that no feedback instruction of the accelerator executing the current command is received within a specific time after the current command is issued, and determines that an abnormality occurs in the execution of the current command.

[0156] In the embodiment of the present disclosure, when the central processing unit determines that no feedback instruction of the accelerator executing the current command is received within a specific time after the current command is issued, it can determine that an abnormality occurs in the execution of the current command.

[0157] For example, the CPU needs to wait for the command in the accelerator to be executed before sending the command to the accelerator. If the command in the accelerator is not executed, the CPU waits.

[0158] The following processing methods can also be added:

[0159] 1. Set the timeout period for executing the second command. If the command execution time exceeds the timeout period, an exception will be reported to the CPU.

[0160] 2. This command is designed with a return value given point register, and the return value is the third return value and the fourth return value. Specifically, 0 and 1 can be used to indicate whether the command is set successfully, or other values ​​can be used to indicate it. The embodiment of the present disclosure does not limit this. In one example, if the command in the accelerator has not been executed, the command returns a return value of 0 to the central processing unit, indicating that the command has not been set successfully. If the command in the accelerator has been executed, the command returns a return value of 1 to the central processing unit, indicating that the command has been set successfully.

[0161] By implementing the embodiments of the present disclosure, the central processing unit can directly send commands to the accelerator through the command interface and receive the execution results fed back by the accelerator to complete data transmission, thereby improving data transmission speed and efficiency.

[0162] In order to implement the above embodiments, the present disclosure further proposes a central processing unit and accelerator interaction device.

[0163] As shown in FIG3 , the central processing unit and accelerator interaction device includes a sending unit 301 and a receiving unit 302 .

[0164] The sending unit 301 is configured to send a command to the register of the accelerator through the command interface when determining that there is a data transmission demand, so that the accelerator executes the command, wherein the register is a local random access memory inside the accelerator;

[0165] The receiving unit 302 is configured to receive the execution result of the accelerator execution command.

[0166] In one possible implementation, in the apparatus provided by the embodiment of the present disclosure, the command includes a blocking mode and a non-blocking mode.

[0167] In a possible implementation, in the apparatus provided by the embodiment of the present disclosure, the sending unit 301 is specifically configured to:

[0168] In response to the first control instruction, a first command is sent to the register through the command interface, where the first command is used to instruct to store the first data into the accelerator.

[0169] In a possible implementation, in the apparatus provided by the embodiment of the present disclosure, the sending unit 301 is specifically configured to:

[0170] In response to the second control instruction, a second command is sent to the register through the command interface, where the second command is used to instruct to obtain second data from the accelerator.

[0171] In one possible implementation, in the apparatus provided by the embodiment of the present disclosure, a specific address space and a command queue are set in the register, and the sending unit 301 is specifically configured to:

[0172] In response to the second control instruction, a second command is sent to the accelerator through the command interface, where the second command is used to instruct to obtain second data from the accelerator.

[0173] In a possible implementation, in the apparatus provided by the embodiment of the present disclosure, the sending unit 301 is specifically configured to:

[0174] In response to the third control instruction, storing the command in a specific address space of the accelerator; or

[0175] In response to the third control instruction, storing the command in the command queue; or

[0176] In response to the fourth control instruction, if it is determined that the accelerator has completed executing the current command, a command is sent to the accelerator.

[0177] In a possible implementation, in the apparatus provided by the embodiment of the present disclosure, the sending unit 301 is specifically configured to:

[0178] When there are no empty items in the command queue, it is determined that the command queue is full;

[0179] Stop sending commands and continue monitoring the command queue until there is an empty item in the command queue, then store the command in the command queue.

[0180] In a possible implementation, in the apparatus provided by the embodiment of the present disclosure, the sending unit 301 is specifically configured to:

[0181] Upon receiving an abnormal instruction fed back by the accelerator, determining that the command queue is full; / or

[0182] receiving a return value of the command, and determining that the command queue is full if the return value is a first preset value indicating that the command was not successfully executed; / or

[0183] If the judgment instruction configured to check whether the queue has an empty item indicates that there is no empty item, it is determined that the command queue is full; or

[0184] If the execution time of the command is greater than or equal to the preset first command timeout time, it is determined that the command queue is full.

[0185] In a possible implementation, in the apparatus provided by the embodiment of the present disclosure, the sending unit 301 is specifically configured to:

[0186] When receiving an abnormal instruction, if it is determined that there is an empty item in the command queue, the command is stored in the command queue; / or

[0187] receiving a return value, and if the return value is a second preset value indicating successful command execution, determining that there is an empty item in the command queue, then storing the command in the command queue; / or

[0188] If the judgment instruction set for checking whether there is an empty item in the queue indicates that there is an empty item, it is determined that there is an empty item in the command queue, and the command is stored in the command queue; / or

[0189] If the execution time of the command is less than the first command timeout time, it is determined that there is an empty item in the command queue, and the command is stored in the command queue.

[0190] In a possible implementation, in the apparatus provided by the embodiment of the present disclosure, the sending unit 301 is specifically configured to:

[0191] If the execution time of the command is greater than or equal to the preset second command timeout time, stop sending the command; / or receive the return value of the command, if the return value is a third preset value indicating that the command was not executed successfully, stop sending the command.

[0192] In a possible implementation, in the apparatus provided by the embodiment of the present disclosure, the sending unit 301 is specifically configured to:

[0193] If the command execution time is less than the second command timeout period, resume sending the command; / or

[0194] A return value of the command is received, and if the return value is a fourth preset value indicating successful execution of the command, sending the command is resumed.

[0195] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0196] In order to implement the above embodiments, the present disclosure further proposes a computer program product. When the instruction processor in the computer program product executes, the central processing unit and accelerator interaction method proposed in the above embodiments of the present disclosure is executed.

[0197] Figure 4 shows a block diagram of an exemplary electronic device suitable for implementing the embodiments of the present disclosure. The electronic device 12 shown in Figure 4 is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0198] 4 , the electronic device 12 is implemented as a general-purpose computing device. Components of the electronic device 12 may include, but are not limited to, one or more processors 16 , a system memory 28 , and a bus 18 connecting various system components (including the system memory 28 and the processor 16 ).

[0199] Bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus architectures. Examples of these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnection (PCI) bus.

[0200] The electronic device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the electronic device 12, including volatile and non-volatile media, removable and non-removable media.

[0201] Memory 28 may include computer-readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. Electronic device 12 may further include other removable / non-removable, volatile / non-volatile computer-readable storage media. By way of example only, storage system 34 may be configured to read and write to non-removable, non-volatile magnetic media (not shown in FIG. 4 , and commonly referred to as a "hard drive").

[0202] Although not shown in FIG4 , a disk drive for reading and writing to a removable non-volatile disk (e.g., a floppy disk) and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a Compact Disc Read Only Memory (CD-ROM), a Digital Video Disc Read Only Memory (DVD-ROM), or other optical media) can be provided. In these cases, each drive can be connected to the bus 18 via one or more data media interfaces. The memory 28 can include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of various embodiments of the present disclosure.

[0203] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may include an implementation of a network environment. Program modules 42 generally implement the functions and / or methods of the embodiments described herein.

[0204] The electronic device 12 can also communicate with one or more external devices 14 (e.g., a keyboard, pointing device, display 24, etc.), one or more devices that enable a user to interact with the electronic device 12, and / or any device that enables the electronic device 12 to communicate with one or more other computing devices (e.g., a network card, a modem, etc.). This communication can occur via an input / output (I / O) interface 22. Furthermore, the electronic device 12 can communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network such as the Internet) via a network adapter 20. As shown, the network adapter 20 communicates with other modules of the electronic device 12 via the bus 18. It should be understood that, although not shown, other hardware and / or software modules can be used in conjunction with the electronic device 12, including but not limited to microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0205] The processor 16 executes various functional applications by running programs stored in the system memory 28, such as implementing the central processing unit and accelerator interaction method mentioned in the above embodiment.

[0206] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0207] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

[0208] It should be noted that, in the description of this disclosure, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance. In addition, in the description of this disclosure, unless otherwise specified, the meaning of "plurality" is two or more.

[0209] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present disclosure belong.

[0210] It should be understood that various parts of the present disclosure can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0211] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0212] In addition, the functional units in the various embodiments of the present disclosure may be integrated into a single processing module, or each unit may exist physically separately, or two or more units may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or in the form of software functional modules. If the integrated modules are implemented in the form of software functional modules and sold or used as independent products, they may also be stored in a computer-readable storage medium.

[0213] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0214] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0215] Although the embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are illustrative and are not to be construed as limitations on the present disclosure. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present disclosure.

Claims

1. A method for interaction between a central processing unit and an accelerator, characterized in that: The method comprises: When it is determined that there is a data transmission demand, sending a command to a register of the accelerator through a command interface so that the accelerator executes the command, wherein the register is a local random access memory inside the accelerator; Receive an execution result of the command executed by the accelerator.

2. The method according to claim 1, characterized in that The command includes a blocking mode and a non-blocking mode.

3. The method according to claim 1, characterized in that The method further comprises: A consistent access channel is set between the central processing unit and the accelerator, so that the accelerator can directly access the memory of the central processing unit through the consistent access channel.

4. The method according to claim 1, wherein When it is determined that there is a data transmission requirement, sending a command to a register of the accelerator through a command interface includes: In response to a first control instruction, a first command is sent to the register through the command interface, where the first command is used to instruct to store first data into the accelerator.

5. The method according to claim 4, characterized in that When it is determined that there is a data transmission requirement, sending a command to a register of the accelerator through a command interface includes: In response to a second control instruction, a second command is sent to the register through a command interface, where the second command is used to instruct to obtain second data from the accelerator.

6. The method according to any one of claims 4 or 5, characterized in that The register is provided with a specific address space and a command queue. When it is determined that there is a data transmission requirement, a command is sent to the register of the accelerator through the command interface, including: In response to a third control instruction, storing the command in the specific address space; or In response to a third control instruction, storing the command in the command queue; or In response to a fourth control instruction, if it is determined that the accelerator has completed executing the current command, the command is sent to the accelerator.

7. The method according to claim 6, characterized in that After storing the command in the command queue in response to the third control instruction, the method further includes: When there is no empty item in the command queue, determining that the command queue is full; Stop sending the command, and continue monitoring the command queue until there is an empty item in the command queue, and then store the command in the command queue.

8. The method according to claim 7, characterized in that When there is no empty item in the command queue, determining that the command queue is full includes: Upon receiving the abnormal instruction fed back by the accelerator, determining that the command queue is full; / or receiving a return value of the command, and determining that the command queue is full if the return value is a first preset value indicating that the command was not successfully executed; / or If the judgment instruction configured to check whether the queue has an empty item indicates that there is no empty item, it is determined that the command queue is full; or If the execution time of the command is greater than or equal to the preset first command timeout time, it is determined that the command queue is full.

9. The method according to claim 8, characterized in that The continuously monitoring the command queue until an empty item exists in the command queue, and storing the command in the command queue, comprises: When the abnormal instruction stops being received, it is determined that there is an empty item in the command queue, and the command is stored in the command queue; / or receiving the return value, and if the return value is a second preset value indicating that the command is successfully executed, determining that there is an empty item in the command queue, and storing the command in the command queue; / or If the judgment instruction set for checking whether there is an empty item in the queue indicates that there is an empty item, it is determined that there is an empty item in the command queue, and the command is stored in the command queue; / or If the execution duration of the command is less than the first command timeout duration, it is determined that there is an empty item in the command queue, and the command is stored in the command queue.

10. The method according to claim 6, characterized in that The step of sending the command to the accelerator in response to the fourth control instruction and upon determining that the accelerator has completed executing the current command includes: If the execution time of the command is greater than or equal to the preset second command timeout time, stop sending the command; / or A return value of the command is received, and if the return value is a third preset value indicating that the command was not successfully executed, sending the command is stopped.

11. The method according to claim 10, characterized in that The method further comprises: If the execution time of the command is less than the timeout period of the second command, resume sending the command; / or A return value of the command is received, and if the return value is a fourth preset value indicating that the command is successfully executed, sending the command is resumed.

12. A central processing unit and accelerator interaction device, characterized in that: The device comprises: a sending unit, configured to, when determining that there is a data transmission demand, send a command to a register of the accelerator through a command interface so that the accelerator executes the command, wherein the register is a local random access memory inside the accelerator; A receiving unit is used to receive an execution result of the command executed by the accelerator.

13. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 11.

14. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 11.

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