Monolithic device including a transistor and a capacitor that are co-integrated onto a diamond-based substrate, and process for producing such a device

Abstract

The invention relates to a monolithic device (200), including a field-effect transistor (100) and a capacitor (150), comprising: - a carrier substrate (50); - an active layer (40) made of single-crystal diamond containing p-type dopants, in which active layer the conduction channel (41) of the transistor (100) is formed, and which active layer is arranged on the carrier substrate (50); - a stack comprising a first conductive layer (10) and a second conductive layer (20) made of single-crystal diamond containing p-type dopants, and an intermediate layer (30) made of electrically insulating single-crystal diamond, the intermediate layer being between the first and second conductive layers, which form first and second contacts (11, 21) of the capacitor (150), respectively. The first conductive layer (10) has an epitaxial interface (61) with the active layer (40); it is structured and forms a source electrode (12) and a drain electrode (13) of the transistor (100).

Description

Monolithic device including a transistor and a capacitor cointegrated on a diamond-based substrate, and method of manufacturing such a device FIELD OF THE INVENTION

[0001] The present invention relates to the field of microelectronics and semiconductors. In particular, the invention relates to a device comprising a transistor and at least one capacitor, monolithically integrated on a diamond-based substrate, said device being suitable for power applications. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] Monocrystalline diamond is a very wide bandgap semiconductor. It has properties and characteristics that theoretically allow the production of power components, such as diodes, transistors and capacitors, with performances not previously achieved with other semiconductors. A transistor made on diamond makes it possible to drastically reduce switching losses, which allows a power converter to operate at very high frequencies (typically beyond 1 MHz). At these frequencies, the voltage switching edges are very steep and each switching at the terminals of the transistor generates an overvoltage of several hundred or even several thousand volts; this requires an oversizing of the transistor voltage compared to the initial specification of the converter. SUBJECT OF THE INVENTION

[0003] The present invention makes it possible to limit this overvoltage at the terminals of the transistor during switching by adding one or more high-voltage capacitors. The invention relates to a monolithic device including at least one transistor and at least one capacitor, co-integrated on diamond. The invention also relates to a method for monolithic integration of a transistor and at least one capacitor on a diamond-based substrate. BRIEF DESCRIPTION OF THE INVENTION

[0004] The present invention relates to a monolithic device including a field effect transistor and at least one capacitor, comprising:

[0005] - a support substrate,

[0006] - an active layer of monocrystalline diamond comprising p-type dopants, in which the conduction channel of the transistor is formed, the active layer extending parallel to a main plane and being arranged on the support substrate,

[0007] - a stack comprising a first conductive layer and a second conductive layer of monocrystalline diamond comprising p-type dopants, and an intermediate layer of monocrystalline diamond, electrically insulating, interposed between the first conductive layer and the second conductive layer, the first conductive layer and the second conductive layer respectively forming a first and a second contact of the capacitor.

[0008] Further, the first conductive layer has an epitaxial interface with the active layer; and the first conductive layer is structured in a plane parallel to the principal plane and forms a source electrode and a drain electrode of the transistor.

[0009] According to advantageous characteristics of the invention, taken alone or in any feasible combination: the active layer has a boron concentration of between 10 15 / cm 3 and 1019 / cm 3 ,the first conductive layer and the second conductive layer have a boron concentration greater than 10 19 / cm 3 ,the intermediate layer has a nitrogen or phosphorus concentration of between 10 14 / cm 3 and 10 21 / cm 3,the first conductive layer and the second conductive layer have a thickness, along an axis normal to the main plane, of between 5 nm and 50 μm, preferably between 50 nm and 1 μm, the intermediate layer has a thickness, along an axis normal to the main plane, of between 10 nm and 2 mm, preferably between 500 nm and 50 μm, the active layer has a thickness, along an axis normal to the main plane, of between 100 nm and 20 μm, preferably between 100 nm and 5 μm, the support substrate has a resistivity greater than 10 kohm.cm,the capacitor is connected in parallel with the transistor,the support substrate is made of monocrystalline diamond or comprises a surface film of monocrystalline diamond, and an epitaxial interface is defined between said support substrate and the active layer,a bonding interface is defined between the support substrate and the active layer,the support substrate comprises monocrystalline or polycrystalline diamond, and / or monocrystalline or polycrystalline silicon carbide, and / or a dielectric film adjacent to the bonding interface.

[0010] The invention also relates to a method of manufacturing a monolithic device as above, comprising the following steps:

[0011] (a) the provision of the support substrate,

[0012] b) the formation of the active layer on the support substrate,

[0013] c) the formation of the first conductive layer on the active layer by epitaxial growth,

[0014] d) the formation of the intermediate layer on the first conductive layer,

[0015] e) the formation of the second conductive layer on the intermediate layer,

[0016] f) structuring the second conductive layer, the intermediate layer and the first conductive layer in the principal plane, to form the capacitor, adjacent to the transistor, and defining the source electrode of the transistor, the drain electrode of the transistor and the first contact of the capacitor in the first conductive layer.

[0017] According to advantageous characteristics of the invention, taken alone or in any feasible combination: the source and the first contact, or the drain and the first contact are electrically connected by continuity of the first conductive layer, the sequence of steps c), d), e) is repeated N times to form N stacked capacitors, the support substrate is made of monocrystalline diamond or comprises a surface film of monocrystalline diamond, and step b) is carried out by epitaxial growth, in particular by implementing a microwave plasma-assisted chemical vapor deposition technique, step b) is carried out by transfer of the active layer onto the support substrate, step b) comprises the following sub-steps: - the implantation of light species of the hydrogen, helium type or a combination of these two species into a donor substrate, to define a buried fragile plane, - the assembly of the donor substrate onto the support substrate via a bonding interface,- separation along the buried fragile plane leading to the transfer of a useful layer, originating from the donor substrate and intended to form the active layer, onto the support substrate.,

[0018] Other characteristics and advantages of the invention will emerge from the detailed description which follows with reference to the appended figures in which:

[0019]

[0020]

[0021] Figures 1a, 1b and 1c show embodiments of a monolithic device according to the invention,

[0022]

[0023]

[0024]

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[0026]

[0027]

[0028] Figures 2a, 2b, 2c, 2d, 2e, 2f and 2f' show a first embodiment of the manufacturing method, in accordance with the present invention;

[0029]

[0030]

[0031]

[0032]

[0033]

[0034]

[0035]

[0036]

[0037]

[0038] Figures 3a, 3b, 3b', 3b'', 3b''', 3c, 3d, 3e, 3f and 3f' show a second mode of implementation of the manufacturing method, in accordance with the invention.

[0039] The figures are schematic representations which, for readability purposes, are not to scale. In particular, the layer thicknesses along the z axis are not to scale with the lateral dimensions along the x and y axes.

[0040] The same references in the figures or in the description may be used for elements of the same nature. DETAILED DESCRIPTION OF THE INVENTION

[0041] The invention relates to a monolithic device 200 including at least one field effect transistor 100 (JFET, MESFET, MOSFET, ...) and at least one capacitor 150, said components being monolithically cointegrated on a diamond-based substrate (,,).

[0042] The device 200 comprises an active layer 40 made of monocrystalline diamond comprising p-type dopants, an active layer in which the conduction channel 41 of the transistor 100 is formed. The active layer 40, like the other layers and stack described later, extends parallel to a main plane (x,y) and has a thickness along a z axis normal to said plane.

[0043] Preferably, the active layer 40 has a boron concentration of between 10 15 / cm 3 and 10 19 / cm 3 ; its thickness is typically between 100 nm and 20 μm, preferably between 100 nm and 5 μm.

[0044] The device 200 also includes a monocrystalline diamond stack comprising a first conductive layer 10, a second conductive layer 20 and an electrically insulating intermediate layer 30, interposed between the first conductive layer 10 and the second conductive layer 20.

[0045] The first conductive layer 10 and the second conductive layer 20 comprise p-type dopants and have a resistivity typically between 1 mohm.cm and 10 kohm.cm, advantageously less than or equal to 1 ohm.cm, less than or equal to 100 mohm.cm, or even less than or equal to 10 mohm.cm. Preferably, the first conductive layer 10 and the second conductive layer 20 therefore have a boron concentration typically greater than 10 19 / cm 3 They respectively form a first 11 and a second 21 contact of the capacitor 150.

[0046] The intermediate layer 30 advantageously comprises deep n-type dopants producing energy levels located more than 0.4 eV from the diamond conduction band. The intermediate layer 30 may have a nitrogen or phosphorus concentration of between 10 14 / cm 3 and 10 21 / cm 3 These species constitute deep donors for diamond and will give the intermediate layer 30 a resistivity greater than 10 kohm.cm.

[0047] The first 10 and second 20 conductive layers typically have a thickness of between 5 nm and 50 μm, preferably between 50 nm and 1 μm. The thickness of the intermediate layer 30 may be between 10 nm and 2 mm, preferably between 500 nm and 50 μm.

[0048] In the monolithic device 200, the first conductive layer 10 comprises an epitaxial interface 61 with the active layer 40. The first conductive layer 10 is structured in a plane parallel to the main plane (x,y), so as to form on the one hand a source electrode 12 of the transistor 100 and on the other hand a drain electrode 13.

[0049] Thus, in the same plane parallel to the main plane (x,y), the source electrode 12, the drain electrode 13 of the transistor 100 and the first contact 11 of the capacitor 150 are defined in the first conductive layer 10.

[0050] The capacitor 150 is preferably connected in parallel with the transistor 100. The RC circuit (capacitor 150), mounted in parallel with the switch (transistor 100) protects the terminals of the latter from switching overvoltages.

[0051] As illustrated in Figures 1a to 1c, the source 12 of the transistor 100 and the first contact 11 of the capacitor 150 are electrically connected. This connection, made possible by the production of a single continuous layer (the first conductive layer 10), is particularly advantageous because it avoids the addition of unfavorable connections in terms of parasitic inductances. The drain 13 of the transistor 100 is connected to the second contact 21 of the capacitor 150 (not illustrated in the figures), either by wire connection or by metal interconnection (involving an additional lithography level, a passivation layer and metallization).

[0052] Alternatively, drain 13 could be connected to first contact 11 and source 12 to second contact 21.

[0053] As illustrated in Figures 1a, 1b, 1c, the monolithic device 200 comprises a support substrate 50. Preferably, the support substrate 50 has a resistivity greater than 10 kohm.cm. The use of a support substrate 50 capable of providing good insulation is advantageous in the present case of lateral architecture of the transistor 100, to avoid current leaks, via the support substrate 50, and to allow the efficient closing of the conduction channel 41 by application of the gate voltage. This also makes it possible to increase the blocking voltage of the transistor at a given gate-drain length of the transistor 100 and at a given active layer thickness 40.

[0054] The support substrate 50 may comprise one or more materials chosen from monocrystalline or polycrystalline diamond, monocrystalline or polycrystalline silicon carbide, or a dielectric material.

[0055] The active layer 40 is arranged on the support substrate 50. The first conductive layer 10 is arranged on the active layer 40 and the epitaxial interface 61 is defined between the first conductive layer 10 and the active layer 40. Said first conductive layer 10 is structured in a plane parallel to the main plane (x,y) to form the source electrode 12 of the transistor 100, the drain electrode 13 of the transistor 100 and the first contact 11 of the capacitor 150. The intermediate layer 30 is arranged on the first contact 11 of the capacitor 150. Finally, the second conductive layer 20 is arranged on the intermediate layer 30.

[0056] The gate electrode G of the transistor 100 is formed on the active layer 40, between the source 12 and drain 13 electrodes.

[0057] This configuration of the device 200 greatly simplifies its manufacturing process and allows efficient monolithic cointegration of one (or more) transistor(s) and one (or more) capacitor(s). The synergy of developing the transistor(s) and the capacitor(s), with a low number of stacked layers due to the multifunctionality of said layers, is also an advantage for obtaining high-quality layers.

[0058] This monolithic integration is also advantageous in that the two components 100,150 benefit from excellent heat transfer due to the thermal conductivity properties of diamond. In addition, the geographical proximity of the components 100,150 makes it possible to considerably reduce parasitic inductances.

[0059] According to a first embodiment (), an epitaxial interface 63 is defined between the support substrate 50 and the active layer 40. In this case, the support substrate 50 is formed from monocrystalline diamond or comprises a surface film (on the side of its face intended to receive the active layer 40) from monocrystalline diamond, to allow growth by epitaxy of the active layer 40, during the development of the monolithic device 200.

[0060] According to a second embodiment (,), a bonding interface 71 is defined between the support substrate 50 and the active layer 40. In this case, the support substrate 50 can be formed from a very wide variety of materials. Advantageously, it comprises a dielectric film 51, adjacent to the bonding interface 71, which makes it possible to guarantee or improve the vertical insulation between the active layer 40 and the support substrate 50.

[0061] The manufacturing method of the monolithic device 200 will now be described. It comprises a step a) consisting of providing the support substrate 50 (,). As mentioned previously, the support substrate 50 may comprise one or more materials chosen from monocrystalline or polycrystalline diamond, monocrystalline or polycrystalline silicon carbide, or a dielectric material. The nature of the support substrate 50 may nevertheless be constrained according to the different modes of implementation of the subsequent step b) of the method.

[0062] The support substrate 50 may be in the form of a circular wafer, as is usually the case in the field of microelectronics, with a diameter of 25mm, 50mm, 100mm, 150mm or 200mm. Its thickness is typically between 50 μm and 900 μm, preferably between 200 μm and 700 μm. Of course, the support substrate 50 is not limited to the aforementioned shape and dimensions, and may also be in a square or rectangular form with smaller or larger dimensions.

[0063] It is manufactured using a known technique such as HPHT (High Pressure High Temperature) or CVD (Chemical Vapor Deposition).

[0064] Advantageously, the support substrate 50 has a resistivity greater than 10 kohm.cm.

[0065] The method then comprises a step b) corresponding to the formation of the active layer 40 on the support substrate 50, by epitaxial growth, according to a first embodiment (), or by thin layer transfer, according to a second embodiment (,','',''').

[0066] The active layer 40 in monocrystalline diamond, intended to form the conduction channel 41 of the transistor 100, is preferably expected with a boron concentration (p-type dopants) of between 10 15 / cm 3 and 10 19 / cm 3 , and with a thickness typically between 100 nm and 20 μm, preferably between 100 nm and 5 μm.

[0067] In the first embodiment, a support substrate 50 made of monocrystalline diamond is required to allow epitaxial growth of the active layer 40, itself intended to be made of monocrystalline diamond. The support substrate 50 can then be entirely monocrystalline, or consist of a composite structure 50' including a base substrate 501 and a surface film 502 made of monocrystalline diamond which will serve as a seed for the epitaxial growth (). The composite structure 50' offers more flexibility as to the nature of the base substrate 501, which can be polycrystalline or monocrystalline of lower quality or even made of a material different from that of the surface film 502. This type of composite structure 50' can in particular be produced by a thin layer transfer process such as the Smart Cut process TM, which involves implantation of light ions into a donor substrate, direct assembly between said donor substrate and the base substrate, and finally, separation along the buried fragile plane formed by the implantation; this leads to the transfer of a surface film 502 from the donor substrate, onto the base substrate 501.

[0068] In the remainder of this description, only the case of a solid support substrate 50 will be described and illustrated, for simplification; this obviously does not exclude the option mentioned of a composite structure 50'.

[0069] Epitaxial growth according to the first embodiment of step b) can be carried out by any known technique, preferably by a microwave plasma-enhanced chemical vapor deposition (MW-PECVD) technique. Parameters such as pressure in the deposition chamber, temperature, gases and microwave power can be defined in the following ranges:

[0070] - Pressure: between 100 Pascal and 100 kiloPascal;

[0071] - Temperature: between 500 and 1200°C;

[0072] - Power: between 50 Watts and 10 kWatts;

[0073] - Gases: methane, hydrogen, trimethyl borane, diborane, dioxygen, dinitrogen, argon, phosphine and trimethyl phosphine.

[0074] An epitaxial interface 63 is created between the active layer 40 and the support substrate 50 (). The front face of the support substrate 50, which serves as a seed for the growth of the active layer 40, is chosen so as to provide excellent crystalline quality to said active layer 40.

[0075] In the second embodiment, the choice of the nature of the support substrate 50 is more flexible, because the active layer 40 is transferred via a direct bonding interface onto said substrate 50 and therefore does not require a growth seed. The support substrate 50 is preferably chosen so as to minimize the difference in thermal expansion compared to a monocrystalline diamond substrate.

[0076] To carry out the transfer, the following sub-steps can be implemented. First, an implantation of light species of hydrogen, helium type or a combination of these two species is carried out in a donor substrate 4 made of monocrystalline diamond whose characteristics and properties correspond to those expected for the active layer 40. These implanted species will define a buried fragile plane 1, according to the principal plane (x,y), in the donor substrate 4 ('). An implantation energy between 10 keV and 250 keV, and an implantation dose between 1.10 16 / cm 2 and 1.10 18 / cm 2may be used to form a buried fragile plane 1 at a depth of between 10 nm and 1500 nm, more particularly between a few tens of nm and 1000 nm. Note that a protective layer may be deposited on the donor substrate 4 before ion implantation. Similarly, cleaning sequences may be applied before and / or after the implantation sub-step, so as to eliminate potential particulate, hydrocarbon or metallic contamination. The protective layer may be retained or removed prior to the next sub-step.

[0077] The implanted donor substrate 4 is then assembled, by molecular adhesion, on the support substrate 50 via a direct bonding interface 71 (''). A dielectric film 51 may be raw or deposited on the support substrate 50 prior to assembly ('''). The role of this film 51 may be to facilitate bonding or to improve the adhesion forces of the interface 72; it may also have an electrical (vertical insulation) or thermal (improvement of thermal conductivity) function in the targeted device 200.

[0078] In the remainder of the description of the method, this dielectric film 51 will not be illustrated for reasons of simplification of the figures.

[0079] The faces to be assembled of the donor substrates 4 and support 50 advantageously undergo cleaning (for example, RCA) and / or surface activations (in particular by N2 or O2 plasma) so as to improve the quality and mechanical strength of the bonding interface 71. Direct bonding by molecular adhesion does not require an adhesive material, since bonds are established at the atomic scale between the assembled surfaces. Several types of bonding by molecular adhesion exist, which differ in particular by their temperature, pressure, atmosphere or treatment conditions, prior to bringing the surfaces into contact. We can cite bonding at room temperature with or without prior plasma activation of the surfaces to be assembled, bonding by atomic diffusion ("Atomic diffusion bonding" or ADB according to the English terminology), bonding with surface activation ("Surface-activated bonding" or SAB), etc.

[0080] Finally, the sub-step of separation along the buried fragile plane 1 is usually carried out by applying a heat treatment, at a temperature between 400°C and 1200°C. Such a heat treatment induces the development of cavities and microcracks in the buried fragile plane 1, and their pressurization by the light species present in gaseous form, until the propagation of a fracture along said fragile plane 1. Alternatively or jointly, a mechanical stress can be applied to the bonded assembly and in particular at the level of the buried fragile plane 1, so as to propagate or help to mechanically propagate the fracture leading to the separation. When the separation is complete, a useful layer 40' is obtained, originating from the donor substrate 4 and intended to form the active layer 40, transferred onto the support substrate 50 (). The free face of the useful layer 40' is usually rough after separation.Heat treatments or surface treatments can be applied to it to improve the crystalline quality of the layer and its surface roughness, and thus obtain the active layer 40.

[0081] When standard implantation energies are used, the useful layer 40' has a thickness of less than 2 μm after separation. If the active layer 40 is expected to have a greater thickness, an epitaxial growth sub-step (for example by MW-PECVD) can be carried out to increase this thickness.

[0082] Returning to the general description of the method, once the active layer 40 has been formed on the surface of the support substrate 50, a step c) corresponding to the formation of the first conductive layer 10 on the active layer 40 is carried out (,).

[0083] Preferably and as mentioned above in the description of the monolithic device 200, the first conductive layer 10 has a boron concentration greater than 10 19 / cm 3 and a thickness between 5 nm and 50 μm, preferably between 50 nm and 1 μm.

[0084] This step can be carried out by any known technique allowing epitaxial growth, preferably by a MW-PECVD deposition technique. Parameters in the same ranges of values ​​as previously mentioned can be used.

[0085] An epitaxial interface 61 is then defined between the first conductive layer 10 and the active layer 40. The active layer 40 having very good crystalline quality, the same is true for the first conductive layer 10.

[0086] The next step d) corresponds to the formation of the intermediate layer 30 on the first conductive layer 10 (,).

[0087] Preferably, the intermediate layer 30 has a nitrogen or phosphorus concentration of between 10 14 / cm 3 and 10 21 / cm 3 The thickness of the intermediate layer 30 may be between 10 nm and 2 mm, preferably between 500 nm and 50 μm.

[0088] Like the previous step c), step d) can be carried out by any technique allowing epitaxial growth, advantageously by a MW-PECVD deposition technique. An epitaxial interface 61' is then created between the intermediate layer 30 and the first conductive layer 10.

[0089] The next step e) corresponds to the formation of the second conductive layer 20 on the intermediate layer 30 (,).

[0090] Preferably, the second conductive layer 20 has a boron concentration greater than 10 19 / cm 3and a thickness between 5 nm and 50 μm, preferably between 50 nm and 1 μm (as mentioned previously).

[0091] Like the two previous steps, step e) can be carried out by any technique allowing epitaxial growth, preferably by a MW-PECVD deposition technique. An epitaxial interface 61'' is then defined between the second conductive layer 20 and the intermediate layer 30.

[0092] Optionally, the sequence of steps c), d), e) is repeated N times to form N stacked capacitors. By connecting them in parallel in the final device 200, it is then possible to increase the value of the capacitance, depending on the needs of the application.

[0093] Advantageously, this sequence of steps c), d), e) is carried out in the deposition chamber of an MW-PECVD equipment, without exit to the ambient atmosphere, so as to avoid any contamination. If one or more exits to the ambient atmosphere had to be made, cleaning would be required before returning to the deposition chamber so as to rid the surface of particulate, metallic or hydrocarbon contamination.

[0094] Finally, the manufacturing method comprises a step f) of structuring the conductive layers 10, 20 and the intermediate layer 30 in the main plane (x, y). It is based on successive local etchings of the three layers 20, 30, 10, making it possible to form the capacitor 150, adjacent to the transistor 100, and to define the source electrode 12, the drain electrode 13 of the transistor 100 and the first contact 11 of the capacitor 150 in the first conductive layer 10 (,). In the figures, the source 12 of the transistor 100 and the first contact 11 of the capacitor 150 are electrically connected by continuity of the first conductive layer 10, with the aim of connecting the capacitor 150 in parallel with the transistor 100. Other electrical connection modes could of course be implemented to connect the source 12 and the first contact 11, the continuity of the first conductive layer 10 remaining the simplest and most effective option.

[0095] To locally etch the layers, a mask, for example made of silicon nitride, is deposited and structured on the surface of the second conductive layer 20 by photolithography and etching, so as to mask only the areas in which the second conductive layer 20 must be preserved. The etching of the second conductive layer 20 can be carried out by dry etching, for example by oxygen plasma.

[0096] In the examples of figures 2f and 3f, the etching of the intermediate layer 30 can be carried out while keeping the same mask, because the design of the capacitor 150 provides that the second conductive layer 20 covers the entirety of the intermediate layer 30. The etching of the intermediate layer 30 can be carried out by dry etching (plasma).

[0097] A second mask must then be deposited and structured, to define the areas to be etched of the first conductive layer 10. The first mask can be removed prior to the formation of the second mask, or at the end of step f) at the same time as the second mask. The same etching solutions as for the second conductive layer 20 can be used to structure the first conductive layer 10.

[0098] After removing the masks, the device 200 comprises the capacitor 150 in the vicinity of the transistor 100, as well as the source 12 and drain 13 electrodes of said transistor 100 (,).

[0099] Step f) may optionally comprise the formation of insulation between the region of the active layer 40 under the transistor 100, and the region of the active layer 40 under the capacitor 150. For this, trenches, extending over all or part of the thickness of the active layer 40, filled with an insulating material (such as silicon oxide or nitride), may be defined around the transistor 100 and the capacitor 150.

[0100] Step f) also comprises the formation of a gate electrode G, between the source 12 and drain 13 electrodes, above the conduction channel 41 (','). This gate electrode G comprises an insulating layer, for example made of aluminum oxide, in contact with the active layer 40 and a metal layer, for example made of aluminum, in contact with said insulating layer. Conventional steps of deposition, photolithography and etching can be implemented for the preparation of the gate electrode G.

[0101] As mentioned above, the transistor 100 and the capacitor 150 are advantageously connected in parallel. The source 12 and the first contact 11 are directly connected via the first conductive layer 10, if the latter remains continuous. If the first conductive layer 10 were to be interrupted, the source 12 and the first contact 11 can be connected as described below with reference to the drain 13 and the second contact 21.

[0102] The drain 13 and the second contact 21 of the capacitor 150 can be connected by a metal wire (“wire bonding” according to English terminology). The proximity of the two cointegrated components reduces the length of the metal connection wire and therefore limits the problems of parasitic inductances. Alternatively, to further limit these parasitic phenomena, a metal interconnection level (involving an additional lithography level, a passivation layer and a metallization line connecting the drain 13 and the second contact 21) can be produced.

[0103] Of course, the invention is not limited to the embodiments described and variant embodiments can be made without departing from the scope of the invention.

Claims

Monolithic device (200) including a field effect transistor (100) and at least one capacitor (150), comprising: - a support substrate (50), - an active layer (40) made of monocrystalline diamond comprising p-type dopants, in which the conduction channel (41) of the transistor (100) is formed, the active layer (40) extending parallel to a main plane (x,y) and being arranged on the support substrate (50), - a stack comprising a first conductive layer (10) and a second conductive layer (20) made of monocrystalline diamond comprising p-type dopants, and an intermediate layer (30) made of monocrystalline diamond, electrically insulating, interposed between the first conductive layer (10) and the second conductive layer (20), the first conductive layer (10) and the second conductive layer (20) respectively forming a first (11) and a second (21) contact of the capacitor (150),and wherein:- the first conductive layer (10) comprises an epitaxial interface (61) with the active layer (40),- the first conductive layer (10) is structured in a plane parallel to the main plane (x,y) and forms a source electrode (12) and a drain electrode (13) of the transistor (100),- the support substrate (50) has a resistivity greater than 10 kohm.cm,- the support substrate (50) is made of monocrystalline diamond or comprises a surface film of monocrystalline diamond, and an epitaxial interface (63) is defined between said support substrate (50) and the active layer (40); or a bonding interface (71) is defined between the support substrate (50) and the active layer (40)., Monolithic device (200) according to claim 1, wherein:- the active layer (40) has a boron concentration of between 10 15 / cm 3 and 10 19 / cm 3, and / or- the first conductive layer (10) and the second conductive layer (20) have a boron concentration greater than 10 19 / cm 3 , and / or- the intermediate layer (30) has a nitrogen or phosphorus concentration of between 10 14 / cm 3 and 10 21 / cm 3 . Monolithic device (200) according to one of claims 1 and 2, wherein:- the first conductive layer (10) and the second conductive layer (20) have a thickness, along an axis (z) normal to the main plane (x,y), of between 5 nm and 50 μm, preferably between 50 nm and 1 μm, and / or- the intermediate layer (30) has a thickness, along an axis (z) normal to the main plane (x,y), of between 10 nm and 2 mm, preferably between 500 nm and 50 μm, and / or- the active layer (40) has a thickness, along an axis (z) normal to the main plane (x,y), of between 100 nm and 20 μm, preferably between 100 nm and 5 μm. Monolithic device (200) according to one of claims 1 to 3, wherein the capacitor (150) is connected in parallel with the transistor (100). The monolithic device (200) of claim 1, wherein the support substrate (50) comprises monocrystalline or polycrystalline diamond, and / or monocrystalline or polycrystalline silicon carbide, and / or a dielectric film (51) adjacent to the bonding interface (71). A method of manufacturing a monolithic device (200) according to one of claims 1 to 5, comprising the following steps: a) providing the support substrate (50), b) forming the active layer (40) on the support substrate (50), c) forming the first conductive layer (10) on the active layer (40) by epitaxial growth, d) forming the intermediate layer (30) on the first conductive layer (10), e) forming the second conductive layer (20) on the intermediate layer (30), f) structuring the second conductive layer (20), the intermediate layer (30) and the first conductive layer (10) in the main plane (x,y), to form the capacitor (150), adjacent to the transistor (100), and defining the source electrode (12) of the transistor (100), the drain electrode (13) of the transistor (100) and the first contact (11) of the capacitor (150) in the first conductive layer (10). Manufacturing method according to claim 6, wherein the source (12) and the first contact (11), or the drain (13) and the first contact (11) are electrically connected by continuity of the first conductive layer (10). Manufacturing method according to one of claims 6 and 7, in which the sequence of steps c), d), e) is repeated N times to form N stacked capacitors. Manufacturing method according to one of claims 6 to 8, in which:- the support substrate (50) is made of monocrystalline diamond or comprises a surface film (502) of monocrystalline diamond, and- step b) is carried out by epitaxial growth, in particular by implementing a microwave plasma-assisted chemical vapor deposition technique. Manufacturing method according to one of claims 6 to 8, in which step b) is carried out by transferring the active layer (40) onto the support substrate (50). Manufacturing method according to claim 10, in which step b) comprises the following sub-steps: - the implantation of light species of the hydrogen, helium type or a combination of these two species in a donor substrate (4), to define a buried fragile plane (1), - the assembly of the donor substrate (4) on the support substrate (50) via a bonding interface, - the separation along the buried fragile plane (1) leading to the transfer of a useful layer (40'), originating from the donor substrate (4) and intended to form the active layer (40), onto the support substrate (50).

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