Motor drive circuitry

Abstract

A motor circuit including a motor having three or more phases, the motor circuit comprising: a motor bridge having, for each phase of the motor, a bridge arm comprising an upper switch and a lower switch that in normal operation may each be opened and closed to modulate the voltage applied to the respective phases, each bridge arm of the motor bridge being connected to a respective phase of the motor through a phase isolation relay SSPIR, each SSPIR when closed electrically connecting the phase to the bridge and when held open isolating the phase from the bridge, and a processing means that during normal operation of the bridge keeps each SSPIR closed to allow currents to flow in the motor phases, and in which in the event that the processing means receives a signal indicating that a fault has been detected in the bridge the processing means is configured to open all of the SSPIRs following at least two different strategies that are selected for use as a function of the speed of the motor.

Description

[0001] MOTOR DRIVE CIRCUITRY

[0002] This invention relates to improvements in motor drive circuitry, especially but not exclusively for use in electric steering assemblies.

[0003] Electric steering systems are known of the kind in which an electric motor applies assistance torque to a part of the steering to assist the driver of the vehicle in turning the wheel. The motor may typically act upon the steering column or may act upon the steering rack, through a reduction gearbox. A measurement of the torque applied to the steering apparatus by the driver when turning the wheel is passed to a processor which produces a torque demand signal which is in turn used to control the motor to produce the required assistance torque. Applying an assistance torque of the same sense as the driver applied torque reduces the amount of effort needed to turn the wheel.

[0004] In an alternative the steering wheel may be decoupled from the road wheels with a motor provided primarily to apply a resisting torque to a steering column that gives the driver a natural feel when holding the steering wheel. An electric motor is coupled to the steering wheel and a processor like that required for an electric power assisted steering system provides a torque demand signal which is used to control the motor to provide the required resistance.

[0005] The motor, which may be a star or wye connected motor, such as a multiphase permanent magnet motor, is controlled by a motor control circuit and a motor drive circuit. The motor drive circuit comprises switches which can be opened and closed to connect the phases of the motor to a DC source, such as a battery or an earth, in response to a control pattern provided by the control circuit. Specifically, each phase is connected to a positive supply rail through a top transistor which when turned on connects the motor phase to a battery positive terminal connected to the positive supply rail. Similarly, each phase is connected through a bottom transistor to a negative supply rail through a bottom transistor. When switched on the bottom transistor connects the phase to the negative rail which is in turn connected to a battery negative or earth, The two transistors- top and bottom- form one arm of a multiple arm bridge circuit that is the heart of the drive circuit. By opening and closing the switches it is possible to selectively and independently route current through each phase of the motor.

[0006] The motor control circuit comprises a digital or analogue circuit or some combination of both. The function of the control circuit is to supply control signals to the bridge transistors to open and close them in a pattern which in turn causes the current to flow through the phases as required for a given motor torque and speed. Generally, the pattern will be set by the control circuit according to the motor position and the torque measured in the steering system by a torque sensor. Typically, the pattern for each arm of the bridge comprises a pulse width modulated waveform.

[0007] An example of a typical prior art motor and drive circuit 1 is shown in Figure 1 of the drawings. A battery (not shown) supplies power to a 3 phase bridge with top switches 2, 3, 4 and bottom switches 5, 6, 7 which feed a 3 phase permanent magnet motor 8. The switches shown are MOSFETS but could be any other type of semiconductor switch such as Bipolar transistors. Where reference is made in this document to MOSFET devices the reader should understand that this is intended generally to cover any solid state relay or switch.

[0008] A problem with such an arrangement is that a fault mode can arise in which a top switch in an arm of the bridge or a bottom switch in an arm of the bridge may be stuck in a closed position, resulting in a permanent path for AC current to flow and making it unsafe to close the other FET in that arm. When such a fault condition occurs the motor resists turning, making it difficult for the driver to turn the wheel.

[0009] To prevent the current being drawn from the supply along the path described in the previous paragraph, the remaining bridge switches on either the top or bottom side of the bridge could be placed by a switch control circuit into a fault mode where the bridge switches are all turned OFF (i.e. open circuit). However, it is still possible for current to flow through the motor along a path as shown in Figure 2 of the drawings. Due to the inductance of the Motor, any current flowing in the fault mode will continue to flow through the faulty bridge switch and the body diodes of two other top or bottom MOSFETs - dependant on the direction of current flow. The direction of flow will change periodically as the motor rotates. When the current changes from one direction to the other it will pass through zero current and then ramp up over time.

[0010] To ensure that current cannot flow due to back EMF Vbemfl,2 as the motor is physically rotated, for example by a driver, it is known to place in each motor phase an additional isolation switch referred to in this text as a solid state phase isolation relay (SSPIR). This term encompasses a range of solid-state switches including MOSFETS and their associated body diodes. When a fault has occurred, the drive circuit is placed in a fault event mode in which these switches are held open (non-conducting) to ensure no current can flow in the phase. A simple circuit with an isolation switch, herein referred to as a solid state phase isolation relay (SSPIR), in each phase, is shown in Figure 5.

[0011] Although the use of SSPIRs would appear to be a perfect and total solution to the problem, the applicant has previously appreciated that an issue with an SSPIR arises when a SSPIR opens either intentionally or unintentionally whilst a high current is flowing through it. Under this circumstance, the voltage across the SSPIR will rise rapidly due to the increasing drain-source resistance in the moments before opening until the breakdown voltage of the switch is reached (avalanche condition). This combination of high voltage in the presence of high current flow results in a short high-power pulse. The energy contained within this pulse may result in the short-circuit failure of the SSPIR, defeating its purpose. This is shown in Figure 6.

[0012] An object of the present invention is to ameliorate the problems associated with the use of SSPIRs when used to isolate a motor from a faulty bridge circuit.

[0013] According to a first aspect the invention provides a motor circuit including a motor having three or more phases, the motor circuit comprising: a motor bridge having, for each phase of the motor, a bridge arm comprising an upper switch and a lower switch that in normal operation may each be opened and closed to modulate the voltage applied to the respective phases, each bridge arm of the motor bridge being connected to a respective phase of the motor through a phase isolation relay SSPIR, each SSPIR when closed electrically connecting the phase to the bridge and when held open isolating the phase from the bridge, and a processing means that during normal operation of the bridge keeps each SSPIR closed to allow currents to flow in the motor phases, and in which in the event that the processing means receives a signal indicating that a fault has been detected in the bridge the processing means is configured to open all of the SSPIRs following at least two different strategies that are selected for use as a function of the speed of the motor.

[0014] The motor circuit may include a motor speed determining means for determining the speed of the motor which is used to select at least one of the two or more different strategies for use in opening the SSPIRs.

[0015] The processing means may more than one strategy such that the strategy that is fastest to determine a safe window of time which to opens the SSPIRS will do so without waiting for results from any other running strategy.

[0016] During normal running of the motor a first strategy may be used which comprises identifying safe zero crossing events by sampling the voltages on each phase and opening one or more SSPIRs when a safe crossing event is detected. This first strategy may be running by the processing means for all motor speeds but configured to not open any SSPIRs if the back emf generated by the motor is insufficient. The processing means can determine that the back emf is insufficient by observing the phase voltages over time. To allow for safe opening of the SSPIRs when the back emf is too low for the first strategy, the processing means may run a second strategy of the at least two different strategies that comprises monitoring the motor electrical position to identify when the motor is in a position where it is safe to switch off an SSPIR.

[0017] In one preferred arrangement the second strategy comprises identifying which phase is electrically before and after a faulty phase calculating an angular position of the motor that corresponds to the middle of a safe range of positions for opening an SSPIR and opening the SSPIR once the motor reaches that safe position. The skilled person will understand that in a PWM driven motor the waveforms applies to all three phases will generally be the same but they will be offset temporally. For a three phase motor the waveforms will be offset by roughly 120 degrees. A phase is considered to be the one that is electrically before a given phase where it is offset by -120 degrees and considered electrically after where it is offset by +120 degrees.

[0018] The second strategy may be run by the processing means when the motor speed is below a first intermediate threshold motor speed that substantially corresponds to the speed below which the back emf induced in any phase of the motor in the event of a fault is insufficient to reverse bias both of the FETS in any arm of the bridge by an amount in excess of the body diode reverse voltage of the switches.

[0019] In one preferred arrangement the motor circuit may also employ a third strategy of the at least two different strategies that comprises identifying which of the bridge switches has failed and determining the motor position when there will be zero current flowing in a phase, and at that time opening the SSPIR of that phase. As with the second strategy this third strategy uses motor position information to identify safe times to open the SSPIRs.

[0020] The third strategy may be run when the motor speed is below a second intermediate threshold motor speed that is lower than the first intermediate threshold speed.

[0021] In another preferred arrangement the processing means may run a fourth strategy of the at least two different strategies comprises switching off all SSPIRS together after an elapsed period of time, the fourth strategy only running when the motor speed is below a third threshold speed that is lower than the second intermediate threshold speed. The elapsed time may be dependent on the motor distance from the safe switch off position used in the second strategy, the greater the distance the greater the elapsed period of time before opening all the SSPIRs. The invention encompasses a motor control circuit that includes any two of the first, second, third and fourth strategies. The first strategy is preferred as it will generally be able to open the SSPIRs faster but as noted is not effective when the motor speed is too low to generate a sufficiently large back emf in a phase.

[0022] In one especially advantageous arrangement the first strategy as described above may comprise as soon as the bridge has been turned off taking samples of the voltage on each phase of the motor and from the samples determine a safe zero current crossing event to occur after the fault signal has been received, a safe zero current crossing event comprising a period of time immediately after the current in a phase has stopped flowing in the direction in which it was flowing immediately prior to the zero crossing event, and in which the processing means thereafter opens one or more of the SSPIR before the end of the safe zero current crossing event.

[0023] The motor circuit may include a phase voltage sensing means that measures the voltage on each phase at a point in between the SSPIR FETs and the motor rather than between the SPPIR FETs and the motor bridge.

[0024] The motor circuit may detect and open one of more SSPIRs when the first safe zero crossing has been identified after the delay period has ended, or the second or the third or any other integer number of PWM cycles after the delay period has ended. Importantly once a safe zero current crossing period has been identified the opening of an SSPIR or SSPIRs is done immediately within that same safe zero current crossing event.

[0025] The motor circuit may include a switch control circuit that determines that a fault in the bridge has occurred and turns off the bridge in addition to causing the fault signal to be sent to the processing means, and in which the processing means only compares voltage samples captured after a predefined delay time has elapsed from receiving the signal indicating that a fault has occurred in the bridge in order to identity the first safe zero current crossing event.

[0026] The first strategy of the invention, which may be considered the main strategy, ensures that the SSPIR is not damaged on initial opening due to excessive power dissipation in the SSPIR by opening within the zero current crossing event, a period of time commencing with the current changing direction up to when the current may have risen to a level where it is unsafe to open the SSPIR. By identifying the instant at which this zero current crossing zone starts and switching within that zone no damage to the SSPIR will occur as the current is sufficiently low.

[0027] The processing means may determine that a fault in the bridge has occurred upon receiving a trigger signal from a switch control circuit that determines that a fault in the bridge has occurred and turns off the bridge in addition to causing the fault signal to be sent to the processing means.

[0028] The processing means of the invention is configured to only compare samples captured after a predefined delay time has elapsed from receiving the signal indicating that a fault has occurred in the bridge to identify a first safe zero current crossing.

[0029] This allows time for the switches of the bridge to fully open following the command to turn off the bridge and for the bridge transients to decay. The delay time may therefore be selected to be the time required for the bridge switches to fully open after the signal that the bridge is faults has been received. It is preferable that this delay time is kept as short as possible.

[0030] In practice, after the delay time has passed the processing means will sample the voltage on each phase repeatedly at least until a zero crossing event has been identified, preferably identifying the first zero crossing that occurs in a phase.

[0031] The processing means may start talking voltage samples prior to the end of this delay time but after a second shorter delay time has elapsed sufficient for all the circuit affecting the bridge to have turned off. The longer delay time gives additional time for the bridge to settle after being turned off and any transient effects to decay. The processing means may use these samples captured between the end of the shorter delay and the end of the longer delay to determine the supply voltage and ground voltage as explained later on.

[0032] The processing means may be arranged to identify a safe zero current crossing event by identifying the moment at which the phase voltage has risen of fallen between the pair of compared samples by an amount in excess of the forward bias voltage of a body diode of switches used in the bridge. To allow for changes in the supply voltage the motor circuit between samples the processing means must be able to compensate for that in determining the voltage drop. The motor circuit of the invention uses the phase voltage signals to switch off the SSPIR FETs when one bridge FET has failed. It does this by using the phase voltage to estimate the direction of the current in the phase (i.e. towards or away from the motor).

[0033] The reason that the phase voltages can be used to identify the current lies in the design of the three-phase inverter. Each MOSFET in the inverter contains a body diode, allowing current to flow in only one direction if the MOSFET is switched off. Additionally, each MOSFET has its body diode facing from ground towards SUPPLY VOLTAGE.

[0034] If the inverter is switched off, that means for each half-bridge, the half-bridge can do one of the following: sink current using its high-side MOSFET’ s body diode, source current using its low-side MOSFET’ s body diode or conduct zero current. However, to sink or source current, the voltage needs to be great enough to overcome the voltage drop of the body diode, which means that the phase voltage would have to be greater than the supply voltage or lower than ground, which wouldn’t happen in normal operation.

[0035] When the motor is spinning and the half-bridge is fully switched off, the motor will induce a back EMF on that phase. This back EMF can raise the phase voltage above the supply voltage or below ground. When the half-bridge is switched off and the motor is turning fast, the half-bridge can source or sink current with this effect. SSPIR would typically be used to prevent this, but to turn the SSPIR off (to stop current flow) we need to find a safe window to do so in.

[0036] The requirement for the body diode voltage to be overcome allows us to use the difference between the phase voltage measurements and SUPPLY VOLTAGE measurements to check which body diode is conducting. For example, if we measure SUPPLY VOLTAGE and find that it is 12 V, then measure the phase voltage and find that it is 12.7 V, we can say that the forward voltage on the high side body diode is 12.7 - 12 = 0.7 V. Assuming the voltage drop of the body diode is 0.7 V, in this case the diode would be conducting. Of course, the invention may be applied to motor circuits that use supply voltages that are not nominally 12 volt and the skilled person will understand that this example of a typical vehicle 12 volt battery supply is merely used as an example that falls within the scope of the invention.

[0037] The processing means may be configured so that it does not identify as a safe zero crossing event a zero crossing event that corresponds to the time when the phase voltage decreases by an amount in excess of the forward bias voltage of the body diode of a bridge switch and hence not open the SSPIR during such a zero crossing event. However, in some embodiments these events may also be considered safe and switching off an SSPIR may take place when such an event is detected. The processing means may further be arranged so that after detecting a safe zero crossing event in a phase the processing means continues to sample the voltage on the remaining phases to determine the safe zero crossing on any of the remaining phases and upon detecting each safe zero crossing event opens one or more of the remaining closed SSPIRs.

[0038] The processing means may determine if the phase containing the SSPIR corresponds to a healthy arm of the bridge from the change of voltage between voltage samples on a phase and only opens immediately where the phase is not a faulty phase.

[0039] By healthy we mean that the switches off the bridge are not stuck in a closed position with the bridge turned off which indicates a short across the input and output side of the switch.

[0040] Each sample of the phase voltage may be assigned to one of three states comprising a high state meaning the top side FET’s body diode is forward biased, a low state meaning the bottom side FET’s body diode is forward biased, or a middling state meaning neither diode is forward biased, the control circuit comparing the states of at least two samples to identify a safe zero current crossing event.

[0041] The processing means may be configured to detect zero current crossing events that correspond to a rising edge of the phase voltage, or a falling edge of the phase voltage, or both.

[0042] For example, where rising edges are detected the processing means may determine that an arm of the bridge is healthy and that a zero current crossing event is a safe zero current crossing event when the voltage state of a phase changes from the low state to the middling state or from a low state to a high state or from a middling state to a high state, and in one of these changes the processing means increments the value of a rising edge counter. A similar approach can be applied for falling edges of the phase voltage.

[0043] The rising edge represents a phase which either has just stopped sourcing current or was previously not sourcing current, and now has either zero current oris sinking a very small current - which should be broken before it begins to sink more current.

[0044] After incrementing the rising edge counter the processing means may compare the next captured sample voltage to determine if the phase remains in the new state or has moved to a higher state, and where this has occur increments the rising edge counter again and repeats this comparison for subsequent samples until rising edge counter reaches a predetermined threshold value or until a sample is observed in which the state has fallen to a lower phase state and in that event the rising edge counter is set to zero.

[0045] The threshold value may be any set integer value and is preferably as low as possible to achieve a given level of confidence in the processing of the voltage samples to correctly identify a safe zero current crossing event. The applicant has found that a value of 4 works well in a practical implementation of the invention although in theory a count as low as one could be used.

[0046] By taking a series of samples and comparing them, the processing means only identifies a zero crossing as a safe zero current crossing when the counter reaches the predefined target value. This reduces the risk of a zero crossing event being falsely identified, for instance due to signal noise or where there has been a sudden and unexpected rise or drop of the supply voltage.

[0047] Too many samples will introduce delay in opening an SSPIR reducing the risk that this cannot be done before the end of the zero crossing event. A high sample rate and a threshold value of 4 or 5 has been to be a suitable compromise.

[0048] The processing means may cause one or more of the SSPIRS to be opened immediately upon the rising edge threshold being reached. By immediately we mean before the next processing cycle of the processing means, for instance before the next sample would be taken.

[0049] Following at least one SSPIR being turned off so that the phase can no longer sink current, the processing means on each sample may increment the rising edge counter of any remaining phase whenever the state of a sample for that phase is in a middling state or in a high state until the threshold is reached for turning off and SSPIR.

[0050] With one SSPIR already turned off so that it is open and no current can flow through it, a high voltage now also represents a phase with zero current in it. Therefore, a healthy phase with SSPIR off and either a middling or high voltage should increment its rising edge counter regardless of the previous voltage.

[0051] The processing means may be arranged such that after all the SSPIRs in phases where the bridge FETs are healthy have been turned off and a short period of time has passed that is sufficient for the phase currents to restabilise the processing means waits for a rising edge on the phase electrically before the faulty phase to turn off the SSPIR of a remaining faulty phase.

[0052] The short period may be identified by: i. waiting for the phase that is electrically before the faulty phase’s rising edge counter to reach its maximum and ii. wait for the phase electrically after the faulty phase’s rising edge counter to reach its maximum.

[0053] In an enhancement, the processing means may not wait for the end of the short period before turning off a faulty phase when it determines that the rising edge counters of all healthy phases with SSPIRS that already turned off are equal to the threshold value.

[0054] The motor circuit may include a bridge monitor circuit the condition of the motor bridge to determine that a fault condition is present where a switch of the bridge is not operating correctly and in response outputs the fault signal that is fed to the processing means.

[0055] The duration of a safe zero current crossing event withing which the SSPIR must be opened may be stored in an area of memory that is part of the monitoring means or accessible to the monitoring means. This defines the duration of the zero current crossing event.

[0056] The threshold may have a fixed value or may have a variable value that is varied as a function of one or more properties of the motor drive circuit or of the motor driven by the motor drive circuit. These may include the temperature of at least one part of the motor drive circuit or of the motor.

[0057] The processing means may during normal use apply, or cause to be applied, a voltage to the gate of each of the SSPIRs to hold them closed.

[0058] As mentioned, the invention may provide an SSPIR in each phase of the motor, and the monitoring means and control means will control each SSPIR independently. For a motor having three phases there may be three SSPIRs and each phase may be connected to a different one of three arms of a bridge circuit.

[0059] According to a second aspect the invention provides a method of operating a motor circuit including a motor having three or more phases, the motor circuit comprising: a motor bridge having, for each phase of the motor, a bridge arm comprising an upper switch and a lower switch that in normal operation may each be opened and closed to modulate the voltage applied to the respective phases, each bridge arm of the motor bridge being connected to a respective phase of the motor through a phase isolation relay SSPIR, each SSPIR when closed electrically connecting the phase to the bridge and when held open isolating the phase from the bridge, and the method comprising: during normal operation of the bridge keeping each SSPIR closed to allow currents to flow in the motor phases, and in the event that the processing means receives a signal indicating that a fault has been detected in the bridge the processing means is configured to open all of the SSPIRs following at least two different strategies that are selected for use as a function of the speed of the motor.

[0060] The method may embody any of the features described above in relation to the motor circuit of the first aspect of the invention.

[0061] There will now be described, by way of example only, three embodiments of the present invention with reference to and as illustrated in the accompanying drawings of which:

[0062] Figure 1 is a general schematic representation of a prior art motor circuit for use in an automotive electric power assisted steering system,

[0063] Figure l is a schematic corresponding to Figure 1 showing the potential path of current flowing round the motor when one of the switches on a high side of the bridge is faulty;

[0064] Figure 3 is a schematic corresponding to Figure 1 showing an alternative path for current to flow even after the bridge has been closed caused by inductive decay of current in the motor associated with the motor inductance;

[0065] Figure 4 is a schematic also corresponding to figure 1 showing a further source of current flow due to back emf in the motor as it is rotated at speed;

[0066] Figure 5 is a schematic of an alternative circuit in which each phase of the motor is protected by a serially connected switch SSPIR between the motor phase and the bridge;

[0067] Figure 6 is a schematic corresponding to Figure 5 showing a path for current flow due to back emf in the motor even when the bridge is closed; Figure 7 is a schematic of an embodiment of a motor drive circuit according to a first aspect of the present invention connected to a motor.

[0068] Figure 8 shows an example where the measured value of SUPPLY VOLTAGE = 12 V.

[0069] Figure 9(a) is a graph showing the phase current as a function of phase voltage and Figure 9(b) is an electrical circuit used to generate graph;

[0070] Figure 10 is an example fault showing how the phase voltages correlate to the current direction in each phase;

[0071] Figure Ila is a Graph showing the phase voltage as a function of phase current and Figure 1 lb shows a circuit used to generate graph.

[0072] Figure 12 shows a simulation result where there is a short zero current period before sinking current. After the low to middling rise in voltage, there is zero current, so the SSPIR should be switched off. After the middling to high rise in voltage, the current begins growing, so the SSPIR should be switched off to prevent that.

[0073] Figure 13 is a graph showing the phase voltage being tracked with a constant supply voltage;

[0074] Figure 14 is a graph showing the phase voltage being tracked when the supply voltage suddenly decreases;

[0075] Figure 15 is a graph of phase currents when a bridge has a high side short circuit fault on phase 1, and the SSPIR is turned off on phase 2 and 3;

[0076] Figure 16 is a flowchart showing the steps performed by the motor control circuit from first identifying a fault in the bridge to opening all the SSPIR relays by selecting an appropriate strategy or strategies according to motor speed; and

[0077] Figure 17 shows in more detail the main strategy used at the highest speeds. As shown in Figure 7 which is an overview of a generic embodiment of the invention a motor drive circuit 100 for use in an electric power assisted steering system comprises a motor, a motor bridge, a sampling circuit and a processing means. The motor 101 comprise a three-phase motor, having three phase U, V and W connected at a common star point 102. The ends of each phase, not connected at the star point, are connected to respective branches of a motor bridge circuit 103 via a plurality of solid-state phase isolation relays (SSPIRs) 104,105,106, one in series with each phase.

[0078] The motor bridge circuit will typically be in line with that shown in Figure 1. Each arm or branch comprises an upper portion which connects the motor to a positive side of a battery supply through a top MOSFET switch, and a lower portion which connects the motor phases to a negative side of the battery supply through a bottom MOSFET switch. The top and bottom switches in each arm enable the phase to be connected to the positive side by closing a top transistor and simultaneously opening the bottom one. They also enable it to be connected to the earth by closing the bottom transistor and simultaneously opening the top one. Similarly, they allow the phase to be left floating by simultaneously opening both the top and bottom transistors. The skilled person will understand that each MOSFET will include a body diode in that a voltage is dropped across the MOSFET source to drain terminals when the MOSFET is reverse biased and this can be used to identify whether current is flowing through a turned off MOSFET and the direction of the current flow.

[0079] The opening and closing of the top and bottom MOSFETs of the bridge is controlled by a switching pattern applied to the switches by a control circuit (not shown) which may form a part of the motor circuit of the invention. The switching pattern defines the timing at which each of the bridge switches should be opened and closed at any time. The skilled person will understand that many different patterns may be used with a pulse width modulated pattern being commonly used for motors in electric power steering systems. The choice of switching pattern depends on the position of the motor at any given time, the desired motor torque that is to be achieved, and the desired motor speed. Provided that the motor position and speed are measured and fed to the microprocessor, together with a torque demand signal indicative of the torque required from the motor. These measurements and signals are processed by the microprocessor to produce the desired patterns. Additional signals may be used to determine the desired inverter switching pattern. Such a control circuit is well known in the art, and so will not be discussed here in any detail.

[0080] Associated with the bridge is a switch control circuit This comprises a microprocessor circuit that determines an event in which a switch of the bridge is faulty and opens the remaining switches of the bridge by turning the bridge off. At the same time this switch control circuit issues a fault signal to a processing means 130 which controls the timing of the opening of the SSPIRS to isolate the phases of the bridge and prevent any current from flowing. The operation of the processing means is explained below.

[0081] Each SSPIR is a solid-state switch 104a, 105a, 106a. In use each SSPIR is normally closed (drain-source conductive) due to a voltage applied to the gate of the SSPIR by an output of the processing means.

[0082] The processing means of this embodiment uses four different strategies to identify safe times to open the SSPIRs. At high motor speeds above the first threshold only the first strategy is running. Below that two or more are running at any time. The applicant has appreciated that using multiple strategies allows safe switching over a wide range of motor speeds. Figure 16 shows the main steps carried out by the motor circuit to open the SSPIRs using different strategies that are selected according to the speed of the motor.

[0083] First strategy- motor speed above first motor speed threshold

[0084] The first motor control strategy is embodied in the processing means which is typically a microprocessor circuit and which receives as inputs voltage values indicative of the voltage in each phase and the signal indicative of a fault in the bridge from the switch control circuit. The microprocessor also receives a signal indicative of the supply voltage to the bridge and a signal indicative of the ground voltage for the bridge which as explained below are used to determine the boundaries of the low, middling and high states for the phase voltage measurements. The microprocessor outputs voltages applied to the gate of each SSPIR which at any time has a high value to hold the SSPIR closed or a low value to hold the SSPIR open.

[0085] The microprocessor 130 in this embodiment may not receive a directly measured value of the SUPPLY VOLTAGE. Instead, the SUPPLY VOLTAGE used for this comparison is estimated, rather than using the measured value of SUPPLY VOLTAGE, as described later. In some instances the microprocessor may receive a directly measured value of the supply voltage by connection of an input terminal to a point in the circuit exposed to the supply voltage but this may only be used indirectly, with the directly used value coming from an estimation.

[0086] The microprocessor may check is a high side body diode is conducting by referencing the phase voltage to the estimated supply voltage.

[0087] The microprocessor may also check if the low side body diode is conducting, albeit this time referenced to ground instead of SUPPLY VOLTAGE. If upon measuring the phase voltage and find that it was -0.7 V, and we know that ground is 0 V, we can then say that the forward voltage on the low side body diode is 0 - -0.7 = 0.7 V, which would cause the low side body diode to conduct.

[0088] In practice, component tolerances and other inaccuracies such as noise mean it would be unwise to try and measure the actual diode drop across a FET using a phase voltage sense circuit. As such, a significant tolerance is used. Any value within the tolerance will be assumed to mean a conducting diode. This in practice means that some values close to SUPPLY VOLTAGE or ground but not great enough to forward bias the relevant body diode will be misinterpreted as actually forward biasing the diode.

[0089] Figure 8 shows an example where the measured value of SUPPLY VOLTAGE = 12 V. The overlap between the red and yellow regions signifies the tolerance in the body diode forward voltage. Should a voltage be misinterpreted as high when it is just shy of being high (or the same for low), the voltage would not be sufficient to forward bias the body diode which the strategy assumed. However, the voltage would be much too far away to forward bias the opposing body diode, so with neither body diode conducting there would be zero current in the phase. Zero current is also a safe window to switch off a phase in, so this tolerance does not cause any issues with the safety of the strategy.

[0090] The tolerance used is ratio metric, being a ratio of the maximum variation on the phase. The range of variation is driven by the speed of the motor, which in turn induces a proportional back EMF. If the motor speed is high enough, the range will be limited by the body diodes on the top and bottom side of the phase - limiting the range to approximately SUPPLY VOLTAGE to ground.

[0091] Figure 9(a) is a graph showing the phase current as a function of phase voltage. And Figure 9(b) is an electrical circuit used to generate graph. Notice that all intermediate voltages are safe - a large tolerance won’t compromise safety, only the minimum motor speed in RPM for the strategy to work.

[0092] This effect means that we can identify the direction of current from the phase voltage. If the phase voltage is close to SUPPLY VOLTAGE, the current is flowing through the high-side FET and as such the phase is sinking current. If the voltage is close to ground, the current is flowing through the low-side FET and as such the phase is sourcing current. If the voltage is between these two values, neither body diode can be overcome, meaning that no current is flowing. Figure 10 is an example fault showing how the phase voltages correlate to the current direction in each phase. The example fault is a short circuit in the top side FET on phase 3.

[0093] Whilst the SSPIR remains on, the phase currents induced by the back EMF from the motor come in what is largely a fixed pattern. Figure 15 shows an example of one of many different PWM patterns may be present in the motor phases. If the motor RPM is high, a very large back EMF will be induced, meaning the time at zero phase current will be too short to detect. Instead, the phase current will change direction seemingly immediately from the strategy’s point of view, with no intermediate voltage to use to safely switch off the SSPIR.

[0094] However, the immediate change in current direction provides enough information for a safe SSPIR switch off. At the sample immediately before the current changes direction (the zero current crossing), the current will be small, as the back EMF will be close to zero (as it will soon change sign). Then, for the sample immediately after the zero current crossing, the current will also be small but in the opposite direction, for the same reason. If switched off at this time, the MOSFET will endure a small but safe avalanche current, meaning at this zero crossing point it is safe to switch off the SSPIR.

[0095] This difference in current direction between the two samples is something the processing means identifies to distinguish between rising edge zero current crossings and trailing edge zero current crossings. By looking for rising edges on the phase voltage sense, a zero current crossing from sourcing to sinking can be identified, providing the ideal time to switch off the SSPIR. When a rising edge is detected, the SSPIR should immediately switch off. Switching could also take place with a trailing edge zero current crossing in some embodiments.

[0096] Figure 1 la is a Graph showing the phase voltage as a function of phase current and figure 1 lb shows a circuit used to generate graph. Notice that on the rising phase voltage edges, the current is very close to zero - it is safe to switch off at that time. The yellow blocks represent a safe zero current crossing event.

[0097] Under some circumstances the back EMF induced may not be sufficient to forward bias the opposing body diode after the expected zero crossing point. This may mean that there is a delay before the opposing body diode conducts (whilst the back EMF continues to grow) or that the opposing body diode never conducts, and only one body diode ever conducts for that half-bridge. This would mean that for that half-bridge, there is a time where zero current is flowing in the phase. Zero current is a safe opportunity to switch off the SSPIR FET.

[0098] When the phase voltage is below ground or above SUPPLY VOLTAGE (±diode drop) the half-bridge is conducting. Conversely, if the phase voltage is between ground and SUPPLY VOLTAGE there is zero current in the phase. As such, when the phase voltage rises from a low to a middling phase voltage, the SSPIR can be switched off.

[0099] Note that the SSPIR rising from a low to a middling phase voltage is not sufficient information to determine the current direction. If it has just risen from low to a middling phase voltage, it may be about to raise to a high phase voltage, and the result is slowed due to the time constant of the phase sense circuit.

[0100] The rise in phase voltage means the real phase voltage (not sensed) is either middling or high. If it is middling, it makes sense to switch immediately, as this zero current period may not be available for long. However, if the phase voltage is high, it also makes sense to switch immediately - to prevent the avalanche current from growing. As such, any rise in phase voltage, whether it be from a low to middling, low to high or middling to high voltage is a valid switch point.

[0101] The invention does not delay and instead will switch on any rising edge, without knowing what the real state of the phase voltage is, this being considered to be a safe zero current crossing event provided the switching is done immediately before the end of the zero crossing event.

[0102] By switching on the rise from low to middling, which will happen much earlier in time than the rise from middling to high. This in turn means the strategy switches on a smaller avalanche current.

[0103] Figure 12 shows a simulation result where there is a short zero current period before sinking current. After the low to middling rise in voltage, there is zero current, so the SSPIR should be switched off. After the middling to high rise in voltage, the current begins growing, so the SSPIR should be switched off to prevent that.

[0104] The theory presented so far only holds true for healthy phases - the same assumptions cannot be made for the faulty phase. Depending on the fault, either the phase sense values could be affected or the response at a given phase voltage could be different. For example, if a FET was short circuit (drain to source), the phase voltage would always be stuck at either SUPPLY VOLTAGE or ground, regardless of if the phase was sinking or sourcing current. A second example would be if a FET were to fail open circuit, then the body diode may no longer conduct, meaning that phase wouldn’t ever either sink or source current (depending on which FET failed) regardless of the phase voltage.

[0105] For a three phase motor with each phase having an SSPIR relay the following overall method set out in Figure 17 would be used at high motor speeds. The method has the following steps:

[0106] 1. Detection and identification of a fault in the bridge circuit.

[0107] 2. Turning of the bridge so that all bridge FETs are switched off.

[0108] 3. Start a timer at zero to compare against two delay periods .

[0109] 4. Wait until a preset delay time has elapsed on the timer - parameter value of perhaps 5ms to 10 ms may be used set according to the manufacturer stated time taken for all circuits affecting the bridge to completely switch off.

[0110] 5. Begin sampling the phase and SUPPLY VOLTAGE voltages every sample period (assumed to be before 5 ps and 10 ps for this embodiment). These early values are used only to run the phase tracking, boundary setting, and state identification logic.

[0111] 6. Wait until the delay set in step 4 has elapsed on the timer - parameter value of perhaps 15m to 20 ms may be used, meaning an additional 10-15 ms. This delay allows the state of the bridge to settle.

[0112] 7. Continue to sample the SUPPLY VOLTAGE sense and each phase sense every 10 ps or so. The sampling preferably happens at as fast a rate as possible by the microprocessor, faster sampling rates providing a more accurate and immediate identification of the precise moment that a zero current event commences.

[0113] 8. Use the measured values of SUPPLY VOLTAGE sense and phase senses to identify the state of the phase. It will be either high - meaning the top side FET’s body diode is forward biased, low - meaning the bottom side FET’s body diode is forward biased, or middling - meaning neither diode is forward biased.

[0114] 9. Every 10 ps or so identify the state of each of the phases, either low, middling, or high.

[0115] 10. If a healthy phase has just changed state from a lower state to a higher state (low — middling, low — high, or middling — high), the rising edge counter is incremented for that phase. Each phase has its own counter, and at the start of the method all may be set to the same zero value. The rising edge represents a phase which either has just stopped or was previously not sourcing current, and now has either zero current or is sinking a very small current - which should be broken before it begins to sink more current. a. Should the healthy phase still be in the new state (or a higher state) on the next sample, the rising edge counter will increment again. b. Should the healthy phase fall to a lower state, the rising edge counter shall be set to zero. c. Should the rising edge counter reach the maximum count value, for example a count of four, the SSPIR for that phase shall turn off. The rising edge counter shall then be reset to zero.

[0116] 11. If the SSPIR for a phase has been turned off, it can no longer sink current, as the turned off SSPIR FET blocks that conduction path. As such, a high voltage now also represents a phase with zero current in it. Therefore, a healthy phase with SSPIR off and either a middling or high voltage should increment its rising edge counter regardless of the previous voltage.

[0117] 12. After the two healthy SSPIR FETs have been turned off, wait for a short period for the phase currents to restabilise. a. This short period is identified by: i. First, wait for the phase before the faulty phase’s rising edge counter to reach its maximum ii. Second, wait for the phase after the faulty phase’s rising edge counter to reach its maximum b. If the strategy detects that both healthy phases’ rising edge counters are equal to SSPIR PFB REC HIGH at the same time, it can turn off the final SSPIR FET. The bridge would then be safe.

[0118] 13. After this short period, when the phase before the faulty phase’s rising edge counter reaches its maximum, the final SSPIR FET should be switched off. The bridge is then safe.

[0119] The processing means aims to identify the current state of a phase - whether the voltage is close to the SUPPLY VOLTAGE (high), close to ground (low), or in between the two (middling) - using only the phase sense itself. By achieving this, the worst-case tolerance in the phase sense circuit can be disregarded. For example, if the phase sense is 10% higher than it should be, an 80% boundary will become an 88% boundary, correcting for the error caused by circuit tolerance.

[0120] To achieve this, the processing means needs to know the full range of the values expected on the phase sense and to set the upper and lower boundaries of the middling voltage state. One way to do this is set out below.

[0121] Firstly, the processing means records the estimated SUPPLY VOLTAGE from this phase, and the maximum positive and negative offsets seen on this phase compared to that estimated SUPPLY VOLTAGE. Note that the SUPPLY VOLTAGE is not needed to estimate this (in the first instance) - it is instead approximated as the diode reverse bias voltage (0.7 V in this embodiment) less than the maximum voltage ever seen.

[0122] The difference between expected diode reverse bias voltage and any actual diode drop across the top side FET is believed to be too insignificant to cause any serious inaccuracy in the operation of the motor circuit.

[0123] Figure 13 is a graph showing the phase voltage being tracked. Note the blue and green lines tracking the phase voltage. The green line (phase reference point) stays 0.7 V below the greatest seen voltage, and the blue lines (phase reference point plus offsets) tracks exactly the highest and lowest seen voltages. The red lines are then calculated from the values of the blue lines.

[0124] To prevent noise from distorting the set point and two offsets, a buffer of the five most recent samples is kept for each phase. The median value of these five is then used as the phase voltage value. It is believed that the additional few samples worth of delay for the correct value will not be significant compared to the frequency of the phase currents.

[0125] If an SSPIR FET is turned off, the boundaries for that FET will not be updated for a short period of time thereafter assumed to be 1 ms in this embodiment. This is to prevent the avalanche voltage of the SSPIR FET causing an impossibly high estimated SUPPLY VOLTAGE.

[0126] To ensure that the processing means is not trying to detect an indiscernible variation, a minimum difference between the two offsets is used. If this difference is not yet met (i.e. the back EMF is not easily discernible, or the phase tracking logic hasn’t seen a full period of the waveform yet) then the strategy is prevented from initialising the rising edge counter, preventing any trips.

[0127] The minimum difference is provided by the constant SSPIR back EMF which is assumed to be 3 V in this embodiment. This value is driven largely by the minimum expected back EMF at the lowest speed the strategy works at with a significant tolerance so as to not reintroduce a reliance on having a low worst-case tolerance.

[0128] If the SUPPLY VOLTAGE value were to change from one point to another, the set point (and because of this the offsets) would be incorrect. This can be a problem if the SUPPLY VOLTAGE reduces. Consider the example where the SUPPLY VOLTAGE starts at 12 V, there is 12 V of range on the phase voltage sense, and assume the high side boundary is 80% - meaning the actual value is 9.6 V. Should SUPPLY VOLTAGE then drop to 8 V, then the top side FETs would conduct at around 8.7 V. However, this new conduction value is lower than the set high side boundary, meaning the strategy would mistake this as a zero current period, causing a dangerous switch off behaviour.

[0129] Figure 14 is a graph showing the phase voltage being tracked when SUPPLY VOLTAGE suddenly decreases. The decrease means the maximum phase voltage point is now incorrect, leading to incorrect calculation of the boundaries. This will then lead to a false trip.

[0130] To ensure that the set point is always at (approximately) SUPPLY VOLTAGE, the SUPPLY VOLTAGE sense is used to track the percentage change in SUPPLY VOLTAGE. At the end of the 10 ms delay before the strategy, each phase is given a variable multiplier, which should initialise as l.The SUPPLY VOLTAGE sense has the same denoising strategy applied to it as the phase senses do before a value is used.

[0131] This multiplier is then updated on every sample by SUPPLY VOLTAGE divided by the previous sample of SUPPLY VOLTAGE. The phase reference point is multiplied by this multiplier to get an ephemeral phase reference point for each sample. It is from this ephemeral phase reference point that the immediate phase sense value (after noise rejection) is tested to see if it defines a new minimum or maximum offset.

[0132] Should the maximum observed phase voltage be much lower than SUPPLY VOLTAGE, defined as being below SUPPLY VOLTAGE times by a tolerance factor assumed to be 0.75 in this analysis, The processing circuit assumes that the reference point is not SUPPLY VOLTAGE. This would be the case if there is a bottom side FET SC, and the back EMF does not cause the top side FET’s body diode to conduct. If the strategy assumes the reference point is not SUPPLY VOLTAGE, the SUPPLY VOLTAGE tracking is disabled, and the multiplier is locked. Additionally, the reference point is reset to the maximum phase voltage minus 0.7 V, in case the multiplier was changed by this action (this compensates for the change).

[0133] The check for if the reference point is not SUPPLY VOLTAGE is also satisfied once the SSPIR FET is turned off - as there is no longer any path to SUPPLY VOLTAGE from the phase sense.

[0134] For a given sample, after the ephemeral phase reference point and the new minimum and maximum offsets are calculated, the minimum and maximum phase voltages are calculated by applying the offsets to the ephemeral point. The minimum phase voltage is also ensured to always be at least zero, as below zero the bottom side FET’s body diode will be assumed to be conducting regardless.

[0135] With the minimum and maximum phase voltages for a phase established, the boundaries for a low and high phase value are calculated. Generally, the low boundary is 0.2 times the voltage range plus the minimum voltage and the high boundary is the same calculation using instead the value 0.8.

[0136] This rule is only applied when the range of phase values makes up the full range of ground to SUPPLY VOLTAGE. This is assessed using a different method if there is a top side (including open circuit and gate low faults) or bottom side FET fault. If it is a top side fault, the range of voltage seen on the phase is compared to SUPPLY VOLTAGE multiplied by 0.75. If it is a bottom side fault, the maximum seen voltage is compared to SUPPLY VOLTAGE multiplied by 0.75. For the bottom side fault, this is the same condition as enabling SUPPLY VOLTAGE tracking.

[0137] Should the general rule not apply, one of two additional rules are used. If the minimum observed phase voltage is greater than SUPPLY VOLTAGE multiplied by 0.25, the first separate rule is used. First, the phase’ s low boundary is set to negative infinity. The phases high boundary is then calculated using the wide multiplier 0.4 instead of the standard 0.8.

[0138] Should that condition be false, the inverse of that rule is applied- the high boundary becomes positive infinity, and the low boundary uses the wide multiplier0.6.

[0139] The benefit of having these extra wide boundaries in this case is to prevent switching off due to noise rather than actual behaviour. If these conditions are met, it means that the range of the phase voltage sense is small, and the phase voltage never changes enough to drive the other FET. As such, there is no need for an opposing boundary, and it makes sense to instead increase the important boundary to reduce the chance of noise causing a false trip.

[0140] With all these considerations taken into account, the processing circuit will have a phase low and phase high value which may be stored in an area of memory for use when samples of the phase voltages are taken. If the immediate phase sense voltage is above the phase high value, the phase is in the high state, and we assume current is conducting in the top side FET’s body diode. If below the phase low value, the low state, and the bottom side FET’s body diode. If it is between these two values, the state is middling, and we assume no current is flowing in that phase. High-side FET Short circuit

[0141] In the case of a high-side FET short circuit, when the two healthy phases have had their SSPIR switched off, the uniform pattern of the back EMF causes there to be many periods where no current flows between the bridge and the motor (in any phase). These zero current periods always happen immediately after starting a zero current period on the phase electrically before the faulty phase, so the strategy can infer the position of this zero current period.

[0142] Figure 15 is a graph of phase currents when a bridge has a low side short circuit fault on phase 1, and the SSPIR is turned off on phase 2 and 3. Notice large zero current periods occur when the phase before the faulty phase (PH3 before PHI) returns to 0 A - the SSPIR can be switched off then.

[0143] Low-side FET short circuit

[0144] In the case of a low-side FET short circuit, when the two healthy phases have had their SSPIR switched off, the situation is different to a high-side short. At the higher motor speeds, there are no guaranteed zero current periods, instead only a pattern of large and small current values. The strategy must therefore switch in these small current periods, under the assumption that the current is not high enough to damage the SSPIR FETs.

[0145] These small current periods are, in a similar fashion to the zero current periods of a high- side short, produced in a uniform pattern, and occur immediately after the phase electrically before the faulty phase stops conducting, so their location can be inferred using the phase voltage of that phase.

[0146] FET open circuit or gate stuck low

[0147] A FET open circuit fault or gate stuck low fault would for the purposes of the invention be the same as no fault. In the case of a gate stuck low fault, the conduction of the affected FET is the same as if it were to be turned off. In the case of an open circuit FET, it will never conduct, which means it is easier to work with.

[0148] Once the two healthy phases have had their SSPIR turned off, the faulty phase can no longer source current (as neither healthy phase can sink that current). As such, the low side body diode will never conduct. Therefore, a high-side open circuit will mean no current will ever conduct, which will be identified as zero current on the two healthy phases, turning off the faulty SSPIR FET. If the fault is instead a gate stuck low or a low-side FET open circuit, the phase currents will be almost the same as if the fault was a high-side short circuit. This is because the phase can only sink current (due to the SSPIR being off on the two other phases), which is also true in the case of a high-side short circuit. The only difference is that the current will be slightly lower in this case due to the additional body diode drop needed to conduct.

[0149] As such, and as the strategy works for a high-side short circuit fault, it will also work for a FET open circuit or gate stuck low fault.

[0150] FET with indeterminate gate source voltage

[0151] As the strategy only has a single response to all faults, there is no concern if a FET fails (or the FET drive circuitry fails) in a manner where the gate source voltage is indeterminate. The fault will be handled in the same manner as any other fault.

[0152] Second strategy - motor speed below a first intermediate speed.

[0153] Below a first intermediate motor speed, typically of around 900 to 1500rpm but dependent on the motor parameters the first strategy is theoretically viable for use, but due to the reduced speed of the motor the back EMF is expected to be particularly low. The first strategy requires a minimum back EMF to reduce the chance of noise causing a false trip, which would ideally be as large as possible to reduce the chance further.

[0154] The method therefore includes a second strategy to switch off each SSPIR FET using the motor position sense. Over the whole electrical rotation of the motor, there will be a separate period for each SSPIR associated with the healthy bridge FET pair, where that FET alone is not conducting current. These periods (represented by an angular range) can be calculated based on information about the fault and motor direction. By employing a strategy that uses motor position at this speed, the minimum speed and therefore minimum back EMF for the first strategy can be increased.

[0155] Already described is the requirement to identify which phase is electrically before and after the faulty phase for the main strategy, so that information is used here. For both, an angle is calculated as the middle of the safe range, and then a tolerance is used to expand that to a range. For the exemplary three phase motor the phase after’s angle is first calculated as 30 ° plus 120° multiplied by one higher than the phase number of the faulty phase. As an example, if the faulty phase was phase 1, this value would be 270°. This value (and all other angle values) is modulo 360°. The phase before’s angle is then calculated as this value plus 90° (0° for the example).

[0156] If the fault is that a bottom side FET has failed short circuit, both angles have 180° added to them.

[0157] Finally, if the motor has negative angular velocity, the phase after’s angle alone has 180° added to it. No change is made to the phase before’s angle.

[0158] To get the range for each angle, 30° is added and subtracted to it (to get the maximum and minimum respectively.

[0159] The method for calculating the safe range may be identified based on observed safe values from simulation.

[0160] With these values, when the motor position is within the range described the SSPIR FET will immediately be turned off.

[0161] Once the healthy phases have had their SSPIR FETs switched off, the faulty phase can be switched off. A lookup table (shared with the alternate strategy described in 0) is indexed to find the range. In a similar manner to before, when the motor position sense is within this range, the faulty phase’s SSPIR FET is switched off. The bridge is then safe.

[0162] Note that the maximum speed at which the second strategy is best used is that at which the back EMF developed from the motor will not cause the opposing FET’s body diode to conduct. As such, it is found through calculation of the back EMF against the operating envelope of the motor circuit and will in practice be different for each motor.

[0163] Third strategy- motor speed below a second intermediate speed.

[0164] Below a second intermediate speed, that is lower than the first intermediate speed, say 500 to 1000 rpm, the first strategy is not likely to find a safe switching point due to the reduced back EMF from the motor. However, due to the reduced back EMF, there are consistently periods in the motors rotation where there is no current being conducted. These periods are dictated by the uniform pattern of the back EMF waveforms from the three-phase motor, so with the motor position (and inferred from that the current electrical angle) whether it is currently safe to switch off can be ascertained.

[0165] Note that at this speed it is still possible to use the second strategy.

[0166] Due to the uniform pattern of the three-phase back EMF, the safe electrical angle will be the same for every fault of a specific nature. The two variables that make up this specific nature are which of the six FETs has failed and the direction of the motor. These two variables are then combined to get an index for a lookup table. If the failed FET is unknown due to an open circuit fault, the choice of FET defaults to the high side FET.

[0167] With the index found from the type of fault, the lookup tables are indexed to provide the minimum and maximum angles of the safe range. Then, when the motor position sense infers that the electrical angle is within this safe range, all three SSPIR FETs should be turned off at once. The bridge is then safe.

[0168] Fourth strategy- motor speed below a very low motor speed

[0169] Below a very low motor speed, in this example of around lOOrpm to 300rpm, none of the first three strategies are guaranteed to work. This is because the motor will be turning too slowly to guarantee the safe switch off angle will be reached during the turn off requirement period which is a common requirement for all four strategies. The back emf at such low speeds is far too low for the first strategy to be used. However, because the motor is turning so slowly, turning off the SSPIR will either not cause an avalanche current (as the back EMF induced is not enough to drive a body diode) or the avalanche current caused will always be below the maximum limit.

[0170] Immediately turning off all SSPIR FETs can induce a significant avalanche current which, whilst the magnitude is lower than the identified limit, the strategy intends to avoid when possible. Below this previously identified very low motor speed the motor is not guaranteed to reach the safe switch off angle from any initial rotor angle, but there are many possible situations where it will. Take for example if the motor started 10 ° before the safe switch off angle - even at a low speed it is likely to reach the safe angle within the requirement period for turning off.

[0171] To avoid this avalanche current, this alternate substrategy has low priority. When running this substrategy, all other substrategies will be running at the same time. The main substrategy won’t trip due to the reduced back EMF, but one of the two other alternate substrategies may turn off one or more SSPIR FETs within the fault tolerant time, before this strategy will turn off all remaining (if any) SSPIR FETs. 1

[0172] The main idea to give this substrategy low priority is to provide a delay which must be reached before this strategy works.

[0173] The applicant has appreciated that to just provide a delay may not always be appropriate. Imagine an example where the motor sits at 0 RPM for and then jumps to a high RPM - the immediate switch off will be disabled due to the too high speed, but due to the too low average speed there is no guarantee that the second strategy that is also running will be able to turn off the SSPIR fast enough to prevent back emf damaging the SSPIRs when opened.

[0174] The strategy may therefore be modified to use a dynamic delay, based on the current distance from the safe switch off angle. The distance is divided by the speed of the motor to give an expected time duration if this strategy was disabled due to increased speed. The delay to switch off is then set as a fixed maximum switch off requirement period reduced by this duration, meaning that this last strategy will trip if it is possible that not doing so may lead to an unsafe opening of the SSPIRs by one of the other strategies.

Claims

CLAIMS1. A motor circuit including a motor having three or more phases, the motor circuit comprising: a motor bridge having, for each phase of the motor, a bridge arm comprising an upper switch and a lower switch that in normal operation may each be opened and closed to modulate the voltage applied to the respective phases, each bridge arm of the motor bridge being connected to a respective phase of the motor through a phase isolation relay SSPIR, each SSPIR when closed electrically connecting the phase to the bridge and when held open isolating the phase from the bridge, and a processing means that during normal operation of the bridge keeps each SSPIR closed to allow currents to flow in the motor phases, and in which in the event that the processing means receives a signal indicating that a fault has been detected in the bridge the processing means is configured to open all of the SSPIRs following at least two different strategies that are selected for use as a function of the speed of the motor.

2. A motor circuit according to claim 1 which includes a motor speed determining means for determining the speed of the motor which is used to select at least one of the two or more different strategies for use in opening the SSPIRs.

3. A motor circuit according to claim 1 or claim 2 in which the processing means runs more than one strategy such that the strategy that is fastest to determine a safe window of time which to opens the SSPIRS will do so without waiting for results from any other running strategy.

4. A motor control circuit according to any preceding claim in which a first strategy of the at least two different strategies comprises identifying safe zero crossing events by sampling the voltages on each phase and opening one or more SSPIRs when a safe crossing event is detected.

5. A motor control circuit according to claim 4 in which the first strategy is running for all motor speeds but is configured to not open any SSPIRs if the back emf generated by the motor is insufficient.

6. A motor control circuit according to any one of claims 4 or 5 in which at least one of the strategies comprises monitoring the motor electrical position to identify when the motor is in a position where it is safe to switch off an SSPIR.

7. A motor control circuit according to claim 6 in which a second strategy comprises identifying which phase is electrically before and after a faulty phase calculating an angular position of the motor that corresponds to the middle of a safe range of positions for opening an SSPIR and opening the SSPIR once the motor reaches that safe position.

8. A motor control circuit according to claim 7 in which the second strategy is run when the motor speed is below a first intermediate threshold motor speed that substantially corresponds to the speed below which the back emf induced in any phase of the motor in the event of a fault is insufficient to forward bias the body diode of any of the bridge switches by an amount in excess of the body diode reverse voltage of the switch.

9. A motor control circuit according to claim 6 or claim 7 in which a third strategy of the at least two different strategies comprises identifying which of the bridge switches has failed and determining the motor position when there will be zero current flowing in a phase, and at that time opening the SSPIR of that phase.

10. A motor control circuit according to claim 9 in which the third strategy is run when the motor speed is below a second intermediate threshold motor speed that is lower than the first intermediate threshold speed.

11. A motor control circuit according to any one of claims 4 to 10 in which a fourth strategy of the at least two different strategies comprises switching off all SSPIRS together after an elapsed period of time, the third strategy only running when the motor speed is below a third threshold speed that is lower than the second intermediate threshold speed.

12. A motor control circuit according to claim 11 in which the elapsed time is dependent on the motor distance from the safe switch off position used in the second strategy, the greater the distance the smaller the elapsed period of time before opening all the SSPIRs.

13. A motor control strategy according to claim 12 in which the second strategy is also run when the motor speed is below the second threshold.

14. A motor control strategy according to any preceding claim when dependent on claim 4 in which the first strategy comprises as soon as the bridge has been turned off taking samples of the voltage on each phase of the motor and from the samples determine the first safe zero current crossing event to occur after the fault signal has been received,a safe zero current crossing event comprising a period of time immediately after the current in a phase has stopped flowing in the direction in which it was flowing immediately prior to the zero crossing event, and in which the processing means thereafter opens one or more of the SSPIR before the end of the safe zero current crossing event, and further in which the motor circuit a switch control circuit that determines that a fault in the bridge has occurred and turns off the bridge in addition to causing the fault signal to be sent to the processing means.

15. A motor circuit according to claim 14 in which the processing means only compares voltage samples captured after a predefined delay time has elapsed from receiving the signal indicating that a fault has occurred in the bridge in order to identity a safe zero current crossing event.

16. A motor circuit according to claim 15 in which the first strategy includes the processing means taking voltage samples before the delay time has elapsed but after a second shorter delay time has elapsed that is sufficient for all the circuits affecting the bridge to turn off, and from those samples estimates the supply voltage and ground voltage .

17. A method of operating a motor circuit including a motor having three or more phases, the motor circuit comprising: a motor bridge having, for each phase of the motor, a bridge arm comprising an upper switch and a lower switch that in normal operation may each be opened and closed to modulate the voltage applied to the respective phases, each bridge arm of the motor bridge being connected to a respective phase of the motor through a phase isolation relay SSPIR, each SSPIR when closed electrically connecting the phase to the bridge and when held open isolating the phase from the bridge, and the method comprising: during normal operation of the bridge keeping each SSPIR closed to allow currents to flow in the motor phases, and in the event that the processing means receives a signal indicating that a fault has been detected in the bridge the processing means is configured to open all of the SSPIRs following at least two different strategies that are selected for use as a function of the speed of the motor.

Images