Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor in which high reliability against moisture is ensured. A multilayer ceramic capacitor 1 has a stacking-direction central area 203, a first inner-layer portion main-surface-side area 201, and a second inner-layer portion main-surface-side area 202 of a laminate 8, in which the dimension, in a width direction W, of the stacking-direction central area 203 on a first end face 7 and / or a second end face 8 is larger than the dimensions, in the width direction W, of the first inner-layer portion main-surface-side area 201 and the second inner-layer portion main-surface-side area 202 on the first end face 7 and / or the second end face 8, and the dimensions, in the width direction W, of the first inner-layer portion main-surface-side area 201 and the second inner-layer portion main-surface-side area 202 on the first end face 7 and / or the second end face 8 are smaller than the dimensions, in the width direction W, of the first inner-layer portion main-surface-side area 201 and the second inner-layer portion main-surface-side area 202 in a cross section parallel to the width direction W and a stacking direction L in a central portion in the length direction.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors, which comprise a laminate in which dielectric layers and internal electrodes are alternately stacked, and external electrodes electrically connected to the internal electrodes, are a type of electronic component used in a wide range of fields, including communications, IoT, automotive, and medical. In recent years, multilayer ceramic capacitors have been installed in devices used to protect people's safety, creating an increasing demand for improved quality. In particular, the moisture resistance reliability of multilayer ceramic capacitors is one of the factors that significantly influences the likelihood of equipment failure, making it urgent to improve the moisture resistance reliability of multilayer ceramic capacitors.

[0003] For example, Patent Document 1 discloses a technique for adjusting the Si content in a dielectric ceramic in order to provide a multilayer ceramic capacitor that is free from moisture penetration and has excellent moisture resistance reliability.

[0004] Patent Publication No. 2015-029158

[0005] However, in recent years, there has been a demand for higher moisture resistance reliability, and so with conventional multilayer ceramic capacitors, if moisture penetrates inside the capacitor, the moisture easily reaches the inner layer consisting of the internal electrodes and dielectric layers, which poses the problem of not being able to sufficiently guarantee high moisture resistance reliability.

[0006] The present invention has been made to solve the above problems, and an object of the present invention is to provide a multilayer ceramic capacitor that ensures high moisture resistance reliability.

[0007] The multilayer ceramic capacitor of the present invention comprises: an inner layer portion in which a plurality of dielectric layers and a plurality of internal electrodes are alternately stacked; a laminate having first and second main surfaces opposing each other in the stacking direction; first and second side surfaces opposing each other in a width direction perpendicular to the stacking direction; and first and second end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction; a first external electrode provided on the first end surface; and a second external electrode provided on the second end surface, wherein the plurality of internal electrodes include a first internal electrode extended to the first end surface and a second internal electrode extended to the second end surface, and a region of the inner layer portion near the center in the stacking direction is defined as a stacking direction central region, and a region of the inner layer portion on the first main surface side in the stacking direction is defined as a stacking direction central region. If the first inner layer portion main surface side region and the region on the second main surface side of the inner layer portion in the stacking direction are defined as a second inner layer portion main surface side region, the widthwise dimension of the stacking direction central region on at least one of the first end face and the second end face is larger than the widthwise dimension of the first inner layer portion main surface side region and the second inner layer portion main surface side region on at least one of the first end face and the second end face, and the widthwise dimension of the first inner layer portion main surface side region and the second inner layer portion main surface side region on at least one of the first end face and the second end face is smaller than the widthwise dimension of the first inner layer portion main surface side region and the second inner layer portion main surface side region in the cross section in the width direction and the stacking direction at the longitudinal center.

[0008] According to the present invention, it is possible to provide a multilayer ceramic capacitor that ensures high reliability in moisture resistance.

[0009] FIG. 1 is an external perspective view of a multilayer ceramic capacitor according to a first embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line 101-101 in FIG. 1 . FIG. 3 is a cross-sectional view taken along line 102-102 in FIG. 1 . FIG. 4 is a cross-sectional view taken along line 103-103 in FIG. 1 . FIG. 5 is a cross-sectional view of a multilayer ceramic capacitor along a plane parallel to the width direction W and stacking direction T, showing a second end face. FIG. 6 is a view corresponding to FIG. 5 of a conventional multilayer ceramic capacitor. FIG. 7 is a cross-sectional view of a multilayer ceramic capacitor according to another embodiment of the present disclosure along a plane parallel to the width direction W and stacking direction T, showing a second end face. FIG. 8 is a cross-sectional view taken along line 104-104 in FIG. 1 . FIG. 9 is a view of the multilayer ceramic capacitor as seen from a first side. FIG. 10 is a cross-sectional view of a multilayer ceramic capacitor according to a second embodiment of the present disclosure along a plane parallel to the width direction W and stacking direction T. FIG. 11 is a table showing the results of a moisture resistance reliability test. FIG. 12 is a view showing a chip body, a first side gap sheet, and a second side gap sheet. FIG. 13 is a diagram showing a laminated chip in which a first side gap sheet and a second side gap sheet are attached to a chip body.

[0010] First Embodiment A multilayer ceramic capacitor 1 according to one embodiment of the present disclosure will be described with reference to the drawings. Fig. 1 is a perspective view of the appearance of the multilayer ceramic capacitor 1 according to the first embodiment of the present disclosure.

[0011] 1, the multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 2 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 disposed at opposite ends of the laminate 2 and spaced apart from each other.

[0012] An arrow T shown in Fig. 1 indicates the lamination direction T of the multilayer ceramic capacitor 1 and the laminate 2. An arrow L indicates the length direction L of the multilayer ceramic capacitor 1 and the laminate 2, which is perpendicular to the lamination direction T. An arrow W indicates the width direction W of the multilayer ceramic capacitor 1 and the laminate 2, which is perpendicular to the lamination direction T and the length direction L. The lamination direction T, the length direction L, and the width direction W are perpendicular to one another. In figures other than Fig. 1, the arrows T, L, and L each indicate the same directions as those described above.

[0013] One of the pair of external electrodes 40 is provided at one end of the laminate 2 in the longitudinal direction L, and the other is provided at the other end. One of the external electrodes 40 is referred to as a first external electrode 41. The other external electrode 40 is referred to as a second external electrode 42.

[0014] (1) Laminate The laminate 2 will be described with reference to Figures 2, 3, and 4 in addition to Figure 1. Figure 2 is a cross-sectional view taken along line 101-101 of Figure 1. Figure 3 is a cross-sectional view taken along line 102-102 of Figure 1. Figure 4 is a cross-sectional view taken along line 103-103 of Figure 1. As shown in Figure 2, the laminate 2 includes a plurality of laminated dielectric layers 20 and a plurality of internal electrodes 30. The internal electrodes 30 include a first internal electrode 31 and a second internal electrode 32.

[0015] The two surfaces of the laminate 2 facing each other in the stacking direction T are called the first main surface 3 and the second main surface 4. The two surfaces of the laminate 2 facing each other in the width direction W are called the first side surface 5 and the second side surface 6. The two surfaces of the laminate 2 facing each other in the length direction L are called the first end surface 7 and the second end surface 8.

[0016] The laminate 2 has a rectangular parallelepiped shape. It is preferable that the corners and ridges of the laminate 2 are rounded. A corner is a portion where three faces of the laminate 2 intersect, and a ridge is a portion where two faces of the laminate 2 intersect. Concaves and recesses may be formed on some or all of the main faces, side faces, and end faces.

[0017] (Dielectric Layer) The total number of dielectric layers 20 included in the laminate 2 is preferably 15 or more and 700 or less.

[0018] The ceramic material contained in the dielectric layer 20 is, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , CaZrO ３ Furthermore, ceramic materials containing these main components and additionally containing subcomponents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, and Mg compounds may also be used.

[0019] The thickness of one dielectric layer 20 is preferably 0.5 μm or more and 10 μm or less.

[0020] The dimensions of the laminate 2 are not particularly limited, but it is preferable that the dimension of the length direction L of the laminate 2 is 0.2 mm or more and 10 mm or less, the dimension of the width direction W of the laminate 2 is 0.1 mm or more and 10 mm or less, and the dimension of the stacking direction T of the laminate 2 is 0.1 mm or more and 5 mm or less.

[0021] (2) Internal Electrodes The internal electrodes 30 will now be described. The internal electrodes 30 include a plurality of first internal electrodes 31 and a plurality of second internal electrodes 32. The first internal electrodes 31 are internal electrodes 30 exposed at the first end face 7. The second internal electrodes 32 are internal electrodes 30 exposed at the second end face 8. Figure 3 shows the first internal electrodes 31.

[0022] The first internal electrode 31 has a first opposing portion 33 opposing the second internal electrode 32 and a first lead portion 35 extending from the first opposing portion 33 to the first end face 7. The second internal electrode 32 has a second opposing portion 34 opposing the first internal electrode 31 and a second lead portion 36 extending from the second opposing portion 34 to the second end face 8.

[0023] The shape of the first opposing portion 33 of the first internal electrode 31 is not particularly limited, but is preferably rectangular. However, the corners may be rounded or obliquely formed (tapered). Alternatively, the corners may be tapered so that they are inclined in either direction. The shape of the second opposing portion 34 of the second internal electrode 32 is not particularly limited, but is preferably rectangular. However, the corners may be rounded or obliquely formed (tapered). Alternatively, the corners may be tapered so that they are inclined in either direction.

[0024] The shape of the first lead portion 35 of the first internal electrode 31 is not particularly limited, but is preferably rectangular. However, the corners may be rounded or obliquely formed (tapered). Also, a tapered shape with a slope increasing in either direction may be used. The shape of the second lead portion 36 of the second internal electrode 32 is not particularly limited, but is preferably rectangular. However, the corners may be rounded or obliquely formed (tapered). Also, a tapered shape with a slope increasing in either direction may be used.

[0025] In the above description, the corner portion refers to the portion located at the corner of the outer shape of the internal electrode 30 when the internal electrode 30 is viewed in a cross section parallel to the length direction L and width direction W of the laminate 2.

[0026] The width in the width direction W of the first opposing portion 33 of the first internal electrode 31 and the width in the width direction W of the first lead portion 35 of the first internal electrode 31 may be the same, or one of the widths may be formed narrower. The width in the width direction W of the second opposing portion 34 of the second internal electrode 32 and the width in the width direction W of the second lead portion 36 of the second internal electrode 32 may be the same, or one of the widths may be formed narrower.

[0027] The first internal electrode 31 and the second internal electrode 32 can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0028] The thickness of each of the first internal electrode 31 and the second internal electrode 32 is preferably, for example, about 0.2 μm or more and 2.0 μm or less.

[0029] The total number of the first internal electrodes 31 and the second internal electrodes 32 is preferably 15 or more and 200 or less.

[0030] (Outer Layer Portion and Inner Layer Portion) The divisions of the laminate 2 will be described. First, the divisions of the laminate 2 in the stacking direction T will be described. As shown in Figures 2 and 4, the laminate 2 can be divided into an inner layer portion 10, a first outer layer portion 12, and a second outer layer portion 13 in the stacking direction T.

[0031] The inner layer portion 10 refers to the portion of the laminate 2 included between the position of the internal electrode 30 closest to the first main surface 3 and the position of the internal electrode 30 closest to the second main surface 4 in the stacking direction T.

[0032] The first outer layer portion 12 is a portion of the laminate 2 included between the first main surface 3 and the position of the internal electrode 30 closest to the first main surface 3 in the stacking direction T. In other words, the first outer layer portion 12 is the laminate 2 included between the inner layer portion 10 and the first main surface 3.

[0033] The second outer layer portion 13 refers to a portion of the laminate 2 included between the second main surface 4 and the position of the internal electrode 30 closest to the second main surface 4 in the stacking direction T. In other words, the second outer layer portion 13 refers to the laminate 2 included between the inner layer portion 10 and the second main surface 4. The first outer layer portion 12 and the second outer layer portion 13 are collectively referred to as the outer layer portion 11.

[0034] (Core Portion and Side Gap Portion) Next, the division of the laminate 2 in the width direction W will be described. As shown in FIGS. 3 and 4 , the laminate 2 can be divided into a core portion 25, a first side gap portion 15, and a second side gap portion 16 in the width direction W. The core portion 25 is the portion of the laminate 2 in which the internal electrode 30 is provided in the width direction W. The first side gap portion 15 is the portion of the laminate 2 between the core portion 25 and the first side surface 5. The second side gap portion 16 is the portion of the laminate 2 between the core portion 25 and the second side surface 6. The first side gap portion 15 and the second side gap portion 16 do not have the internal electrode 30 provided therein, and only the dielectric layer 20 is provided therein. The first side gap portion 15 and the second side gap portion 16 are collectively referred to as the side gap portion 14. The side gap portion is also referred to as a W gap.

[0035] (Effective Portion and Ineffective Portion) Next, the division of the core portion 25 in the stacking direction T will be described. As shown in FIG. 4 , the core portion 25 can be divided into an effective portion 26, a first ineffective portion 28, and a second ineffective portion 29 in the stacking direction T. The effective portion 26 is the portion of the core portion 25 in which the first internal electrode 31 or the second internal electrode 32 is arranged in the stacking direction T. The first ineffective portion 28 is the portion between the effective portion 26 and the first main surface 3 in the stacking direction T of the core portion 25. The second ineffective portion 29 is the portion between the effective portion 26 and the second main surface 4 in the stacking direction T of the core portion 25. The first ineffective portion 28 and the second ineffective portion 29 do not have an internal electrode 30, and only have a dielectric layer 20 provided therein. The first ineffective portion 28 and the second ineffective portion 29 are collectively referred to as an ineffective portion 27.

[0036] (Opposite Electrode Portion) The portion where the first internal electrode 31 and the second internal electrode 32 overlap is called the opposite electrode portion 38. The opposite electrode portion 38 is the portion where the first opposite portion 33 and the second opposite portion 34 overlap. In the multilayer ceramic capacitor 1, capacitance is formed when the opposite portions of the internal electrodes 30 face each other with the dielectric layer 20 interposed therebetween, thereby realizing the characteristics of the capacitor. In other words, capacitance is formed in the opposite electrode portion 38.

[0037] 2 and 3 , in the laminate 2, a portion located between the opposing electrode portion 38 and the end face and including the lead portion of either the first internal electrode 31 or the second internal electrode 32 is referred to as the L gap 17. The L gap 17 includes a first L gap 18 and a second L gap 19. The first L gap 18 is located between the opposing electrode portion 38 and the first end face 7 and is a portion including the first lead portion 35. The second L gap 19 is located between the opposing electrode portion 38 and the second end face 8 and is a portion including the second lead portion 36.

[0038] (3) External Electrode The external electrode 40 includes a first external electrode 41 and a second external electrode 42. The first external electrode 41 is connected to the first internal electrode 31 and is disposed on the first end face 7. The first external electrode 41 may also be disposed on a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6. In this embodiment, the first external electrode 41 is formed to extend from the first end face 7 to a portion of the first main surface 3 and a portion of the second main surface 4, as well as a portion of the first side surface 5 and a portion of the second side surface 6.

[0039] The second external electrode 42 is connected to the second internal electrode 32 and is disposed on the second end face 8. The second external electrode 42 may also be disposed on a portion of the first main surface 3 and a portion of the second main surface 4, a portion of the first side surface 5 and a portion of the second side surface 6. In this embodiment, the second external electrode 42 is formed to extend from the second end face 8 to a portion of the first main surface 3 and a portion of the second main surface 4, a portion of the first side surface 5 and a portion of the second side surface 6.

[0040] The first external electrode 41 and the second external electrode 42 preferably have a base electrode layer 50 and a plating layer 60. The base electrode layer 50 included in the first external electrode 41 is referred to as the first base electrode layer 51, and the base electrode layer 50 included in the second external electrode 42 is referred to as the second base electrode layer 52. Furthermore, the plating layer 60 included in the first external electrode 41 is referred to as the first plating layer 61, and the plating layer 60 included in the second external electrode 42 is referred to as the second plating layer 62.

[0041] (Base Electrode Layer) The base electrode layer 50 will be described. The base electrode layer 50 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like. The case where the base electrode layer 50 is a baked layer will be described. The baked layer includes a glass component and a metal. The glass component of the baked layer includes at least one element selected from, for example, B, Si, Ba, Mg, Al, and Li. The metal of the baked layer includes at least one element selected from, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, and Au.

[0042] The baking layer may be formed in multiple layers. The baking layer is formed by applying a conductive paste containing a glass component and a metal to the laminate and baking it. The baking layer may be simultaneously baked with the internal electrodes and the dielectric layers, or may be baked after the internal electrodes are baked. When the baking layer is simultaneously baked with the internal electrodes and the dielectric layers, it is preferable to form the baking layer by adding a dielectric material instead of the glass component.

[0043] At the center position in the stacking direction T connecting the first main surface 3 and the second main surface 4 of the baking layer located at the first end surface 7 and the second end surface 8, the thickness in the length direction L connecting the first end surface 7 and the second end surface 8 of the baking layer is preferably, for example, approximately 3 μm or more and 160 μm or less.

[0044] Furthermore, when a baked layer as the base electrode layer 50 is provided on a portion of the first main surface 3 and a portion of the second main surface 4, as well as on a portion of the first side surface 5 and a portion of the second side surface 6, it is preferable that the thickness in the stacking direction T connecting the first main surface 3 and the second main surface 4 at the center of the length direction L connecting the first end surface 7 and the second end surface 8 of the base electrode layer 50 located on the first main surface 3 and the second main surface 4, and the first side surface 5 and the second side surface 6 is, for example, approximately 3 μm or more and 40 μm or less.

[0045] (Plating Layer) Next, the plating layer 60 will be described. The plating layer 60 has a first plating layer 61 and a second plating layer 62. The first plating layer 61 is disposed so as to cover the first base electrode layer 51. The second plating layer 62 is disposed so as to cover the second base electrode layer 52.

[0046] The material constituting the plating layer 60 includes at least one selected from the group consisting of Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, and Au.

[0047] The plating layer 60 may be formed of multiple layers. In this embodiment, the first plating layer 61 and the second plating layer 62 each include two plating layers. When the plating layer 60 has a two-layer structure, preferably, one layer is a Ni plating layer and the other is a Sn plating layer. The Ni plating layer included in the first plating layer 61 is the first Ni plating layer 63, and the Ni plating layer included in the second plating layer 62 is the second Ni plating layer 64. The Sn plating layer included in the first plating layer 61 is the first Sn plating layer 65, and the Sn plating layer included in the second plating layer 62 is the second Sn plating layer 66. The Ni plating layer can prevent the base electrode layer 50 from being eroded by solder when mounting ceramic electronic components. The Sn plating layer improves the wettability of solder when mounting ceramic electronic components, allowing for easier mounting. Therefore, it is preferable that the plating layers be an Ni plating layer and an Sn plating layer in that order, starting from the plating layer in contact with the base electrode layer 50. The plating layer 60 may be three or more layers, and may contain a metal species other than Ni and Sn as a main component.

[0048] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less.

[0049] (When no base electrode layer is provided) The external electrodes may be formed only with plating layers, without providing a base electrode layer. A structure in which only plating layers are provided without providing a base electrode layer will be described below. The first external electrode and the second external electrode may each not be provided with a base electrode layer, and the plating layer may be formed directly on the surface of the laminate. In other words, the multilayer ceramic capacitor may have a structure including a plating layer that is directly and electrically connected to the first internal electrode or the second internal electrode. When the external electrodes have such a structure, the plating layer may be formed after a catalyst is disposed on the surface of the laminate as a pretreatment before plating.

[0050] The plating layer preferably includes a lower-layer plating electrode formed on the surface of the laminate and an upper-layer plating electrode formed on the surface of the lower-layer plating electrode. The lower-layer plating electrode and the upper-layer plating electrode each preferably include at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal. The lower-layer plating electrode is preferably formed using Ni, which has solder barrier properties. The upper-layer plating electrode is preferably formed using Sn or Au, which have good solder wettability.

[0051] Furthermore, for example, when the first internal electrode and the second internal electrode are formed using Ni, it is preferable that the lower-layer plated electrode be formed using Cu, which has good bonding properties with Ni. Note that the upper-layer plated electrode may be formed as needed, and the first external electrode and the second external electrode may each be composed of only the lower-layer plated electrode. The upper-layer plated electrode may be the outermost layer of the plating layer, or another plated electrode may be formed on the surface of the upper-layer plated electrode.

[0052] The thickness of each plating layer disposed without a base electrode layer is preferably 1 μm or more and 15 μm or less. The plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0053] (5) Dimensions of the Multilayer Ceramic Capacitor When the size of the multilayer ceramic capacitor 1 including the laminate 2 and the external electrodes 40 is described as "length direction (L) dimension × width direction (W) dimension × stacking direction (T) dimension," it is generally expected to be, for example, "1.6 mm × 0.8 mm × 0.8 mm," "1.0 mm × 0.5 mm × 0.5 mm," "0.6 mm × 0.3 mm × 0.3 mm," "0.4 mm × 0.2 mm × 0.2 mm," or "0.2 mm × 0.1 mm × 0.1 mm," but is not limited to the above sizes.

[0054] The thickness of the first outer layer portion 12 and the thickness of the second outer layer portion 13 can be set to, for example, 10 μm or more and 80 μm or less.

[0055] (End Faces of the Laminate) The multilayer ceramic capacitor 1 of this embodiment differs from the conventional multilayer ceramic capacitor 100 in the shape of the end faces of the laminate 2. This will be described with reference to FIG. 5. FIG. 5 is a cross-sectional view of the second end face 8 taken along a plane parallel to the width direction W and lamination direction T of the multilayer ceramic capacitor. FIG. 5 shows a cross section of the multilayer ceramic capacitor 1 taken along line 105-105 in FIGS. 2 and 3. Note that the matters described below with reference to the second end face 8 also apply to the first end face 7.

[0056] (Regions in the inner layer portion) The inner layer portion 10 is divided into three regions. The region near the center of the stacking direction T of the inner layer portion 10 is referred to as a stacking direction central region 203, the region on the first main surface 3 side of the inner layer portion 10 in the stacking direction T is referred to as a first inner layer portion main surface side region 201, and the region on the second main surface 4 side of the inner layer portion 10 in the stacking direction T is referred to as a second inner layer portion main surface side region 202.

[0057] The range of each of the above regions can be determined as follows: In FIG. 5, the dimension of the inner layer portion 10 in the stacking direction T is indicated by dimension 300.

[0058] The first inner layer portion main surface side region 201 is a region on the first main surface 3 side extending from the internal electrode 30 closest to the first main surface 3 toward the second main surface 4 up to 30% of the dimension 300. The dimension 301 is the dimension of the first inner layer portion main surface side region 201 in the stacking direction T. The dimension 301 is 30% of the dimension 300.

[0059] The second inner layer portion main surface side region 202 is a region on the second main surface 4 side extending from the internal electrode 30 closest to the second main surface 4 toward the first main surface 3 up to 30% of the dimension 300. The dimension 302 is the dimension of the second inner layer portion main surface side region 202 in the stacking direction T. The dimension 302 is 30% of the dimension 300.

[0060] The stacking direction central region 203 is a region of the inner layer portion 10 other than the first inner layer portion main surface side region 201 and the second inner layer portion main surface side region 202. Dimension 303 is the dimension of the first inner layer portion main surface side region 201 in the stacking direction T. Dimension 303 is 40% of dimension 300.

[0061] (Shape of inner layer portion at end face) In the multilayer ceramic capacitor 1 of this embodiment, the dimension in the width direction W of the stacking direction central region 203 at least one of the first end face 7 and the second end face 8 is larger than the dimension in the width direction W of the first inner layer portion main surface side region 201 and the second inner layer portion main surface side region 202 at least one of the first end face 7 and the second end face 8.

[0062] 5, the maximum dimension in the width direction W of the stacking direction central region 203 is indicated by dimension Wc, the minimum dimension in the width direction W of the first inner layer portion main surface side region 201 is indicated by dimension Wp1, and the minimum dimension in the width direction W of the second inner layer portion main surface side region 202 is indicated by dimension Wp2. Dimension Wc is larger than dimensions Wp1 and Wp2. Note that the relationship between dimensions Wp1 and Wp2 may be such that dimension Wp1 is larger than, smaller than, or equal to dimension Wp2.

[0063] (Shape of External Electrodes on End Faces) In the multilayer ceramic capacitor 1 of this embodiment, the thickness of the external electrodes 40 in the width direction W can be increased near the main surfaces.

[0064] 5, the thickness Ec indicates the thickness in the width direction W of the second external electrode 42 at a position in the stacking direction T corresponding to the stacking direction central region 203. The thickness Ec is the thickness in the width direction W of the second external electrode 42 at the central position in the stacking direction T of the laminate 2.

[0065] The thickness Ep1 indicates the thickness in the width direction W of the second external electrode 42 at a position in the stacking direction T corresponding to the first inner layer portion main surface side region 201. The thickness Ep1 is the thickness of the second external electrode 42 disposed on an extension line in the width direction W of the internal electrode 30 closest to the first main surface 3.

[0066] The thickness Ep2 denotes the thickness in the width direction W of the second external electrode 42 at a position in the stacking direction T corresponding to the second inner layer portion main surface side region 202. The thickness Ep2 is the thickness of the second external electrode 42 disposed on an extension line in the width direction W of the internal electrode 30 closest to the second main surface 4.

[0067] The thickness Ec, the thickness Ep1, and the thickness Ep2 indicate the thickness of the second external electrode 42 in the width direction W on one of the two side surfaces. Note that the thickness Ec, the thickness Ep1, and the thickness Ep2 in Fig. 5 indicate the thickness of the second external electrode 42 formed on the first side surface 5, but the thickness of the second external electrode 42 formed on the second side surface 6 is also the same as the thickness of the second external electrode 42 formed on the first side surface 5.

[0068] As described above, in the multilayer ceramic capacitor 1 of this embodiment, the dimension Wc of the inner layer portion 10 is larger than the dimensions Wp1 and Wp2. Due to this shape of the inner layer portion 10, the thicknesses Ep1 and Ep2 are larger than the thickness Ec. In other words, the thickness of the second outer electrode 42 in the first inner layer portion main surface side region 201 and the second inner layer portion main surface side region 202 is larger than the thickness of the second outer electrode 42 in the stacking direction central region 203.

[0069] Here, the ends of the internal electrodes 30 in the width direction W are referred to as internal electrode width direction ends 37. As shown in Fig. 5 , in the multilayer ceramic capacitor 1 of this embodiment, the external electrodes 40 arranged at the internal electrode width direction ends 37 of the internal electrodes 30 near the outer layer portions 11 in the stacking direction T are thicker than the external electrodes 40 arranged on the first side faces 5 and the second side faces 6 in the stacking direction central region 203.

[0070] (Conventional Multilayer Ceramic Capacitor) FIG. 6 is a diagram corresponding to FIG. 5 of a conventional multilayer ceramic capacitor 100. The dimension W100 shown in FIG. 6 is the dimension in the width direction W of the inner layer portion 10 in the conventional multilayer ceramic capacitor 100. As shown in FIG. 6, the dimension W100 is constant throughout the entire area of ​​the inner layer portion 10 in the stacking direction T. In other words, unlike the multilayer ceramic capacitor 1 of this embodiment shown in FIG. 5, the dimension in the width direction W of the inner layer portion 10 in the conventional multilayer ceramic capacitor 100 is constant. The dimension E100 in FIG. 6 is the dimension in the width direction W of the external electrode 40 in the conventional multilayer ceramic capacitor 100. Because the dimension W100 is constant throughout the entire area of ​​the inner layer portion 10 in the stacking direction T, the dimension E100 is also constant throughout the entire area of ​​the inner layer portion 10 in the stacking direction T.

[0071] As described above, in the multilayer ceramic capacitor 1 of this embodiment, unlike the conventional multilayer ceramic capacitor 100, the external electrodes 40 arranged at the internal electrode width direction ends 37 of the internal electrodes 30 near the outer layer portions 11 in the stacking direction T are thicker than the external electrodes 40 arranged on the first side faces 5 and the second side faces 6 in the stacking direction central region 203. This makes it possible to lengthen the moisture penetration path in the second external electrode 42 to the internal electrode width direction ends 37 near the outer layer portions 11 in the stacking direction T, where moisture penetration is relatively likely to occur. As a result, the moisture resistance reliability of the multilayer ceramic capacitor 1 can be ensured.

[0072] 5, the outline of the second end face 8 is depicted by straight lines and right-angle bends. However, FIG. 5 shows the outline of the second end face 8 in a modeled manner. For example, the boundary between the stacking direction central region 203 and the first inner layer portion main surface side region 201, indicated by arrows 211 and 212, may be rounded rather than right-angled.

[0073] Furthermore, the shape of the end face of the laminate 2 is not limited to the shape shown in FIG. 5 . The shape of the end face of the laminate 2 can be modified in various ways. FIG. 7 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along a plane parallel to the width direction W and stacking direction T, showing the second end face of another shape. The dimension Wt1 shown in FIGS. 5 and 7 described above indicates the maximum dimension in the width direction W of the laminate 2 of the first outer layer portion 12. The dimension Wt2 indicates the maximum dimension in the width direction W of the laminate 2 of the second outer layer portion 13. In the example shown in FIG. 5 , the dimension Wt1 is approximately equal to the dimension Wp1, and the dimension Wt2 is approximately equal to the dimension Wp2. However, the dimension Wt1 may be smaller than the dimension Wp1, and the dimension Wt2 may be smaller than the dimension Wp2.

[0074] In the example shown in FIG. 5 , the dimension Wt1 was approximately equal to the dimension Wp1. Furthermore, the dimension Wt2 was approximately equal to the dimension Wp2. In contrast, in the example shown in FIG. 7 , the dimension Wt1 was larger than the dimension Wp1, and the dimension Wt2 was larger than the dimension Wp2. Thus, in the example shown in FIG. 7 , the dimension of the laminate 2 in the width direction W is smaller in the first inner layer portion main surface side region 201 and the second inner layer portion main surface side region 202 than in the stacking direction central region 203, but is the same as that in the stacking direction central region 203 in the outer layer portion 11. Even in the example shown in FIG. 7 , the moisture penetration path in the second external electrode 42 to the internal electrode width direction end 37 near the outer layer portion 11 in the stacking direction T, where moisture penetration is relatively likely to occur, can be lengthened. As a result, the moisture resistance reliability of the multilayer ceramic capacitor 1 can be ensured.

[0075] 7, the dimension of the laminate 2 in the width direction W in the outer layer portion 11 is larger than the dimensions in the first inner layer portion main surface side region 201 and the second inner layer portion main surface side region 202. Therefore, in the example shown in FIG. 7, it is easy to ensure the strength of the laminate 2.

[0076] The following describes preferred dimensions in the width direction W of the laminate 2. The ratio (Wp1 / Wc) of the minimum width dimension Wp1 of the first inner layer portion main surface side region 201 to the maximum width dimension Wc of the stacking direction central region 203, and the ratio (Wp2 / Wc) of the minimum width dimension Wp2 of the second inner layer portion main surface side region 202 to the maximum width dimension Wc of the stacking direction central region 203 are preferably 0.85 or more and 0.98 or less.

[0077] When each dimension is within the above range, there is a more significant difference in the thickness in the width direction W of the external electrode 40 between the first inner layer portion main surface side region 201 and the second inner layer portion main surface side region 202 and the stacking direction central region 203. This makes it possible to lengthen the path for moisture penetration in the external electrode 40 to the internal electrode width direction end portion 37. As a result, the moisture resistance reliability of the multilayer ceramic capacitor 1 can be more reliably improved.

[0078] If the ratio is greater than 0.95, the difference in thickness of the external electrodes 40 is insufficient, and moisture resistance reliability is not sufficiently ensured. On the other hand, if the ratio is less than 0.5, the overall thickness of the external electrodes 40 is difficult to increase, and moisture resistance reliability is not sufficiently ensured.

[0079] (Method of Measuring Wp1 / Wc and Wp2 / Wc) The method of measuring the ratios (Wp1 / Wc) and (Wp2 / Wc) will be described. 1. The multilayer ceramic capacitor 1 is polished down to the end faces. Specifically, the multilayer ceramic capacitor 1 is polished on a surface parallel to the width direction W and the stacking direction T to expose the end faces. 2. The exposed end faces are examined using an optical microscope, and the dimension Wp1 in the first inner layer portion main surface side region 201, the dimension Wc in the stacking direction central region 203, and the dimension Wp2 in the second inner layer portion main surface side region 202 are measured. 3. The ratios (Wp1 / Wc) and (Wp2 / Wc) are calculated based on the measured dimensions.

[0080] (Method for measuring Ep1 / Ec and Ep2 / Ec) Next, the method for measuring the ratios (Ep1 / Ec) and (Ep2 / Ec) will be described. First, the end face is exposed using the same method as in 1 above. 2. The end face is examined using an optical microscope, and the thickness Ep1 of the external electrode 40 arranged on an extension in the width direction W of the internal electrode 30 closest to the first main surface 3, the thickness Ec of the external electrode 40 arranged at the center of the laminate 2 in the stacking direction T, and the thickness Ep2 of the external electrode 40 arranged on an extension in the width direction W of the internal electrode 30 closest to the second main surface 4 are measured. 3. The ratios (Ep1 / Ec) and (Ep2 / Ec) are calculated based on the measured thicknesses.

[0081] (Moisture Resistance Reliability Test) The results of the moisture resistance reliability test will be described with reference to FIG. 11 . FIG. 11 is a table showing the results of the moisture resistance reliability test. The moisture resistance reliability test was carried out using the following criteria: 1. The fabricated multilayer ceramic capacitor 1 was mounted on a substrate, and a moisture resistance test was carried out. The moisture resistance test was carried out at a humidity of 95% and a temperature of 120°C, with a voltage of 25 V applied to the substrate on which the multilayer ceramic capacitor 1 was mounted for 200 hours. 2.1 The appearance of the multilayer ceramic capacitor 1 mounted on the substrate was observed using an optical microscope. Multilayer ceramic capacitors 1 in which metal was deposited on the surface of the laminate 2 where the first external electrode 41 and the second external electrode 42 were not formed were determined to be defective. The number of defectives was counted for each sample. A defect rate of less than 10% was determined to be "good," a defect rate of less than 5% was determined to be "very good," and anything else was determined to be "defective."

[0082] As shown in Fig. 11, samples in which the ratio (Wp1 / Wc) and the ratio (Wp2 / Wc) were 0.85 or more and 0.98 or less were judged to be "very good." On the other hand, samples in which the ratio (Wp1 / Wc) and the ratio (Wp2 / Wc) were 1 were judged to be "poor." The other samples were judged to be "good."

[0083] (Central Portion in the Lengthwise Direction) FIG. 8 is a cross-sectional view taken along line 104-104 in FIG. 1. FIG. 8 shows a cross section of the multilayer ceramic capacitor 1 at a plane parallel to the width direction W and the lamination direction T at the central portion in the lengthwise direction L. As shown in FIG. 8, at the central portion in the lengthwise direction L, the dimension in the width direction W of the laminate 2 is uniform regardless of the position in the height direction T from the first main surface 3 to the second main surface 4. As shown in FIGS. 5 and 7, the dimensions Wp1 and Wp2 are not smaller than the dimension Wc. In other words, the dimensions Wp1 and Wp2 at the end faces are smaller than the dimensions Wp1 and Wp2 at the central portion in the lengthwise direction L.

[0084] Thus, in the multilayer ceramic capacitor 1 of this embodiment, the width direction W dimension of the first inner layer portion main surface side region 201 and the second inner layer portion main surface side region 202 on at least one of the first end face 7 and the second end face 8 is smaller than the width direction dimension of the first inner layer portion main surface side region and the second inner layer portion main surface side region on a cross section parallel to the width direction W and the stacking direction T at the center of the length direction L of the multilayer ceramic capacitor 1.

[0085] Furthermore, for example, when the dimensions in the width direction W of the first inner layer portion main surface side region 201 and the second inner layer portion main surface side region 202 of the first end face 7 are smaller than the dimensions in the width direction W of the first inner layer portion main surface side region 201 and the second inner layer portion main surface side region 202 in a cross section taken along a plane parallel to the width direction W and the stacking direction T at the center of the length direction L, the second end face 8 may or may not have the above-described configuration. Furthermore, in the above-described configuration, the first end face 7 and the second end face 8 may be interchanged.

[0086] When the external electrodes 40 are formed on the end faces having the above-described shape, the external electrodes 40 arranged at the internal electrode width direction ends 37 near the outer layer portions 11 are thicker than the external electrodes 40 arranged on the first side faces 5 and the second side faces 6 in the stacking direction central region 203. This makes it possible to lengthen the path for moisture to penetrate to the internal electrode width direction ends 37 near the outer layer portions 11, where moisture penetration is relatively likely to occur, and as a result, the moisture resistance reliability of the multilayer ceramic capacitor 1 can be ensured.

[0087] (Protruding Portion) The protruding portion 223 of the laminate 2 will be described with reference to Fig. 9. Fig. 9 is a view of the multilayer ceramic capacitor 1 as seen from the first side surface. A protruding portion 223 that protrudes in the length direction L beyond the first inner layer portion main surface side region 201 and the second inner layer portion main surface side region 202 is formed on at least one of the first end face 7 side and the second end face 8 side in the central portion of the laminate 2 in the stacking direction T.

[0088] The dimensions of the protrusion will now be described. Dimension 313 in Fig. 9 indicates the dimension of the protrusion 223 in the stacking direction T at the second end surface 8. Dimension 310 in Fig. 9 indicates the dimension of the laminate 2 in the stacking direction T. It is preferable that (dimension 313 of protrusion 223) / (dimension 310 of laminate 2) is 1 / 3 or more and 8 / 10 or less.

[0089] When the external electrodes 40 are formed on the surfaces of the laminate 2 by the application process, the external electrodes 40 are formed without conforming to the outer shape of the laminate 2 due to the surface tension (viscosity) of the external electrode paste applied to the laminate 2. In the multilayer ceramic capacitor 1 of the embodiment, a protrusion 223 is provided on the end face side of the center portion in the stacking direction T of the laminate 2. This makes it possible to increase the thickness of the external electrodes 40 near the outer layer portions 11, i.e., in the main surface side region of the inner layer portions. This makes it possible to lengthen the moisture penetration path at the width direction end portions of the internal electrodes near the outer layer portions, thereby more reliably improving moisture resistance reliability.

[0090] (Recess) The recess of the laminate 2 will be described with reference to Fig. 9. As shown in Fig. 9, recesses, which are recessed portions of the laminate 2, are formed on both sides of the protruding portion 223 in the stacking direction T.

[0091] In the first inner layer main surface side region 201, a first recess 221 is formed on at least one of the end faces, and the dimension in the width direction W of the laminate 2 is smaller than that of the center in the length direction L. In the second inner layer main surface side region 202, a second recess 222 is formed on at least one of the end faces, and the dimension in the width direction W of the laminate 2 is smaller than that of the center in the length direction L.

[0092] 9, the area in which the recesses are formed is not limited to the inner layer portion main surface side region. The first recess 221 may extend beyond the first inner layer portion main surface side region 201 to the first outer layer portion 12. The second recess 222 may extend beyond the second inner layer portion main surface side region 202 to the second outer layer portion 13.

[0093] The dimension of the recess in the length direction L will now be described. Dimension 321 in Fig. 9 indicates the dimension of the second recess 222 in the length direction L from the second end face 8. The dimension of the first recess 221 in the length direction L from the second end face 8 is also the same as dimension 321. Dimension 321 is also the dimension of the protrusion 223 in the length direction L. The recess is called a protrusion because the part that remains after the recess is formed becomes the protrusion; in other words, the recess is formed in order to form the protrusion.

[0094] 9 indicates the dimension in the length direction L of the laminate 2. Here, the recess or protrusion 223 is preferably formed in an area extending from the end face to 25% of the dimension 323 in the length direction L of the laminate 2. In other words, (dimension 321 of the second recess) / (dimension 323 of the laminate 2) is preferably 1 / 4 or less. In other words, the first recess 221 and the second recess 222 are preferably provided in an area extending from the end face to 25% of the dimension in the length direction L of the laminate 2.

[0095] According to the above configuration, the first recess 221 and the second recess 222 are present in a region extending from the end face to 25% of the longitudinal dimension of the laminate 2. In other words, the protrusion 223 is present in a region extending from the end face to 25% of the longitudinal dimension of the laminate 2. This more reliably increases the thickness of the external electrode 40 in the inner layer portion main surface side region. In other words, the thickness of the external electrode 40 in the external electrode main surface side region can be reliably formed thicker than the thickness of the external electrode 40 in the central region in the stacking direction. This lengthens the path for moisture penetration to the internal electrode width direction end 37. As a result, the moisture resistance reliability of the multilayer ceramic capacitor 1 can be more reliably ensured.

[0096] The dimensions of the recesses in the stacking direction T will be described. Dimension 311 in Fig. 9 indicates the dimension of the first recess 221 in the stacking direction T from the first main surface 3. Dimension 312 indicates the dimension of the second recess 222 in the stacking direction T from the second main surface 4. Dimension 310 indicates the dimension of the stack 2 in the stacking direction T.

[0097] It is preferable that the ratios of the dimension 311 in the stacking direction T of the first recess 221 and the dimension 312 in the stacking direction T of the second recess 222 to the dimension 310 in the stacking direction T of the laminate 2 at the end face, i.e., the ratio (dimension 311 / dimension 310) and the ratio (dimension 312 / dimension 310), are greater than or equal to 1 / 10 and less than or equal to 1 / 3, respectively.

[0098] By setting the ratios of the dimension 311 in the stacking direction T of the first recess 221 and the dimension 312 in the stacking direction T of the second recess 222 to the dimension 310 in the stacking direction T of the laminate 2 to be 1 / 10 or more and 1 / 3 or less, respectively, the probability that the thickness of the external electrode 40 in the inner layer portion main surface side region will be thicker than the thickness of the external electrode 40 in the stacking direction central region 203 increases. As a result, the moisture resistance reliability of the multilayer ceramic capacitor 1 can be more reliably ensured.

[0099] 9 is the dimension of the protrusion 223 in the stacking direction T. The dimension 313 is the dimension obtained by subtracting the dimensions 311 and 312 from the dimension 310.

[0100] Furthermore, it is preferable that the first recess 221 and the second recess 222 are filled with the external electrode 40. By filling the recesses with the external electrode 40, the current path is shortened and the resistance value is suppressed during mounting while maintaining moisture resistance reliability. Such a multilayer ceramic capacitor is suitable for use in power supply circuits, etc.

[0101] The external electrode 40 of this embodiment will be described in more detail, summarizing its features. On the first end face 7, the thickness of the first external electrode 41 arranged in the first inner layer portion main surface side region 201 and the second inner layer portion main surface side region 202 is smaller than the thickness of the first external electrode 41 arranged in the stacking direction central region 203. On the second end face 8, the thickness of the second external electrode 42 arranged in the first inner layer portion main surface side region 201 and the second inner layer portion main surface side region 202 is smaller than the thickness of the second external electrode 42 arranged in the stacking direction central region 203. This structure may be present on one or both of the first end face 7 and the second end face 8.

[0102] The thickness of the base electrode layer 50 will now be described. At the first end face 7, the thickness of the first base electrode layer 51 disposed in the first inner-layer portion main surface side region 201 and the second inner-layer portion main surface side region 202 is smaller than the thickness of the first base electrode layer 51 disposed in the stacking direction central region 203. At the second end face 8, the thickness of the second base electrode layer 52 disposed in the first inner-layer portion main surface side region 201 and the second inner-layer portion main surface side region 202 is smaller than the thickness of the second base electrode layer 52 disposed in the stacking direction central region 203. This structure may be present at both the first end face 7 and the second end face 8. This structure can lengthen the moisture penetration path, via a plating layer or the like, to the internal electrode width direction end 37 near the outer layer portion 11, where moisture penetration is relatively likely to occur, thereby ensuring moisture resistance reliability.

[0103] The thickness of the external electrode 40 will be described in more detail. The thickness Ep1 of the external electrode 40 in the first inner layer portion main surface side region 201 and the thickness Ep2 of the external electrode 40 in the second inner layer portion main surface side region 202 described above are defined as the thickness Ep of the external electrode 40 in the inner layer portion main surface side region. The ratio of the thickness Ep of the external electrode 40 in the inner layer portion main surface side region to the thickness Ec of the external electrode 40 in the stacking direction central region 203 (Ep / Ec) is preferably 1.05 or more and 1.3 or less, more preferably 1.1 or more and 1.3 or less.

[0104] If the ratio (Ep / Ec) is less than 1.05, the path for moisture penetration to the internal electrode width direction end 37 is short, and moisture resistance reliability cannot be guaranteed. On the other hand, if the ratio (Ep / Ec) exceeds 1.3, the surface tension of the external electrode paste is overcome by gravity, and it is difficult to achieve an external electrode 40 with an Ep / Ec ratio exceeding 1.3 in the first place. If the ratio (Ep / Ec) is 1.05 or more and 1.3 or less, moisture resistance reliability can be improved.

[0105] (External Electrode End Surface Regions and External Electrode Side Surface Regions) The external electrode end surface regions and external electrode side surface regions will be described with reference to FIGS. 1 and 9 . As described above, the external electrode 40 is disposed not only on the end surfaces but also on parts of the main surfaces and side surfaces. As shown in FIGS. 1 and 9 , the region of the first external electrode 41 that covers the first end surface 7 is referred to as the first external electrode end surface region 44. Furthermore, the region of the first external electrode 41 that covers parts of the first side surface 5 and the second side surface 6 is referred to as the first external electrode side surface region 46. The region of the second external electrode 42 that covers the second end surface 8 is referred to as the second external electrode end surface region 45. Furthermore, the region of the second external electrode 42 that covers parts of the first side surface 5 and the second side surface 6 is referred to as the second external electrode side surface region 47.

[0106] In the multilayer ceramic capacitor 1 of this embodiment, at least one of the first external electrode side surface region 46 and the second external electrode side surface region 47 covers at least a portion of the first recess 221 and the second recess 222. It is preferable that at least one of the first external electrode side surface region 46 and the second external electrode side surface region 47 covers the entire first recess 221 and the second recess 222. It is also preferable that the first recess 221 and the second recess 222 are covered by at least one of the first underlying electrode layer 51 and the second underlying electrode layer 52.

[0107] This configuration allows the thickness of the external electrode 40 or the base electrode layer 50 arranged in the recess to be kept thick, thereby lengthening the path for moisture penetration to the internal electrode width direction end 37 near the outer layer portion 11, where moisture penetration is relatively likely to occur, and reliably ensuring moisture resistance reliability.

[0108] (Method for Manufacturing the Multilayer Ceramic Capacitor of the First Embodiment) A method for manufacturing the multilayer ceramic capacitor 1 of the first embodiment will be described. Note that the method for manufacturing the multilayer ceramic capacitor 1 is not limited to the method described below.

[0109] A dielectric sheet and a conductive paste for the internal electrodes are prepared. The conductive paste for the dielectric sheet and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0110] A dielectric sheet on which an internal electrode pattern is formed is prepared, and a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, screen printing or gravure printing, to form a dielectric sheet on which a pattern of a first internal electrode is formed and a dielectric sheet on which a pattern of a second internal electrode is formed.

[0111] A predetermined number of dielectric sheets not printed with an internal electrode pattern are stacked to form a portion that will become the second outer layer portion, and dielectric sheets printed with a first internal electrode pattern and a second internal electrode pattern are stacked in sequence on top of that to form a portion that will become the inner layer portion, and a predetermined number of dielectric sheets not printed with an internal electrode pattern are further stacked on top of the portion that will become the inner layer portion to form a portion that will become the first outer layer portion, thereby producing a laminated sheet.

[0112] The laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0113] The laminated block is cut into individual pieces to produce laminated chips. Specifically, the laminated block is cut and divided using a cutting blade to create a pre-fired laminate. The cutting blade is applied to the end face side of the main surface side region of the inner layer portion of the divided pre-fired laminate, and a predetermined position is cut. However, the manufacturing method is not limited to this, and a recess may be formed by cutting a predetermined position.

[0114] This allows recesses to be formed in predetermined positions, and the recesses are filled with paste or the like for the external electrodes during the external electrode application process. This makes the thickness of the external electrodes around the internal electrodes close to the main surfaces thicker than usual, improving the moisture resistance reliability of the multilayer ceramic capacitor.

[0115] The laminated chips are fired to produce a laminate. Before firing, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like. The firing temperature is preferably 900°C or higher and 1400°C or lower, although this depends on the materials of the dielectric and internal electrodes.

[0116] Next, the external electrodes 40 are formed. First, a conductive paste that will become the base electrode layer 50 is applied to both end surfaces of the laminate 2 to form the base electrode layer 50. When forming a baked layer as the base electrode layer 50, a conductive paste containing a glass component and a metal is applied by a method such as dipping, and then a baking process is performed to form the base electrode layer 50. The temperature of the baking process at this time is preferably 700°C or higher and 900°C or lower.

[0117] Thereafter, a plating layer 60 is formed on the surface of the base electrode layer 50. A Ni plating layer and a Sn plating layer are formed on the base electrode layer 50. The Ni plating layer and the Sn plating layer are formed in this order by, for example, barrel plating. In this manner, a multilayer ceramic capacitor is obtained.

[0118] (Embodiment 2) A multilayer ceramic capacitor 1 according to embodiment 2 will be described with reference to FIG. 10 . FIG. 10 is a diagram showing the second end face 8 of the laminate 2. In the following description, differences between the multilayer ceramic capacitor 1 according to embodiment 2 and the multilayer ceramic capacitor 1 according to embodiment 1 will be mainly described. Furthermore, embodiment 2 will be described below with reference to the second end face 8. The description of the second end face 8 also applies to the first end face 7.

[0119] Unlike the multilayer ceramic capacitor 1 of the first embodiment, the multilayer body 2 of the multilayer ceramic capacitor 1 of the second embodiment can be divided into a side gap portion 14 and a core portion 25 in the width direction W. These will be described in order below.

[0120] As described above, the laminate 2 has a core portion 25 in which the internal electrodes 30 and the dielectric layers 20 are stacked. The core portion 25 includes an effective portion 26 in which the internal electrodes 30 are arranged, and an ineffective portion 27 arranged to sandwich the effective portion 26 from both sides in the stacking direction T. The laminate 2 further has side gap portions 14 arranged to sandwich the core portion 25 from both sides in the width direction W and in contact with the internal electrodes. The side gap portions 14 are portions that sandwich the effective portion 26 and the ineffective portion 27 from both sides in the width direction W. The thickness of the side gap portions is 2 μm or more and 40 μm or less, but is not limited to this.

[0121] As described above, the side gap 14 includes the first side gap 15 and the second side gap 16. The first side gap 15 is the portion between the core portion 25 and the first side surface 5 in the width direction W. The second side gap 16 is the portion between the core portion 25 and the second side surface 6 in the width direction W.

[0122] The first side gap portion 15 and the second side gap portion 16 each include an inner layer and an outer layer. The inner layer included in the first side gap portion 15 is referred to as a first inner layer 151. The outer layer included in the first side gap portion 15 is referred to as a first outer layer 152. The inner layer included in the second side gap portion 16 is referred to as a second inner layer 161. The outer layer included in the second side gap portion 16 is referred to as a second outer layer 162.

[0123] The material composition of the side gap section 14 may be different from the material composition of the dielectric layer 20. The main component in the material composition of the side gap section 14 is, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , CaZrO ３ The dielectric ceramic material contains, but is not limited to, a dielectric ceramic material mainly composed of, for example, Dy, Ni, Ba, B, Li, K, Na, Mn, Mg, Ho, Ca, V, etc.

[0124] (Inner Layer) The inner layer and the outer layer will be specifically described. The inner layer is disposed in contact with the internal electrode 30. The inner layer is made of, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , CaZrO ３ The inner layer is made of a dielectric ceramic material mainly composed of silicon dioxide. The inner layer may contain glass mainly composed of silicon dioxide. The inner layer may contain a sintering promoting element. Examples of sintering aid elements include Dy, Ni, Ba, B, Li, K, Na, Mn, Mg, Ho, Ca, and V. The sintering promoting element may be one type or two or more types. The thickness of the inner layer in the width direction W is preferably 0.1 μm or more and 10 μm or less.

[0125] (Outer Layer) The outer layer will be described. The outer layer is the layer located on the sidemost side when the laminate 2 is viewed in a cross section parallel to the width direction W and the stacking direction T. The outer layer may be, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , CaZrO ３ The outer layer is made of a dielectric ceramic material mainly composed of silicon dioxide, etc. The outer layer preferably contains glass. The main component of the glass in the outer layer is, for example, silicon dioxide, but is not limited to this. The outer layer may contain a sintering promoting element or a sintering inhibiting element. Examples of sintering promoting elements include Dy, Ni, Ba, B, Li, K, Na, Mn, Mg, Ho, Ca, and V. The sintering promoting element may be one type or two or more types. The thickness of the outer layer in the width direction W is preferably 0.1 μm or more and 10 μm or less.

[0126] In the above description, the first side gap portion 15 and the second side gap portion 16 each consist of two layers. However, the first side gap portion 15 and the second side gap portion 16 may each consist of one layer, or three or more layers.

[0127] In the multilayer ceramic capacitor 1 of this embodiment, at the first end face 7, the distance from the internal electrode width direction end 37 of the first internal electrode 31 in the first internal layer portion main surface side region 201 and the second internal layer portion main surface side region 202 to the first side surface 5 or the second side surface 6 is substantially the same as the distance from the internal electrode width direction end 37 of the first internal electrode 31 in the stacking direction central region 203 to the first side surface 5 or the second side surface 6. At the second end face 8, the distance from the internal electrode width direction end 37 of the second internal electrode 32 in the first internal layer portion main surface side region 201 and the second internal layer portion main surface side region 202 to the first side surface 5 or the second side surface 6 is substantially the same as the distance from the internal electrode width direction end 37 of the second internal electrode 32 in the stacking direction central region 203 to the first side surface 5 or the second side surface 6.

[0128] 10 , the distance from the internal electrode width direction end 37 of the internal electrode 30 in the first internal layer portion main surface side region 201 to the first side surface 5 is indicated by distance 331 on the second end face 8. The distance from the internal electrode width direction end 37 of the internal electrode 30 in the second internal layer portion main surface side region 202 to the first side surface 5 on the second end face 8 is indicated by distance 332. Also, on the second end face 8, the distance from the internal electrode width direction end 37 of the internal electrode 30 in the stacking direction central region 203 to the first side surface 5 is indicated by distance 333. The distances 331 and 332 are substantially the same as the distance 333. While FIG. 10 shows the second end face 8, the same applies to the first end face 7. Also, while FIG. 10 has described the first side surface 5, the same applies to the second side surface 6.

[0129] The distances 331, 332, and 333 can also be considered to be the thicknesses of the corresponding portions of the side gap portion 14 in the width direction W. Therefore, at the first end face 7, the thicknesses of the side gap portion 14 in the first inner layer portion main surface side region 201 and the second inner layer portion main surface side region 202 can also be considered to be substantially the same as the thickness of the side gap portion 14 in the stacking direction central region 203. At the second end face 8, the thicknesses of the side gap portion 14 in the first inner layer portion main surface side region 201 and the second inner layer portion main surface side region 202 can also be considered to be substantially the same as the thickness of the side gap portion 14 in the stacking direction central region 203.

[0130] 10 is also the thickness of the side gap 14 located at half the dimension of the core portion 25 in the stacking direction T. Further, distance 341 shown in Fig. 10 is the thickness of the side gap 14 located on an extension in the width direction W of the internal electrode 30 closest to the first main surface 3. Distance 342 shown in Fig. 10 is the thickness of the side gap 14 located on an extension in the width direction W of the internal electrode 30 closest to the second main surface 4. The ratios of the distances 341 and 342 to the distance 333, i.e., the ratio (distance 341 / distance 333) and the ratio (distance 342 / distance 333), are preferably 0.95 or more and 1.05 or less.

[0131] In the multilayer ceramic capacitor 1 of the second embodiment, the thickness of the side gap portion can be adjusted as appropriate and is substantially uniform in the stacking direction T. Therefore, it is possible to maximize the capacitance relative to the size of the multilayer ceramic capacitor while achieving the same moisture resistance reliability as in the first embodiment due to the shape of the multilayer ceramic capacitor.

[0132] (Method of Manufacturing Multilayer Ceramic Capacitor of Second Embodiment) A method of manufacturing the multilayer ceramic capacitor 1 will be described with reference to Figures 12 and 13. Figure 12 is a diagram showing a chip body 80, a first side gap sheet 91, and a second side gap sheet 92. Figure 13 is a diagram showing a multilayer chip 90 in which the first side gap sheet 91 and the second side gap sheet 92 are attached to the chip body 80. Note that the method of manufacturing the multilayer ceramic capacitor 1 is not limited to the method described below.

[0133] In the method for manufacturing the multilayer ceramic capacitor 1 of this embodiment, the laminate 2 is formed using the chip body 80, the first side gap sheet 91 and the second side gap sheet 92.

[0134] (Correspondence between Laminate and Laminated Chip) In the following description, the laminate 2 before firing is referred to as a laminated chip 90. In the laminated chip 90, a portion corresponding to the first side gap portion 15 after firing is referred to as a first side gap sheet 91, and a portion corresponding to the second side gap portion 16 after firing is referred to as a second side gap sheet 92. In addition, in the laminated chip 90, a portion other than the first side gap sheet 91 and the second side gap sheet 92 is referred to as a chip body 80. The chip body 80 corresponds to the core portion 25 after firing.

[0135] In chip body 80, the portion corresponding to first invalid portion 28 after firing is called first element body invalid portion 81, and the portion corresponding to second invalid portion 29 after firing is called second element body invalid portion 82. In chip body 80, the portion other than first element body invalid portion 81 and second element body invalid portion 82 is called element body valid portion 83. Element body valid portion 83 becomes valid portion 26 after firing.

[0136] (Chip Body) First, dielectric sheets for the first element body invalid portion 81, the second element body invalid portion 82, and the element body valid portion 83 are prepared. In addition, a conductive paste for the element body valid portion 83 is prepared. The dielectric sheets become the dielectric layers 20 in the laminate 2. The conductive paste becomes the internal electrodes 30 in the laminate 2. Both the dielectric sheets and the conductive paste contain a binder and a solvent. The binder and solvent may be known. The conductive paste contains a metal powder, an organic binder, and an organic solvent.

[0137] A conductive paste for the internal electrode 30 is printed onto the dielectric sheet for the element body effective portion 83 using a printing plate designed to have a pattern in the shape of the internal electrode 30. Examples of printing methods include screen printing and gravure printing. In this way, a dielectric sheet on which the pattern of the first internal electrode 31 is formed and a dielectric sheet on which the pattern of the second internal electrode 32 is formed are prepared.

[0138] A predetermined number of dielectric sheets for the second element body invalid portion 82, on which the pattern of the internal electrode 30 is not printed, are stacked to form a portion that will become the second invalid portion 29. On top of this, dielectric sheets for the element body valid portion 83, on which the pattern of the first internal electrode 31 is printed, and dielectric sheets for the element body valid portion 83, on which the pattern of the second internal electrode 32 is printed, are stacked alternately in this order. In this way, the element body valid portion 83 is formed, in which the dielectric sheets 84 for the element body valid portion 83 and the conductive paste 85 printed on the dielectric sheets 84 are stacked alternately.

[0139] Further, a portion that will become the first invalid portion 28 is laminated on top of this. This portion is formed by laminating a predetermined number of dielectric sheets for the first element body invalid portion 81, on which the pattern of the internal electrode 30 is not printed.

[0140] Next, the process proceeds to the cutting process. In the cutting process, the stacked sheets are cut and separated using a cutting blade to obtain the chip body 80 before firing. The cutting blade is applied to the end face side of the portion of the separated chip body 80 before firing that corresponds to the main surface side region of the inner layer portion, and a predetermined position is cut. However, the manufacturing method is not limited to this, and a recess may be formed by cutting a predetermined position. Then, the process proceeds to the side gap sheet attachment process, where a side gap sheet is attached to the chip body 80 that has undergone the cutting process. This is explained below.

[0141] (Side Gap Sheet) The first side gap sheet 91 is obtained by stacking a predetermined number of dielectric sheets for the first side gap sheet 91, on which no conductive paste is printed. The second side gap sheet 92 is obtained in a similar manner. The side gap sheets may be stacked separately, with the dielectric sheet corresponding to the inner layer and the dielectric sheet corresponding to the outer layer. For example, the amount of Si contained may be different between the dielectric sheet corresponding to the inner layer and the dielectric sheet corresponding to the outer layer.

[0142] Next, as shown by arrow 95 in Figure 12, a first side gap sheet 91 is attached to the first LT surface 87 of the chip body 80. As shown by arrow 96, a second side gap sheet 92 is attached to the second LT surface 88 of the chip body 80. This completes the stacked chip 90. The stacked chip 90 is shown in Figure 13.

[0143] The laminated chip is then fired to obtain the laminate 2. Before firing, the laminated chip may be pressed or polished by barrel polishing or the like to round off corners or ridges, as necessary. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode 30, but is preferably, for example, 900°C or higher and 1400°C or lower.

[0144] Next, the external electrodes 40 are formed. First, a conductive paste that will become the base electrode layer 50 is applied to both end surfaces of the laminate 2 to form the base electrode layer 50. When forming a baked layer as the base electrode layer 50, a conductive paste containing a glass component and a metal is applied by a method such as dipping, and then a baking process is performed to form the base electrode layer 50. The temperature of the baking process at this time is preferably 700°C or higher and 900°C or lower.

[0145] Thereafter, a plating layer 60 is formed on the surface of the base electrode layer 50. A Ni plating layer and a Sn plating layer are formed on the base electrode layer 50. The Ni plating layer and the Sn plating layer are formed in this order by, for example, barrel plating. In this manner, a multilayer ceramic capacitor is obtained.

[0146] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various changes, modifications, and combinations are possible.

[0147] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 3 First main surface 4 Second main surface 5 First side surface 6 Second side surface 7 First end surface 8 Second end surface 10 Inner layer portion 11 Outer layer portion 12 First outer layer portion 13 Second outer layer portion 14 Side gap portion 15 First side gap portion 16 Second side gap portion 20 Dielectric layer 25 Core portion 26 Effective portion 27 Ineffective portion 28 First ineffective portion 29 Second ineffective portion 30 Internal electrode 31 First internal electrode 32 Second internal electrode 37 Internal electrode width direction end portion 38 Opposing electrode portion 40 External electrode 41 First external electrode 42 Second external electrode 44 First external electrode end surface region 45 Second external electrode end surface region 46 First external electrode side surface region 47 Second external electrode side surface region 50 Base electrode layer 51 First base electrode layer 52 Second base electrode layer 60 Plating layer 80 Chip body 81 First element body ineffective portion 82 Second element body ineffective portion 83 Element body effective portion 84 Dielectric sheet 85 Conductive paste 90 Laminated chip 91 First side gap sheet 92 Second side gap sheet 100 Multilayer ceramic capacitor 151 First inner layer 152 First outer layer 161 Second inner layer 162 Second outer layer 201 First inner layer portion main surface side region 202 Second inner layer portion main surface side region 203 Central region in stacking direction 221 First recess 222 Second recess 223 Protruding portion

Claims

1. A laminate comprising: an inner layer portion in which a plurality of dielectric layers and a plurality of internal electrodes are alternately stacked; first and second main surfaces opposing each other in the stacking direction; first and second side surfaces opposing each other in a width direction perpendicular to the stacking direction; and first and second end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction; a first external electrode provided on the first end surface; and a second external electrode provided on the second end surface, wherein the plurality of internal electrodes include a first internal electrode extended to the first end surface and a second internal electrode extended to the second end surface, and wherein a region near the center of the stacking direction of the inner layer portion is defined as a stacking direction central region, a region of the inner layer portion on the first main surface side in the stacking direction is defined as a first inner layer portion main surface side region, and a region of the inner layer portion on the second main surface side in the stacking direction is defined as a second inner layer portion main surface side region, a width dimension of the stacking direction central region in at least one of the first end face and the second end face that is larger than the width dimension of the first inner layer portion main surface side region and the second inner layer portion main surface side region in at least one of the first end face and the second end face; and a width dimension of the first inner layer portion main surface side region and the second inner layer portion main surface side region in at least one of the first end face and the second end face that is smaller than the width dimension of the first inner layer portion main surface side region and the second inner layer portion main surface side region in a cross section parallel to the width direction and the stacking direction at the length direction central portion.

2. The multilayer ceramic capacitor according to claim 1, wherein at least one of the first end face side and the second end face side of the central region in the stacking direction has a protruding portion that protrudes further than the first inner layer portion main surface side region and the second inner layer portion main surface side region.

3. A multilayer ceramic capacitor according to claim 1 or 2, wherein at least one of the first end face side and second end face side of the first inner layer portion main surface side region has a first recess that is smaller than the width dimension of the longitudinal center portion, and at least one of the first end face side and second end face side of the second inner layer portion main surface side region has a second recess that is smaller than the width dimension of the longitudinal center portion.

4. The multilayer ceramic capacitor according to claim 3, wherein the first external electrode has a first external electrode end surface region covering the first end surface and a first external electrode side surface region covering a portion of the first side surface and a portion of the second side surface; the second external electrode has a second external electrode end surface region covering the second end surface and a second external electrode side surface region covering a portion of the second side surface and a portion of the second side surface; and at least one of the first external electrode side surface region and the second external electrode side surface region covers the first recess and the second recess.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the laminate has, in the width direction, a core portion in which the internal electrodes are arranged, and side gap portions arranged so as to sandwich the core portion from both sides in the width direction.

6. The multilayer ceramic capacitor according to claim 5, wherein, at the first end face, the distance from the width direction end of the first internal electrode in the first inner layer portion main surface side region and the second inner layer portion main surface side region to the first side surface or the second side surface is approximately the same as the distance from the width direction end of the first internal electrode in the stacking direction central region to the first side surface or the second side surface, and / or, at the second end face, the distance from the width direction end of the second internal electrode in the first inner layer portion main surface side region and the second inner layer portion main surface side region to the first side surface or the second side surface is approximately the same as the distance from the width direction end of the second internal electrode in the stacking direction central region to the first side surface or the second side surface.

7. A multilayer ceramic capacitor according to any one of claims 1 to 6, wherein the ratio (Wp1 / Wc) of the minimum width dimension Wp1 of the first inner layer portion main surface side region to the maximum width dimension Wc of the stacking direction central region and the ratio (Wp2 / Wc) of the minimum width dimension Wp2 of the second inner layer portion main surface side region to the maximum width dimension Wc of the stacking direction central region are 0.85 or more and 0.98 or less.

8. A multilayer ceramic capacitor according to any one of claims 1 to 7, wherein, on the first end face, the thickness of the first external electrodes arranged in the first inner layer portion main surface side region and the second inner layer portion main surface side region is smaller than the thickness of the first external electrode arranged in the central region in the stacking direction.

9. A multilayer ceramic capacitor according to any one of claims 1 to 8 and claim 7, wherein, on the second end face, the thickness of the second external electrodes arranged in the first inner layer portion main surface side region and the second inner layer portion main surface side region is smaller than the thickness of the second external electrode arranged in the central region in the stacking direction.

10. A multilayer ceramic capacitor according to claim 8 or 9, wherein the ratio of the thickness of the first external electrode and the second external electrode in the first inner layer portion main surface side region and the second inner layer portion main surface side region to the thickness of the first external electrode and the second external electrode in the central region in the stacking direction is 1.05 or more and 1.3 or less.

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