Thin-film capacitor and electronic circuit board provided with same

Abstract

[Problem] To provide a highly reliable thin-film capacitor. [Solution] A thin-film capacitor 1 comprises: a metal foil 10 that has an upper surface 11 and a lower surface 12 and in which at least a portion of the upper surface 11 is roughened; a dielectric film D that covers at least a roughened region of the upper surface 11 of the metal foil 10; an electrode layer 31 that is positioned on the upper surface 11 side of the metal foil 10 and is in contact with the metal foil 10; an electrode layer 32 that is positioned on the upper surface 11 side of the metal foil 10 and that covers the dielectric film D without being in contact with the metal foil 10; an insulating member 21 that is positioned between the electrode layer 31 and the electrode layer 32; and an insulating member 22 that covers the insulating member 21. The insulating member 22 has a moisture permeability lower than that of the insulating member 21.

Description

Thin film capacitor and electronic circuit board including the same

[0001] The present disclosure relates to a thin film capacitor and an electronic circuit board including the same.

[0002] Circuit boards on which ICs are mounted usually have decoupling capacitors to stabilize the potential of the power supply supplied to the IC. Multilayer ceramic chip capacitors are generally used as decoupling capacitors, and the required decoupling capacitance is ensured by mounting a large number of multilayer ceramic chip capacitors on the surface of the circuit board.

[0003] In recent years, as circuit boards have become smaller, there is sometimes a shortage of space for mounting a large number of multilayer ceramic chip capacitors, and therefore thin film capacitors that can be embedded in circuit boards are sometimes used instead of multilayer ceramic chip capacitors (see Patent Documents 1 to 4).

[0004] The thin film capacitor described in Patent Document 1 has a configuration in which a porous metal substrate is used and an upper electrode is formed on the surface of the substrate via a dielectric film. The thin film capacitor described in Patent Document 2 has a configuration in which a metal substrate having one main surface roughened is used and an upper electrode is formed on the roughened surface via a dielectric film. The thin film capacitors described in Patent Documents 3 and 4 have a configuration in which a conductive porous substrate is formed on a support portion and an upper electrode is formed on the roughened surface via a dielectric film.

[0005] International Publication No. WO2015-118901 International Publication No. WO2018-092722 International Publication No. WO2017-026247 International Publication No. WO2017-014020

[0006] However, the thin-film capacitor described in Patent Document 1 has a side electrode structure, resulting in long electrode line lengths, which leads to structural problems such as large ESR (equivalent series resistance) and ESL (equivalent series inductance). Furthermore, the thin-film capacitor described in Patent Document 1 uses a metal substrate that is entirely porous, making it difficult to separate the lower electrode made of the metal substrate from the upper electrode covering the metal substrate via a dielectric film, resulting in a problem of prone to short-circuit defects. Furthermore, the thin-film capacitor described in Patent Document 2 has one main surface of the metal substrate functioning as the upper electrode and the other main surface functioning as the lower electrode, which requires routing the electrodes via the side of the element to arrange a pair of terminal electrodes on the same plane, resulting in a complex structure. Furthermore, the thin-film capacitors described in Patent Documents 3 and 4 have a pair of terminal electrodes arranged on both sides of the metal substrate, making it impossible to access the pair of terminal electrodes from one side. Furthermore, the use of a support structure results in a problem of an increased overall thickness.

[0007] Thus, the present disclosure describes an improved thin film capacitor and method for manufacturing the same, as well as an electronic circuit board comprising the thin film capacitor.

[0008] A thin film capacitor according to one aspect of the present disclosure comprises a metal foil having first and second surfaces opposite each other, at least a portion of the first surface being roughened, a dielectric film covering at least the roughened area of ​​the first surface of the metal foil, a first electrode layer located on the first surface side of the metal foil and in contact with the metal foil, a second electrode layer located on the first surface side of the metal foil and covering the dielectric film without contacting the metal foil, a first insulating member located between the first electrode layer and the second electrode layer, and a second insulating member covering the first insulating member, wherein the second insulating member has a lower moisture permeability than the first insulating member.

[0009] An electronic circuit board according to one aspect of the present disclosure comprises a substrate having a wiring pattern, a semiconductor IC provided on the substrate, and the above-mentioned thin film capacitor, and the first and second electrode layers of the thin film capacitor are connected to the semiconductor IC via the wiring pattern.

[0010] According to the present disclosure, since the first insulating member is covered with the second insulating member having a low moisture permeability, it is possible to prevent a decrease in reliability due to moisture absorption by the first insulating member.

[0011] FIG. 1A is a schematic cross-sectional view illustrating the structure of a thin film capacitor 1 according to a first embodiment of the present disclosure. FIG. 1B is a schematic plan view of the thin film capacitor 1. FIGS. 2A to 26A are schematic cross-sectional views illustrating a manufacturing process of the thin film capacitor 1, each showing a cross section along line A-A shown in FIGS. 2B to 26B. FIG. 27 is a schematic cross-sectional view illustrating the structure of a thin film capacitor 2 according to a second embodiment of the present disclosure. FIG. 28 is a schematic cross-sectional view illustrating the structure of a thin film capacitor 3 according to a third embodiment of the present disclosure. FIG. 29 is a schematic cross-sectional view illustrating the structure of a thin film capacitor 4 according to a fourth embodiment of the present disclosure. FIG. 30 is a schematic cross-sectional view illustrating the structure of a thin film capacitor 5 according to a fifth embodiment of the present disclosure. FIG. 31 is a schematic cross-sectional view illustrating the structure of a thin film capacitor 6 according to a sixth embodiment of the present disclosure. FIG. 32 is a schematic cross-sectional view illustrating an electronic circuit board having a configuration in which any of the thin film capacitors 1 to 6 is embedded in a multilayer substrate 400. FIG. 33 is a schematic cross-sectional view illustrating an electronic circuit board having a configuration in which any of the thin film capacitors 1 to 6 is mounted on the surface of a multilayer substrate 600. FIG. 34 is a table showing the rate of change in capacitance before and after the moisture absorption test.

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0013] Fig. 1A is a schematic cross-sectional view for explaining the structure of a thin-film capacitor 1 according to a first embodiment of the present disclosure. Fig. 1B is a schematic plan view of the thin-film capacitor 1. Fig. 1A shows a cross section taken along line AA shown in Fig. 1B.

[0014] As shown in FIGS. 1A and 1B , the thin-film capacitor 1 includes a metal foil 10 made of aluminum or the like, ring-shaped or polygonal annular insulating members 21 and 22 formed on the upper surface 11 of the metal foil 10, an electrode layer 31 formed on the upper surface 11 of the metal foil 10 and located within the area surrounded by the insulating member 21, and an electrode layer 32 formed on the upper surface 11 of the metal foil 10 and surrounded by the insulating member 22 but located outside the area surrounded by the insulating member 21. Instead of aluminum, copper, chromium, nickel, tantalum, or the like may be used as the material for the metal foil 10. The metal foil 10 has an upper surface 11 and a lower surface 12, which are opposite main surfaces. The upper surface 11 of the metal foil 10 is partially roughened. The lower surface 12 of the metal foil 10 is not roughened and is substantially flat. The lower surface 12 of the metal foil 10 may also be roughened, but if the lower surface 12 of the metal foil 10 is left flat without being roughened, the depth of the roughened surface layer on the upper surface 11 can be increased, thereby increasing the capacitance. A central portion 13 located between the upper surface 11 and the lower surface 12 of the metal foil 10 is not roughened. A dielectric film D is formed on the roughened surface of the metal foil 10. When the metal foil 10 is made of aluminum, the dielectric film D may be made of aluminum oxide.

[0015] The insulating members 21 and 22 are made of, for example, a resin material. The electrode layer 31 is made of, for example, a metal material such as copper, nickel, or gold, or an alloy material containing these metals. The electrode layer 31 may have a multilayer structure in which multiple layers made of metal materials or alloy materials are stacked. The electrode layer 31 is connected to the unroughened central portion 13 of the metal foil 10. A seed layer 40 may be interposed between the electrode layer 31 and the metal foil 10. In this case, the seed layer 40 constitutes part of the electrode layer 31. The electrode layer 32 includes conductive members 321 and 322. The conductive member 321 is made of, for example, a conductive polymer material. The conductive member 322 is made of the same metal material as the electrode layer 31. A seed layer 40 may be interposed between the conductive members 321 and 322. In this case, the seed layer 40 constitutes part of the electrode layer 32. The seed layer 40 may be made of a material that has a barrier function to prevent the diffusion of copper and other materials that make up the electrode layer 31 and the conductive member 322, has high adhesion to the metal foil 10 made of aluminum or other materials, the insulating members 21 and 22, and the conductive member 321 made of a conductive polymer or other material, and does not damage the conductive member 321 made of a conductive polymer or other material.

[0016] The ring-shaped or polygonal annular insulating member 21 is disposed within a slit that electrically separates the electrode layer 31 from the electrode layer 32. In the region surrounded by the insulating member 21, i.e., the unroughened central portion 13 of the metal foil 10, part or all of the dielectric film D formed on the upper surface 11 of the metal foil 10 is removed, forming an opening in the dielectric film D. This electrically connects the electrode layer 31 to the metal foil 10 via the seed layer 40. In contrast, outside the region surrounded by the insulating member 21, the dielectric film D formed on the upper surface 11 of the metal foil 10 is not removed. In other words, the electrode layer 32 is in contact with the dielectric film D without contacting the metal foil 10, and the electrode layer 32 and the metal foil 10 are insulated from each other. As a result, the electrode layers 31 and 32 function as a pair of capacitive electrodes facing each other via the dielectric film D. The dielectric film D is formed on the roughened upper surface 11 of the metal foil 10, which increases the surface area of ​​the upper surface 11, thereby achieving a large capacitance.

[0017] Grooves 14 are formed in the metal foil 10 in the areas where the electrode layer 31 is connected. The depth of the grooves 14 is greater than the thickness of the roughened surface portion of the metal foil 10. As a result, the grooves 14 penetrate the roughened surface portion of the metal foil 10, and the unroughened central portion 13 of the metal foil 10 is exposed at the bottom of the grooves 14. The central portion 13 of the metal foil 10 exposed at the bottom of the grooves 14 is flat. The bottom of the grooves 14 contacts the seed layer 40 and the insulating member 21. Because the bottom of the grooves 14 is flat, voids are less likely to occur between the metal foil 10 and the seed layer 40 / insulating member 21. This improves adhesion of the electrode layer 31 and the insulating member 21 to the metal foil 10.

[0018] The surfaces of the insulating members 21 and 22, as well as the surfaces of the electrode layers 31 and 32 located nearby, are covered with the insulating member 80. This prevents the insulating members 21 and 22 from being exposed to the outside. The insulating member 80 also covers the boundary portion B1 between the electrode layer 31 and the insulating member 80, as well as the boundary portion B2 between the electrode layer 32 and the insulating member 80. The insulating member 80 is made of a material with a lower moisture permeability than the insulating members 21 and 22. The moisture permeability of the insulating member 80 is 1.1 g mm / (m ２ / day) or less. ５ The insulating member 80 may be made of, for example, SiO ２ , Al ２ O ３ , Si ３ N ４ The electrode layers 31 and 32 are made of an inorganic insulating material such as AlN, or a resin material such as an epoxy resin or a fluorine resin. Part of the surface of the electrode layers 31 and 32 is not covered with the insulating member 80 and is exposed.

[0019] The thin film capacitor 1 can be used as a decoupling capacitor by being embedded in a multilayer substrate. Furthermore, because the electrode layer 31 is divided into multiple pieces, the ESR and ESL can be reduced compared to when there is a single electrode layer 31. Furthermore, in the thin film capacitor 1, the surfaces of the insulating members 21 and 22 are covered with the insulating member 80, which has a low moisture permeability, so that it is possible to prevent a decrease in reliability due to moisture absorption by the insulating members 21 and 22. Furthermore, if a material with a low moisture permeability, such as an inorganic insulating material, is used as the material for the insulating members 21 and 22 themselves, reliability can be further improved.

[0020] Next, we will explain an example of a method for manufacturing the thin film capacitor 1. Figures 2A to 26A are schematic cross-sectional views taken along line AA shown in Figures 2B to 26B, respectively.

[0021] First, a metal foil 10 having a thickness of approximately 50 μm is prepared ( FIGS. 2A and 2B ), and its upper surface 11 is roughened by etching ( FIGS. 3A and 3B ). The lower surface 12 and central portion 13 of the metal foil 10 are not roughened. As a result, a porous layer 11a is formed on the metal foil 10, located on the upper surface 11 side. Between the porous layer 11a and the lower surface 12 is the un-roughened central portion 13. Alternatively, instead of roughening the flat metal foil 10, a metal foil 10 having a roughened upper surface 11 may be formed by sintering metal powder.

[0022] Next, a dielectric film D is formed on the surface of the metal foil 10 (FIGS. 4A and 4B). The dielectric film D may be formed by oxidizing the metal foil 10, or may be formed by a film formation method with excellent coverage, such as an ALD method, a CVD method, or a mist CVD method. The material of the dielectric film D is Al. ２ O ３ , TiO ２ , Ta ２ O ５ In this case, it is sufficient to form the dielectric film D at least on the upper surface 11, and it is not necessary to form the dielectric film D on the lower surface 12. However, by forming the dielectric film D on the lower surface 12 as well, the insulation properties of the lower surface 12 can be ensured.

[0023] Next, the metal foil 10 is placed on the support substrate 60 via the adhesive layer 61 (FIGS. 5A and 5B), and then a photosensitive liquid resist 71 is applied to the upper surface 11 of the metal foil 10 opposite the support substrate 60 (FIGS. 6A and 6B). The resist 71 is patterned by exposure and development (FIGS. 7A and 7B). The patterned resist 71 has a plurality of openings 71a that expose the dielectric film D. The resist may be either positive or negative.

[0024] Next, the dielectric film D and the metal foil 10 are etched using the resist 71 as a mask to form grooves 14 in the metal foil 10 at positions that overlap with the openings 71a (FIGS. 8A and 8B). As a result, openings are formed in the dielectric film D, and the unroughened central portion 13 of the metal foil 10 is exposed at the bottom of the grooves 14.

[0025] Next, after removing the resist 71 ( FIGS. 9A and 9B ), a photosensitive insulating resin 20 is formed on the upper surface 11 of the metal foil 10 ( FIGS. 10A and 10B ). Next, the insulating resin 20 is patterned by exposing and developing it ( FIGS. 11A and 11B ). This results in the formation of ring-shaped insulating members 21 and 22. The inner peripheral wall of the ring-shaped insulating member 21 may be located inside the groove 14 formed in the metal foil 10. The outer peripheral wall of the ring-shaped insulating member 21 must be located outside the groove 14 formed in the metal foil 10. Next, a conductive member 321 made of a conductive polymer or the like is formed in the area surrounded by the insulating member 22, but outside the area surrounded by the insulating member 21 ( FIGS. 12A and 12B ). The conductive member 321 made of a conductive polymer or the like is not formed in the area surrounded by the insulating member 21 or in areas where the metal foil 10 will be removed during singulation, for example, outside the area surrounded by the insulating member 22.

[0026] Next, a seed layer 40 is formed on the entire surface using a sputtering method or the like ( FIGS. 13A and 13B ). Before forming the seed layer 40, any remaining residue on the surface may be removed by reverse sputtering or the like. Next, a photosensitive liquid resist 72 is applied to the entire surface ( FIGS. 14A and 14B ), and the resist 72 is patterned by exposure and development ( FIGS. 15A and 15B ). This exposes the seed layer 40 in the areas that will ultimately be singulated. Next, electrolytic plating is performed using the seed layer 40 as a power supply film to form the electrode layer 31 and the conductive member 322 of the electrode layer 32 ( FIGS. 16A and 16B ). This connects the electrode layer 31 to the metal foil 10, and the conductive member 322 to the conductive member 321 made of a conductive polymer or the like.

[0027] Next, the resist 72 is removed by ashing or the like ( FIGS. 17A and 17B ), and then the unnecessary seed layer is removed ( FIGS. 18A and 18B ). Next, an insulating member 80 is formed on the entire surface using a PVD method, sputtering method, printing method, or the like ( FIGS. 19A and 19B ). Next, a photosensitive liquid resist 81 is applied to the entire surface, and then the resist 81 is patterned by exposure and development ( FIGS. 20A and 20B ). This exposes the insulating member 80 formed in the surface of the electrode layers 31 and 32 in areas away from the insulating members 21 and 22. Next, the insulating member 80 is etched using the resist 81 as a mask, thereby exposing the surfaces of the electrode layers 31 and 32 ( FIGS. 21A and 21B ). Next, after removing the resist 81 by ashing or the like (FIGS. 22A and 22B), a photosensitive liquid resist 73 is applied to the entire surface (FIGS. 23A and 23B), and the resist 73 is patterned by exposure and development (FIGS. 24A and 24B). Next, the metal foil 10 is etched using the resist 73 as a mask to separate the thin-film capacitors (FIGS. 25A and 25B). After removing the resist 73 by ashing or the like (FIGS. 26A and 26B), the support substrate 60 and adhesive layer 61 are removed, completing the thin-film capacitor 1 shown in FIGS. 1A and 1B.

[0028] In this way, in this embodiment, after forming the insulating member 80 on the entire surface, a portion of the insulating member 80 covering the surfaces of the electrode layers 31 and 32 is removed, thereby making it possible to reliably cover the surfaces of the insulating members 21 and 22 with the insulating member 80 while exposing a portion of the electrode layers 31 and 32.

[0029] FIG. 27 is a schematic cross-sectional view for illustrating the structure of a thin film capacitor 2 according to the second embodiment of the present disclosure.

[0030] 27 , in the thin film capacitor 2, the groove 14 provided in the metal foil 10 is ring-shaped, and the electrode layer 31 is embedded in another groove 15 provided in the area surrounded by the ring-shaped groove 14. The groove 15 penetrates the surface layer portion of the roughened metal foil 10, and the un-roughened central portion 13 of the metal foil 10 is exposed at the bottom of the groove 15. This improves the adhesion between the electrode layer 31 and the metal foil 10.

[0031] FIG. 28 is a schematic cross-sectional view for explaining the structure of a thin film capacitor 3 according to the third embodiment of the present disclosure.

[0032] 28 , in the thin-film capacitor 3, the portion of the upper surface 11 of the metal foil 10 that overlaps with the electrode layer 32 is selectively roughened. This ensures that the central portion 13 of the metal foil 10 at the position where it overlaps with the electrode layer 31 has a sufficient thickness, making it less likely that the metal foil 10 will break due to stress applied via the electrode layer 31.

[0033] FIG. 29 is a schematic cross-sectional view for illustrating the structure of a thin film capacitor 4 according to the fourth embodiment of the present disclosure.

[0034] 29, in thin film capacitor 4, the roughened area of ​​upper surface 11 of metal foil 10 is wider than in thin film capacitor 3 shown in Fig. 28, and even parts of the portions overlapping with insulating members 21 and 22 are roughened. This makes it possible to obtain a larger capacitance.

[0035] FIG. 30 is a schematic cross-sectional view for illustrating the structure of a thin film capacitor 5 according to the fifth embodiment of the present disclosure.

[0036] 30, in the thin film capacitor 5, a groove 16 is provided in the metal foil 10 in a portion that overlaps with the electrode layer 32, and the inner wall of the groove 16 is roughened. This increases the volume of the conductive member 321 made of a conductive polymer or the like, thereby reducing the ESR.

[0037] FIG. 31 is a schematic cross-sectional view for illustrating the structure of a thin film capacitor 6 according to the sixth embodiment of the present disclosure.

[0038] 31, in the thin film capacitor 5, a plurality of grooves 16 are provided in the metal foil 10 in the portion that overlaps with the electrode layer 32, and the inner walls of the grooves 16 are roughened. This increases the volume of the metal foil 10 compared to the thin film capacitor 5 shown in FIG. 30, thereby increasing the mechanical strength of the metal foil 10.

[0039] The above-described thin film capacitors 1 to 6 may be embedded in a multilayer substrate 400 as shown in FIG. 32, or may be mounted on the surface of a multilayer substrate 600 as shown in FIG.

[0040] The electronic circuit board shown in FIG. 32 has a configuration in which a semiconductor IC 500 is mounted on a multilayer substrate 400. The multilayer substrate 400 is a multilayer substrate including multiple insulating layers, including insulating layers 401 to 404, and multiple wiring patterns, including wiring patterns 411 to 413. There is no particular limitation on the number of insulating layers. In the example shown in FIG. 32, one of thin film capacitors 1 to 6 is embedded between insulating layer 402 and insulating layer 403. Multiple land patterns, including land patterns 441 and 442, are provided on the surface of the multilayer substrate 400. The semiconductor IC 500 has multiple pad electrodes, including pad electrodes 501 and 502. The pad electrodes 501 and 502 are, for example, power supply terminals. The pad electrode 501 and the land pattern 441 are connected via solder 511, and the pad electrode 502 and the land pattern 442 are connected via solder 512. The land pattern 441 is connected to the electrode layer 31 of the thin film capacitors 1 to 6 via a via conductor 421, a wiring pattern 411, and a via conductor 431. On the other hand, the land pattern 442 is connected to another electrode layer 31 of the thin film capacitors 1 to 6 via a via conductor 422, a wiring pattern 412, and a via conductor 432. The electrode layer 32 of the thin film capacitors 1 to 6 is connected to another pad electrode provided on the semiconductor IC 500 via a via conductor 433 and a wiring pattern 413. The other pad electrode is, for example, a ground terminal. In this way, the thin film capacitors 1 to 6 function as decoupling capacitors for the semiconductor IC 500.

[0041] The electronic circuit board shown in FIG. 33 has a configuration in which a semiconductor IC 700 is mounted on a multilayer substrate 600. The multilayer substrate 600 is a multilayer substrate including multiple insulating layers, including insulating layers 601 and 602, and multiple wiring patterns, including wiring patterns 611 and 612. There is no particular limitation on the number of insulating layers. In the example shown in FIG. 33, any one of thin film capacitors 1 to 6 is surface-mounted on a surface 600a of the multilayer substrate 600. Multiple land patterns, including land patterns 641 to 645, are provided on the surface 600a of the multilayer substrate 600. The semiconductor IC 700 has multiple pad electrodes, including pad electrodes 701 and 702. For example, one of the pad electrodes 701 and 702 is a power terminal, and the other is a ground terminal. The pad electrode 701 and the land pattern 641 are connected via solder 711, and the pad electrode 702 and the land pattern 642 are connected via solder 712. The land pattern 641 is connected to the electrode layers 32 of the thin film capacitors 1 to 6 via the via conductor 621, the wiring pattern 611, the via conductor 631, the land pattern 643, and the solder 713. On the other hand, the land pattern 642 is connected to the electrode layers 31 of the thin film capacitors 1 to 6 via the via conductor 622, the wiring pattern 612, the via conductor 632, the land pattern 644, and the solder 714. Furthermore, the land pattern 645 is connected to another electrode layer 31 via the solder 715. As a result, the thin film capacitors 1 to 6 function as decoupling capacitors for the semiconductor IC 700.

[0042] The above describes embodiments of the technology according to the present disclosure, but the technology according to the present disclosure is not limited to the above embodiments, and various modifications are possible within the scope of the gist of the technology, and it goes without saying that these modifications are also included within the scope of the technology according to the present disclosure.

[0043] The technology according to the present disclosure includes, but is not limited to, the following configuration examples.

[0044] A thin film capacitor according to one aspect of the present disclosure includes a metal foil having first and second surfaces opposite each other, at least a portion of the first surface being roughened, a dielectric film covering at least the roughened region of the first surface of the metal foil, a first electrode layer located on the first surface side of the metal foil and in contact with the metal foil, a second electrode layer located on the first surface side of the metal foil and covering the dielectric film without contacting the metal foil, a first insulating member located between the first electrode layer and the second electrode layer, and a second insulating member covering the first insulating member, wherein the second insulating member has a lower moisture permeability than the first insulating member, thereby improving the reliability of the thin film capacitor.

[0045] In the above-described thin film capacitor, the second insulating member may further cover the boundary between the first electrode layer and the first insulating member, and the boundary between the second electrode layer and the first insulating member, thereby further improving the reliability of the thin film capacitor.

[0046] In the above-described thin film capacitor, the first surface of the metal foil may have grooves whose bottoms are not roughened, and the first electrode layer may be in contact with the bottoms of the grooves. This improves adhesion between the first electrode layer and the metal foil. In this case, the depth of the grooves may be greater than the thickness of the roughened surface layer of the metal foil. This allows grooves with flat bottoms to be formed by forming grooves that are deeper than the roughened surface layer of the metal foil, even when the entire first surface of the metal foil is roughened.

[0047] In the thin film capacitor, the second surface of the metal foil may be flat without being roughened, which increases the depth of the roughened surface layer of the metal foil, thereby increasing the capacitance.

[0048] In the above thin film capacitor, the first surface of the metal foil may have grooves with roughened inner walls, and the dielectric film may cover the inner walls of the grooves, thereby reducing the ESR.

[0049] In the above-described thin film capacitor, the second insulating member may be made of an inorganic insulating material, which can reduce the moisture permeability of the second insulating member.

[0050] In the above-mentioned thin film capacitor, the second insulating member has a moisture permeability of 11 g·mm / (m ２ / day), which makes it possible to suppress changes in capacitance due to moisture absorption.

[0051] According to one aspect of the present disclosure, an electronic circuit board includes a substrate having a wiring pattern, a semiconductor IC provided on the substrate, and the thin film capacitor, the first and second electrode layers of the thin film capacitor being connected to the semiconductor IC via the wiring pattern, thereby making it possible to provide a highly reliable electronic circuit board.

[0052] Samples A1 to A5 were fabricated, each having the same configuration as the thin film capacitor 1 shown in Figure 1, but with different materials for the insulating member 80. Furthermore, sample B was fabricated, which had a structure in which the insulating member 80 was omitted from the thin film capacitor 1. A moisture absorption test was conducted on these samples A1 to A5 and B. The materials and moisture permeabilities of the insulating member 80 are as shown in Figure 34. The rate of change in capacitance before and after the moisture absorption test was then measured.

[0053] The results are shown in Fig. 34. As shown in Fig. 34, in sample B which does not have the insulating member 80 and sample A1 in which the insulating member 80 is made of a silicone-based resin, the capacitance changed by 10% or more, whereas in sample A2 in which the insulating member 80 is made of an epoxy-based resin, the change in capacitance was less than 10%, and in sample A3 in which the insulating member 80 is made of a fluorine-based resin and sample A4 in which the insulating member 80 is made of a SiO ２ Sample A4 is made of Al ２ O ３ The change in capacitance of sample A5 was less than 1%. The silicon-based resin used as the material for the insulating member 80 of sample A1 has a moisture permeability of 11 g·mm / (m ２ / day) and has the same moisture permeability as the material constituting the insulating members 21 and 22.

[0054] In contrast, the material of the insulating member 80 of samples A2 to A5 has a moisture permeability of 1.1 g mm / (m ２ From this point of view, the material of the insulating member 80 should have a moisture permeability of 11 g·mm / (m ２ / day), and a material with a moisture permeability of 1.1 g mm / (m ２ / day) or less is more preferable. Furthermore, the materials of the insulating member 80 of samples A3 to A5 have a moisture permeability of 0.02 g·mm / (m ２ / day) or less, the material of the insulating member 80 has a moisture permeability of 0.02 g mm / (m ２ / day) or less is more preferable.

[0055] REFERENCE SIGNS LIST 1 to 6 thin film capacitor 10 metal foil 11 upper surface 11 surface 11a porous layer 12 lower surface 13 central portion 14 to 16 groove 20 insulating resin 21, 22 insulating member 31, 32 electrode layer 40 seed layer 60 support substrate 61 adhesive layer 71 to 73 resist 71a opening 80 insulating member 81 resist 321, 322 conductive member 401 to 404 insulating layer 402, 403 insulating layer 411 to 413 wiring pattern 421 to 433 via conductor 441, 442 land pattern 442 land pattern 500 semiconductor IC 501, 502 pad electrode 511, 512 solder 600 multilayer substrate 600a surface 601, 602 Insulating layer 611, 612 Wiring pattern 621, 622, 631, 632 Via conductor 641 to 645 Land pattern 700 Semiconductor IC 701, 702 Pad electrode 711 to 715 Solder B1, B2 Boundary portion D Dielectric film

Claims

1. A thin film capacitor comprising: a metal foil having first and second surfaces positioned opposite each other, at least a portion of the first surface being roughened; a dielectric film covering at least the roughened area of ​​the first surface of the metal foil; a first electrode layer positioned on the first surface side of the metal foil and in contact with the metal foil; a second electrode layer positioned on the first surface side of the metal foil and covering the dielectric film without contacting the metal foil; a first insulating member positioned between the first electrode layer and the second electrode layer; and a second insulating member covering the first insulating member, wherein the second insulating member has a lower moisture permeability than the first insulating member.

2. The thin film capacitor according to claim 1, wherein the second insulating member further covers the boundary portion between the first electrode layer and the first insulating member, and the boundary portion between the second electrode layer and the first insulating member.

3. The thin film capacitor according to claim 1, wherein the first surface of the metal foil has grooves whose bottoms are not roughened, and the first electrode layer contacts the bottoms of the grooves.

4. The thin film capacitor according to claim 3, wherein the depth of the groove is greater than the thickness of the roughened surface portion of the metal foil.

5. The thin film capacitor according to claim 1, wherein the second surface of the metal foil is flat without being roughened.

6. The thin film capacitor according to claim 1, wherein the first surface of the metal foil has grooves with roughened inner walls, and the dielectric film covers the inner walls of the grooves.

7. The thin film capacitor according to claim 1, wherein the second insulating member is made of an inorganic insulating material.

8. The second insulating member has a moisture permeability of 11 g mm / (m ２ 2. The thin film capacitor of claim 1, wherein the thin film capacitor is made of a material having a dielectric constant of less than 1 / day.

9. An electronic circuit board comprising: a substrate having a wiring pattern; a semiconductor IC provided on said substrate; and a thin film capacitor according to any one of claims 1 to 8, wherein said first and second electrode layers of said thin film capacitor are connected to said semiconductor IC via said wiring pattern.

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