Wiring board and probe card

Abstract

This wiring board comprises: a ceramic substrate which has a first wiring layer; a plurality of first wiring conductors which contains at least one low-resistance metal that is selected from the group consisting of Cu, Au, and Ag, and at least one high-melting-point metal that is selected from among Mo and W, and which are positioned in the first wiring layer; and a first dummy pattern which contains a low-resistance metal and is positioned in the first wiring layer. The first dummy pattern is positioned along a first path that surrounds the plurality of first wiring conductors all together.

Description

Wiring board and probe card

[0001] The present disclosure relates to a wiring board and a probe card.

[0002] Japanese Patent Application Laid-Open No. 2010-080677 describes a wiring substrate for a probe card having wiring conductors containing a low-resistance metal and a high-melting-point metal.

[0003] The wiring board of the present disclosure comprises: a ceramic substrate having a first wiring layer; a plurality of first wiring conductors located in the first wiring layer, the first wiring conductors including at least one low-resistance metal selected from the group consisting of Cu, Au, and Ag, and at least one high-melting-point metal selected from Mo and W; and a first dummy pattern located in the first wiring layer, the first dummy pattern including the low-resistance metal, wherein the first dummy pattern is located along a first path that collectively surrounds the plurality of first wiring conductors.

[0004] The probe card of the present disclosure comprises the above-described wiring substrate and a plurality of probe pins.

[0005] FIG. 1B is a plan view showing a first wiring layer of a wiring board according to embodiment 1 of the present disclosure. FIG. 1C is a plan view showing one insulating layer of a wiring board according to embodiment 1 of the present disclosure. FIG. 1D is a plan perspective view of the first wiring layer of FIG. 1A and the insulating layer of FIG. 1B. FIG. 1E is a longitudinal cross-sectional view of a wiring board according to embodiment 1 of the present disclosure. FIG. 1F is a plan perspective view of a wiring board according to embodiment 2 of the present disclosure. FIG. 1G is a longitudinal cross-sectional view of a wiring board according to embodiment 2 of the present disclosure. FIG. 1H is a plan view showing a first wiring layer of a wiring board according to embodiment 3 of the present disclosure. FIG. 1I is a partially enlarged view showing the first wiring layer of a wiring board according to embodiment 3 of the present disclosure. FIG. 1I is a plan view showing a first wiring layer of a wiring board according to embodiment 4 of the present disclosure. FIG. 1I is a plan view showing a first wiring layer of a wiring board according to embodiment 5 of the present disclosure. FIG. 1I is a plan view showing a first wiring layer of a wiring board according to embodiment 6 of the present disclosure. FIG. 1I is a longitudinal cross-sectional view of a wiring board according to embodiment 6 of the present disclosure. FIG. 1I is a plan view showing a first wiring layer of a wiring board according to embodiment 7 of the present disclosure. FIG. 1I is a diagram showing a probe card according to an embodiment of the present disclosure.

[0006] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings.

[0007] 1A to 1C show a wiring board according to a first embodiment of the present disclosure, where Fig. 1A is a plan view showing a first wiring layer, Fig. 1B is a plan view showing one insulating layer, and Fig. 1C is a plan perspective view of one insulating layer and the first wiring layer. Fig. 2 is a vertical cross-sectional view of the wiring board according to the first embodiment of the present disclosure. The vertical cross-sectional view is shown with an aspect ratio different from the actual one.

[0008] The wiring board 10 of the first embodiment may be a wiring board 10 for a probe card. The wiring board 10 may include a ceramic substrate 11 having a plurality of wiring layers 111, wiring conductors 21 located in each wiring layer 111, and dummy patterns 23 located in each wiring layer 111. In the first embodiment, any one of the wiring layers 111 corresponds to an example of a "first wiring layer" according to the present disclosure. Furthermore, the wiring conductor 21 of the wiring layer 111 corresponds to an example of a "first wiring conductor" according to the present disclosure. Furthermore, the dummy pattern 23 of the wiring layer 111 corresponds to an example of a "first dummy pattern" according to the present disclosure.

[0009] The wiring board 10 may further include a plurality of ground layers 112 and a ground conductor 31 located on each ground layer 112. The ground conductor 31 may be a solid conductor that extends across each ground layer 112. A solid conductor is a conductor that extends across more than half of the area of ​​the ground layer 112 in a plan view.

[0010] The multiple wiring layers 111 and the multiple ground layers 112 may be alternately stacked such that one wiring layer 111 is located between a pair of adjacent ground layers 112, 112.

[0011] The ceramic substrate 11 may further have a first surface S1 and a second surface S2 facing opposite to each other, and a plurality of wiring layers 111 and a plurality of ground layers 112 may be located between the first surface S1 and the second surface S2. A plurality of conductor pads 51 may be located on the first surface S1. A plurality of conductor pads 52 may be located on the second surface S2.

[0012] The wiring substrate 10 may further include a plurality of via conductors 41 located between two adjacent layers of the plurality of wiring layers 111 and the plurality of ground layers 112, and a plurality of electrode pads 25 located on the plurality of wiring layers 111. The electrode pads 25 may be electrodes to which the via conductors 41 are connected.

[0013] Some of the via conductors 41 may be configured to electrically connect two wiring conductors 21 located on two wiring layers 111, respectively. Some of the via conductors 41 may be configured to electrically connect conductor pads 51 on the first surface S1 and the wiring conductors 21 of the wiring layer 111. Some of the via conductors 41 may be configured to electrically connect conductor pads 52 on the second surface S2 and the wiring conductors 21 of the wiring layer 111. When a ground layer 112 is located between two wiring layers 111, between the first surface S1 and the wiring layer 111, or between the second surface S2 and the wiring layer 111, the ground conductor 31 of the ground layer 112 may have a through hole, and the via conductor 41 may be configured to connect the two wiring layers 111, or between the first surface S1 and the wiring layer 111, or between the second surface S2 and the wiring layer 111, through the through hole. The wiring board 10 may have a configuration in which any one of the conductor pads 51 on the first surface S1 and any one of the conductor pads 52 on the second surface S2 are electrically connected via a plurality of via conductors 41 and a plurality of wiring conductors 21.

[0014] Some of the via conductors 41 may be configured to electrically connect the ground conductors 31 of two adjacent ground layers 112. Some of the via conductors 41 may be configured to electrically connect the wiring conductors 21 or dummy patterns 23 of the wiring layer 111 to the ground conductors 31 of the ground layer 112.

[0015] The ceramic substrate 11 may be a ceramic sintered body such as an aluminum oxide sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a mullite sintered body, or a glass ceramic.

[0016] The ceramic substrate 11 may have a regular polygonal shape (specifically, a regular square, a regular dodecagon, a regular hexagon, a regular bisquadrilateral, etc.) or a circular shape in a plan view. The regular polygonal shape and the circular shape are not limited to strictly regular polygons and strictly circular shapes, but are concepts that include shapes that include slight distortions, rounded corners, etc.

[0017] The wiring conductors 21 and electrode pads 25 of each wiring layer 111 may be configured to include at least one low-resistance metal selected from the group consisting of Cu (copper), Au (gold), and Ag (silver), and at least one high-melting-point metal selected from Mo (molybdenum) and W (tungsten). The wiring conductors 21 and electrode pads 25 may be primarily composed of a mixed metal of the low-resistance metal and the high-melting-point metal. The term "primary component" refers to a component with a mass ratio of 80% or more. More specifically, the material of the wiring conductors 21 and electrode pads 25 may be a mixed metal of Cu and Mo.

[0018] The dummy pattern 23 may be configured to include the above-mentioned low-resistance metal, or may be mainly composed of the low-resistance metal. The dummy pattern 23 may be configured to include the above-mentioned low-resistance metal and the above-mentioned high-melting-point metal, or may be mainly composed of a mixed metal of the low-resistance metal and the high-melting-point metal. The dummy pattern 23 may be a conductor of the same composition as the wiring conductor 21 and the electrode pad 25. By using the same composition, the wiring conductor 21, dummy pattern 23, and electrode pad 25 of one wiring layer 111 can be produced in the same pattern formation process during the manufacturing stage of the wiring substrate 10, thereby reducing the number of manufacturing steps.

[0019] The ground conductors 31 and the via conductors 41 of each ground layer 112 may contain the above-mentioned high-melting-point metal or may be mainly composed of the high-melting-point metal. More specifically, the ground conductors 31 and the via conductors 41 may be made of Mo.

[0020] <First Dummy Pattern> The dummy pattern 23 refers to a conductor pattern that does not contribute to the transmission of signals or the supply of voltage on the wiring board 10. The dummy pattern 23 may be a conductor pattern that is not electrically connected to the wiring conductor 21 through which signals or voltages are transmitted on the wiring board 10. The dummy pattern 23 may have a floating configuration in which the potential is independent, or may have a configuration in which a part of the dummy pattern 23 is grounded.

[0021] Next, any one of the multiple wiring layers 111 will be referred to as the first wiring layer 111, some or all of the multiple wiring conductors 21 included in the first wiring layer 111 will be referred to as the multiple first wiring conductors 21, and the dummy pattern 23 included in the first wiring layer 111 will be referred to as the first dummy pattern 23.

[0022] The first dummy pattern 23 may be located along a first path R1 that surrounds a plurality of first wiring conductors 21. "Located along a path" means "located on the path." The first dummy pattern 23 may have a ring-shaped configuration and may be located around the entire circumference of the first path R1 without being interrupted along the way. The plurality of first wiring conductors 21 surrounded by the first path R1 may be all of the wiring conductors 21 located in the first wiring layer 111, or may be all of the remaining wiring conductors 21 excluding some of the wiring conductors 21. In other words, some of the wiring conductors 21 may be located outside the first path R1. The "some of the wiring conductors 21" may be wiring conductors 21 that account for 10% or less, 5% or less, or 1% or less of all the wiring conductors 21 in terms of area ratio.

[0023] This configuration can reduce the phenomenon of the resistance of the first wiring conductor 21 increasing during the manufacturing stage of the wiring substrate 10. Specifically, a portion of the low-resistance metal contained in the first wiring conductor 21 diffuses into the ceramic substrate 11 during firing of the wiring substrate 10, and a large amount of diffusion increases the resistance of the first wiring conductor 21. Furthermore, during firing, heat is applied from the outside of the wiring substrate 10 in a plan view, so the first wiring conductor 21 located closer to the outer edge of the first wiring layer 111 tends to have more low-resistance metal diffusion. Therefore, by positioning the first dummy pattern 23 so as to surround a plurality of first wiring conductors 21, the diffusion of the low-resistance metal from the first dummy pattern 23 progresses, and the diffusion of the low-resistance metal from the plurality of first wiring conductors 21 inside surrounded by the first dummy pattern 23 can be suppressed accordingly. Therefore, the phenomenon of the resistance of the first wiring conductor 21 increasing due to the diffusion of the low-resistance metal can be efficiently reduced.

[0024] The first path R1 on which the first dummy pattern 23 is located may surround a plurality of electrode pads 25. The first path R1 may surround all of the electrode pads 25 of the first wiring layer 111, or may surround the remaining electrode pads 25 excluding some of them.

[0025] The first dummy pattern 23 may be a pattern having a line width similar to that of the wiring conductor 21. The first dummy pattern 23 may be a pattern having a line width larger than that of the wiring conductor 21. For example, the line width of the first dummy pattern 23 may be 100 μm to 300 μm. With this configuration, it is possible to further suppress the diffusion of low-resistance metal from the multiple first wiring conductors 21 inside surrounded by the first dummy pattern 23, while reducing the generation of excessive stress around the first dummy pattern 23.

[0026] The first dummy pattern 23 may have a shape that follows the sides of a circle or a regular polygon (specifically, a regular square, a regular dodecagon, a regular hexagon, a regular dicagon, etc.). The first dummy pattern 23 may be located inside the outer periphery E11 of the ceramic substrate 11 in a planar view, along the outer periphery E11. With this configuration, when the wiring substrate 10 is fired, heat is applied to the first dummy pattern 23 substantially uniformly from all directions outward in a planar view. Therefore, a substantially uniform diffusion of the low-resistance metal occurs in all directions inward from the first dummy pattern 23. This allows the diffusion of the low-resistance metal from the multiple first wiring conductors 21 located inside the first dummy pattern 23 to be uniformly reduced, thereby reducing variations in the resistance of the multiple first wiring conductors 21.

[0027] 1B and 1C , in a plan view, the outer peripheral edge E31 of the ground conductor 31 may be located along the outer peripheral edge E11 of the ceramic substrate 11 and further inward than the outer peripheral edge E11. In a planar perspective view, the first dummy pattern 23 may be located between the outer peripheral edge E31 of the ground conductor 31 and the outer peripheral edge E11 of the ceramic substrate 11. That is, in a planar perspective view, the first dummy pattern 23 may be located so as not to overlap with the ground conductor 31. By not overlapping, the thickness of the wiring board 10 can be reduced. That is, when conductors are located in overlapping positions in multiple layers, the thickness of the wiring board 10 increases accordingly, but this effect can be reduced.

[0028] The ground layer 112 does not need to have a configuration equivalent to the dummy pattern 23. The ground conductor 31 can have a higher resistivity than the wiring conductor 21, and can be made of a high-melting-point metal that is less likely to diffuse. Therefore, in the ground layer 112, it is not necessary to reduce the diffusion effect of the conductor by using a dummy pattern.

[0029] Each dummy pattern 23 in the multiple wiring layers 111 may be similar to the first dummy pattern 23 in the first wiring layer 111. As shown in FIG. 2 , the first dummy pattern 23 may be positioned so as to overlap with dummy patterns 23 in multiple wiring layers 111 other than the first wiring layer 111 over the entire path. That is, the first dummy pattern 23 and the other dummy patterns 23 may be positioned in the same location in a planar perspective view. With this configuration, the same effect of the dummy patterns 23 can be obtained in the multiple wiring layers 111, and variations in the resistance of the wiring conductors 21 among the multiple wiring layers 111 can be reduced.

[0030] 3A and 3B are a plan perspective view and a longitudinal cross-sectional view, respectively, showing a wiring board 10A according to a second embodiment of the present disclosure. The wiring board 10A according to the second embodiment may be the same as that according to the first embodiment, except that the pattern shapes of the dummy patterns 23Aa to 23Ac are different. The dummy pattern 23Aa corresponds to an example of a "first dummy pattern" according to the present disclosure.

[0031] 3A and 3B, the dummy patterns 23Aa to 23Ac located on different wiring layers 111 may be located at different positions in a planar perspective view. The dummy patterns 23Aa to 23Ac may be located so as not to intersect with each other in a planar perspective view, or may be located so as to partially intersect with each other.

[0032] When there are differences in the arrangement or density of the wiring conductors 21 among the multiple wiring layers 111, the locations of the dummy patterns 23Aa to 23Ac can be varied depending on the arrangement or density, thereby allowing the dummy patterns 23Aa to 23Ac of each wiring layer 111 to produce an effect of reducing diffusion of low-resistance conductors suitable for the wiring conductors 21 of each wiring layer 111. Therefore, the phenomenon in which the resistance of the wiring conductors 21 becomes high during the manufacturing stage can be reduced in accordance with the state of each wiring layer 111.

[0033] Each of the dummy patterns 23Aa to 23Ac may have a shape that follows the sides of a circle or a regular polygon, as in embodiment 1. The dummy patterns 23Aa to 23Ac may be located along the outer periphery E11 of the ceramic substrate 11 in a plan view, but may be located inside the outer periphery E11. The multiple dummy patterns 23Aa to 23Ac may have different diameters and may be located so as not to overlap each other in a planar perspective view.

[0034] This configuration allows the thickness of the wiring board 10A to be reduced. Furthermore, when the wiring board 10A is fired, heat is applied to the dummy patterns 23 in each wiring layer 111 approximately uniformly from all directions outward in a plan view. Therefore, in each wiring layer 111, the diffusion of the low-resistance metal occurs approximately uniformly in all directions inward from the dummy patterns 23. Therefore, in each wiring layer 111, the diffusion of the low-resistance metal from the multiple wiring conductors 21 located inside the dummy patterns 23 can be uniformly reduced, and variations in the resistance of the multiple wiring conductors 21 can be reduced.

[0035] 4A is a plan view showing the first wiring layer 111 of a wiring board 10B of embodiment 3. Fig. 4B is an enlarged view of a portion C1 of Fig. 4A. The wiring board 10B of embodiment 3 may be the same as embodiment 1 except that the pattern shape of the first dummy pattern 23B of the first wiring layer 111 is different.

[0036] The first dummy pattern 23B may have a shape different from the shape along the outer periphery of the ceramic substrate 11. In the example of Fig. 4A, the ceramic substrate 11 has a regular polygonal shape, while the first dummy pattern 23B is located on a first path R1b that follows a plurality of first wiring conductors 21 located near the outer periphery.

[0037] 4A , the first path R1b in the third embodiment may be a path that runs along the outer periphery of a plurality of first wiring conductors 21 that are located near the outer periphery of the ceramic substrate 11. Here, the "plurality of first wiring conductors 21 that are located near the outer periphery" refers to a set of a plurality of first wiring conductors 21 that are obtained by selecting the first wiring conductors 21 that are closest to a section of the outer periphery E11 of the ceramic substrate 11 and performing this selection for the entire section of the outer periphery E11. The "path that runs along the outer periphery of the first wiring conductors 21" refers to a path that runs between the selected first wiring conductor 21 and a section of the outer periphery E11 of the ceramic substrate 11 that is close to the first wiring conductor 21, but that is closer to the first wiring conductor 21 than the section of the outer periphery E11.

[0038] 4A, for example, a pattern with a steeply undulating path may be included among all the first wiring conductors 21. For the first wiring conductor 21A having such a shape, the undulating portion may be regarded as a flat path, and the first dummy pattern 23B may be positioned along the flat path.

[0039] Since the first dummy pattern 23B is close to the first wiring conductor 21, the low-resistance metal diffuses from the first dummy pattern 23B to the vicinity of the first wiring conductor 21. This can further reduce the effect of the low-resistance metal diffusing from the first wiring conductor 21. This can further reduce the phenomenon in which the resistance of the first wiring conductor 21 becomes high during the manufacturing stage.

[0040] In the portion where the first dummy pattern 23B is along the first wiring conductor 21, the distance between the first dummy pattern 23B and the first wiring conductor 21 may be 200 μm to 300 μm so that the first dummy pattern 23B and the first wiring conductor 21 are not too close. By ensuring this distance, it is possible to reduce the effect of the low-resistance metal diffusing from the first wiring conductor 21, and also to reduce the negative effect of the low-resistance metal diffused from the first dummy pattern 23B on the first wiring conductor 21.

[0041] The line width of the first dummy pattern 23B may be 100 μm to 300 μm, which is approximately the same as or greater than the wiring conductor 21, as in the first embodiment. Furthermore, as shown in FIG. 4A , the first dummy pattern 23B may include a section 231 having a line width wider than the other sections. In the section 231, the first dummy pattern 23B may have a pattern that spreads out in a planar shape. This configuration can further reduce the diffusion of low-resistance metal from the first wiring conductor 21 in a region close to the section 231. Therefore, if there is a first wiring conductor 21 for which a particularly low resistance is desired, or if there is a region with a high density of first wiring conductors 21, positioning the pattern of the section 231 near that region can further reduce the resistivity of the first wiring conductor 21 in that region.

[0042] Some or all of the electrode pads 25 may be located outside the first dummy pattern 23B because the electrode pads 25 are less susceptible to diffusion of the low-resistance metal and are less affected by this diffusion.

[0043] 4B, the end of the wide section 231 may have a tapered section 231a where the line width gradually narrows. This configuration can reduce the concentration of stress in the first dummy pattern 23B. Furthermore, this configuration can reduce the sudden change in the density of the low-resistance metal diffused from the first dummy pattern 23B in a certain region.

[0044] The configuration of the first dummy pattern 23B in the first wiring layer 111 described above may be similarly applied to the dummy patterns 23 in some or all of the other wiring layers 111.

[0045] 5A is a plan view showing a first wiring layer 111 of a wiring board 10C of embodiment 4. The wiring board 10C of embodiment 4 may be similar to embodiments 1 and 2 except that the pattern shape of the first dummy pattern 23C is different.

[0046] 5A , the first dummy pattern 23C may be located along a first path R1 that collectively surrounds a plurality of first wiring conductors 21, and may have one or more decoupling points B1 to B4 along the first path R1. The first path R1 of the fourth embodiment may be the same as the first path R1 of the first embodiment. The total length of the decoupling points B1 to B4 may be 20% or less, 10% or less, or 5% or less of the length of the first path R1.

[0047] The first wiring layer 111 may have regions A1 to A4 where the first wiring conductors 21 are sparsely located, and these regions A1 to A4 are less useful for diffusing the low-resistance metal from the first dummy pattern 23C. Therefore, the division points B1 to B4 of the first dummy pattern 23C may be located near these regions A1 to A4 to reduce the diffusion of the low-resistance metal from the first dummy pattern 23C.

[0048] The configuration of the first dummy pattern 23C described above may be similarly applied to the dummy patterns 23 of some or all of the other wiring layers 111.

[0049] 5B is a plan view showing a first wiring layer 111 of a wiring board 10D of embodiment 5. The wiring board 10D of embodiment 5 may be similar to embodiment 3 except that the pattern shape of the first dummy pattern 23D is different.

[0050] 5B , the first dummy pattern 23D may be located along a first path R1b that collectively surrounds a plurality of first wiring conductors 21, and may have one or more decoupling points B5 to B8 along the first path R1b. The first path R1b in the fifth embodiment may be the same as the first path R1b in the third embodiment. The total length of the decoupling points B5 to B8 may be 20% or less, 10% or less, or 5% or less of the length of the first path R1b.

[0051] The first wiring layer 111 may have regions A5 to A8 where the first wiring conductors 21 are sparsely located, and these regions A5 to A8 are less useful for diffusing the low-resistance metal from the first dummy pattern 23D. Therefore, the division points B5 to B8 of the first dummy pattern 23D may be located near these regions A5 to A8 to reduce the diffusion of the low-resistance metal from the first dummy pattern 23D.

[0052] The above-described configuration of the first dummy pattern 23D may be similarly applied to the dummy patterns 23 of some or all of the other wiring layers 111.

[0053] 6A is a plan view showing a first wiring layer 111 of a wiring board 10E of embodiment 6. FIG. 6B is a longitudinal cross-sectional view showing the wiring board 10E of embodiment 6. The wiring board 10E of embodiment 6 may be similar to embodiments 1 to 5, except that the dummy pattern 23E of the first wiring layer 111 is different.

[0054] 6A , the dummy pattern 23E may include a first dummy pattern 23Ea located along a first path R11 that collectively surrounds a plurality of first wiring conductors 21, and a second dummy pattern 23Eb located along a second path R12 that collectively surrounds a plurality of first wiring conductors 21. The first path R11 and the second path R12 may not intersect, and the second path R12 may surround the first path R11.

[0055] The first dummy pattern 23Ea may have a divided portion like the first dummy pattern 23C of embodiment 4, or may have an undivided annular shape like the first dummy pattern 23 of embodiment 1. The second dummy pattern 23Eb may have a divided portion like the first dummy pattern 23C of embodiment 4, or may have an undivided annular shape like the first dummy pattern 23 of embodiment 1. The example of Fig. 6A shows a configuration in which both the first dummy pattern 23Ea and the second dummy pattern 23Eb are annular.

[0056] The configuration of the dummy pattern 23E described above may be similarly applied to the dummy patterns 23 of all other wiring layers 111, or may be similarly applied only to the dummy patterns 23 of a specific layer. In the example of Fig. 6B, a first dummy pattern 23Ea and a second dummy pattern 23Eb are included in two wiring layers 111B and 111D.

[0057] The inclusion of the first dummy pattern 23Ea and the second dummy pattern 23Eb can further reduce the thermal effect on the first wiring conductor 21 located inside when the wiring substrate 10E is fired, thereby further reducing the phenomenon in which the resistance of the first wiring conductor 21 increases.

[0058] Although Figures 6A and 6B show an example in which multiple first wiring conductors 21 are surrounded doubly by dummy patterns 23E, a configuration in which the first wiring conductors 21 are surrounded by more dummy patterns, such as n-fold (n is an integer greater than or equal to 3), may also be adopted.

[0059] 7 is a plan view showing a first wiring layer 111 of a wiring board 10F of embodiment 7. The wiring board 10F of embodiment 7 may be the same as embodiments 1 to 6 except for the dummy pattern 23F.

[0060] 7 , the dummy pattern 23F may include a first dummy pattern 23Fa located along a first path R21 that collectively surrounds a plurality of first wiring conductors 21, and a second dummy pattern 23Fb located along a second path R22 that collectively surrounds a plurality of first wiring conductors 21. The first path R21 and the second path R22 may not intersect, and the second path R22 may surround the first path R21. Specifically, the second path R22 of the seventh embodiment may be similar to the first path R1 of the first embodiment. The first path R21 of the seventh embodiment may be similar to the first path R1b of the third embodiment.

[0061] The first dummy pattern 23Fa may have a divided portion like the first dummy pattern 23D of embodiment 5, or may be an undivided ring-shaped pattern like the first dummy pattern 23B of embodiment 3. The second dummy pattern 23Fb may have a divided portion like the first dummy pattern 23C of embodiment 4, or may be an undivided ring-shaped pattern like the first dummy pattern 23 of embodiment 1. The example of Fig. 7 shows a configuration in which both the first dummy pattern 23Fa and the second dummy pattern 23Fb are ring-shaped.

[0062] The above-described configuration of the dummy pattern 23F may be similarly applied to the dummy patterns 23 of all other wiring layers 111, or may be similarly applied only to the dummy patterns 23 of a specific layer.

[0063] The inclusion of the first dummy pattern 23Fa and the second dummy pattern 23Fb can further reduce the thermal effect on the first wiring conductor 21 located inside when the wiring substrate 10F is fired, thereby further reducing the phenomenon in which the resistance of the first wiring conductor 21 becomes high.

[0064] 7 shows an example in which the first dummy pattern 23Fa and the second dummy pattern 23Fb have different shapes, but both the first dummy pattern 23Fa and the second dummy pattern 23Fb may have shapes that follow the outer periphery of the first wiring conductor 21. Also, while Fig. 7 shows an example in which a plurality of first wiring conductors 21 are surrounded doubly by dummy patterns 23F, a configuration in which the first wiring conductor 21 is surrounded by more dummy patterns, such as n-fold (n is an integer of 3 or more), may be employed.

[0065] (Probe Card) Fig. 8 is a side view showing a probe card 100 according to an embodiment of the present disclosure. The probe card 100 according to the first embodiment of the present disclosure includes a wiring substrate 10 and a plurality of probe pins 61. The probe pins 61 may be joined to the conductor pads 52 via a joining material such as solder. The wiring substrate 10 may be replaced with wiring substrates 10A to 10F according to other embodiments.

[0066] The probe card 100 is supported by a frame (not shown) and electrically connected to an inspection device (not shown) via a plurality of conductor pads 51. Meanwhile, probe pins 61 of the probe card 100 are connected to electrodes of an electronic circuit (e.g., an electronic circuit formed on a silicon wafer) to be inspected. Then, the inspection device (not shown) exchanges signals and / or power supply voltages between the wiring board 10 and the electronic circuit to be inspected via the plurality of probe pins 61, thereby inspecting the object to be inspected.

[0067] The probe pins 61 do not have to be directly bonded to the conductor pads 51, but may be electrically connected to the conductor pads 51 via a resin substrate having a thin-film wiring layer. The resin substrate may be made of, for example, polyimide.

[0068] The above describes each embodiment of the present disclosure. However, the wiring board and probe card of the present disclosure are not limited to the above embodiments. To the extent that no contradiction occurs, some of the components of the wiring boards 10 and 10A to 10F of embodiments 1 to 7 may be appropriately combined and applied to a single wiring board. Furthermore, the details shown in the embodiments may be appropriately modified without departing from the spirit of the invention.

[0069] In one embodiment of the present disclosure, (1) a wiring board includes: a ceramic substrate having a first wiring layer; a plurality of first wiring conductors located in the first wiring layer, the first wiring conductors including at least one low-resistance metal selected from the group consisting of Cu, Au, and Ag, and at least one high-melting-point metal selected from Mo and W; and a first dummy pattern located in the first wiring layer, the first dummy pattern including the low-resistance metal, the first dummy pattern being located along a first path surrounding the plurality of first wiring conductors.

[0070] (2) In the wiring board of (1) above, the first dummy pattern is annular.

[0071] (3) In the wiring board of (1) above, the first dummy pattern has one or more disconnected portions.

[0072] (4) The wiring board according to any one of (1) to (3) above, wherein the ceramic substrate has a circular or regular polygonal shape in a plan view, and the first dummy pattern has a shape that follows a side of the circle or regular polygon in a plan view.

[0073] (5) In the wiring board according to any one of (1) to (3) above, the first dummy pattern has a shape different from a shape along the outer periphery of the ceramic substrate.

[0074] (6) The wiring board of any one of (1) to (5) above further comprises a second dummy pattern containing the low-resistance metal and located in the first wiring layer, and the second dummy pattern is located along a second path that collectively surrounds the plurality of first wiring conductors.

[0075] (7) The wiring board according to any one of (1) to (6) above, wherein the ceramic substrate further has a plurality of wiring layers in addition to the first wiring layer, and further comprises a plurality of wiring conductors each including the low resistance metal and the high melting point metal and located in each of the plurality of wiring layers, and a dummy pattern each including the low resistance metal and located in each of the plurality of wiring layers along a path surrounding the plurality of wiring conductors.

[0076] (8) In the wiring board of (7) above, the first dummy pattern is located in the same position as the dummy patterns located in each of the plurality of wiring layers in a planar perspective view.

[0077] (9) In the wiring board of (7) above, the first dummy pattern is located at a position different from at least one of the plurality of dummy patterns located in the plurality of wiring layers in a planar perspective view.

[0078] (10) A probe card includes the wiring board according to any one of (1) to (9) above, and a plurality of probe pins.

[0079] The present disclosure can be used for wiring boards and probe cards.

[0080] 10, 10A to 10F Wiring substrate 11 Ceramic substrate 111, 111B, 111D Wiring layer 112 Ground layer 21 First wiring conductor 23, 23B, 23C, 23Ea, 23Fa First dummy pattern 23Eb, 23Fb Second dummy pattern 23Aa to 23Ac Dummy pattern 231 Section 231a Tapered portion 25 Electrode pad 31 Ground conductor 41 Via conductor 51, 52 Conductor pad 61 Probe pin 100 Probe card B1 to B8 Separation point R1, R1b, R11, R21 First path (path) R12, R22 Second path (path) E11, E31 Outer periphery

Claims

1. A wiring board comprising: a ceramic substrate having a first wiring layer; a plurality of first wiring conductors located in the first wiring layer, the first wiring conductors comprising at least one low-resistance metal selected from the group consisting of Cu, Au, and Ag, and at least one high-melting-point metal selected from Mo and W; and a first dummy pattern located in the first wiring layer, the first dummy pattern comprising the low-resistance metal, wherein the first dummy pattern is located along a first path that collectively surrounds the plurality of first wiring conductors.

2. The wiring board according to claim 1, wherein the first dummy pattern is annular.

3. The wiring board according to claim 1, wherein the first dummy pattern has one or more disconnected portions.

4. The wiring board according to any one of claims 1 to 3, wherein the ceramic substrate has a circular or regular polygonal shape in a planar view, and the first dummy pattern has a shape that follows a side of the circle or regular polygon in a planar view.

5. The wiring board according to any one of claims 1 to 3, wherein the first dummy pattern has a shape different from a shape along the outer periphery of the ceramic substrate.

6. The wiring board according to any one of claims 1 to 5, further comprising a second dummy pattern that includes the low-resistance metal and is located in the first wiring layer, the second dummy pattern being located along a second path that collectively surrounds the plurality of first wiring conductors.

7. A wiring board according to any one of claims 1 to 6, wherein the ceramic substrate further has a plurality of wiring layers in addition to the first wiring layer, and further comprises: a plurality of wiring conductors containing the low-resistance metal and the high-melting-point metal and located in each of the plurality of wiring layers; and a dummy pattern containing the low-resistance metal and located in each of the plurality of wiring layers along a path surrounding the plurality of wiring conductors.

8. The wiring board according to claim 7, wherein, in planar perspective, the first dummy pattern is located in the same position as the dummy patterns located in each of the plurality of wiring layers.

9. The wiring board according to claim 7, wherein, in planar perspective, the first dummy pattern is located at a position different from at least one of the plurality of dummy patterns located in the plurality of wiring layers.

10. A probe card comprising: a wiring board according to any one of claims 1 to 9; and a plurality of probe pins.

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