Ferroelectric tunnel junction element and memory device including same

Abstract

The present invention relates to a ferroelectric junction element that is self-rectifying and has a non-linear current-voltage profile and a high on / off current ratio, and to a memory device comprising the ferroelectric junction element.

Description

Ferroelectric tunnel junction device and memory device including the same

[0001] The present invention relates to a ferroelectric tunnel junction device and a memory device including the same. The present invention claims the benefit of Korean Patent Application No. 10-2024-0040698, filed with the Korean Intellectual Property Office on March 25, 2024, the entire contents of which are incorporated herein by reference.

[0002] With the advent of the Fourth Industrial Revolution, core technologies such as artificial intelligence, big data, the Internet of Things, and autonomous vehicles are exploding the demand for information and semiconductor devices. Ferroelectric memory devices operate according to the electrostatic model of spontaneous polarization of ferroelectrics. This spontaneous polarization can be switched by applying an electric field above a critical coercive field, and the stored polarization state is maintained even after the electric field is removed, making them ideal for non-volatile memory devices.

[0003] Ferroelectric tunnel junction (FTJ) devices are two-terminal devices based on a capacitor structure, and have the advantage of being applicable to crossbar arrays (CBAs) that allow for high integration. However, conventional FTJ devices have the characteristic of allowing current to flow in both directions depending on the voltage applied to both ends. Therefore, when applied to an array, sneak current, which is current that flows along an unintended path, can flow. To prevent read errors caused by this, there was a problem that additional selection devices, such as transistors, had to be included.

[0004] The technical problem to be achieved by the present invention is to provide a ferroelectric junction device having self-rectifying characteristics and nonlinear current-voltage characteristics and a high on / off current ratio.

[0005] However, the problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

[0006] One embodiment of the present invention comprises: a lower electrode; a ferroelectric layer positioned on the lower electrode and including a ferroelectric; and an energy band gap (E) positioned on the ferroelectric layer and larger than the ferroelectric. g ) a first dielectric layer including a first dielectric having a large energy band gap (E ) and positioned on the first dielectric layer; and having an energy band gap (E ) greater than that of the ferroelectric. g ) a second dielectric layer including a small second dielectric; and an upper electrode positioned on the second dielectric layer, and a ferroelectric tunnel junction (FTJ) device satisfying the following mathematical expression 1 is provided:

[0007] [Mathematical Formula 1]

[0008]

[0009] In the above mathematical expression 1, χ FE is the electron affinity of the ferroelectric, χ2 is the electron affinity of the second dielectric, and φ BE is the work function of the lower electrode, and φ TE is the work function of the upper electrode.

[0010] Another embodiment of the present invention provides a memory device including the ferroelectric tunnel junction element.

[0011] A ferroelectric tunnel junction device according to one embodiment of the present invention has self-rectifying characteristics and nonlinear current-voltage characteristics, and can have a high on / off current ratio.

[0012] A memory device including a ferroelectric tunnel junction element according to one embodiment of the present invention can prevent the flow of sneak current without a separate selection element and can have a large array size.

[0013] A ferroelectric tunnel junction device according to one embodiment of the present invention can store multiple levels of resistance states rather than just two states of 0 and 1.

[0014] The effects of the present invention are not limited to the effects described above, and effects not mentioned will be clearly understood by those skilled in the art from the present specification and the attached drawings.

[0015] Figure 1 is a cross-sectional view of a ferroelectric tunnel junction device according to one embodiment of the present invention.

[0016] FIG. 2 is a drawing showing an energy band diagram of a ferroelectric tunnel junction device according to one embodiment of the present invention.

[0017] FIG. 3 is a schematic diagram (a) showing the path of a sneak current that may occur in a three-dimensional crossbar array structure and the path of a current flowing through a selected element, and a graph (b) showing the case where a self-rectification characteristic appears and the case where both a self-rectification characteristic and a nonlinear current-voltage characteristic appear depending on the size of a read voltage applied to an element according to one embodiment of the present invention.

[0018] Figure 4 is an energy band diagram in the direction of the thickness of the device layer in a situation where voltage is applied to the upper electrode or the lower electrode of the device of Example 2.

[0019] Figure 5 is an energy band diagram showing the polarization direction of the ferroelectric layer being switched by applying -3 V to the device of Example 2.

[0020] Figure 6 is an energy band diagram showing the polarization direction of the ferroelectric layer being switched by applying +3 V to the device of Example 2.

[0021] Figure 7 is a diagram showing the GIXRD analysis results for the devices of Example 2 and Comparative Example 1.

[0022] Figure 8 is a diagram showing an IV curve for the device of Example 1.

[0023] Figure 9 is a diagram showing IV curves for the devices of Comparative Example 1 (a), Comparative Example 2 (b), Comparative Example 3 (c), and Comparative Example 4 (c).

[0024] Figure 10 is a drawing showing the preservation characteristics of the device of Example 1.

[0025] Figure 11 is a schematic diagram (a) of an N by M three-dimensional CBA structure and its equivalent circuit, and a schematic diagram (b) of a two-dimensional CBA structure and its circuit with potentials induced in the read process of F, Vr / 3, and Vr / 2.

[0026] Figure 12 is a diagram showing the current values ​​read when applying the floating, Vr / 2, and Vr / 3 reading methods to the device of Example 1, respectively.

[0027] Fig. 13 is a diagram showing the CBA array size according to the read margin (%) when applying the element (a) of Example 1 and the element (b) of Comparative Example 3 to an array of an N by N CBA structure.

[0028] Figure 14 is a diagram showing a voltage pulse (a) applied to the device of Example 1 to record multi-level resistance and the electrical conductivity (b) of the device measured through the voltage pulse.

[0029] Figure 15 is a cumulative distribution function for the electrical conductivity of the device of Example 1.

[0030] Figure 16 is a diagram showing the results of constructing and training a neural network that infers handwritten digits from 0 to 9 in the MNIST database based on the cumulative distribution function for the elements of Example 1.

[0031] Figure 17 is a plane-view image of the CBA manufactured in Example 3.

[0032] Fig. 18 is a drawing showing the IV curves of Cell (i) and Cell (ii) shown in Fig. 17 among the CBAs produced in Example 3.

[0033] Figure 19 shows the results of measuring multiple resistance values ​​of cells in the entire CBA manufactured in Example 3.

[0034] Figure 20 shows the current measured in each state of the cells of the CBA manufactured in Example 3 as a cumulative distribution function.

[0035] Throughout this specification, whenever a part is said to "include" a component, this does not mean that it excludes other components, but rather that it may include other components, unless otherwise specifically stated.

[0036] Throughout this specification, when it is said that an element is "on" another element, this includes not only cases where the element is in contact with the other element, but also cases where another element exists between the two elements.

[0037] Throughout this specification, the unit “parts by weight” may mean the weight ratio between each component.

[0038] Throughout this specification, “A and / or B” means “A and B, or A or B.”

[0039] One embodiment of the present invention comprises: a lower electrode; a ferroelectric layer positioned on the lower electrode and including a ferroelectric; and an energy band gap (E) positioned on the ferroelectric layer and larger than the ferroelectric. g ) a first dielectric layer including a first dielectric having a large energy band gap (E ) and positioned on the first dielectric layer; and having an energy band gap (E ) greater than that of the ferroelectric. g ) a second dielectric layer including a small second dielectric; and an upper electrode positioned on the second dielectric layer, and a ferroelectric tunnel junction (FTJ) device satisfying the following mathematical expression 1 is provided:

[0040] [Mathematical Formula 1]

[0041]

[0042] In the above mathematical expression 1, χ FE is the electron affinity of the ferroelectric, χ2 is the electron affinity of the second dielectric, and φ BE is the work function of the lower electrode, and φ TE is the work function of the upper electrode.

[0043] A ferroelectric tunnel junction device according to one embodiment of the present invention has self-rectifying characteristics and nonlinear current-voltage characteristics, and may have a high on / off current ratio. Here, the on / off current ratio of the device means the ratio of the current intensity flowing when the device is in a low resistive state (LRS) at a constant voltage to the current intensity flowing when the device is in a high resistive state (HRS). The ferroelectric tunnel junction device may have a self-rectifying characteristic in which a current flowing from the lower electrode toward the upper electrode is suppressed.

[0044] Figure 1 is a cross-sectional view of a ferroelectric tunnel junction device according to one embodiment of the present invention.

[0045] A ferroelectric tunnel junction device (100) according to one embodiment of the present invention comprises: a lower electrode (10); a ferroelectric layer (20) positioned on the lower electrode (10) and including a ferroelectric; and an energy band gap (E) positioned on the ferroelectric layer (20) and larger than the ferroelectric. g ) a first dielectric layer (30) including a first dielectric having a large energy band gap (E) greater than that of the ferroelectric, positioned on the first dielectric layer (30) g ) includes a second dielectric layer (40) including a small second dielectric; and an upper electrode (50) positioned on the second dielectric layer (40).

[0046] A ferroelectric tunnel junction device according to one embodiment of the present invention satisfies the following mathematical expression 1:

[0047] [Mathematical Formula 1]

[0048]

[0049] In the above mathematical expression 1, χ FE is the electron affinity of the ferroelectric, χ2 is the electron affinity of the second dielectric, and φ BE is the work function of the lower electrode, and φ TE is the work function of the upper electrode.

[0050] Figure 2 is a drawing showing an energy band diagram of a ferroelectric tunnel junction device according to one embodiment of the present invention. In Figure 2, χ Fe is the electron affinity of the ferroelectric, χ2 is the electron affinity of the second dielectric, and φ BE is the work function of the lower electrode, and φ TE is the work function of the upper electrode, and △E TE is the conduction band offset of the upper electrode, φ TE -Corresponds to χ2, △E BE is the conduction band offset of the lower electrode, φ BE -χ Fe It corresponds to .

[0051] Referring to Fig. 2, the ferroelectric tunnel junction device according to the present invention satisfies the above mathematical expression 1, thereby obtaining △E TE A △E BE It can be larger, and a Schottky barrier difference between the upper and lower electrodes is formed, which allows the device to have self-rectifying characteristics.

[0052] According to one embodiment of the present invention, the work function of the lower electrode may be greater than the work function of the upper electrode.

[0053] According to one embodiment of the present invention, the work function of the lower electrode may be 5 eV or more and 8 eV or less, and the work function of the upper electrode may be 3 eV or more and 6.5 eV or less.

[0054] According to one embodiment of the present invention, as a material constituting the upper electrode and the lower electrode, a material satisfying the work function condition according to the mathematical expression 1 may be used.

[0055] According to one embodiment of the present invention, the lower electrode is Pt, Ir, Mo2N, MoO x , RuO x and IrO x It may include one or more selected from the group consisting of .

[0056] According to one embodiment of the present invention, the upper electrode may include at least one selected from the group consisting of Sc, TaN, Ta, W, Ti, Mo, and TiN.

[0057] When the upper electrode and the lower electrode include the above-described material, the difference in the Schottky barrier formed can be large and the self-rectifying characteristics of the device can be excellent.

[0058] According to one embodiment of the present invention, the ferroelectric layer positioned on the lower electrode includes a ferroelectric.

[0059] According to one embodiment of the present invention, the ferroelectric material can be represented by the following chemical formula 1.

[0060] [Chemical Formula 1]

[0061] Hf 1-x M x O2

[0062] In the above chemical formula 1, M is at least one of Zr, Si, Al, Y, Sr, La, and Gd, and x is 0.01 or more and 0.99 or less.

[0063] According to one embodiment of the invention, the ferroelectric represented by the above chemical formula 1 may be a ferroelectric material in which at least one element selected from the group consisting of Zr, Si, Al, Y, Sr, La, and Gd is doped into hafnium oxide (HfO2). By controlling the type and content of the element doped into the hafnium oxide within the above-described range, the ferroelectric properties of the ferroelectric layer can be changed and improved.

[0064] Preferably, the ferroelectric may be hafnium-zirconium oxide (HZO) in which Zr is doped into hafnium oxide (HfO2). Specifically, the ferroelectric may be represented by the following chemical formula 2.

[0065] [Chemical Formula 2]

[0066] Hf 1-x Zr x O2

[0067] In the above chemical formula 2, x is 0.4 or more and 0.6 or less.

[0068] According to one embodiment of the present invention, by controlling the Hf:Zr ratio of the HZO, the ferroelectricity of the ferroelectric layer can be controlled, and the coercive field of the ferroelectric layer can be changed.

[0069] According to one embodiment of the present invention, the HZO may be polycrystalline including an orthorhombic phase.

[0070] According to one embodiment of the present invention, in order to improve the ferroelectricity of the ferroelectric layer so that the device can achieve a high on-off ratio, it is preferable that the polycrystalline HZO contains a large amount of the orthorhombic phase, which is a crystal phase having ferroelectricity. As the proportion of Hf in hafnium-zirconium oxide increases, the proportion of the monoclinic phase increases, and as the proportion of Zr increases, the proportion of the tetragonal phase increases. Since the monoclinic and tetragonal phases in polycrystalline HZO are known to have non-ferroelectricity, it is preferable that the ratio of Hf and Zr in HZO is close to 1:1 in order to enable the device of the present invention to have a high on-off ratio.

[0071] Furthermore, from the standpoint of coercivity, the coercivity may increase when polycrystalline HZO contains a monoclinic phase, and the coercivity may decrease when polycrystalline HZO contains a tetragonal phase. Therefore, in order to ensure that the device has an appropriate operating voltage, it is desirable that the ratio of Hf to Zr in HZO be close to 1:1.

[0072] According to one embodiment of the present invention, the polycrystal of HZO included in the ferroelectric layer may be affected by the thickness of the ferroelectric layer in addition to the Hf:Zr ratio. As the thickness of the ferroelectric layer decreases and the ratio of Hf is high, the orthorhombic phase is more likely to be stabilized, and the tendency for the tetragonal phase to be formed due to Zr becomes stronger. Conversely, as the thickness of the ferroelectric layer increases, the tendency for the tetragonal phase to be formed due to Zr becomes smaller, so even if the ratio of Zr is high, the orthorhombic phase is more likely to be stabilized, and the tendency for the monoclinic phase to be stabilized due to Hf becomes stronger.

[0073] Therefore, from the above-described viewpoint, it is preferable that x in the chemical formula 2 is 0.4 or more and 0.6 or less, and when the thickness of the ferroelectric layer is low, it is more preferable that x is 0.4 or more and 0.5 or less, and when the thickness of the ferroelectric layer is large, it is more preferable that x is 0.5 or more and 0.6 or less.

[0074] According to one embodiment of the present invention, the ferroelectric layer can operate in a manner that affects the electrical conductivity of the device by causing a change in the energy barrier depending on the polarization direction.

[0075] The magnitude of the writing voltage for changing the polarization direction of the ferroelectric layer may be greater than the magnitude of the coercive voltage corresponding to the coercive field of the ferroelectric layer.

[0076] When a negative write voltage is applied to the upper electrode, the ferroelectric layer forms positive charges at the interface toward the upper electrode, and accordingly, the energy states of the ferroelectric layer, the first dielectric layer, and the second dielectric layer change, so that the energy barrier in the direction from the upper electrode to the lower electrode can be lowered. Due to the lowered energy barrier, the electrical conductivity of the device increases, and the device can enter a low resistive state (LRS).

[0077] Conversely, when a positive write voltage is applied to the upper electrode, the ferroelectric layer forms positive charges at the interface toward the lower electrode, thereby changing the energy states of the ferroelectric layer, the first dielectric layer, and the second dielectric layer, which may increase the energy barrier in the direction from the upper electrode to the lower electrode. Due to the increased energy barrier, the electrical conductivity of the device decreases, and the device may enter a high resistive state (HRS).

[0078] According to one embodiment of the present invention, the degree of polarization of the ferroelectric layer can change depending on the magnitude of the applied writing voltage, and thus, the device according to the present invention can store multiple levels of resistance states rather than just two states of 0 and 1.

[0079] According to one embodiment of the invention, the thickness of the ferroelectric layer may be 0.5 to 10 nm. Preferably, the thickness of the ferroelectric layer may be 0.5 to 6 nm, or 0.5 to 3 nm. When the thickness of the ferroelectric layer satisfies the above preferred range, the thickness of the device may be thin, enabling high integration, while the ferroelectric layer may exhibit ferroelectricity.

[0080] According to one embodiment of the present invention, the first dielectric layer positioned on the ferroelectric layer has an energy band gap (E) greater than that of the ferroelectric. g ) includes a large first dielectric. Specifically, the energy band gap of the first dielectric may be 6 eV or more.

[0081] Energy band gap (E) higher than that of the above ferroelectric g ) The first dielectric layer including the large first dielectric can increase the resistance value of the high-resistance state device, thereby increasing the on-off ratio of the device.

[0082] In addition, the first dielectric layer can act as a high energy barrier to suppress the flow of reverse current when the difference between the electron affinity of the ferroelectric and the work function of the lower electrode is not sufficiently large in a reverse electric field that applies a negative voltage to the lower electrode and when the reverse electric field is high.

[0083] According to one embodiment of the present invention, the first dielectric may include at least one selected from the group consisting of Al2O3 and SiO2. When the first dielectric includes the above-described material, the energy band gap may be higher than that of the ferroelectric, and since it is an oxide, it may prevent defects such as oxygen vacancies from occurring in the ferroelectric layer, thereby ensuring the operational reliability of the device.

[0084] According to one embodiment of the present invention, the thickness of the first dielectric layer may be 0.1 to 5 nm.

[0085] According to one embodiment of the present invention, the second dielectric layer positioned on the first dielectric layer has an energy band gap (E) greater than that of the ferroelectric. g ) includes a small second dielectric. Specifically, the energy band gap of the second dielectric may be 5 eV or less. For example, the second dielectric may include at least one selected from the group consisting of TiO2, MoO3, WO3, and Ta2O5.

[0086] According to one embodiment of the present invention, the thickness of the second dielectric layer may be 5 to 30 nm or 10 to 30 nm. When the thickness of the second dielectric layer satisfies the above-described range, the nonlinear current-voltage characteristics of the device may be prominent.

[0087] The second dielectric layer can act as a barrier in the direction of the thickness of the second dielectric layer at low voltage, and at high voltage, the slope of the energy band becomes steeper, causing the barrier thickness to become thinner, thereby causing the device to have nonlinear current-voltage characteristics.

[0088] According to one embodiment of the present invention, the upper electrode and the lower electrode described above can be formed by a deposition method known in the art, and preferably can be formed by ion sputtering.

[0089] According to one embodiment of the present invention, the first dielectric layer, the second dielectric layer, and the ferroelectric layer described above can be formed by a deposition method known in the art, and preferably can be formed by atomic layer deposition. When the first dielectric layer, the second dielectric layer, and the ferroelectric layer are formed by atomic layer deposition, uniform deposition is possible, and compatibility with existing semiconductor processes is high, which is advantageous for commercialization.

[0090] Another embodiment of the present invention provides a memory device including the ferroelectric tunnel junction element.

[0091] According to one embodiment of the present invention, the ferroelectric tunnel junction element can store multiple levels of resistance states depending on the polarization direction and degree of the ferroelectric layer. The ferroelectric tunnel junction element stores high resistance states and low resistance states, and can be applied to a resistance change memory device due to its high on-off ratio.

[0092] According to one embodiment of the present invention, a memory device including the ferroelectric tunnel junction element may be a memory device having a crossbar array structure including a plurality of the ferroelectric tunnel junction elements.

[0093] A memory device including a ferroelectric tunnel junction element according to one embodiment of the present invention can prevent the flow of sneak current without a separate selection element and can have a large array size.

[0094] Specifically, the memory device may include a plurality of bit lines arranged parallel to each other on a substrate; word lines positioned over the bit lines, intersecting the bit lines, and arranged parallel to each other; and a ferroelectric tunnel junction element positioned at a portion where the bit lines and the word lines intersect.

[0095] According to one embodiment of the present invention, the bit lines may be conductive lines connected to the lower electrode of the ferroelectric tunnel junction element or may directly form the lower electrode. The word lines may be conductive lines connected to the upper electrode of the ferroelectric tunnel junction element or may directly form the upper electrode.

[0096] Part (a) of Fig. 3 shows the path of sneak current that may occur in a three-dimensional crossbar array structure and the path of current flowing through selected elements. Referring to part (a) of Fig. 3, a unit cell of a two-terminal structure may experience sneak current flow through other cells that share word lines and bit lines in the crossbar array structure, which may result in read errors. Specifically, the path indicated by the sneak current path passes through three unselected cells, and in Cell A and Cell C, a forward current flows in which electrons move from the upper electrode toward the lower electrode, and in Cell B, a reverse current flows in which electrons move from the lower electrode toward the upper electrode.

[0097] Therefore, a method can be used to prevent reverse current flow in the unselected cell B in a way that suppresses the current that can flow in the sneak current path while maintaining a readout current sufficient for the read operation.

[0098] When a ferroelectric tunnel junction element according to an embodiment of the present invention having self-rectifying characteristics is applied to such an array structure, a high voltage is applied to cell B, which is an element in a sneak current path and through which current flows in the reverse direction, because the resistance is high, and therefore, a low voltage is applied to cell A and cell C, which are elements in a sneak current path and through which current flows in the forward direction.

[0099] Part (b) of FIG. 3 is a diagram showing a case where a self-rectifying characteristic appears depending on the size of a read voltage applied to a device according to one embodiment of the present invention, and a case where both a self-rectifying characteristic and a nonlinear current-voltage characteristic appear.

[0100] Referring to part (b) of FIG. 3, in a memory device applying a device according to an embodiment of the present invention, -V is applied to cell B through which reverse current flows. read It can be seen that the current flows significantly lower due to the self-commutating characteristic in the V, thereby suppressing the sneak current. In addition, V read When driven in a read mode of / 3, the voltage applied to cells A and C in the sneak current path is +V read / 3 The nonlinear nature of the device allows for low current flow and high overall resistance corresponding to the sneak current path.

[0101] A ferroelectric tunnel junction device according to one embodiment of the present invention has a self-rectifying characteristic that suppresses the flow of reverse current and a nonlinear current-voltage characteristic in which the conductivity decreases rapidly at a voltage lower than a read voltage, and has a high on / off current ratio, thereby enabling the implementation of a selector-only memory device without a selection element.

[0102] Hereinafter, the present invention will be described in detail using examples. However, the examples according to the present invention may be modified in various ways, and the scope of the present invention is not limited to the examples described below. The examples in this specification are provided to more fully explain the present invention to those of ordinary skill in the art.

[0103] Example 1: Fabrication of Tin / TiO2(17nm) / Al2O3(1nm) / HZO(1:1_6nm) / Pt devices

[0104] First, Pt was deposited on a Si substrate using an ion sputter coater to form a lower electrode. Then, to deposit HZO on the Pt, [(CH3)(C2H5)N]4Hf (TEMAH) and [(CH3)(C2H5)N]4Zr (TEMAZ) were used as metal precursors and ozone (O3) was used as an oxidizer. Atomic layer deposition (ALD) was performed for a total of 60 cycles at a substrate temperature of ~290°C to form a HZO layer with a thickness of approximately 6 nm. The deposited HZO layer was composed of HfO2 and ZrO2 in a 1:1 ratio (Hf 0.5 Zr 0.5 It is in the form of a solid solution with O2).

[0105] Then, atomic layer deposition was performed for a total of 10 cycles using (CH3)3Al(TMA) as a precursor and ozone (O3) as an oxidizer at the same substrate temperature to form an Al2O3 layer with a thickness of approximately 1 nm. After forming the Al2O3 layer, rapid thermal processing (RTP) was used to perform heat treatment at 600°C for 30 s in a N2 atmosphere to crystallize HZO.

[0106] After heat treatment, a TiO2 layer was formed using plasma-enhanced ALD (PEALD). [(CH3)2N]4Ti (TDMAT) was used as a precursor, and O2 plasma was used as an oxidizer. 256 cycles of PEALD using 600 W plasma at a chamber temperature of 150°C, O2 180 sccm, and Ar 120 sccm were performed to form a 17 nm thick TiO2 layer.

[0107] As the upper electrode, a TiN electrode was deposited and formed through RF (radio frequency) sputtering with a plasma power of 200 W, a process pressure of 1 mTorr, and a process time of approximately 15 minutes.

[0108] Example 2: Fabrication of Sc / TiO2(17nm) / Al2O3(1nm) / HZO(1:1_6nm) / Pt devices

[0109] A device was manufactured in the same manner as in Example 1, except that a Sc electrode was formed by depositing it instead of TiN as the upper electrode through DC (direct current) sputtering at a plasma power of 200 Wm, a process pressure of 3 mTorr, and a process time of approximately 3 minutes.

[0110] Comparative Example 1: Fabrication of Tin / TiO2(17nm) / Al2O3(1nm) / HfO2(6nm) / Pt device

[0111] In Example 1, a device was manufactured in the same manner as in Example 1, except that a 6 nm thick HfO2 layer was formed instead of forming the HZO layer. The HfO2 layer was formed by performing atomic layer deposition (ALD) for a total of 60 cycles at a substrate temperature of ~290°C using [(CH3)(C2H5)N]4Hf (TEMAH) as a metal precursor and ozone (O3) as an oxidizer.

[0112] Comparative Example 2: Fabrication of Tin / TiO2 (17 nm) / Al2O3 (1 nm) / Pt devices

[0113] In Example 1, a device was manufactured in the same manner as in Example 1, except that the HZO layer was not formed and heat treatment for HZO crystallization was not performed.

[0114] Comparative Example 3: Fabrication of Tin / Al2O3(1nm) / HZO(1:1_6nm) / Pt devices

[0115] In Example 1, a device was manufactured in the same manner as in Example 1, except that the TiO2 layer was not formed.

[0116] Comparative Example 4: Fabrication of Tin / TiO2 (17 nm) / HZO (1:1_6 nm) / Pt devices

[0117] In Example 1, a device was manufactured in the same manner as in Example 1, except that the Al2O3 layer was not formed.

[0118] Experimental Example 1: Energy Band Diagram of the Device

[0119] In order to draw an energy band diagram corresponding to the Sc / TiO2(17nm) / Al2O3(1nm) / HZO(1:1_6nm) / Pt device of Example 2, the Multi-Dielectric Energy Band Diagram Program from The Quantum DNA Research Group, Boise State University was used to draw an energy band diagram based on the values ​​described below.

[0120] The work function, electron affinity, and energy band gap of each material used typical values, and the permittivity was measured using a Wayne Kerr 4100 LCR meter under the conditions of -2~2 V / 0.2 V step / signal level 0.05 V / frequency 10 kHz.

[0121] - Work function of Sc: 3.5 eV, electron affinity of TiO2: 2.95 eV, energy band gap of TiO2: 3.5 eV, relative permittivity of TiO2: 30, electron affinity of Al2O3: 1.35 eV, energy band gap of Al2O3: 5.5 eV, relative permittivity of Al2O3: 9, electron affinity of HZO(1:1_6nm): 2.65 eV, energy band gap of HZO(1:1_6nm) 5.7 eV, relative permittivity of HZO(1:1_6nm) 30, work function of Pt: 5.6 eV.

[0122] FIG. 4 is an energy band diagram in the direction of the thickness of the device layer in a situation where voltage is applied to the upper electrode or the lower electrode of the device of Example 2. More specifically, part (a) of FIG. 4 is an energy band diagram showing a process in which a read operation occurs by applying -2 V to the upper electrode of the device of Example 2 in a high-resistance state. Part (b) of FIG. 4 is an energy band diagram showing a process in which a read operation occurs by applying -2 V to the upper electrode of the device of Example 2 in a low-resistance state. Part (c) of FIG. 4 is an energy band diagram showing a situation in which -2 V is applied to the lower electrode of the device of Example 2 in a low-resistance state.

[0123] Referring to parts (a) and (b) of Fig. 4, the device of Example 2 according to the present invention can have a high resistance state or a low resistance state depending on the polarization direction of the ferroelectric layer. Referring to part (b) of Fig. 4, in a device in a low resistance state in which the ferroelectric layer is polarized so that positive charges are formed at the interface in the direction of the upper electrode, it can be confirmed that a slope is formed in the energy bands of the second dielectric layer and the first dielectric layer due to the polarization state of the ferroelectric layer, thereby lowering the energy barrier in the direction from the upper electrode to the lower electrode. Referring to part (a) of Fig. 4, in a device in a high resistance state in which the ferroelectric layer is polarized so that positive charges are formed at the interface in the direction of the lower electrode, it can be confirmed that a slope is formed in the energy bands of the second dielectric layer and the first dielectric layer due to the polarization state of the ferroelectric layer, thereby raising the energy barrier in the direction from the upper electrode to the lower electrode.

[0124] Referring to part (c) of FIG. 4, it can be confirmed that the device of Example 2 according to the present invention has excellent self-rectification characteristics in that the Schottky barrier is low and current can flow well when a negative voltage is applied to the upper electrode, whereas the Schottky barrier is high and current cannot flow easily when a negative voltage is applied to the lower electrode.

[0125] Figure 5 is an energy band diagram showing the polarization direction of the ferroelectric layer being switched by applying -3 V to the device of Example 2.

[0126] Figure 6 is an energy band diagram showing the polarization direction of the ferroelectric layer being switched by applying +3 V to the device of Example 2.

[0127] Referring to FIGS. 5 and 6, it can be confirmed that the element can be switched to a low-resistance state or a high-resistance state by switching the polarization direction of the ferroelectric layer by applying a negative or positive write voltage that is larger than the resistive voltage corresponding to the resistive field.

[0128]

[0129] Experimental Example 2: Structural Analysis Using GIXRD

[0130] Grain boundary angle incidence X-ray diffraction (GIXRD) analysis was performed on the devices manufactured in Example 2 and Comparative Example 1. The kα line of a copper (Cu) X-ray source was used, and measurements were performed for 3 seconds at each step at an incidence angle of ω = 0.5°.

[0131] Fig. 7 is a diagram showing the results of GIXRD analysis for the devices of Example 2 and Comparative Example 1. Referring to Fig. 7, it was confirmed that the HfO2 layer included in the device of Comparative Example 1 had peaks corresponding to the non-ferroelectric monoclinic phase, which is a stable phase of HfO2, observed around 2O=28.5 and 2O=32. On the other hand, it was confirmed that the HZO layer included in the device of Example 2 had peaks corresponding to the orthorhombic phase, which exhibits ferroelectricity through ZrO2 doping, observed around 2O=30.5.

[0132]

[0133] Experimental Example 3: IV Curve Analysis of the Device

[0134] The IV curves for the devices of Example 1 and Comparative Examples 1 to 4 were obtained by DC sweep voltage measurement using the 4200-SMU module of the 4200a-scs semiconductor parameter analyzer from Keithley. For the device of Example 1, the sweep was performed 50 times in 0.2 V steps in the range of ±3.6 V, for the devices of Comparative Examples 1 and 2, the sweep was performed twice in 0.1 V steps in the range of ±4 V, and for the devices of Comparative Examples 3 and 4, the sweep was performed twice in 0.1 V steps in the range of ±2.8 V.

[0135] Figure 8 is a diagram showing an IV curve for the device of Example 1.

[0136] Referring to FIG. 8, it can be confirmed that the device of Example 1 according to the present invention does not have a change in the voltage value at which the resistance changes for each operation even after 50 repetitions of the cycle. That is, it was confirmed that the device of Example 1 exhibits very high reliability in terms of cycle-to-cycle variation. In addition, it can be confirmed that the device of Example 1 according to the present invention has a self-rectifying characteristic in which current does not flow well under the condition that a positive voltage is applied to the upper electrode, and has a nonlinear characteristic under the condition that a negative voltage is applied to the upper electrode, and has a high on-off ratio according to the polarization of the ferroelectric layer.

[0137] More specifically, the device of Example 1 has excellent self-rectification characteristics with a ratio of (current flowing in the device at -2 V) / (current flowing in the device at +2 V) of 49546, and nonlinear characteristics were confirmed with a ratio of (current flowing in the device at -2 V) / (current flowing in the device at -1 V) of 208. In addition, the on-off ratio, which is the ratio of (current flowing in the device when -2 V is applied to a device polarized by about -4 V) / (current flowing in the device when -2 V is applied to a device polarized by about +4 V), was calculated to be about 9840, confirming that the on-off ratio was high.

[0138] Figure 9 is a diagram showing IV curves for the devices of Comparative Example 1 (a), Comparative Example 2 (b), Comparative Example 3 (c), and Comparative Example 4 (c).

[0139] Referring to parts (a) and (b) of Fig. 9, the device of Comparative Example 1 in which HfO2 of the same thickness was formed instead of the ferroelectric layer including HZO, and the device of Comparative Example 2 in which the ferroelectric layer including HZO was not formed, did not exhibit a characteristic of resistance changing even when voltage was applied.

[0140] Referring to part (c) of Fig. 9, it was confirmed that, unlike the device of Example 1, which had excellent self-rectification characteristics due to the formation of a low Schottky barrier at the interface between the upper electrode and the TiO2 layer, the device of Comparative Example 3, which omitted the TiO2 layer, had a lower current density at negative voltage and significantly deteriorated self-rectification characteristics.

[0141] Referring to part (d) of Fig. 9, the device of Comparative Example 4, which omitted the Al2O3 layer, had an overall higher current density by omitting the Al2O3 layer that formed the highest energy barrier, but the resistance change characteristics and self-rectification characteristics were significantly deteriorated.

[0142] Experimental Example 4: Analysis of retention characteristics of devices

[0143] The retention characteristics of the device of Example 1 were analyzed. Using the 4225-PMU module in the 4200a-scs semiconductor parameter analyzer from Keithley, +4 V was applied to the upper electrode for the high resistance state (HRS) and -4 V was applied to the lower electrode for the low resistance state (LRS). After the retention time, a reading operation was performed at -2 V to obtain the resistance value.

[0144] A depolarizing electric field is applied to the ferroelectric layer polarized by a specific write voltage due to the difference in work functions of the upper and lower electrodes, which causes the device to experience a decrease in remanent polarization over time. Depolarization occurs until the decrease in the depolarizing electric field due to the decrease in remanent polarization of the ferroelectric layer becomes lower than the coercive electric field.

[0145] Fig. 10 is a diagram showing the preservation characteristics of the device of Example 1. Referring to Fig. 10, the device of Example 1 maintained an on-off ratio of 13 or more for more than 1000 seconds in a heated state of 80°C. Through extrapolation, it was confirmed that the device could maintain an on-off ratio of 10 or more for up to 10 years.

[0146]

[0147] Experimental Example 5: Memory Array Calculation

[0148] The device of Example 1 according to the present invention is connected to a 500 Ω pull-up resistor (R pull ) was applied to the crossbar array, the integrable array size was calculated. -2V was used as the read voltage (V r ) was set to floating (F), V r / 3 and V r Array size was calculated according to read margin within various read methods including / 2.

[0149] Part (a) of Fig. 11 is a schematic diagram of an N by M three-dimensional CBA structure and its equivalent circuit. Referring to part (a) of Fig. 11, the cell selected for reading and the half-selected cell connected to the word line and bit line are R, respectively. s1 and R s3 , and unselected cells are indicated by R s2In part (a) of Fig. 11, the current path passing through the selected cell and the sneak current path passing through the semi-selected and unselected cells are shown. The entire current path passing through the sneak current path can be represented by (M-1)(N-1) strings, where one string is (M-1)R s1 +R s2 +(N-1)R s3 is. Part (b) of Fig. 11 is a diagram showing a two-dimensional CBA with potentials induced in the read processes of F, Vr / 3, and Vr / 2, respectively. In Fig. 11 (b), cells to which reverse bias is applied are indicated by white dots, and the lower circuit diagram shows resistors composed of cells surrounded by dotted lines and selected cells (cells in the lower left corner) in the two-dimensional CBA in the read process. In the F method, the resistance of reverse bias is about 10 times higher than that of parallel selected cells. 3 Because the boat is high, the current flowing through the sneak current can be suppressed. In the case of the Vr / 3 method, R s1 and R s3 can be lowered, but if the Vr drop is lowered, R s2 can be lowered. In the Vr / 2 method, R s2 Since the voltage drop is 0, only the semi-selected cells induce sneak current. Fig. 12 is a diagram showing the current values ​​read when the floating, Vr / 2, and Vr / 3 reading methods are applied to the device of Example 1, respectively.

[0150] The read margin is the pull-up voltage (V pull ) normalized output voltage (V out ) is defined as follows. Assuming an N x N square CBA, the read margin can be calculated as shown in the following mathematical expression 2.

[0151] [Equation 2]

[0152]

[0153] In the above mathematical expression 2, R pull is the pull-up resistor, and Rs1 is the resistance of each cell that shares a word line with the selected cell, and R s3 is the resistance of each cell that shares a bitline with the selected cell, and R s2 is the resistance of each cell that does not share a line with the selected cell, and R LRS is the low resistance state resistance value of the cell (element) to be read, and R HRS is the high resistance state resistance of the cell, and V out(LRS) is the surrounding R s1 , R s2 and R s3 V in the absence of out Voltage is △V out is the difference in output voltage.

[0154] Fig. 13 is a diagram showing the CBA array size according to the read margin (%) when applying the element (a) of Example 1 and the element (b) of Comparative Example 3 to an array of an N by N CBA structure.

[0155] Referring to Fig. 13, when the read margin is set to 10%, the CBA array using the element of Example 1 according to the present invention has a read margin of 10% for the Vr / 3 read method. 3 It could have an array size of 10 or more, and for floating read mode, 4 It was confirmed that the array size above can be achieved, and that high integration is possible compared to the device of Comparative Example 3.

[0156] Experimental Example 6: Application to Neuromorphic Computing

[0157] In order to evaluate the possibility of using the device according to the present invention as a neuromorphic computing synapse device, a simulation was conducted, and specifically, the simulation was conducted using the 4225-PMU module of the 4200a-scs semiconductor parameter analyzer of Keithley and the CrossSim simulator of Andia National Lab.

[0158] Part (a) of Fig. 14 is a diagram showing a voltage pulse applied to the device of Example 1 to record multi-level resistance, and part (b) of Fig. 14 is a diagram showing the electrical conductivity of the device measured through the voltage pulse.

[0159] Referring to parts (a) and (b) of Fig. 14, it can be confirmed that the device of Example 1 can store a multi-level resistance state rather than two states of 0 and 1 by pulses with different voltage strengths.

[0160] The above pulse application and electrical conductivity measurement were repeated three times to represent the cumulative distribution function, and based on this, a neural network was constructed and trained to infer handwritten digits from 0 to 9 from the MNIST (modified National Institute of Standards and Technology) database. The neural network consisted of 754 input neurons, 300 hidden neurons, and 10 output neurons. The input neurons and hidden neurons utilized the sigmoid function, and the output neurons used softmax.

[0161] Figure 15 is a cumulative distribution function for the electrical conductivity of the device of Example 1, and Figure 16 is a diagram showing the results of constructing and training a neural network that infers handwritten digits from 0 to 9 of the MNIST database based on the cumulative distribution function for the device of Example 1.

[0162] Referring to Fig. 15 and Fig. 16, comparing the case where the connection of each neuron is configured as an ideal memory-like synaptic element (ideal) and the case where the device of the present invention is utilized (Exp. data), the ideal case showed an accuracy of approximately 97%, and when the device of the present invention was applied as a synaptic element, it also showed a high accuracy of 94%. These results suggest that the device of the present invention can show high accuracy while solving the energy consumption problem of existing volatile memory devices or the speed problem that occurs when using non-volatile NAND.

[0163] Example 3: Fabrication of a 9 by 9 crossbar array

[0164] The surface was treated by applying hexamethyldisilazane (HMDS) to the Si substrate using a spin coater at 1500 rpm for 10 s. Photoresist (product name: AZ5214) was applied onto the surface-treated Si substrate using a spin coater sequentially at 500 rpm for 5 s, 3000 rpm for 40 s, and 500 rpm for 5 s. Then, a soft bake was performed at 120°C for 2 minutes, and then lower patterning was performed at 385 mW for 5.8 s using a maskless patterning system. After a post-exposure bake (PEB) at 120°C for 2 minutes, an additional exposure was performed at 385 mW for 58 s. Finally, a development process was performed to pattern the Si substrate.

[0165] After Pt was deposited on a patterned Si substrate using an ion sputter coater, a lift-off process was performed using acetone. Thereafter, HZO / Al₂O₃ was deposited in the same manner as in Example 1, and TiO₂ was deposited after RTP (rapid thermal processing).

[0166] As described above, after depositing the ferroelectric layer (HZO), the first dielectric layer (Al2O3), and the second dielectric layer (TiO2), AZ5214 photoresist was applied, and then the upper electrode patterning was performed in the same order as above. Thereafter, TiN was deposited by RF sputtering in the same manner as in Example 1, and lift-off was completed using acetone to complete the crossbar array (CBA).

[0167] Fig. 17 is a plane-view image of the CBA manufactured in Example 3. Fig. 18 is a diagram showing the IV curves of Cell (i) and Cell (ii) shown in Fig. 17 among the CBAs manufactured in Example 3. When measuring using Keithley's 4200A-SCS and 4200-SMU modules, the IV curves of Cell (i), the closest cell to where the power supply module applies voltage, and Cell (ii), the farthest cell, were compared, and it was confirmed that the difference in resistance of the electrode line depending on the cell location was negligible.

[0168] Figure 19 shows the results of measuring the multiple resistance values ​​of cells in the entire CBA fabricated in Example 3. A write operation was performed by applying a voltage between -3 V and -3.8 V, and a read operation was performed at -2 V. The current of each state is represented as a cumulative distribution function in Figure 20, and this result shows that a 3-bit state can be stored in one cell, and each state is well distinguished without state interference in a 9x9 cell.

[0169] Although the present invention has been described above through limited embodiments, the present invention is not limited thereto, and it is obvious that various modifications and variations are possible within the scope of the technical idea of ​​the present invention and the equivalent scope of the patent claims to be described below by a person having ordinary skill in the art to which the present invention pertains.

[0170] [Explanation of symbols]

[0171] 100: Ferroelectric tunnel junction device

[0172] 10: Lower electrode

[0173] 20: Ferroelectric layer

[0174] 30: First genetic layer

[0175] 40: Second genetic layer

[0176] 50: Upper electrode

Claims

1. Lower electrode; A ferroelectric layer positioned on the lower electrode and containing a ferroelectric; It is located on the above ferroelectric layer and has an energy band gap (E) greater than that of the ferroelectric. g ) a first genetic layer containing a large first genetic material; It is located on the first dielectric layer and has an energy band gap (E) greater than that of the ferroelectric. g ) a second dielectric layer comprising a small second dielectric; and A ferroelectric tunnel junction (FTJ) device comprising an upper electrode positioned on the second dielectric layer and satisfying the following mathematical expression 1: [Mathematical Formula 1] In the above mathematical expression 1, χ FE is the electron affinity of the ferroelectric, χ2 is the electron affinity of the second dielectric, and φ BE is the work function of the lower electrode, and φ TE is the work function of the upper electrode.

2. In claim 1, The above ferroelectric is a ferroelectric tunnel junction element represented by the following chemical formula 1: [Chemical Formula 1] Hf 1-x M x O2 In the above chemical formula 1, M is at least one of Zr, Si, Al, Y, Sr, La, and Gd, and x is 0.01 or more and 0.99 or less.

3. In claim 1, The above ferroelectric is a ferroelectric tunnel junction element represented by the following chemical formula 2: [Chemical Formula 2] Hf 1-x Zr x O2 In the above chemical formula 2, x is 0.4 or more and 0.6 or less.

4. In claim 1, The above lower electrode is Pt, Ir, Mo2N, MoO x , RuO x and IrO x A ferroelectric tunnel junction device comprising at least one member selected from the group consisting of:

5. In claim 1, A ferroelectric tunnel junction device wherein the upper electrode comprises at least one selected from the group consisting of Sc, TaN, Ta, W, Ti, Mo, and TiN.

6. In claim 1, A ferroelectric tunnel junction device wherein the first dielectric comprises at least one selected from the group consisting of Al2O3 and SiO2.

7. In claim 1, A ferroelectric tunnel junction device wherein the second dielectric comprises at least one selected from the group consisting of TiO2, MoO3, WO3, and Ta2O5.

8. In claim 1, A ferroelectric tunnel junction device wherein the thickness of the ferroelectric layer is 0.5 to 10 nm.

9. In claim 1, A ferroelectric tunnel junction device, wherein the thickness of the first dielectric layer is 0.1 to 5 nm.

10. In claim 1, A ferroelectric tunnel junction device wherein the thickness of the second dielectric layer is 5 to 30 nm.

11. In claim 1, The above ferroelectric tunnel junction device is a ferroelectric tunnel junction device having a self-rectifying characteristic in which a current flowing from the lower electrode toward the upper electrode is suppressed.

12. A memory device comprising a ferroelectric tunnel junction element according to claim 1.

13. In claim 12, A memory device having a crossbar array structure including a plurality of ferroelectric tunnel junction elements.

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