Circuit, power module unit and motor control circuit with voltage monitoring unit

Abstract

A circuit (300) includes a power semiconductor device (310) and a current mirror circuit (320). The power semiconductor device (310) is located in a switched current path (315) between a switching node (620) and a reference potential. The current mirror circuit (320) includes a first transistor (Q1) and a second transistor (Q2) and mirrors a reference current IRef through the first transistor (Q1) by controlling an output current Iout through the second transistor (Q2). The first transistor (Q1) is outside the switched current path (315) and is electrically connected in series with the power semiconductor device (310) in a first current path (100). The second transistor (Q2) is located in a second current path (200). The first current path (100) and the second current path (200) are electrically connected in parallel.

Description

TECHNICAL AREA

[0001] The present disclosure relates to a circuit for voltage monitoring of power semiconductor devices. The circuit can be combined with or integrated into a power module unit or a motor control circuit. BACKGROUND

[0002] The resilience of technical systems is of paramount importance. Real-time monitoring techniques capable of tracking the status of power semiconductor devices enable the sending of an early warning signal before a catastrophic system failure occurs and / or can be used for failure prediction. For some power semiconductor devices, the voltage drop across the device when powered on provides information about its health / aging state. There is a continuing need to perform reliable voltage measurements in circuits containing power semiconductor devices during operation with minimal effort.

[0003] US 7,436,160 B2 discloses a circuit for detecting a high-voltage offset. The circuit senses the midpoint voltage of a switching half-bridge and can determine when the midpoint voltage reaches a specific value to prevent hard switching in the half-bridge switches. The midpoint voltage of the switching half-bridge is applied via a buffer to a current-limited MOSFET, which generates a voltage equal to the midpoint voltage of the switching half-bridge. The voltage generated by the MOSFET can be fed to a comparator with a threshold input to obtain a signal indicating when the switches of the switching half-bridge can be turned on to prevent hard switching.An adaptive dead-time circuit and method can comprise the sensor circuit described above, a first circuit for generating a first signal indicating a transition of the medium voltage from high to low, and an output circuit for generating an adaptive dead-time output signal based thereon. A second circuit can generate a second signal indicating a transition of the voltage from low to high; the output circuit generating the adaptive dead-time output signal based on both the first and second signals. The second circuit preferably generates the second signal by reproducing the first signal.The first circuit can generate the first signal by charging a capacitor in response to pulses, and the second circuit can generate the second signal by charging a second capacitor equivalent to the first, and the adaptive dead-time output signal can respond to the charges of the first and second capacitors. SUMMARY

[0004] A circuit includes a power semiconductor device and a current mirror circuit. The power semiconductor device is located in a switched current path between a switching node and a reference potential. The current mirror circuit includes a first transistor and a second transistor and mirrors a reference current Iref through the first transistor by controlling an output current Iout through the second transistor. The first transistor is outside the switched current path and is electrically connected in series with the power semiconductor device in a first current path. The second transistor is located in a second current path. The first and second current paths are electrically connected in parallel.

[0005] The current mirror circuit allows the voltage drop across the power semiconductor device to be mapped to a voltage drop, or a combination of voltage drops, across elements in the first and second current paths. The monitored voltages can be kept free from the high switching voltages handled by the power semiconductor device. Voltage monitoring can be performed without shunts in the circuit at the low voltages typical of logic circuits.

[0006] A compensation pn junction is used to map a voltage drop across the power semiconductor device to a voltage drop across one of the elements in the second current path. The second current path can be kept free of the high switching voltages handled by the power semiconductor device. The voltage across the power semiconductor device can be monitored by observing a single voltage in the low-voltage domain.

[0007] The expert will recognize additional features and advantages by reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are provided for a further understanding of the embodiments and form an integral part of this description. The drawings illustrate embodiments of a circuit, a power module unit, and a motor control circuit and, together with the description, explain the principles underlying the embodiments. Further embodiments are described in detail below and in the claims. Features of the different embodiments can be combined. Fig. Figure 1 is a circuit diagram of a current mirror circuit based on two npn bipolar junction transistors, to discuss background that is useful for understanding the embodiments. Fig. Figure 2 is a circuit diagram of a current mirror circuit based on two pnp bipolar junction transistors, to discuss background information useful for understanding the embodiments. Fig. Figure 3 is a circuit diagram of a circuit with a power semiconductor device and a current mirror circuit based on two npn bipolar transition transistors, according to one embodiment. Fig. Figure 4 is a circuit diagram of a circuit with a power semiconductor device and a current mirror circuit based on two npn bipolar transition transistors and high-voltage diodes, according to one embodiment. Fig. Figure 5 is a circuit diagram of a circuit with a power semiconductor device and a current mirror circuit based on two pnp bipolar transition transistors and high-voltage diodes, according to one embodiment. Fig. Figure 6 is a circuit diagram of a circuit with a power semiconductor device and a current mirror circuit based on two npn bipolar junction transistors and with a compensation pn junction, according to one embodiment. Fig. Figure 7 is a circuit diagram of a circuit comprising a power semiconductor device and a current mirror circuit based on two n-channel field-effect transistors (FETs) and a compensation FET, according to one embodiment. Fig. Figure 8 is a circuit diagram of a circuit with a power semiconductor device and a current mirror circuit based on two pnp bipolar junction transistors and a compensation pn junction, according to one embodiment. Fig. Figure 9 is a circuit diagram of a circuit with a power semiconductor device and a current mirror circuit based on two p-channel FETs and a compensation FET, according to one embodiment. Fig. Figure 10 is a simplified circuit diagram of a power module unit comprising a circuit with a power semiconductor device, a current mirror circuit based on two npn bipolar transition transistors, and a voltage monitoring unit according to an embodiment relating to a measurement via a transistor load path in an output branch of the current mirror circuit. Fig. Figure 11 is a simplified circuit diagram of a motor control circuit comprising a circuit with a power semiconductor device, a current mirror circuit based on two npn bipolar junction transistors, and a voltage monitoring unit according to an embodiment which includes a measurement via a compensation pn junction in an output branch of the current mirror circuit. Fig. Figure 12 is a schematic diagram of a multi-device housing integrating three transistors, according to one embodiment. Fig. Figure 13 is a schematic diagram of a multi-diode package integrating two matching diodes, according to one embodiment. Fig. Figure 14 is a simplified circuit diagram of an integrated gate driver support circuit according to one embodiment. DETAILED DESCRIPTION

[0009] The following detailed description refers to the accompanying drawings, which form part of this document and in which certain embodiments of a circuit, a power module unit, and a motor control circuit are shown for illustration. Structural or logical modifications may be made to the illustrated embodiments without altering the scope of protection of this disclosure. For example, features shown or described for one embodiment may be used in or in combination with other embodiments, resulting in a different embodiment. This disclosure is intended to include such modifications and variations. The embodiments are described in a manner that should not be construed as limiting the scope of protection of the appended claims.The drawings are not to scale and are for illustrative purposes only. Corresponding elements are designated with the same reference symbols in the various drawings, unless otherwise indicated.

[0010] The terms "have," "contain," "include," "contain," and the like are open-ended and indicate the presence of certain structures, elements, or features, but do not exclude the presence of additional elements or features. The articles "a," "an," and "the" include both the plural and the singular unless the context clearly indicates otherwise.

[0011] The term "directly electrically connected" can describe a permanent low-resistance ohmic connection between the directly electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or heavily doped semiconductor material.

[0012] The terms "signal-linked" and "electrically coupled" can refer to a permanent, low-resistance ohmic connection between electrically connected elements, such as direct contact between the elements in question or a low-resistance connection via a metal and / or heavily doped semiconductor material. However, they do not preclude the presence of other passive and / or active elements in the signal path between the "signal-linked" or "electrically coupled" elements. These other elements may include, for example, resistors, ohmic conductors, capacitors and / or inductors, transistors, semiconductor diodes, Schottky diodes, transformers, optocouplers, and others.

[0013] The term "power semiconductor device" refers to semiconductor devices with a voltage blocking capability of at least 30 V, for example 48 V, 100 V, 600 V, 1.6 kV, 3.3 kV or more, and with a rated one-state current or forward current of at least 200 mA, for example 1 A, 10 A or more.

[0014] The present disclosure relates to a circuit that may include a power semiconductor device and a current mirror circuit. The power semiconductor device is located in a switched current path between a switching node and a reference potential. The current mirror circuit may include a first transistor and a second transistor and may copy a reference current IRef through the first transistor by controlling an output current Iout through the second transistor. The first transistor may be located outside the switched current path and electrically connected in series with the power semiconductor device in a first current path. The second transistor may be located in a second current path. The first and second current paths may be electrically connected in parallel.

[0015] The power semiconductor device can be, for example, a field-effect transistor (FET), e.g., an insulated-gate field-effect transistor (IGFET), such as a silicon metal oxide semiconductor FET (Si-MOSFET) or a silicon carbide metal oxide semiconductor FET (SiC-MOSFET), a high electron mobility transistor (HEMT), or an insulated-gate bipolar transistor (IGBT).

[0016] The potential of the switching node can change between a high potential and a low potential. For example, the switching node can be the switching node of a half-bridge, which includes a high-side switch and a low-side switch connected in series between a high potential and the reference potential GND.

[0017] The controlled load path between the load terminals of the power semiconductor device is electrically connected between the switching node and the reference potential. The controlled load path can be the emitter-collector path of an IGBT or the source-drain path of a FET or HEMT. Apart from parasitic elements, the controlled load path of the power semiconductor device can be the only component in the switched current path. A first load terminal, such as the collector of an IGBT or the drain of a FET, can be directly connected to the switching node, and the emitter of the IGBT or the source of the FET can be directly connected to the reference potential.

[0018] A controlled load path of the first transistor of the current mirror circuit is electrically connected in series with the controlled load path of the power semiconductor device and outside the switched current path. In the on-state of the power semiconductor device, the total current flowing through the controlled load path of the power semiconductor device includes a switching current Isw, which flows between the switching node and the reference potential, and the reference current Iref.

[0019] The first and second transistors can be a matched transistor pair with identical nominal characteristics and absolute maximum values, and can be arranged such that no junction temperature difference or only a marginal junction temperature difference develops between the first and second transistors. Then, an output current Iout through the controlled load path of the second transistor matches the reference current Iref through the controlled load path of the first transistor in the current mirror.

[0020] When the power semiconductor device is switched on, the total current through the power semiconductor device generates a voltage drop Vdrop across the controlled load path of the power semiconductor device. Since the total voltage drop in the loop of the first current path is equal to the total voltage drop in the loop of the parallel second current path, the voltage drop Vdrop causes the voltages across active devices in the second current path. From one or more voltage measurements across active devices in the second current path, a conclusion about the voltage drop Vdrop can be drawn.

[0021] According to one embodiment, the circuit may further include a voltage monitoring unit configured to monitor a voltage in the second current path.

[0022] The voltage monitoring unit can include a comparator that compares a voltage received from the second current path with one or more threshold voltages. Alternatively, the voltage monitoring unit can include an analog-to-digital converter that converts the voltage in the second current path into a digital voltage value.

[0023] Voltages can be tapped from more than two nodes of the first and / or second current path, with the voltage monitoring unit potentially including a voltage subtraction circuit for combining more than one tapped voltage. Alternatively, one or two voltages can be tapped from the second current path and routed directly to the voltage monitoring unit. The voltage to be monitored can be tapped from terminals of the second transistor. The voltage monitoring unit can be a separate circuit or can be integrated into an integrated gate driver circuit or an integrated motor control circuit.

[0024] According to one embodiment, the circuit can further include a compensation pn junction, wherein the compensation pn junction and the second transistor in the second current path are electrically connected in series.

[0025] The compensation pn junction is electrically connected in series with the controlled load path of the second transistor. The cathode sides of the compensation pn junction and the second transistor can be directly electrically connected.

[0026] If the forward characteristics of the compensating pn junction and the corresponding characteristics of the second transistor in the current mirror circuit are sufficiently similar, the forward voltage drop across the compensating pn junction can be nearly identical to a voltage drop between the base and emitter or between the gate and source of the second transistor. A single voltage measurement in the second current path may be sufficient to determine the voltage drop.

[0027] According to one embodiment, the compensation pn junction can include an auxiliary transistor in a diode configuration, wherein a base-emitter junction or a body-source junction of the auxiliary transistor and the second transistor are electrically connected in series.

[0028] A transistor in a diode configuration is diode-connected. A diode-connected transistor is created by directly connecting the base and collector of a BJT or the gate and drain of an IGFET.

[0029] The first transistor, the second transistor, and the auxiliary transistor can be matched transistors with identical or nearly identical nominal characteristics and absolute maximum values, and can be arranged such that no junction temperature difference, or nearly no junction temperature difference, can develop between the first transistor, the second transistor, and the auxiliary transistor. Then, the base-emitter voltage of the auxiliary transistor and the base-emitter voltage of the second transistor (bipolar junction transistor, BJT type), or the gate-source voltage of the auxiliary transistor and the gate-source voltage of the second transistor (field-effect transistor with insulated gate), are always sufficiently similar that the voltage drop Vdrop can be obtained from a single voltage measurement in the second current path.

[0030] According to one embodiment, the compensation pn junction, the first transistor and the second transistor can be integrated in a multi-device package.

[0031] Integrating the first transistor, the second transistor, and the auxiliary transistor into a single package can reduce differences in junction temperatures between the first transistor, the second transistor, and the auxiliary transistor.

[0032] According to one embodiment, the circuit may further include a power supply circuit configured to provide an auxiliary supply voltage via the first current path and the second current path.

[0033] The power supply circuit can be a dedicated circuit with the sole purpose of providing auxiliary supply voltage for the first and second current paths of the circuit. Alternatively, the power supply circuit can be a power supply circuit used to power other circuits, such as logic circuits integrated into integrated gate driver circuits and / or integrated motor control circuits.

[0034] According to one embodiment, the first current path can include further first electrical elements and the second current path can include further second electrical elements, wherein for a predefined current a first voltage drop across the first electrical elements and a second voltage drop across the second electrical elements can be equal or nearly equal.

[0035] The additional first and second electrical elements can include resistors, diodes, and / or further transistors. Each additional first electrical element can have a corresponding additional second electrical element. The first voltage drop is the total voltage drop across all additional first electrical elements. The second voltage drop is the total voltage drop across all additional second electrical elements. For any current within a current range of interest, any voltage drop across one of the additional first elements can be equal to or nearly equal to the voltage drop across the corresponding additional second element.

[0036] If, for every current within the current range of interest, a current produces the same voltage drop across symmetrical elements in the first and second current paths, the voltage monitored in the second current path can be a linear function or even an identity function of the voltage drop across the power semiconductor switch in the on state.

[0037] According to one embodiment, an ohmic resistance in the first current path and an ohmic resistance in the second current path differ from each other by no more than 5% of an average value of the ohmic resistances.

[0038] For example, the ohmic resistance in the first current path and the ohmic resistance in the second current path differ from each other by no more than 2% or 1% of an average value of the ohmic resistances.

[0039] The smaller the difference between the ohmic resistance in the first current path and an ohmic resistance in the second current path, the simpler the relationship between the voltage monitored in the second current path and the voltage drop Vdrop.

[0040] According to one embodiment, the circuit may further include a first diode in the first current path and a second diode in the second current path, wherein the first diode is configured to block a reverse voltage across the power semiconductor device in an off state of the power semiconductor device, wherein the first diode and the second diode are forward-biased when the power semiconductor device is in an on state, and wherein the first diode and the second diode have identical nominal characteristics.

[0041] The smaller the difference between the forward voltages between the first diode and the second diode at the same current, the simpler the relationship between the voltage monitored in the second current path and the voltage drop Vdrop.

[0042] According to one embodiment, the first diode and the second diode can be integrated in a multi-diode package.

[0043] Integrating the first and second diodes into a single package can reduce differences in their junction temperatures. The less the difference in forward voltages between the first and second diodes depends on temperature, the better the voltage drop (Vdrop) can be approximated by a single voltage monitored in the second current path. The first and second diodes can be individual diode devices selected from the same batch and / or such that the measured diode parameters match better than 50% of any pair of diode devices with the same nominal characteristics. Alternatively, the first and second diodes can be formed on the same semiconductor chip.

[0044] According to one embodiment, the first transistor, the second transistor, the first diode, the second diode, the further first electrical elements and the further second electrical elements are integrated in a multi-device housing.

[0045] For example, an integrated gate driver support circuit can integrate the first transistor, the second transistor, the first diode, the second diode, the remaining first electrical elements, and the remaining second electrical elements. Alternatively, the first transistor, the second transistor, the first diode, the second diode, the remaining first electrical elements, and the remaining second electrical elements can be integrated into a gate driver circuit or a motor control circuit.

[0046] According to one embodiment, the first transistor and the second transistor can include bipolar transition transistors, and an emitter of the first transistor and an emitter of the second transistor can be directly electrically connected.

[0047] According to another embodiment, the first transistor and the second transistor can include field-effect transistors, and a source of the first transistor and a source of the second transistor can be directly electrically connected.

[0048] According to one embodiment, the first transistor and the second transistor can include p-channel field-effect transistors, or the first transistor and the second transistor can include pnp-bipolar junction transistors.

[0049] According to one embodiment, the circuit may further include a voltage monitoring unit configured to monitor a voltage across the second transistor.

[0050] According to another embodiment, the first transistor and the second transistor include n-channel field-effect transistors, or the first transistor and the second transistor include npn-bipolar junction transistors.

[0051] According to one embodiment, the circuit may further include a voltage monitoring unit, electrically connected to load electrodes of the second transistor and configured to monitor a voltage across the second transistor.

[0052] According to one embodiment, the circuit may further include a voltage monitoring unit configured to monitor a voltage between an anode side of the compensation pn junction and a network node of the first current path between the power semiconductor device and the first transistor.

[0053] Another embodiment of the present disclosure relates to a power module unit. The power module unit can include a circuit as described above and a gate driver circuit. The gate driver circuit can drive a gate signal to a gate of the power semiconductor device. The gate driver circuit and the voltage monitoring unit can be integrated in an integrated gate driver circuit.

[0054] Another embodiment of the present disclosure relates to a motor control circuit. The motor control circuit can include a circuit as described above and a motor controller driving an H-bridge, which includes the power semiconductor device of the circuit, wherein the motor controller and the voltage monitoring unit are integrated in an integrated motor control circuit.

[0055] Another embodiment of the present disclosure relates to an integrated gate driver support circuit. The integrated gate driver support circuit may include a current mirror circuit comprising a first transistor and a second transistor, configured to copy a reference current Iref through the first transistor by controlling an output current Iout through the second transistor. The first transistor is electrically connected between a sensing terminal SNS and a reference terminal REF. A first diode may be electrically connected between a supply terminal V+ and a driver terminal DRV, with a cathode of the first diode facing the driver terminal DRV.A second diode can be electrically connected in series with the second transistor between the supply terminal V+ and the reference terminal REF, with one anode of the second diode facing the supply terminal V+. The first and second diodes can have identical nominal characteristics.

[0056] Fig. Figure 1 shows a current mirror circuit 320 comprising a first transistor Q1 and a second transistor Q2, where the first and second transistors Q1 and Q2 are npn-bipolar junction transistors. A resistor R and a load path of the first transistor Q1 between collector and emitter are electrically connected in series in a first current path 100 between an auxiliary supply voltage VCC and a reference potential GND. A load path of the second transistor Q2 between collector and emitter is connected in a second current path 200 between the auxiliary supply voltage VCC and the reference potential. The emitter of the first transistor Q1 and the emitter of the second transistor Q2 are directly connected to each other and to the reference potential GND. A DC current gain β Q1 of the first transistor Q1 is the ratio between the collector current I c_Q1 and the base current I b_Q1 of the first transistor Q1 (Eq. (1)). A DC current gain βQ2 of the second transistor Q2 is the ratio between the collector current I c_Q2 and the base current I b_Q2 of the second transistor Q2 (Eq.(2)): βQ1=Ic_Q1Ib_Q1 βQ2=Ic_Q2Ib_Q2

[0057] The first and second transistors Q1 and Q2 are a matched pair of transistors, e.g., a differential pair. The nominal characteristics include the DC gain β. Q1 of the first transistor Q1 and the DC gain β Q2 of the second transistor are identical (Eq.(3)): βQ1=βQ2=β

[0058] In the current mirror circuit 320, the base-emitter voltage V be_Q1 of the first transistor Q1 and the base-emitter voltage V be_Q2 of the second transistor Q2 equal to (Eq.(5)), so that the base current I b_Q1 of the first transistor Q1 and the base current I b_Q2 of the second transistor Q2 are equal (Eq.(4)): Ib_Q1=Ib_Q2=Ib Vbe_Q1=Vbe_Q2=Vbe

[0059] As in Eq. (6), with a DC gain β » 1, a reference current Iref through the resistance R in the first current path 100 is almost equal to the collector current I. c_Q1 of the first transistor Q1 and the collector current I c_Q2 of the second transistor Q2. The collector current I c_Q2 The output current Iout of the second transistor Q2 is equal to the output current Iout of the current mirror circuit 320 in the second current path: Iref~Ic_Q1=Ic_Q2=Iout

[0060] The reference current Iref, which flows through the first current path 100, generates the base-emitter voltage V be_Q1 between the base and emitter of the first transistor Q1. The second base-emitter voltage V be_Q2 The voltage between the base and emitter of the second transistor Q2 adjusts to the first base-emitter voltage V. be_Q1Since the characteristics of the first and second transistors Q1, Q2 are identical, the output current lout, driven by the second transistor Q2 in the second current path 200, is equal to the reference current Iref, assuming that the DC current gain β of both transistors Q1, Q2 is significantly greater than 1.

[0061] In the current mirror circuit 320 of Fig. In the second transistor, Q1 and Q2 are PNP bipolar junction transistors. A load path of Q1, between its emitter and collector, and a resistor R are connected in series in a first current path (100 Ω) between an auxiliary supply voltage VCC and a reference potential GND. A load path of Q2, between its emitter and collector, is connected in a second current path (200 Ω) between an auxiliary supply voltage VCC and a reference potential GND. The emitters of Q1 and Q2 are directly connected to each other and to the auxiliary supply voltage VCC. The DC current gain β Q1 of the first transistor Q1 and the DC gain β Q2 The second transistor Q2 is defined by the equations Eq.(1), Eq. (2) above.

[0062] The first and second transistors Q1 and Q2 are a matched pair of transistors, e.g., a differential pair. The nominal characteristics include the DC gain β. Q1 of the first transistor Q1 and the DC gain β Q2 The values ​​of the second transistor are identical, as shown in equation (3) above.

[0063] The base-emitter voltage V be_Q1 of the first transistor Q1 and the base-emitter voltage V be_Q2 of the second transistor Q2 are equal and the base current I b_Q1 of the first transistor Q1 and the base current I b_Q2 The values ​​of the second transistor Q2 are the same as given by equations Eq.(4) and Eq.(5).

[0064] With the DC gain β » 1, a reference current Iref through the resistor R in the first current path 100 approaches the collector current I. c_Q1 of the first transistor Q1 and the collector current I c_Q2of the second transistor Q2. The collector current I c_Q2 The output current Iout of the second transistor Q2 is equal to the output current Iout of the current mirror circuit 320 in the second current path 200, as specified in equation Eq.(6).

[0065] The reference current Iref, which flows through the first current path 100, generates the base-emitter voltage V be_Q1 between the base and emitter of the first transistor Q1. The second base-emitter voltage V be_Q2 The voltage between the base and emitter of the second transistor Q2 adjusts to the first base-emitter voltage V. be_Q1 Since the characteristics of the first and second transistors Q1, Q2 are approximately identical, the output current lout driven by the second transistor Q2 in the second current path 200 is approximately equal to the reference current Iref, assuming that the DC gain β of the first and second transistors Q1, Q2 is significantly greater than 1.

[0066] Fig. Figure 3 shows a circuit 300 with a power semiconductor device 310 and a current mirror circuit 320. The power semiconductor device 310 is an IGBT operating as a low-side switch in a half-bridge 600. In an on-state, the power semiconductor device 310 conducts a switching current Isw, which flows in a switched current path between a switching node 620 of the half-bridge 600 and a switching reference potential AGND.

[0067] The current mirror circuit 320 includes a first transistor Q1 and a second transistor Q2. The power semiconductor device 310, the first transistor Q1 and first additional elements 190, which provide a first additional voltage V p1The first current path 100 is electrically connected in series between the auxiliary supply voltage VCC and a logic reference potential VEE. The second transistor Q2 and second further elements 290, which generate a second additional voltage V p2 The currents generated are connected in series in a second current path 200 between an auxiliary supply voltage VCC and the logic reference potential VEE. The first current path 100 and the second current path 200 are connected in parallel. The switching current Isw and a reference current Iref flowing through the first transistor Q1 generate a voltage drop V. drop above the power semiconductor device 310. A total voltage drop in the first current path 100 is equal to the total voltage drop in the second current path 200 (Eq. (7)): Vp1+Vdrop+Vbe_Q1=Vp2+Vce_Q2

[0068] The current mirror circuit 320 replicates a reference current Iref flowing through the first transistor Q1 and the power semiconductor device 310 by controlling an output current Iout through the second transistor Q2. The first additional elements 190 in the first current path 100 and the second additional elements 290 in the second current path 200 are provided symmetrically, such that the first additional voltage V p1 , which is caused by the reference current Iref in the first current path 100, and the second additional voltage V p2 , which are generated by the output current Iout in the second current path 200, are identical. Equation (7) simplifies to equation (8): Vdrop+Vbe_Q1=Vce_Q2 Vdrop=Vce_Q2−Vbe_Q1=Vce_Q2−VbeQ2

[0069] The voltage drop V drop The voltage above the power semiconductor device 310 can be determined by subtracting the base-emitter voltage V. be_Q2from the collector-emitter voltage V ce_Q2 can be obtained (Eq. (9)). For example, the collector-emitter voltage V can be ce_Q2 and the base-emitter voltage V be_Q2 a voltage monitoring unit which includes a voltage subtraction circuit, wherein the voltage subtraction circuit generates an output voltage proportional to the voltage difference of two input signals applied to the inputs of the inverting and non-inverting terminals of an operational amplifier.

[0070] In the illustrated example, a first voltage monitoring unit 381 is electrically connected between the collector and the emitter of the second transistor Q2, and a second voltage monitoring unit 382 is electrically connected between the base and the emitter of the second transistor Q2.

[0071] Fig. Figure 4 shows a circuit 300 with the first additional elements in the first current path, which include a first diode 130 and a first resistor 140, and the second additional elements in the second current path 200, which include a second diode 230 and a second resistor 240.

[0072] The first resistor 140 can include the entire ohmic resistance in the first current path 100 and can include the wiring resistance and / or one or more discrete resistors. The second resistor 240 can include the entire ohmic resistance in the second current path 200 and can include the wiring resistance in the second current path 200 and / or one or more discrete resistors. The first resistor 140 and the second resistor 240 have the same resistance, or the resistances of the first resistor 140 and the second resistor 240 differ from each other by no more than 5%, e.g., by no more than 2% or 1% of the average value of the two resistances. Since the reference current Iref through the first resistor 140 and the output current Iout through the second resistor 240 are equal, the voltages V R1 above the first resistance 140 and the V R2 above the second resistor 240 equal (Eq.(10)): VR1=VR2=VR

[0073] The first current path 100 includes a first diode 130, and the second current path 200 includes a second diode 230. The first diode 130 is electrically connected between the auxiliary supply voltage VCC and the power semiconductor device 310 and blocks a reverse voltage across the power semiconductor device 310 when the power semiconductor device 310 is off. The first diode 130 and the second diode 230 are forward-biased when the power semiconductor device 310 is on.

[0074] The first diode 130 and the second diode 230 can have the same type and nominal characteristics and can show the same or nearly the same dependencies of the forward voltage on the forward current, so that at least in a region of interest for the reference current Iref and the output current Iout the diode forward voltage V D1above the first diode 130 and the diode forward voltage V D2 across the second diode 230 are equal if the reference current Iref in the first current path is 100 and the output current Iout in the second current path is 200 (Eq.(11)): VD1=VD2=VD

[0075] The total voltage drop in the first current path 100 and the total voltage drop in the second current path 200 are equal (Eq.(12)): VR1+VD1+Vdrop+Vbe_Q1=VR2+VD2+Vce_Q2

[0076] If the output current Iout and the reference current Iref are equal, equation (12) simplifies to equation (12a): Vdrop=Vce_Q2−Vbe_Q1=Vce_Q2−VbeQ2=Vcb_Q2

[0077] A single voltage monitoring unit 380 can directly measure the collector-to-base voltage V cb_Q2 .

[0078] An integrated gate driver support circuit 700 can integrate the first transistor Q1, the second transistor C2, the first diode 130, the second diode 230, the first resistor 140, and the second resistor 240. The bases of the first and second transistors Q1 and Q2 are directly connected to a sensing terminal SNS of the integrated gate driver support circuit 700. The cathode of the first diode 130 is electrically connected to a driver output DRV. The first and second current paths 100 and 200 are connected in parallel between a supply terminal V+ and a reference terminal REF.

[0079] In the illustrated example, the integrated gate driver support circuit 700 further integrates the voltage monitoring unit 380. Alternatively or in addition to the integrated voltage monitoring unit 380, the integrated gate driver support circuit 700 can include a monitoring terminal MON that is directly connected to the collector of the second transistor Q2.

[0080] A power supply circuit 350 provides the auxiliary supply voltage VCC via the first current path 100 and the second current path 200. The power supply circuit 350 can be electrically connected between the supply terminal V+ and the reference terminal REF.

[0081] Fig. Figure 5 shows an equivalent circuit where the first transistor Q1 and the second transistor Q2 are PNP transistors. The first diode 130 and the first resistor 140 are connected in series between the collector of the first transistor Q1 and the switching node 620. The second diode 230 and the second resistor 240 are connected in series between the collector of the second transistor Q2 and the reference potential GND.

[0082] In Fig. In the second current path 200, an auxiliary transistor Q3 is included in a diode configuration. A base-emitter junction of the auxiliary transistor Q3 and a controlled load path of the second transistor Q2 are electrically connected in series. The base-emitter junction of the auxiliary transistor Q3 forms a compensation pn junction 295, with the compensation pn junction 295 and the second transistor Q2 being electrically connected in series in the second current path 200. When the compensation pn junction 295 is forward-biased, a compensation voltage V is applied. be_Q3 above the compensation pn junction 295. The total voltage drop along the first current path 100 and the total voltage drop along the second current path 200 are equal (Eq. 13): VR1+VD1+Vdrop+Vbe_Q1=VR2+VD2+Vbe_Q3+Vce_Q2

[0083] Auxiliary transistor Q3 has the same nominal characteristics as the first transistor Q1 and the second transistor Q2. Auxiliary transistor Q3, the first transistor Q1, and the second transistor Q2 can be selected from the same batch and / or selected such that the measured transistor parameters match better than 50% of any triplet of transistors with the same nominal characteristics. Auxiliary transistor Q3, the first transistor Q1, and the second transistor Q2 form a matching triplet. If the reference current Iref and the output current Iout are equal, the base-emitter voltages of the first transistor Q1, the second transistor Q2, and the auxiliary transistor Q3 are equal (Eq. (14)): Vbe_Q1=Vbe_Q2=Vbe_Q3

[0084] Equation (13) simplifies to equation (15): Vdrop=Vce_Q2

[0085] The voltage drop V dropis applied to the collector-emitter voltage V ce_Q2 of the second transistor Q2 and can be monitored by a single voltage monitoring unit 380, which is connected to the collector and emitter of the second transistor Q2.

[0086] In Fig. 7. The first transistor Q1 and the second transistor Q2 are n-channel field-effect transistors, with one source of the first transistor Q1 and one source of the second transistor Q2 being directly electrically connected. The voltage drop V drop is applied to the drain-source voltage V ds_Q2 of the second transistor Q2.

[0087] In Fig. 8. The first transistor Q1 and the second transistor Q2 are pnp-bipolar junction transistors, with one emitter of the first transistor Q1 and one emitter of the second transistor Q2 being directly electrically connected to each other and to the auxiliary supply voltage VCC. The voltage drop V dropis applied to the collector-emitter voltage V ce_Q2 of the second transistor Q2.

[0088] In Fig. 9. The first transistor Q1 and the second transistor Q2 are p-channel field-effect transistors, with one source of the first transistor Q1 and one source of the second transistor Q2 being directly electrically connected. The voltage drop V drop is applied to the drain-source voltage V ds_Q2 of the second transistor Q2.

[0089] Fig. Figure 10 shows an integrated gate driver circuit 400, which integrates a gate driver circuit 410 and an analog-to-digital converter 420, used as a voltage monitoring unit 380. The analog-to-digital converter 420 converts a voltage received between an analog input pin ADin and a signal ground pin SGND into a digital value. The analog input pin ADin is electrically connected to the collector of the second transistor Q2. The signal ground pin SGND is electrically connected to the emitter of the second transistor Q2 with the logic reference potential VEE. The power semiconductor device 310 is electrically connected between a switching node 620 and a switching reference potential AGND.

[0090] The signal ground pin SGND is independent of the switching reference potential AGND and can assume the potential of the emitters of the first and second transistors Q1, Q2, which is lower (more negative) than the switching reference potential AGND.

[0091] In Fig. Figure 11 integrates an integrated motor control circuit 500, a motor control circuit 510 that controls a plurality of power semiconductor devices arranged to control a motor, and an analog-to-digital converter 420 that converts a voltage received between an analog input pin ADin and an internal reference potential. The integrated motor control circuit 500 has an internal connection between the internal reference potential and the reference potential GND, so that the analog-to-digital converter 420 does not operate over the full range required to convert the collector-emitter voltage V. ce_Q2 is required. Taking into account equation (15), the voltage drop V is drop equal to the sum of the collector-base voltage V cb_Q2 and the base-emitter voltage V be_Q2 of the second transistor Q2 (Eq.(16)): Vdrop=Vcb_Q2+Vbe_Q2

[0092] The second transistor Q1 and the third transistor Q3 are matched transistors (Eq.(17)): Vbe_Q2=Vbe_Q3

[0093] The measurement for the voltage drop V drop can the base-emitter voltage V be_Q3 of the auxiliary transistor Q3 instead of the base-emitter voltage V be_Q2 use the second transistor Q2 (Eq.(18)): Vdrop=Vcb_Q2+Vbe_Q3

[0094] Accordingly, the analog input pin ADin of the integrated motor control circuit 500 is electrically connected to the base or collector of the auxiliary transistor Q3.

[0095] The analog-to-digital converter 420 is used as a voltage monitoring unit 380, as described above. The integrated motor control circuit 500 can output digital values ​​of the voltage drop Vdrop at regular intervals or as needed via a data interface to a higher processing instance for estimating remaining service life or for checking states preceding a failure.

[0096] Fig. Figure 12 shows a multi-device package 340 that integrates at least the first transistor Q1, the second transistor Q2, and the auxiliary transistor Q3. In the shared multi-device package 340, the first transistor Q1, the second transistor Q2, and the auxiliary transistor Q3 are exposed to the same temperature and the same temperature budget, so that the equality or approximate equality of the device parameters is not affected by different junction temperatures of the first transistor Q1, the second transistor Q2, and the auxiliary transistor Q3.

[0097] If the first transistor Q1, the second transistor Q2 and the auxiliary transistor Q3 are from the same semiconductor chip, the characteristic parameters of the first transistor Q1, the second transistor Q2 and the auxiliary transistor Q3 can be highly identical.

[0098] Fig. Figure 13 shows a multi-diode package 345 that integrates at least the first diode 130 and the second diode 230. In the shared multi-diode package 345, the first diode 130 and the second diode 230 are exposed to the same temperature and the same temperature budget, so that the equality or approximate equality of the device parameters is not affected by different junction temperatures of the first diode 130 and the second diode 230.

[0099] If the first diode 130 and the second diode 230 come from the same semiconductor chip, the characteristic parameters of the first diode 130 and the second diode 230 can be highly identical.

[0100] Fig.Figure 14 shows an integrated gate driver support circuit 700, which integrates a current mirror circuit 320 with a first transistor Q1 and a second transistor Q2. The current mirror circuit 320 copies a reference current Iref through the first transistor Q1 by controlling an output current Iout through the second transistor Q2. A load path of the first transistor Q1 is electrically connected between a sensing terminal SNS and a reference terminal REF. A base of the second transistor Q2 and a base of the first transistor Q1 are electrically connected to the sensing terminal SNS. The emitter of the first transistor Q1 and the emitter of the second transistor Q2 are electrically connected to a reference terminal REF.

[0101] A first diode 130 and a first resistor 140 are electrically connected between a supply terminal V+ and a driver terminal DRV, with one cathode of the first diode 130 facing the driver terminal DRV. A second diode 230 and a second resistor 240 are electrically connected between the supply terminal V+ and the collector of the second transistor Q2, with one cathode of the second diode 230 facing the collector of the second transistor Q2. The collector of the second transistor Q2 is electrically connected to a monitoring terminal MON. The first diode 130 and the second diode 230 have identical nominal characteristics. The first resistor 140 and the second resistor 240 have identical nominal resistances.

[0102] The integrated gate driver support circuit 700 may further include a voltage monitoring unit and / or a compensation pn junction as described above and can be used for any of the circuits described above.

Claims

[1] Circuit (300), comprising: a power semiconductor device (310) in a switched current path (315) between a switching node (620) and a reference potential; a current mirror circuit (320) comprising a first transistor (Q1) and a second transistor (Q2) and configured to copy a reference current IRef through the first transistor (Q1) by controlling an output current Iout through the second transistor (Q2), and a compensation pn transition (295), wherein the first transistor (Q1) is electrically connected outside the switched current path (315) and in series with the power semiconductor device (310) in a first current path (100), the compensation pn junction (295) and the second transistor (Q2) are electrically connected in series in a second current path (200), and the first current path (100) and the second current path (200) are electrically connected in parallel. [2] Circuit according to the preceding claim, further comprising: a voltage monitoring unit (380), configured to monitor a voltage in the second current path (200). [3] Circuit according to one of the preceding claims, wherein the compensation pn junction (295) has an auxiliary transistor (Q3) in a diode configuration, wherein a base-emitter junction or a body-source junction of the auxiliary transistor (Q3) and the second transistor (Q2) are electrically connected in series. [4] Circuit according to one of the preceding claims, wherein the compensation pn junction (295), the first transistor (Q1) and the second transistor (Q2) are integrated in a multi-device housing (340). [5] Circuit according to any of the preceding claims, further comprising: a power supply circuit (350) configured to provide an auxiliary supply voltage via the first current path (100) and the second current path (200). [6] Circuit according to one of the preceding claims, wherein the first current path (100) has further first electrical elements (190) and the second current path (200) has further second electrical elements (290), and wherein for a predefined current a first voltage drop across the further first electrical elements (190) and a second voltage drop across the further second electrical elements (290) are equal. [7] Circuit according to one of the preceding claims, wherein an ohmic resistance in the first current path (100) and an ohmic resistance in the second current path (200) differ from each other by no more than 5% of an average value of the ohmic resistances. [8] Circuit according to one of the preceding claims, further comprising: a first diode (130) in the first current path (100) and a second diode (230) in the second current path (200), wherein the first diode (130) is configured to block a reverse voltage across the power semiconductor device (310) in an off state of the power semiconductor device (310), wherein the first diode (130) and the second diode (230) are forward biased when the power semiconductor device (310) is in an on state, and wherein the first diode (130) and the second diode (230) have the same nominal characteristics. [9] Circuit according to the preceding claim, wherein the first diode (130) and the second diode (230) are integrated in a multi-diode package (345). [10] Circuit according to claim 8, wherein the first transistor (Q1), the second transistor (Q2), the first diode (130), the second diode (230), the further first electrical elements (190) and the further second electrical elements (290) are integrated in a multi-device housing. [11] Circuit according to any one of claims 1 to 10, wherein the first transistor (Q1) and the second transistor (Q2) are bipolar transition transistors and an emitter of the first transistor (Q1) and an emitter of the second transistor (Q2) are electrically directly connected to each other. [12] Circuit according to any one of claims 1 to 10, wherein the first transistor (Q1) and the second transistor (Q2) are field-effect transistors and a source of the first transistor (Q1) and a source of the second transistor (Q2) are electrically directly connected to each other. [13] Circuit according to any one of claims 1 to 10, wherein the first transistor (Q1) and the second transistor (Q2) comprise p-channel field-effect transistors or the first transistor (Q1) and the second transistor (Q2) comprise pnp-bipolar junction transistors. [14] Circuit according to the preceding claim, further comprising a voltage monitoring unit (380) configured to monitor a voltage across the second transistor (Q2). [15] Circuit according to any one of claims 1 to 10, wherein the first transistor (Q1) and the second transistor (Q2) comprise n-channel field-effect transistors or the first transistor (Q1) and the second transistor (Q2) comprise npn-bipolar junction transistors. [16] Circuit according to the preceding claim, further comprising a voltage monitoring unit (380) electrically connected to load electrodes of the second transistor (Q2) and configured to monitor a voltage across the second transistor (Q2). [17] Circuit according to claim 15, further comprising a voltage monitoring unit (380) configured to monitor a voltage between an anode side of the compensation pn junction (295) and a network node of the first current path (100) between the power semiconductor device (310) and the first transistor (Q1). [18] Power module unit comprising: a circuit (300) according to any one of claims 14 to 17; and a gate driver circuit (410) configured to drive a gate signal to a gate of the power semiconductor device (310), wherein the gate driver circuit (410) and the voltage monitoring unit (380) are integrated in an integrated gate driver circuit (400). [19] Engine control circuit comprising: a circuit (300) according to any one of claims 14 to 17; and a motor control circuit (510) configured to drive an H-bridge comprising the power semiconductor device (310) of the circuit (300), wherein the motor control circuit (510) and the voltage monitoring unit (380) are integrated in an integrated motor control circuit (500). [20] Integrated gate driver support circuit (700) comprising: a current mirror circuit (320) comprising a first transistor (Q1) and a second transistor (Q2) and configured to copy a reference current Iref through the first transistor (Q1) by controlling an output current Iout through the second transistor (Q2), wherein the first transistor (Q1) is electrically connected between a sensing terminal SNS and a reference terminal REF; a first diode (130) electrically connected between a supply terminal V+ and a driver terminal DRV, wherein a cathode of the first diode (130) is aligned with the driver terminal DRV; and a second diode (230) electrically connected in series with the second transistor (Q2) in a path between the supply terminal V+ and the reference terminal REF, wherein an anode of the second diode (230) is aligned with the supply terminal V+, and wherein the first diode (130) and the second diode (230) have the same nominal characteristics.

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