Circuit board and semiconductor package including same

Abstract

An embodiment of the present invention provides a circuit board comprising: a first build-up structure comprising multiple insulating layers stacked in the vertical direction, multiple wiring parts, each of which is disposed on one surface of a corresponding insulating layer among the multiple insulating layers, and multiple via electrodes connecting the multiple wiring parts in the vertical direction; and second build-up structure disposed on the first build-up structure and including multiple insulating layers stacked in the vertical direction, multiple wiring parts, each of which is disposed on one surface of a corresponding insulating layer among the multiple insulating layers, and multiple via electrodes connecting the multiple wiring parts in the vertical direction, wherein: the multiple insulating layers of the first build-up structure are different from the multiple insulating layers of the second build-up structure; the multiple via electrodes of the first build-up structure include a via electrode inclined to have a width that varies along the vertical direction; and at least one of the multiple via electrodes of the second build-up structure includes a first part having a constant width in the vertical direction and a second part disposed on the first part and having a curved surface such that the width of the second part increases in a direction from the first build-up structure toward the second build-up structure.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices, such as mobile devices, and the adoption of High Bandwidth Memory (HBM) have led to larger package sizes. Furthermore, as the number of functions required for application processors increases, there is a growing demand for separate processor chips for each function, along with circuit boards capable of mounting these processor chips. Even when the application processor is split into two processor chips, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal quantity. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability issues such as circuit board warpage and product price increase. Therefore, increasing the circuit pattern density is more advantageous in terms of product price, reliability issues such as warpage, and product miniaturization than increasing the area and thickness of circuit boards. Therefore, miniaturization of circuit patterns and through-holes is required.

[0006] However, in forming these through-electrodes, problems such as cracks, peeling, or breakage between the through-electrodes and pad electrodes are occurring due to the through-electrodes being tilted or being made finer.

[0007] An embodiment of the present invention implements a circuit board and a semiconductor package including the same, in which the reliability of an electrode portion is improved by positioning the upper surface of a via metal layer above the upper surface of a first build-up layer.

[0008] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved mechanical strength and improved electrical characteristics such as signal integrity by increasing the contact area between the via electrode and the wiring portion.

[0009] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved reliability by improving the contact area between the build-up layer and the electrode portion.

[0010] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0011] A circuit board according to an embodiment of the present invention comprises a first build-up structure including a plurality of insulating layers stacked along a vertical direction, a plurality of wiring portions arranged on one surface of each of the plurality of insulating layers, and a plurality of via electrodes connecting the plurality of wiring portions along the vertical direction; and a second build-up structure disposed on the first build-up structure and including a plurality of insulating layers stacked along a vertical direction, a plurality of wiring portions arranged on one surface of each of the plurality of insulating layers, and a plurality of via electrodes connecting the plurality of wiring portions along the vertical direction, wherein the plurality of insulating layers of the first build-up structure are different from the plurality of insulating layers of the second build-up structure, and the plurality of via electrodes of the first build-up structure include via electrodes that are inclined so as to have different widths along the vertical direction, and at least one of the plurality of via electrodes of the second build-up structure includes a first portion having a constant width along the vertical direction, and a second portion disposed on the first portion and having a curved surface so as to have a wider width in a direction from the first build-up structure toward the second build-up structure.

[0012] The second build-up structure may include a first build-up layer; a second build-up layer disposed on the first build-up layer; a first electrode portion including a first wiring portion disposed on the first build-up layer and a first via electrode penetrating the first build-up layer; and a second electrode portion including a second wiring portion disposed on the second build-up layer and a second via electrode penetrating the second build-up layer.

[0013] The first electrode portion may include a via metal layer, a first metal layer disposed on the via metal layer, and a second metal layer disposed on the first metal layer.

[0014] The above via metal layer may include a first via metal layer horizontally overlapping the first build-up layer and a second via metal layer positioned on an upper surface of the first build-up layer.

[0015] The upper surface of the above via metal layer may be arranged adjacent to the upper surface of the second build-up layer compared to the upper surface of the first build-up layer.

[0016] The first metal layer may include a first region disposed between an upper surface of the via metal layer and an upper surface of the via metal layer; a second region disposed above an upper surface of the via metal layer; and a third region disposed between the first region and the second region.

[0017] The first region may be located on the outer side of the via metal layer and may be in contact with the outer surface of the via metal layer.

[0018] The first region may include a first groove that is concave inwardly on the outer surface.

[0019] The above first groove may be arranged at an edge of the first metal layer.

[0020] The above first groove can overlap with the above second metal layer in the lamination direction.

[0021] The outermost surface of the second metal layer may be positioned outside at least a portion of the first groove.

[0022] The width of the lower surface of the first metal layer may be smaller than the width of the second metal layer.

[0023] The first build-up layer may include a second groove surrounding an outer surface of the via metal layer.

[0024] The third region may be placed in the second home.

[0025] The third region may be positioned lower than the first region and the second region.

[0026] The first region may be disposed between the second region and the third region in the stacking direction.

[0027] The second groove may be arranged along an edge of the via metal layer.

[0028] The second metal layer may overlap at least partially in the horizontal direction with the via metal layer.

[0029] The first metal layer may be a chemical plating layer, and the via metal layer and the second metal layer may be electroplating layers.

[0030] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, in which the reliability of an electrode portion is improved by positioning the upper surface of a via metal layer above the upper surface of a first build-up layer.

[0031] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, in which mechanical strength is improved and electrical characteristics such as signal integrity are improved by increasing the contact area between the via electrode and the wiring portion.

[0032] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved reliability by improving the contact area between the build-up layer and the electrode portion.

[0033] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0034] Figure 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

[0035] Figure 2 is an enlarged view of part K1 in Figure 1,

[0036] Figure 3 is a plan view of the first metal layer and the via metal layer in the circuit board according to the first embodiment.

[0037] Fig. 4 is a plan view of the first wiring portion and the via metal layer in the circuit board according to the first embodiment.

[0038] Figure 5 is an enlarged view of part K2 in Figure 1,

[0039] Figures 6 and 7 are application examples of a circuit board according to the first embodiment.

[0040] Figures 8 to 18 are drawings explaining a method for manufacturing a circuit board according to the first embodiment.

[0041] Fig. 19 is a cross-sectional view of a circuit board according to the second embodiment;

[0042] Figure 20 is an enlarged view of part K3 in Figure 19,

[0043] Fig. 21 is a plan view of the first metal layer and the via metal layer in a circuit board according to the second embodiment.

[0044] Figures 22 to 32 are drawings explaining a method for manufacturing a circuit board according to the second embodiment.

[0045] Fig. 33 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0046] Fig. 34 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0047] Fig. 35 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0048] Fig. 36 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0049] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0050] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0051] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0052] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0053] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0054] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “and (and) at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0055] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as a "first component," and similarly, a first component may also be referred to as a "second component." The terms "and / or" include a combination of multiple related items described herein or any of multiple related items described herein. These terms are only used to distinguish the component from other components and are not limited by the nature, order, or sequence of the component.

[0056] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0057] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0058] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0059] Additionally, the expression that configuration A is positioned between configurations B and C should also include the meaning that configuration A is positioned so that it overlaps configurations B and C at least partially in the horizontal and / or vertical directions.

[0060] Expressions referring to directions include horizontal directions, vertical directions, and include a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. For example, these are referred to as a first horizontal direction (x-axis), a second horizontal direction (y-axis), and a vertical direction (z-axis) according to the Cartesian coordinate system, and the meaning of overlapping along the horizontal direction should also include the meaning of overlapping along the first horizontal direction and / or overlapping along the second horizontal direction.

[0061] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0062] Additionally, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood only as being in "direct contact" with a component B, it is described as being in "direct contact."

[0063] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0064] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0065] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may further include a circuit board, a plurality of semiconductor elements arranged on the circuit board, and a connecting member electrically connecting the plurality of semiconductor elements.

[0066] The circuit board may include a plurality of laminated insulating layers, wiring or circuit patterns arranged within each of the plurality of laminated insulating layers, and via electrodes for connecting the wiring or circuit patterns arranged within each of the insulating layers.

[0067] The semiconductor device may be mounted on a circuit board, and may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions or more active and / or passive devices are integrated into a single chip. For example, the semiconductor device may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), a field programmable gate array (FPGA), etc., or a chip set including a specific combination of the above-mentioned. In addition, the semiconductor device may be a memory device such as a high bandwidth memory (HBM).

[0068] A connecting member is a component that functions to electrically connect a plurality of semiconductor elements, and may be placed between the semiconductor elements and the circuit board. For example, the connecting member may be embedded in the circuit board, or may be placed on the circuit board. When embedded in the circuit board, it may have the advantage of being able to reduce the thickness of the semiconductor package. The connecting member may be formed of silicon, but is not limited thereto, and may be formed of an organic material. Since it functions to electrically interconnect a plurality of semiconductor elements, it may be referred to as a bridge.

[0069] Additionally, the connecting member may be positioned on a circuit board. When positioned on a circuit board, the connecting member may be covered with a molding member, and the circuit board, semiconductor element, and connecting member may be electrically interconnected through a Through Mold Via (TMV) penetrating the molding member. Additionally, a rewiring section may be positioned between the molding member and the semiconductor element.

[0070] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0071] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0072] FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, FIG. 2 is an enlarged view of a portion K1 in FIG. 1, FIG. 3 is a plan view of a first metal layer and a via metal layer in a circuit board according to the first embodiment, FIG. 4 is a plan view of a first wiring portion and a via metal layer in a circuit board according to the first embodiment, FIG. 5 is an enlarged view of a portion K2 in FIG. 1, and FIGS. 6 and 7 are application examples of a circuit board according to the first embodiment.

[0073] Referring to FIG. 1, a circuit board (100) according to the first embodiment may include an insulating layer (110) and an electrode portion (120). Furthermore, the circuit board (100) may further include a protective layer disposed on the electrode portion (120) or a core layer, which is an insulating layer disposed within the insulating layer (110). In addition, as illustrated, the circuit board may have a coreless structure.

[0074] In an embodiment, the insulating layer (110) may be provided in a structure in which multiple insulating layers are laminated. The electrode portion (120) may be disposed by being embedded in each insulating layer of the multiple insulating layers (110), thereby performing the function of transmitting signals and / or power from a main board (not shown) to a semiconductor element.

[0075] In addition, the circuit board may include a first build-up structure (BT1) and a second build-up structure (BT2). For example, when the circuit board is a core board, the circuit board may include a core layer and a core electrode portion in either the first build-up structure (BT1) or the second build-up structure (BT2). In addition, when the circuit board is a coreless board, the insulating layer (110) may include the first build-up structure (BT1) and the second build-up structure (BT2) that are sequentially stacked in a stacking direction (Y-axis direction). The first build-up structure (BT1) may include a plurality of insulating layers, a plurality of wiring portions (PE1) arranged on the plurality of insulating layers, and a plurality of via electrodes (UE1) that connect the plurality of wiring portions (PE1) in a vertical direction (Y-axis direction). Additionally, the second build-up structure (BT2) may include a plurality of insulating layers, a plurality of wiring portions (PE2) arranged on the plurality of insulating layers, and a plurality of via electrodes (UE2) connecting the plurality of wiring portions (PE2) in a vertical direction (Y-axis direction).

[0076] In the present embodiment, the second build-up structure (BT2) may be positioned on the first build-up structure (BT1). The plurality of insulating layers of the first build-up structure (BT1) and the plurality of insulating layers of the second build-up structure (BT2) may include different materials. For example,

[0077] The plurality of insulating layers of the first build-up structure (BT1) and the plurality of insulating layers of the second build-up structure (BT2) may be formed of fillers having different sizes. The size of the filler in the plurality of insulating layers of the first build-up structure (BT1) may be larger than the size of the filler in the plurality of insulating layers of the second build-up structure (BT2). For example, the plurality of insulating layers of the second build-up structure (BT2) may include a nano filler. In addition, the width (or spacing) of the wiring portion (PE1) disposed in the plurality of insulating layers of the first build-up structure (BT1) may be larger than the width (or spacing) of the wiring portion (PE2) disposed in the plurality of insulating layers of the second build-up structure (BT2).

[0078] In addition, the plurality of via electrodes (UE1) of the first build-up structure (BT1) may include inclined via electrodes so that the width (Wa) varies along the vertical direction (Y-axis direction). The first build-up structure (BT1) may have a plurality of via electrodes having different inclined angles. In addition, when the core layer is disposed on the first build-up structure (BT1), the width of the via electrode may increase in some areas and decrease in other areas along the stacking direction.

[0079] And the plurality of insulating layers of the second build-up structure (BT2) may include a first build-up layer (111) and a second build-up layer (112). Furthermore, the insulating layer (110) may include a third build-up layer (113) disposed under the first build-up layer (111). However, the following description will be based on the first build-up layer (111) and the second build-up layer (112) excluding this. And the electrode portion (120) may be composed of a via electrode and a wiring portion as described below.

[0080] Hereinafter, in the case of the insulating layer (110), the first build-up layer (111) and the second build-up layer (112) among the multiple insulating layers of the first build-up structure (BT1) will be described as the basis. In addition, the electrode portion will also be described as the first electrode portion (121) and the second electrode portion (122) arranged on the first build-up layer (111) and the second build-up layer (112). In addition, a third build-up layer (an insulating layer of the first and second build-up structures) may be positioned below the first build-up layer (111).

[0081] In the insulating layer (110), the first build-up layer (111) and the second build-up layer (112) may be sequentially positioned along the stacking direction or the vertical direction (the first direction or the Y-axis direction). That is, the second build-up layer (112) may be positioned on the upper surface (US1) of the first build-up layer (111), and the first build-up layer (111) may be positioned under the lower surface of the second build-up layer (112). Furthermore, as described above, the insulating layer (110) of the circuit board may further include an additional insulating layer in addition to the first build-up layer (111) and the second build-up layer (112). For example, the insulating layer (110) of the circuit board may include an additional insulating layer (the third build-up layer) positioned under the first build-up layer (111). In addition, the insulating layer (1110) of the circuit board may include an additional insulating layer positioned on the second build-up layer (112).

[0082] And the insulating layer (110) of the circuit board (100) may be rigid or flexible. For example, the insulating layer (110) of the circuit board (100) may include glass or plastic. For example, the insulating layer (110) of the circuit board or each insulating layer constituting the insulating layer (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer (110) of the circuit board may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer (110) of the circuit board may include sapphire. For example, the insulating layer (110) of the circuit board may include an optically isotropic film. For example, the insulating layer (110) of the circuit board may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer (110) of the circuit board may be formed of a material including a filler and an insulating resin. For example, the insulating layer (110) of the circuit board may have a structure in which a filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

[0083] The insulating layer (110) may have a structure in which a plurality of different insulating materials are laminated.

[0084] In addition, the first build-up layer (111) and the second build-up layer (112) may be provided with any insulating resin such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin can be used. The above-mentioned arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material provided with glass fiber or aramid fiber. For example, the insulating layer (110) can use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., as an example, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. can be used. For example, the first build-up layer (111) and the second build-up layer (112) can include multiple layers composed of ABF. In addition, each insulating layer can be composed of the same or different materials.

[0085] In addition, the wiring or electrode portion (120) according to the embodiment is arranged for electrical connection between a main board, etc. and a chip (or semiconductor element, die), and the electrode portion (120) includes a wiring portion (circuit pattern or circuit pattern layer, pad, pattern portion) and a via portion (or via electrode).

[0086] For example, the wiring portion of the electrode portion (120) may include a pattern and a pad on the upper surface of the insulating layer. Hereinafter, the wiring portion is described interchangeably with the terms 'circuit pattern' and 'pattern portion'. In addition, the electrode portion (120) may include a via portion or a via electrode penetrating the insulating layer. Accordingly, in the embodiment, the electrode portion (120) is described below as including a wiring portion (circuit pattern) and a via electrode in each insulating layer. In addition, the wiring portion in the electrode portion (120) may be designed in various forms for transmitting signals and / or power to and from the semiconductor element, and is arranged in each insulating layer of the first and second build-up layers (111, 112).

[0087] In the electrode portion (120), a via electrode (or via portion) is disposed to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns disposed on each insulating layer of the first and second build-up layers (111, 112). The via electrode can connect a plurality of circuit patterns (wiring portions) to each other. The via electrode may also be formed in multiple pieces like the wiring portion. That is, the insulating layer may include a via hole for arranging the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and may be freely designed.

[0088] In the electrode portion (120), a wiring portion (circuit pattern) may be arranged on each insulating layer. And the circuit pattern may be electrically connected to the circuit pattern. In addition, the wiring portion (circuit pattern) may be connected to each via electrode. And the circuit pattern arranged on the upper and lower surfaces of the insulating layer in the first and second build-up layers (111, 112) may be electrically connected to a semiconductor element and / or a main board or substrate, etc.

[0089] In an embodiment, the electrode portion (120) may include a first electrode portion (121) and a second electrode portion (122). The first electrode portion (121) and the second electrode portion (122) may be build-up layer electrode portions.

[0090] Furthermore, the electrode portion (120) may further include additional electrode portions arranged on the additional insulating layer when an additional insulating layer is present. Each electrode portion may include a wiring portion and a via electrode as described above.

[0091] The first electrode portion (121) may be positioned on the first build-up layer (111). The second electrode portion (122) may be positioned on the second build-up layer (112). In addition, the first electrode portion (121) may include a first via electrode (121b) and a first wiring portion (121a). In addition, the second electrode portion (122) may include a second via electrode (122b) and a second wiring portion (122a).

[0092] The first wiring portion (121a) may be arranged on the upper surface (US1) of the first build-up layer (111). The first via electrode (122b) may penetrate the first build-up layer (111). The second wiring portion (122a) may be arranged on the upper surface (US2) of the second build-up layer (112). The second via electrode (122b) may penetrate the second build-up layer (112). However, this structure may be changed depending on an additional insulating layer or an additional electrode portion.

[0093] The second electrode part (122) may be positioned above the first electrode part (121). And at least a portion of the second electrode part (122) and the first electrode part (121) may be electrically connected to each other.

[0094] In addition, the circuit board (100) may further include a protective layer (SR) disposed on the outside of the insulating layer (110). For example, a protective layer may be further disposed on the top or bottom. The protective layer (SR) may have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when bonding between the semiconductor element and / or the main board and the circuit board, the protective layer (SR) may be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals may be arranged at a high density. When the plurality of terminals and the pads of the circuit board are bonded, solder may be used, for example. When solder is used, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist that does not have good wettability with the solder may be arranged to solve this short circuit problem. In addition, the protective layer (SR) may be formed of a material that has insulating properties for electrical connection. The protective layer (SR) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. In addition, the protective layer (SR) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. The protective layer (SR) may have at least one opening for connection between a terminal of a semiconductor device and a pad of a circuit board. For example, in an embodiment, the protective layer (SR) may be formed of a filler, which is a reinforcing member, and a resin.

[0095] A protective layer (SR) may be disposed on an insulating layer (110). And the protective layer (SR) may include a plurality of fillers.

[0096] And the insulating layer or protective layer (SR) located on the outside of the circuit board may have an opening. Through the opening, it can be electrically connected to other semiconductor elements, the circuit board, etc.

[0097] Furthermore, a bump portion (not shown) may be disposed on the outer side of the circuit board on the protective layer (SR). For example, the bump portion (not shown) may be disposed on the upper surface of the protective layer (SR). The bump portion (not shown) may include a protrusion disposed on the upper surface of the protective layer (SR) and a via portion penetrating the protective layer (SR). In an embodiment, the via portion and the protrusion portion may each include a plurality of protrusions or convex portions protruding toward an adjacent protective layer (SR).

[0098] A metal layer is additionally disposed on the bump portion (not shown) and can be electrically connected. Accordingly, the durability and reliability of the bump portion (not shown) can be further improved. For example, the metal layer can be formed of at least one metal layer. The metal layer can be formed of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or a combination thereof. Accordingly, the bonding strength between the metal layer and the bump portion (not shown) is improved, the corrosion resistance and durability of the bump portion (not shown) are improved, and the loss of electrical signals can be minimized. The metal layer can be formed on the bump portion (not shown) by deposition, electroplating, or the like of various metals.

[0099] In addition, circuit boards can be divided into package substrates and interposers according to their function. The package substrate functions to mount semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of laminated insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of circuit boards with a high number of laminated layers, the yield of the circuit board can be improved by separating them into an interposer and a package substrate. In addition, as the terminal density of semiconductor devices increases, it may be difficult to implement pads on the package substrate with an area corresponding to the terminals of the semiconductor devices. Therefore, the interposer can act as a buffer between the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices.

[0100] The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0101] Referring further to FIG. 2, in the circuit board (100) according to the embodiment, the first electrode portion (121) may include a first via electrode (121b) and a first wiring portion (121a). Hereinafter, the first via electrode (121b) and the first wiring portion (121a) are distinguished based on the upper surface (US1) and the lower surface (BS1) of the first build-up layer (111). The first via electrode (121b) may refer to an electrode from the upper surface of the wiring portion in contact with the lower surface (BS1) of the first build-up layer (111) to the upper surface (US1) of the first build-up layer (111). In addition, the first wiring portion (121a) may refer to an electrode on the upper surface (US1) of the first build-up layer (111).

[0102] Furthermore, the first electrode portion (121) may be classified according to the plating layer. For example, the first electrode portion (121) may include a via metal layer (ML0), a first metal layer (ML1), and a second metal layer (ML2). The via metal layer (ML0) may be an electroplating layer. And the first metal layer (ML) may be a chemical plating layer. In addition, the second metal layer (ML2) may be an electroplating layer. For example, the first metal layer (ML1) may have denser grains than the via metal layer (ML) and the second metal layer (ML2). The average grain size of the first metal layer (ML1) may be smaller than the average grain sizes of the via metal layer (ML) and the second metal layer (ML2).

[0103] In addition, at least a portion of the via metal layer (ML0) may be positioned on the upper surface (US1) of the first build-up layer (111). Accordingly, the via metal layer (ML0) may penetrate the first build-up layer (111) and may not overlap at least a portion of the via metal layer (ML0) with the first build-up layer (111) in the horizontal direction (X-axis direction). The via metal layer (ML0) may include a first via metal layer (ML0a) and a second via metal layer (ML0b) corresponding to the first via electrode (121b). The second via metal layer (ML0b) may be positioned on the first via metal layer (ML0a) and on the first build-up layer (111). Accordingly, the first via metal layer (ML0a) may overlap the first build-up layer (111) in the horizontal direction (X-axis direction). The second via metal layer (ML0b) may not overlap the first build-up layer (111) in the horizontal direction (X-axis direction).

[0104] The via metal layer (ML0) may be positioned adjacent to the upper surface (US2) of the second build-up layer (112) relative to the upper surface of the first build-up layer (111). For example, the via metal layer (ML0) may be positioned between the upper surface (US1) of the first build-up layer (111) and the upper surface (US2) of the second build-up layer (112). In addition, the distance in the stacking direction (Y-axis direction) between the via metal layer (ML0) and the upper surface (US2) of the second build-up layer (112) may be smaller than the distance in the stacking direction (Y-axis direction) between the upper surface (US1) of the first build-up layer (111) and the upper surface (US2) of the second build-up layer (112). Additionally, the distance in the stacking direction (Y-axis direction) between the via metal layer (ML0) and the upper surface (US2) of the second build-up layer (112) may be smaller than the thickness of the second build-up layer (112).

[0105] By this configuration, the contact area between the first via electrode and the first wiring portion can be increased, thereby improving the mechanical strength. That is, the mechanical reliability of the electrode portion in the circuit board can be improved. Furthermore, the electrical contact area between the via metal layer (ML0) and the first wiring portion (121a) can be increased, thereby reducing the electrical resistance and improving the electrical characteristics such as signal integrity.

[0106] And the relationship between the via metal layer (ML0) and the first build-up layer (111) or the second build-up layer (112) can be equally applied to other via electrodes. For example, in a circuit board, one via electrode can be positioned adjacent to the upper surface of another build-up layer above one build-up layer compared to one build-up layer through which one via electrode penetrates. In other words, the description of the first electrode portion (121), the first build-up layer (111), and the second build-up layer (112) can be equally applied to other electrode portions or build-up layers in a circuit board.

[0107] In addition, in the embodiment, the first wiring portion (121a) may be positioned on the first build-up layer (111). And the first wiring portion (121a) may be positioned on the via metal layer (ML0). In particular, the first wiring portion (121a) may be positioned on the first via metal layer (ML0a). In addition, the first wiring portion (121a) may be in contact with the first via metal layer (ML0a).

[0108] And the first wiring portion (121a) may include a second via metal layer (ML0b), a first metal layer (ML1), and a second metal layer (ML2). The second metal layer (ML2) may be located on the first metal layer (ML1).

[0109] The second via metal layer (ML0b) may be a portion extending upward from the first via metal layer (ML0a). The second via metal layer (ML0b) may be a region protruding above the upper surface of the first build-up layer (111). The second via metal layer (ML0b) may be an electroplated layer, similar to the first via metal layer (ML0a), and may be made of the same material.

[0110] The first metal layer (ML1) may include a first region (AR1) and a second region (AR2). The first region (AR1) may be disposed between the upper surface (US1) of the first build-up layer (111) and the upper surface (USa) of the second via metal layer (ML0b). Accordingly, the first region (AR1) may be located between the upper surface (US1) and the lower surface of the first build-up layer (111). In addition, the first region (AR1) may be located below the upper surface (USa) of the via metal layer (ML0) (or the second via metal layer (ML0b)) and may be in contact with the outer surface of the via metal layer (ML0) (or the second via metal layer). The first region (AR1) may overlap the via metal layer (ML0) in a horizontal direction (X-axis direction).

[0111] The second region (AR2) may be disposed on the upper surface (USa) of the via metal layer (ML0).

[0112] Referring further to FIGS. 3 and 4, the first region (AR1) and the second region (AR2) may overlap at least partially in the stacking direction (Y-axis direction). The first region (AR1) and the second region (AR2) may contact each other.

[0113] In addition, the first region (AR1) may overlap with an outer region of the via metal layer (ML0) (or the second via metal layer) in the stacking direction (Y-axis direction). The second region (AR2) may overlap with the via metal layer (ML0) (or the second via metal layer) in the stacking direction (Y-axis direction). In addition, a part of the second region (AR2) may not overlap with the via metal layer (ML0) (or the second via metal layer) in the stacking direction (Y-axis direction) but may be misaligned. And a part of the second region (AR2) may be located in an outer region of the via metal layer (ML0).

[0114] An overlapping region (OV1) in the stacking direction (Y-axis direction) between the first region (AR1) and the second region (AR2) may be located on the outer region of the via metal layer (ML0) (or the second via metal layer). And the overlapping region (OV1) may be located on the inner side of the outer surface (ESb) of the first metal layer (ML1). In addition, the first region (AR1) and the second region (AR2) may be in contact with each other in the overlapping region (OV1).

[0115] Furthermore, in the embodiment, the first region (AR1) may be positioned outside the via metal layer (ML0) (or the second via metal layer) and may be in contact with the outer surface of the via metal layer (ML0). For example, the first region (AR1) may be in contact with a surface (or area) that protrudes or is exposed above the upper surface (US1) of the first build-up layer (111) from the outer surface of the via metal layer (ML0).

[0116] Furthermore, the first region (AR1) may include a first groove (G1). The first groove (G1) may be located on the outer surface (ESb) of the first region (AR1). For example, the first groove (G1) may have a shape that is concave inward on the outer surface (ESb) of the first region (AR1). The first groove (G1) may be located at the edge of the first wiring portion (121a). Furthermore, the first groove (G1) may have an open loop or closed loop structure.

[0117] The first groove (G1) can accommodate a second build-up layer (112). Accordingly, the first groove (G1) can overlap the second build-up layer (112) in the stacking direction (Y-axis direction).

[0118] The width or distance (gap1) in the horizontal direction (X-axis direction) of the first groove (G1) may increase from the upper surface to the lower surface of the first region (AR1). That is, the distance (gap1) of the first groove (G1) may be greater on the lower surface (or lower) than on the upper surface (or upper portion) of the first region (AR1).

[0119] And the first groove (G1) can overlap with the second metal layer (ML2) in the stacking direction (Y-axis direction). In addition, the first groove (G1) can also overlap with the second build-up layer (112) in the stacking direction (Y-axis direction).

[0120] Furthermore, the second metal layer (ML2) may be positioned on the first metal layer (ML1) and may be in contact with at least a portion of the via metal layer (ML0). For example, the second metal layer (ML2) may be in contact with the upper surface (USa) of the via metal layer (ML0). The second metal layer (ML2) may be positioned to cover the via metal layer (ML0) (or the second via metal layer), and the first metal layer (ML1) may be positioned to surround the via metal layer (ML0) (or the second via metal layer). At least a portion of the second metal layer (ML2) may overlap the via metal layer (ML0 (or the second via metal layer)) in the horizontal direction (X-axis direction). The first groove (G1) may overlap the via metal layer (ML0) (or the second via metal layer) in the horizontal direction (X-axis direction). And the second metal layer (ML2) can be in contact with the outer surface (ESa) of the via metal layer (ML0) (or the second via metal layer). For example, the second metal layer (ML2) can be in contact with the outer surface (ESa) of the via metal layer (ML0) (or the second via metal layer) located on the upper side of the first build-up layer (111).

[0121] In addition, at least a portion of the outer surface (ESc) of the second metal layer (ML2) may be positioned outside the outer surface (ESb) of the first metal layer (ML1). In addition, at least a portion of the outer surface (ESc) of the second metal layer (ML2) may be positioned outside the first groove (G1). And the outer surface (ESa) of the via metal layer (ML0) may be positioned inside the outer surface (ESc) of the second metal layer (ML2) or the outer surface (ESb) of the first metal layer (ML1). Here, the inner side is a direction toward the center of the via metal layer (ML0), and a direction from the center of the via metal layer (ML0) toward the outer side may correspond to the outer side.

[0122] Furthermore, in the embodiment, the width (W1) of the lower surface of the first metal layer (ML1) may be smaller than the width (W2) of the second metal layer (ML2). For example, the maximum length in the horizontal direction (X-axis direction) of the second metal layer (ML2) may be larger than the minimum length in the horizontal direction (X-axis direction) of the first metal layer (ML1).

[0123] Additionally, the first metal layer (ML1) may be a chemical plating layer. And the second metal layer (ML2) may be an electroplating layer.

[0124] Additionally, the thickness of the first metal layer (ML1) may be smaller than the thickness of the second metal layer (ML2).

[0125] Additionally, the second build-up layer (112) may be in contact with the outer surface (ESa) of the first region (AR1). The second build-up layer (112) may be positioned on the outer side of the second region (AR2) and may be spaced apart from the second region (AR2). Accordingly, the second build-up layer (112) may be separated from the second region (AR2) without being in contact with it.

[0126] Referring further to FIG. 5, the number of first via electrodes (121b) according to the embodiment may be plural. Furthermore, the number of first wiring portions (121a) in contact with the first via electrodes (121b) may also be plural. For example, the first via electrode (121b) may include a first-first via electrode (121ba), a first-second via electrode (121bb), and a first-third via electrode (121bc) spaced apart in the horizontal direction (X-axis direction). In addition, the first wiring portion (121a) may include a first-first wiring portion (121aa), a first-second wiring portion (121ab), and a first-third wiring portion (121ac) spaced apart in the horizontal direction (X-axis direction). The first-first wiring portion (121aa) is positioned on the first-first via electrode (121ba) and can be in contact with the first-first via electrode (121ba). The first-second wiring portion (121ab) is positioned on the first-second via electrode (121bb) and can be in contact with the first-second via electrode (121bb). The first-third wiring portion (121ac) is positioned on the first-third via electrode (121bc) and can be in contact with the first-third via electrode (121bc).

[0127] Furthermore, in the embodiment, the via electrodes located in each build-up layer may have outer surfaces having different inclination angles. That is, the angles of the via electrodes penetrating each build-up layer and the upper surface of the build-up layer may be different from each other.

[0128] For example, the angle formed between the outer surface of the 1-1 via electrode (121ba) and the lower surface (or upper surface) of the first build-up layer (111) may be a first inclination angle (θ). The angle formed between the outer surface of the 1-2 via electrode (121bb) and the lower surface (or upper surface) of the first build-up layer (111) may be a second inclination angle (θ). The angle formed between the outer surface of the 1-3 via electrode (121bc) and the lower surface (or upper surface) of the first build-up layer (1112) may be a third inclination angle (θ).

[0129] In the embodiment, the first inclination angle (θ) of the first-first via electrode (121ba), the second inclination angle (θ) of the first-second via electrode (121bb), and the third inclination angle (θ) of the first-third via electrode (121bc) may be different from each other. For example, the first via electrode (121b) may have an outer surface with a different inclination angle, thereby improving the reliability of the via electrode in response to the size or position of the via electrode.

[0130] For example, the first via electrode (121b) may have a vertical inclination angle with respect to the lower surface (or upper surface) of the first build-up layer (111). At this time, the sum of the forces (F1, F2) applied to the first via electrode (121b) by the first build-up layer (111) may be reduced. For example, the first build-up layer (111) may apply a force (F1, F2) inwardly toward the first via electrode (121b). At this time, the force in the stacking direction may be minimized. Accordingly, the forces (F1, F2) applied to the first via electrode (121b) within the first build-up layer (111) act in opposite directions as much as possible, so that the occurrence of peeling or cracking between the first via electrode (121b) and the lower pad due to expansion of the lower insulating layer, etc. may be reduced. In particular, when the inclination angle for the first via electrode (121b) is vertical, the contact area between the first via electrode (121b) and the lower pad increases, so that the reliability of the via metal layer can be further improved.

[0131] And referring to FIGS. 6 and 7, as described above, the insulating layer (110) may or may not include a core layer as described above.

[0132] First, when the insulating layer (110) does not include a core layer, as in FIG. 6, the insulating layer (110) of the circuit board (100a) may include a first build-up structure (BT1) and a second build-up structure sequentially laminated in the lamination direction. The second build-up structure may include a first build-up layer (111) and a second build-up layer (112) among a plurality of insulating layers. And, electrode portions may be present in the plurality of insulating layers of the second build-up structure. For example, the electrode portion (120) may include a first electrode portion (121) disposed on the first build-up layer (111), a second electrode portion (122) disposed on the second build-up layer (112), and a third electrode portion (123) disposed on the third build-up layer (113).

[0133] Furthermore, when the circuit board (100b) includes a core layer (110a) as in FIG. 7, it may include a build-up insulating portion laminated on the core layer. Specifically, as illustrated, the circuit board (100) may include a core layer (110a), build-up insulating portions (111, 112, 113, 114), a core electrode portion (120A), a first electrode portion (121), and a second electrode portion (122).

[0134] For example, when the circuit board (100b) includes a core layer (110a), an upper build-up layer (111, 112) may be positioned above the core layer (110a) based on the core layer (110a). And, a lower build-up layer (113, 114) may be positioned below the core layer (110a).

[0135] And as previously explained, the first build-up structure or the second build-up structure may include a core layer.

[0136] Additionally, the build-up layer (or build-up insulation) may be referred to as a build-up structure or build-up insulation, etc. The following description will be based on this.

[0137] Furthermore, the description of the via metal layer and build-up layer described above can be equally applied to each via electrode and build-up layer regardless of whether the circuit board has a core layer or not.

[0138] Figures 8 to 18 are drawings explaining a method for manufacturing a circuit board according to the first embodiment.

[0139] First, referring to FIG. 8, a build-up layer or core layer for forming a build-up layer and an electrode portion can be first prepared. Hereinafter, the third build-up layer (113) and the third wiring portion (123a) formed on the third build-up layer (113) will be described as standard. In addition, the third build-up layer (113) and the third wiring portion (123a) will be described as being part of the first build-up structure described above.

[0140] Referring to FIG. 9, a first film (DF1) may be formed on the third build-up layer (113) and the third wiring portion (123a). For example, the first film (DF1) may be a dry film. In addition, the first film (DF1) may include various masks for performing masking. Furthermore, lamination may be performed on the first film (DF) on the third build-up layer (113). For example, the first film (DF) may be attached to the build-up layer using heat and pressure. Before such lamination, cleaning of the surface of the build-up layer, etc. may be performed. In addition, removal of air bubbles, etc. may be performed after lamination.

[0141] Referring to Fig. 10, light can be irradiated onto the first film (DF1). This irradiation of light can form a desired pattern. For example, when light is irradiated onto the first film (DF1), a pattern can be formed using various methods. The pattern can be formed using a positive or negative method.

[0142] For example, light may not be irradiated to a desired area (DF1a) on the third wiring section (123a), and light may be irradiated to the remaining area (DF1b).

[0143] Referring to Fig. 11, the light-irradiated area (DF1b) is cured and maintained, and the light-irradiated area can be removed. Accordingly, a pattern can be formed by the cured first film (DF1b).

[0144] Referring to FIG. 12, a via metal layer (121b') may be formed corresponding to the pattern of the first film (DF1b). The via metal layer (121b') may be formed by various methods. For example, the via metal layer (121b') may be formed by various methods such as electroplating, deposition, and filling. The via metal layer (121b') may correspond to the above-described via metal layer.

[0145] Referring to Figure 13, the patterned first film can be removed. Various methods can be applied to remove this film. After removal, various etching processes can be applied to remove any remaining film.

[0146] Referring to Fig. 14, a first build-up layer (111') can be formed on a third build-up layer (113). The first build-up layer (111') can cover a via metal layer (121b').

[0147] Referring to FIG. 15, planarization of the first build-up layer (111) may be performed. Planarization may be performed using various methods such as chemical polishing, mechanical polishing, and etching. Accordingly, the thickness of the first build-up layer may be reduced compared to before. Accordingly, the via metal layer (121b') may protrude above the upper surface of the first build-up layer (111). In addition, a seed layer (ML1') may be formed on the upper surface of the first build-up layer (111). The seed layer (ML1') may include various metal materials. For example, the seed layer (ML1') may include copper (Cu), titanium (Ti), or the like. The seed layer (ML1') may correspond to the first metal layer described above.

[0148] Referring to FIG. 16, a second film (DF2) may be formed on the first build-up layer (111). The second film (DF2) may have a pattern as described above. This pattern may correspond to the first wiring portion.

[0149] Referring to FIGS. 17 and 18, chemical plating (electroless plating) may be performed on the seed layer (ML1') corresponding to the pattern of the second film (DF2). Accordingly, the first metal layer described above may be formed. Furthermore, a second metal layer may be formed after forming the first metal layer. The second metal layer may be formed by electroplating. The first metal layer may be in contact with the outer surface and the upper surface of the via metal layer. And the second metal layer may be located on the upper surface of the first metal layer. And the second film (DF2) may be removed. At this time, when removing the second film (DF2), the etching rates for the first metal layer and the second metal layer may be different. For example, even if the first metal layer and the second metal layer are the same material, their crystal grains may be different. For example, the first metal layer may have a larger porosity than the second metal layer. By this configuration, a first groove can be formed on the outer surface of the first metal layer as described above.

[0150] Furthermore, a second build-up layer can be laminated on the first build-up layer (111). And, like the first electrode portion, a second electrode portion can be formed on the second build-up layer.

[0151] Through this process, circuit boards can be manufactured.

[0152] Fig. 19 is a cross-sectional view of a circuit board according to the second embodiment, Fig. 20 is an enlarged view of part K3 in Fig. 19, and Fig. 21 is a plan view of a first metal layer and a via metal layer in a circuit board according to the second embodiment.

[0153] Referring to FIGS. 19 to 21, a circuit board (100A) according to the second embodiment may include an insulating layer (110) and an electrode portion (120). In addition, the circuit board (100A) may include a first build-up structure (BT1) and a second build-up structure (BT2). Furthermore, the circuit board (100) may further include a protective layer or the like disposed on the electrode portion (120).

[0154] In this example, the circuit board (100A) may have a coreless structure as illustrated, or may include a core layer as described above. In addition, the configuration described in the embodiments of the present invention may be applied equally, except for the contents described below.

[0155] As described above, the via metal layer (ML0) penetrates the first build-up layer (111) and may be positioned adjacent to the upper surface (US2) of the second build-up layer (112) relative to the upper surface of the first build-up layer (111).

[0156] In addition, at least a portion of the via metal layer (ML0) may be positioned on the upper surface (US1) of the first build-up layer (111). Accordingly, the via metal layer (ML0) may penetrate the first build-up layer (111) and may not overlap at least a portion of the via metal layer (ML0) with the first build-up layer (111) in the horizontal direction (X-axis direction). The via metal layer (ML0) may include a first via metal layer (ML0a) and a second via metal layer (ML0b) corresponding to the first via electrode (121b). The second via metal layer (ML0b) may be positioned on the first via metal layer (ML0a) and on the first build-up layer (111). Accordingly, the first via metal layer (ML0a) may overlap the first build-up layer (111) in the horizontal direction (X-axis direction). The second via metal layer (ML0b) may not overlap the first build-up layer (111) in the horizontal direction (X-axis direction).

[0157] And in this example, the first build-up layer (111) may include a second groove (G2) surrounding an outer surface of the via metal layer (ML0) (or the second via metal layer). The second groove (G2) may be located on an upper surface (US1) of the first build-up layer (111). And the second groove (G2) may surround an outer surface (ESa) of the via metal layer (ML0) (or the second via metal layer) and may be in contact with the outer surface (ESa). In addition, the second groove (G2) may be arranged along an edge of the via metal layer (ML0) (or the second via metal layer). The first metal layer (ML1) and the second metal layer (ML2) may be located in the second groove (G2).

[0158] And the second groove (G2) may be located on the inner side of the first groove (G1). That is, the second groove (G2) and the first groove (G1) may be sequentially located on the outer side based on the via metal layer (ML0).

[0159] A second metal layer (ML2) may be positioned in the second groove (G2). Accordingly, at least a portion of the second metal layer (ML2) may overlap the first build-up layer (111) in the horizontal direction (X-axis direction). At least a portion of the second metal layer (ML2) may overlap the via metal layer (ML0) in the horizontal direction (X-axis direction).

[0160] And the first via electrode (121b) (or the first via metal layer) may include a first portion (P1) and a second portion (P2). The first portion (P1) may be positioned below the second portion (P2). The second portion (P2) may be positioned above the first portion (P1) in the stacking direction (Y-axis direction).

[0161] The width (Wc) of the first portion (P1) can be maintained constant along the vertical direction (Y-axis direction). For example, the width (Wc) of the first portion (P1) can be maintained in a range of 10% or less, preferably 5% or less, along the vertical direction (Y-axis direction).

[0162] The second portion (P2) may have an increasing width (Wd) along the stacking direction (Y-axis direction). For example, the second portion (P2) may have an increasing width from the first build-up structure toward the second build-up structure along the stacking direction (Y-axis direction).

[0163] Additionally, the second portion (P2) may have a width (Wd) greater than the width (Wc) of the first portion (P1) at least in some portions. Furthermore, the second portion (P2) may have a curved outer surface.

[0164] And in the embodiment, the first portion (P1) may be formed only by an electroplating layer. The second portion (P2) may include both an electroplating layer and a chemical plating layer. For example, the second portion (P2) may include a second via metal layer (ML0b) and a portion of the first metal layer (ML1). For example, the second portion (P2) may include a third region (AR3) described below.

[0165] In addition, the first metal layer (ML1) may include a first region (AR1), a second region (AR2), and a third region (AR3). The first region (AR1) may be disposed between the upper surface (US1) of the first build-up layer (111) and the upper surface (USa) of the via metal layer (ML0). In addition, the first region (AR1) may be positioned below the upper surface (USa) of the via metal layer (ML0) and may be in contact with the outer surface of the via metal layer (ML0). Accordingly, the first region (AR1) may be positioned between the upper surface (US1) and the lower surface of the first build-up layer (111). In addition, the first region (AR1) may be partially positioned on the outer surface of the via metal layer (ML0). For example, the 1-1 region (AR1a) may be positioned on the outer side of the second groove (G2). And the first-second region (AR1b) may be positioned to overlap the second groove (G2) in the vertical direction (Y-axis direction). Furthermore, the first-first region (AR1a) and the first-second region (AR1b) may be spaced apart from each other in the horizontal direction. And the upper surface of the first-second region (AR1b) may be positioned above the upper surface of the first-first region (AR1a). And the first-first region (AR1a) may be in contact with the third region (AR3), and the first-second region (AR1b) may be in contact with the third region (AR3) and the second region (AR2).

[0166] The first region (AR1) may overlap the via metal layer (ML0) in the horizontal direction (X-axis direction). The second region (AR2) may be disposed on the upper surface (USa) of the via metal layer (ML0).

[0167] And the third region (AR3) can be located between the first region (AR1) and the second region (AR2). The third region (A3) can be located in an area between the first region (AR1) and the second region (AR2) in the horizontal direction (X-axis direction). In addition, the third region (AR3) can be located between the 1-1 region (AR1a) and the 1-2 region (AR1b). One end of the third region (AR3) can be in contact with the 1-1 region (AR1a), and the other end can be in contact with the 1-2 region (AR1b).

[0168] The third region (AR3) may correspond to the second groove (G2). Furthermore, the third region (AR3) may be located in the second groove (G2). That is, the third region (AR3) may correspond to the first metal layer (ML1) accommodated in the second groove (G2).

[0169] Accordingly, the third region (AR3) may be positioned lower than the first region (AR1) and the second region (AR2). In addition, the third region (AR3) may be positioned adjacent to the lower surface of the first build-up layer (111) compared to the first region (AR1) and the second region (AR2).

[0170] Additionally, the first region (AR1) may be located between the second region (AR2) and the third region (AR3) in the stacking direction (Y-axis direction).

[0171] By this configuration, the contact area between the first via electrode and the first wiring portion can be significantly increased, thereby significantly improving the mechanical strength of the electrode portion. Furthermore, depending on the contact area between the first via electrode and the first wiring portion, the electrical characteristics of the circuit board, such as signal integrity, can be improved. Furthermore, the bonding area between the build-up layer and the electrode portion can also be increased, thereby further improving the reliability of the circuit board.

[0172] In addition, the overlapping region (OV1) in the stacking direction (Y-axis direction) between the first region (AR1) and the third region (AR3) may be located in the outer region of the via metal layer (ML0). In addition, the overlapping region (OV2) in the stacking direction (Y-axis direction) between the third region (AR3) and the second region (AR2) may be located on the inner side of the overlapping region (OV1) described above. The overlapping region (OV2) in the stacking direction (Y-axis direction) between the third region (AR3) and the second region (AR2) may overlap with the second groove (G2) in the stacking direction (Y-axis direction). In addition, the overlapping regions (OV1, OV2) may be located on the inner side of the outer surface (ESb) of the first metal layer (ML1).

[0173] In addition, the surface (ESa) of the outer surface of the via metal layer (121a) exposed to the first build-up layer (111) may be located lower than the upper surface of the first build-up layer (111). In addition, the second groove (G2) may also be located closer to the via metal layer (ML0) than the first groove (G1) at the lower portion of the first groove (G1). As a result, the reliability of the electrode portion and the reliability between the build-up layer and the electrode portion can both be improved.

[0174] Figures 22 to 32 are drawings explaining a method for manufacturing a circuit board according to the second embodiment.

[0175] First, referring to Fig. 22, a build-up layer or core layer for forming a build-up layer and an electrode portion can be first prepared. Hereinafter, the third build-up layer (113) and the third wiring portion (123a) formed on the third build-up layer (113) will be described as standard.

[0176] Referring to FIG. 23, a third film (DF3) may be formed on the third build-up layer (113) and the third wiring portion (123a). For example, the third film (DF3) may be a dry film. In addition, the third film (DF3) may include various masks for masking. Furthermore, lamination may be performed on the third film (DF3) on the third build-up layer (113). For example, the third film (DF3) may be attached to the build-up layer using heat and pressure. Before such lamination, cleaning may be performed on the surface of the build-up layer, etc. In addition, removal of air bubbles, etc. may be performed after lamination.

[0177] Referring to Figure 24, light can be irradiated onto the third film (DF3). This irradiation of light can form a desired pattern. For example, when light is irradiated onto the third film (DF3), a pattern can be formed using various methods. The pattern can be formed using a positive or negative method.

[0178] For example, light may be irradiated to a desired area (DF3a) on the third wiring section (123a). And light may not be irradiated to the remaining area (DF3b).

[0179] Referring to Fig. 25, the light-irradiated area (DF3a) is cured and maintained, and the light-irradiated area can be removed. Accordingly, a pattern can be formed by the cured third film (DF3a).

[0180] Referring to FIG. 26, a first build-up layer (111') can be formed on a third build-up layer (113). The first build-up layer (111') can cover a via metal layer (121b').

[0181] Referring to Fig. 27, the first build-up layer (111) may be planarized. Planarization may be accomplished using various methods, such as chemical polishing, mechanical polishing, and etching. Accordingly, the thickness of the first build-up layer may be reduced compared to the previous one.

[0182] Referring to Figure 28, the patterned third film can be removed. Various methods can be applied to remove this film. After removal, various etching processes can be applied to remove any remaining film. At this time, when the third film is removed, a second groove can be formed on the first build-up layer (111).

[0183] Referring to FIG. 29, a seed layer (ML1') may be formed on the upper surface of the first build-up layer (111). The seed layer (ML1') may include various metal materials. For example, the seed layer (ML1') may include copper (Cu), titanium (Ti), or the like.

[0184] Additionally, a fourth film (DF4) may be formed on the first build-up layer (111). The fourth film (DF4) may have a pattern as described above. This pattern may correspond to the first wiring portion.

[0185] Referring to FIG. 30, a via metal layer (121b') may be formed corresponding to the pattern of the third film. The via metal layer (121b') may protrude above the upper surface of the first build-up layer (111). In addition, the via metal layer (121b') may be formed by various methods. For example, the via metal layer (121b') may be formed by various methods such as electroplating, deposition, and peeling.

[0186] And, chemical plating (Electroless Plating) can be performed on the seed layer (ML1') corresponding to the pattern of the fourth film (DF4). Accordingly, the above-mentioned first metal layer can be formed. Furthermore, a second metal layer can be formed after forming the first metal layer. The second metal layer can be formed by electroplating. The first metal layer can be in contact with the outer surface and the upper surface of the via metal layer. And, the second metal layer can be located on the upper surface of the first metal layer.

[0187] Referring to FIGS. 31 and 32, the fourth film (DF4) may be removed. At this time, the etching rates for the first metal layer and the second metal layer may be different when removing the fourth film (DF4). For example, even if the first metal layer and the second metal layer are made of the same material, their crystal grains may be different. For example, the first metal layer may have a larger porosity than the second metal layer. By this configuration, as described above, a first groove may be formed on the outer surface of the first metal layer. The first groove may be located outside the second groove described above.

[0188] Furthermore, a second build-up layer can be laminated on the first build-up layer (111). And, like the first electrode portion, a second electrode portion can be formed on the second build-up layer.

[0189] Through this process, circuit boards can be manufactured.

[0190] Fig. 33 is a cross-sectional view showing a semiconductor package according to the first embodiment, Fig. 34 is a cross-sectional view showing a semiconductor package according to the second embodiment, Fig. 35 is a cross-sectional view showing a semiconductor package according to the third embodiment, and Fig. 36 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0191] In the various semiconductor packages described below, the circuit board described above may be located in some area or may correspond to one substrate.

[0192] Referring to FIG. 33, the semiconductor package of the first embodiment may include a first substrate (1100), a second substrate (1200), and a semiconductor element (1300).

[0193] The first substrate (1100) may mean or include a 'package substrate' or a 'circuit substrate'. For example, the first substrate (1100) may provide a space to which at least one external substrate is coupled. The external substrate may mean a second substrate (1200) coupled on the first substrate (1100). In addition, the external substrate may mean a main board included in an electronic device coupled to a lower portion of the first substrate (1100).

[0194] Additionally, although not shown in the drawing, the first substrate (1100) can provide a space in which at least one semiconductor element is mounted.

[0195] The first substrate (1100) may include at least one insulating layer and an electrode portion disposed on at least one insulating layer.

[0196] A second substrate (1200) may be placed on the first substrate (1100).

[0197] The second substrate (1200) may be an interposer. For example, the second substrate (1200) may provide a space in which at least one semiconductor element is mounted. The second substrate (1200) may be connected to at least one semiconductor element (1300). For example, the second substrate (1200) may provide a space in which a first semiconductor element (1310) and a second semiconductor element (1320) are mounted. The second substrate (1200) may electrically connect the first semiconductor element (1310) and the second semiconductor element (1320), and electrically connect the first and second semiconductor elements (1310, 1320) and the first substrate (1100). That is, the second substrate (1200) may perform a horizontal connection function between a plurality of semiconductor elements and a vertical connection function between the semiconductor element and the package substrate.

[0198] In addition, although the above-described example illustrates two semiconductor elements (1310, 1320) being arranged on the second substrate (1200), the present invention is not limited thereto. For example, one semiconductor element may be arranged on the second substrate (1200), or alternatively, three or more semiconductor elements may be arranged.

[0199] A second substrate (1200) may be placed between at least one semiconductor element (1300) and the first substrate (1100).

[0200] In one embodiment, the second substrate (1200) may be an active interposer that functions as a semiconductor device. When the second substrate (1200) functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first substrate (1100) and may function as a plurality of logic chips. Having the function of a logic chip may mean having the functions of an active device and a passive device. In the case of an active device, unlike a passive device, the characteristics of current and voltage may not be linear, and in the case of an active interposer, it may function as an active device. In addition, the active interposer may perform the function of a corresponding logic chip while performing a signal transmission function between a second logic chip disposed thereon and the first substrate (1100).

[0201] In another embodiment, the second substrate (1200) may be a passive interposer. For example, the second substrate (1200) may function as a signal relay between the semiconductor device (1300) and the first substrate (1100), and may have a passive device function such as a resistor, a capacitor, or an inductor. For example, the number of terminals in the semiconductor device (1300) is gradually increasing due to reasons such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed. That is, the number of terminals provided in the semiconductor device (1300) is increasing, and as a result, the width of the terminals or the spacing between the plurality of terminals is decreasing. At this time, the first substrate (1100) may be connected to the main board of the electronic device. Accordingly, in order for the electrodes provided on the first substrate (1100) to have a width and spacing for connection with the semiconductor element (1300) and the main board, respectively, there is a problem that the thickness of the first substrate (1100) increases or the layer structure of the first substrate (1100) becomes complicated. Therefore, in the first embodiment, a second substrate (1200) can be placed on the first substrate (1100) and the semiconductor element (1300). In addition, the second substrate (1200) can include electrodes having a micro width and spacing corresponding to the terminals of the semiconductor element (1300).

[0202] The semiconductor device (1300) may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. The memory chip may be a stack memory such as HBM.

[0203] Meanwhile, the semiconductor package of the first embodiment may include a connecting portion.

[0204] For example, a semiconductor package may include a first connection portion (1410) disposed between a first substrate (1100) and a second substrate (1200). The first connection portion (1410) may electrically connect the second substrate (1200) to the first substrate (1100) while bonding them thereto.

[0205] For example, the semiconductor package may include a second connection portion (1420) disposed between a second substrate (1200) and a semiconductor element (1300). The second connection portion (1420) may electrically connect the semiconductor element (1300) while bonding them to the second substrate (1200).

[0206] The semiconductor package may include a third connector (1430) disposed on the lower surface of the first substrate (1100). The third connector (1430) may electrically connect the first substrate (1100) to the main board while connecting them therebetween.

[0207] At this time, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can electrically connect the plurality of components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) have the function of electrically connecting the plurality of components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as a part that is electrically connected rather than solder or wire.

[0208] The wire bonding method may refer to electrically connecting a plurality of components using a conductor such as gold (Au). In addition, the solder bonding method may electrically connect a plurality of components using a material including at least one of Sn, Ag, and Cu. In addition, the direct metal-to-metal bonding method may refer to directly bonding a plurality of components by applying heat and pressure between the plurality of components to recrystallize them without the use of solder, wires, conductive adhesives, etc. In addition, the direct metal bonding method may refer to a bonding method using a second connection portion (1420). In this case, the second connection portion (1420) may refer to a metal layer formed between the plurality of components by recrystallization.

[0209] Specifically, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the plurality of components by applying heat and pressure to the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430).

[0210] At this time, in at least one of the first substrate (1100) and the second substrate (1200), the electrodes on which the first connection portion (1410), the second connection portion (1420) and the third connection portion (1430) are arranged may be provided with a protrusion that protrudes outward away from the insulating layer of the corresponding substrate. The protrusion may protrude outward from the first substrate (1100) or the second substrate (1200).

[0211] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode on which a second connection portion (1420) for coupling with a semiconductor element (1300) is arranged among the electrodes of the second substrate (1200). That is, as the pitch of the terminals of the semiconductor element (1300) becomes finer, a short circuit may occur between the plurality of second connection portions (1420) that are respectively connected to the plurality of terminals of the semiconductor element (1300) by a conductive adhesive such as solder. Therefore, in the embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portion (1420). Accordingly, the embodiment may include a protrusion in the electrode of the second substrate (1200) on which the second connecting portion (1420) is arranged to secure a degree of alignment, diffusion, and diffusion-preventing ability to prevent an intermetallic compound (IMC) formed between a conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the substrate.

[0212] Additionally, looking further into FIG. 33, the semiconductor package of the first embodiment may further include a connecting member (1210).

[0213] The connecting member (1210) may be referred to as a bridge substrate. For example, the connecting member (1210) may include a redistribution portion. The connecting member (1210) may have a function of horizontally electrically connecting a plurality of semiconductor devices to each other. For example, since the area that a semiconductor device should have is generally too large, the connecting member (1210) may include a redistribution portion. Since the semiconductor package and the semiconductor device have a large difference in the width or width of the circuit pattern, etc., a buffering function of the circuit pattern for electrical connection is required. The buffering function may mean having a size between the width or width of the circuit pattern of the semiconductor package and the width or width of the circuit pattern of the semiconductor device, and the redistribution portion may include a function of performing a buffering function.

[0214] In an embodiment, the connecting member (1210) may be an organic bridge. For example, the connecting member (1210) may include an organic material. For example, the connecting member (1210) may include an organic substrate instead of a silicon substrate. The connecting member (1210) may be embedded within the second substrate (1200).

[0215] To this end, the second substrate (1200) may include a cavity, and a connecting member (1210) may be placed within the cavity of the second substrate (1200). The connecting member (1210) may horizontally connect a plurality of semiconductor elements placed on the second substrate (1200).

[0216] Referring to FIG. 34, the semiconductor package of the second embodiment may include a second substrate (1200) and a semiconductor element (1300). At this time, the semiconductor package of the second embodiment may have a structure in which the first substrate (1100) is omitted compared to the semiconductor package of the first embodiment.

[0217] That is, the second substrate (1200) of the second embodiment can function as a package substrate while also functioning as an interposer.

[0218] The first connecting portion (1410) arranged on the lower surface of the second substrate (1200) can connect the second substrate (1200) to the main board of the electronic device.

[0219] Referring to FIG. 35, the semiconductor package of the third embodiment may include a first substrate (1100) and a semiconductor element (1300).

[0220] At this time, the semiconductor package of the third embodiment may have a structure in which the second substrate (1200) is omitted compared to the semiconductor package of the first embodiment.

[0221] That is, the first substrate (1100) of the third embodiment can function as a package substrate while also connecting a semiconductor element (1300) and a main board. To this end, the first substrate (1100) can include a connecting member (1110) for connecting a plurality of semiconductor elements. The connecting member (1110) can be an organic bridge connecting a plurality of semiconductor elements.

[0222] Referring to FIG. 36, the semiconductor package of the fourth embodiment may further include a third semiconductor element (1330) compared to the semiconductor package of the fourth embodiment. To this end, a fourth connecting portion may be further arranged on one surface of the first substrate (1100).

[0223] In this way, the semiconductor package of the fourth embodiment may have a structure in which semiconductor elements are mounted on the upper and lower sides, respectively. In this case, the third semiconductor element (1330) may have a structure in which it is placed on the lower surface of the second substrate (1200) in the aforementioned circuit board or semiconductor package.

[0224] And a connecting member (1110) can be embedded in the first substrate (1100). The connecting member (1110) can horizontally connect the first and second semiconductor elements (1310, 1320).

[0225] Additionally, the first substrate (1100) may include a conductive coupling portion (1450). The conductive coupling portion (1450) may further protrude from the first substrate (1100) toward the second semiconductor element (1320). The conductive coupling portion (1450) may be referred to as a bump, or alternatively, as a post. The conductive coupling portion (1450) may be positioned with a protruding structure on an electrode positioned on the uppermost side of the first substrate (1100).

[0226] A third semiconductor element (1330) may be placed on the conductive joint (1450). At this time, the third semiconductor element (1330) may be connected to the first substrate (1100) through the conductive joint (1450). In addition, a second connection (1420) may be placed between the first and second semiconductor elements (1310, 1320) and the third semiconductor element (1330).

[0227] Accordingly, the third semiconductor element (1330) can be electrically connected to the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0228] That is, the third semiconductor element (1330) can be connected to the first substrate (1100) through the conductive joint (1450), and can also be connected to the first and second semiconductor elements (1310, 1320) through the second connection (1420).

[0229] At this time, the third semiconductor element (1330) can receive a power signal and / or electric power through the conductive coupling portion (1450). In addition, the third semiconductor element (1330) can exchange communication signals with the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0230] The semiconductor package of the fourth embodiment can provide sufficient power for driving the third semiconductor element (1330) or enable smooth control of power operation by supplying a power signal and / or power to the third semiconductor element (1330) through the conductive coupling portion (1450).

[0231] Accordingly, the embodiment can improve the driving characteristics of the third semiconductor element (1330). That is, the embodiment can solve the problem of insufficient power provided to the third semiconductor element (1330). Furthermore, the embodiment can provide at least one of the power signal, power, and communication signal of the third semiconductor element (1330) through different paths via the conductive coupling portion (1450) and the second connection portion (1420). Through this, the embodiment can solve the problem of loss of the communication signal caused by the power signal. For example, the embodiment can minimize mutual interference between the power signal and the communication signal.

[0232] Meanwhile, the third semiconductor element (1330) in the fourth embodiment may have a POP (Package On Package) structure in which a plurality of package substrates are stacked and may be placed on the first substrate (1100). For example, the third semiconductor element (1330) may be a memory package including a memory chip. And the memory package may be coupled on the conductive joint (1450). At this time, the memory package may not be connected to the first and second semiconductor elements (1310, 1320).

[0233] Furthermore, the semiconductor package of the modified example may include the first substrate (1100) and first and second semiconductor elements (1310, 1320) arranged on the first substrate (1100) as in the above-described example. Furthermore, the semiconductor package may include a first connection portion (1410) arranged between the first substrate (1100) and the first and second semiconductor elements (1310, 1320). That is, the semiconductor package may have a structure in which the second substrate and the second connection portion are omitted in the above-described example.

[0234] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0235] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of terminals supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0236] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of terminals supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0237] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0238] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. A first build-up structure including a plurality of insulating layers stacked along a vertical direction, a plurality of wiring portions arranged on one surface of each of the plurality of insulating layers, and a plurality of via electrodes connecting the plurality of wiring portions along the vertical direction; and A second build-up structure including a plurality of insulating layers arranged on the first build-up structure and stacked along a vertical direction, a plurality of wiring portions arranged on one surface of each of the plurality of insulating layers, and a plurality of via electrodes connecting the plurality of wiring portions along the vertical direction, The plurality of insulating layers of the first build-up structure are different from the plurality of insulating layers of the second build-up structure, The plurality of via electrodes of the first build-up structure include via electrodes that are inclined so that their widths vary along the vertical direction, A circuit board comprising at least one of a plurality of via electrodes of the second build-up structure, the first portion having a constant width along the vertical direction, and a second portion having a curved surface disposed on the first portion and widening in the width in the direction from the first build-up structure toward the second build-up structure.

2. In paragraph 1, The above second build-up structure is, 1st build-up layer; A second build-up layer disposed on the first build-up layer; A first electrode portion including a first wiring portion arranged on the first build-up layer and a first via electrode penetrating the first build-up layer; and A circuit board comprising a second wiring portion arranged on the second build-up layer and a second electrode portion including a second via electrode penetrating the second build-up layer.

3. In paragraph 2, A circuit board comprising: the first electrode portion; a via metal layer; a first metal layer disposed on the via metal layer; and a second metal layer disposed on the first metal layer.

4. In paragraph 3, A circuit board comprising a first via metal layer horizontally overlapping the first build-up layer and a second via metal layer positioned on an upper surface of the first build-up layer.

5. In paragraph 3, A circuit board in which the upper surface of the above via metal layer is positioned adjacent to the upper surface of the second build-up layer compared to the upper surface of the first build-up layer.

6. In paragraph 3, The first metal layer comprises a first region disposed between the upper surface of the via metal layer and the upper surface of the via metal layer; A second region disposed on the upper surface of the via metal layer; and A circuit board comprising a third region disposed between the first region and the second region.

7. In paragraph 6, A circuit board in which the first region is located on the outer side of the via metal layer and is in contact with the outer surface of the via metal layer.

8. In paragraph 6, A circuit board including a first groove concave inwardly on an outer surface thereof, wherein the first region is a first region.

9. In paragraph 8, A circuit board in which the first groove is positioned at the edge of the first metal layer.

10. In paragraph 8, A circuit board in which the first groove overlaps the second metal layer in the lamination direction.

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