Circuit board and semiconductor package comprising same

Abstract

Disclosed in an embodiment is a circuit board comprising: a core layer; an upper build-up layer including a first build-up layer and a second build-up layer, which are arranged on the core layer in a stacking direction; a connection member arranged on the first build-up layer; a second build-up layer arranged on the first build-up layer and covering the connection member; a first electrode part arranged on the first build-up layer; and a second electrode part arranged on the second build-up layer, wherein the second electrode part overlaps the bottom surface of the connection member in the horizontal direction.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to mount more semiconductor chips on a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices such as mobile devices, servers, and PCs, along with the adoption of High Bandwidth Memory (HBM), have led to larger semiconductor chip areas and the attachment of multiple semiconductor chips to a single package substrate to shorten the electrical connection distance between them, thereby increasing the size of the package. Furthermore, as the functions required for application processors increase, there is a growing need for separate processor chips for each function, and circuit boards capable of mounting these processor chips are required.

[0005] At this time, for the above application processor, even when it is separated into two processor chips by function, the number of terminals (Input / Output) provided in each processor chip is increasing.

[0006] Furthermore, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and faster communication speeds, the number of terminals on processor chips is steadily increasing due to the increase in power and signal capacity. Consequently, the area, thickness, and circuit pattern density of circuit boards are also increasing. Furthermore, increased circuit board area and thickness can make product miniaturization difficult, leading to reliability issues such as board warping and increased product price.

[0007] Furthermore, there is a recent trend toward thicker core layers on circuit boards to prevent issues such as board warpage. However, utilizing thick core layers can lead to difficulties in forming via electrodes on the core layer, such as yield, via electrode spacing density, and productivity. Furthermore, to enhance process efficiency, components such as bridges are mounted within the build-up layer rather than the core layer, thereby reducing manufacturing difficulty.

[0008] However, when embedding elements such as bridges, the manufacturing process is complicated due to etching of the build-up layer, the input / output count is reduced, and there are problems such as peeling at the interface between the build-up layers.

[0009] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, in which a connecting member is embedded as an interposer, and an input / output count is improved when electrically connecting between an upper element and the connecting member, and a reliability deterioration occurring at the interface of the build-up layer is prevented by eliminating etching of the build-up layer for embedding the connecting member.

[0010] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved reliability by suppressing cracks or peeling caused by stress imbalance based on thermal expansion difference even though the thickness of the build-up layer in which the connecting member is embedded in the upper build-up layer is the largest through the structure of the via electrode and the material and thickness of each layer.

[0011] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, in which electrical reliability is improved by accurately implementing electrical connections through the thickness of the via electrode, and plating defects or defects are suppressed depending on the degree of inclination of the via electrode.

[0012] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0013] A circuit board according to an embodiment of the present invention includes a core layer; an upper build-up layer including a first build-up layer and a second build-up layer arranged in a stacking direction on the core layer; a connecting member arranged on the first build-up layer; a second build-up layer arranged on the first build-up layer and covering the connecting member; a first electrode portion arranged on the first build-up layer; and a second electrode portion arranged on the second build-up layer, wherein the second electrode portion horizontally overlaps a lower surface of the connecting member.

[0014] The second build-up layer may have the largest thickness in the upper build-up layer.

[0015] The thickness of the second build-up layer may be greater than the thickness of the connecting member.

[0016] It may include a first protective layer disposed on the upper build-up layer; a lower build-up layer disposed under the core layer; and a second protective layer disposed on the lower build-up layer.

[0017] At least one of the plurality of build-up layers of the lower build-up layer and the second protective layer may include a photocurable material.

[0018] The second electrode portion may include a second wiring portion disposed on the second build-up layer and a second via electrode including a second-1 via electrode and a second-2 via electrode penetrating the second build-up layer.

[0019] The above-mentioned 2-1 via electrode can overlap the above-mentioned connecting member in the horizontal direction.

[0020] The above-mentioned 2-2 via electrode can be electrically connected to the above-mentioned connecting member.

[0021] The outer surface of the above-mentioned 2-1 via electrode may have a concave groove.

[0022] The outer surface of the 2-1 via electrode may have a first inclination angle with respect to the lower surface of the 2-1 via electrode, and the outer surface of the 2-2 via electrode may have a second inclination angle with respect to the lower surface of the 2-2 via electrode.

[0023] The area on the lower surface of the above 2-1 via electrode may be different from the area on the lower surface of the above 2-2 via electrode.

[0024] The above 2-1 via electrode may include a first sub-via electrode and a second sub-via electrode disposed on the first sub-via electrode and having a different inclination angle from the outer surface of the first sub-via electrode.

[0025] The above second sub-via electrode may have the same inclination angle with respect to the lower surface as the above second-2 via electrode.

[0026] The thickness of the second sub-via electrode may be the same as the thickness of the second-2 via electrode.

[0027] The thickness of the first sub-via electrode may be greater than the thickness of the second sub-via electrode.

[0028] The second build-up layer may include a plurality of sub-build-up layers.

[0029] The plurality of sub-build-up layers may include a first sub-build-up layer and a second sub-build-up layer disposed on the first sub-build-up layer.

[0030] The second via electrode may have a protrusion or step protruding outward from the boundary between the first sub-build-up layer and the second sub-build-up layer.

[0031] The first electrode portion may include a first via electrode penetrating the first build-up layer and a first wiring portion disposed on the first build-up layer.

[0032] The thickness of the above-mentioned 2-1 via electrode may be greater than the thickness of the above-mentioned 2-2 via electrode.

[0033] An embodiment of the present invention embeds a connecting member as an interposer, improves input / output counts when electrically connecting between an upper element and the connecting member, and prevents reliability degradation occurring at the interface of the build-up layer by eliminating etching of the build-up layer for embedding the connecting member, thereby implementing a circuit board and a semiconductor package including the same.

[0034] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved reliability by suppressing cracks or peeling caused by stress imbalance based on thermal expansion difference even though the thickness of the build-up layer in which the connecting member is embedded in the upper build-up layer is the largest through the structure of the via electrode and the material and thickness of each layer.

[0035] In addition, the embodiment can implement a circuit board and a semiconductor package including the same in which electrical reliability is improved by accurately implementing electrical connection through the thickness of the via electrode and plating defects or defects are suppressed depending on the degree of inclination of the via electrode.

[0036] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0037] Figure 1 is a plan view of a package substrate according to an embodiment of the present invention.

[0038] Figure 2 is a perspective view of a package substrate according to an embodiment of the present invention;

[0039] Figure 3 is a drawing taken along line II' in Figure 1,

[0040] Figure 4 is a cross-sectional view of a circuit board according to the first embodiment of the present invention.

[0041] Figure 5 is an enlarged view of K1 in Figure 4,

[0042] Figure 6 is an enlarged view of K2 in Figure 4,

[0043] Fig. 7 is another example of Fig. 5,

[0044] Fig. 8 is another example of Fig. 5,

[0045] Fig. 9 is another example of Fig. 5,

[0046] Fig. 10 is another example of Fig. 5,

[0047] Figures 11 to 16 are drawings explaining a method for manufacturing a circuit board according to the first embodiment.

[0048] Fig. 17 is a cross-sectional view of a circuit board according to the second embodiment,

[0049] Figure 18 is an enlarged view of K3 in Figure 17,

[0050] Fig. 19 is another example of Fig. 18,

[0051] Fig. 20 is a cross-sectional view of a circuit board according to the third embodiment,

[0052] Figures 21 to 25 are drawings explaining a method for manufacturing a circuit board according to the third embodiment.

[0053] Fig. 26 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0054] Fig. 27 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0055] Fig. 28 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0056] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0057] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0058] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0059] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0060] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0061] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “and (and) at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0062] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as a "first component," and similarly, a first component may also be referred to as a "second component." The terms "and / or" include a combination of multiple related items described herein or any of multiple related items described herein. These terms are only used to distinguish the component from other components and are not limited by the nature, order, or sequence of the component.

[0063] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0064] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0065] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0066] Additionally, the expression that configuration A is positioned between configurations B and C should also include the meaning that configuration A is positioned so that it overlaps configurations B and C at least partially in the horizontal and / or vertical directions.

[0067] Expressions referring to directions include horizontal directions, vertical directions, and include a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as a first horizontal direction (X-axis), a second horizontal direction (Y-axis), and a vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of overlapping along the horizontal direction should also include the meaning of overlapping along the first horizontal direction and / or overlapping along the second horizontal direction.

[0068] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0069] Furthermore, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood only as being in "direct contact" with a component B, it is described as being in "direct contact."

[0070] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0071] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0072] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may include a circuit board and semiconductor elements, and the semiconductor elements may be mounted on the circuit board.

[0073] A semiconductor device may include active components and / or passive components. An active component may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of components are integrated into a single chip. A semiconductor chip may be a logic chip, a memory chip, or the like. A logic chip may be a non-memory chip such as a central processor (CPU), a graphics processor (GPU), or a field programmable gate array (FPGA). For example, a logic chip may be an application processor (AP) chip that includes at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set that includes a specific combination of the above-mentioned components.

[0074] The memory chip may be a stacked memory such as HBM. Additionally, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0075] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0076] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0077] FIG. 1 is a plan view of a package substrate according to an embodiment of the present invention, FIG. 2 is a perspective view of a package substrate according to an embodiment of the present invention, and FIG. 3 is a view taken along line II' in FIG. 1.

[0078] Referring to FIGS. 1 to 3, a package substrate according to an embodiment may include a main substrate in addition to semiconductor elements (DI1, DI2) and a circuit substrate (100). For example, the main substrate may be an FPGA substrate. In particular, the circuit substrate according to the embodiment may be a substrate having a built-in connecting member.

[0079] The circuit board of the embodiment may include a first semiconductor element (DI1), a second semiconductor element (DI2), and a connecting member (BR). The first semiconductor element (DI1) and the second semiconductor element (DI2) may include a logic chip or a memory chip as described above. In addition, the first semiconductor element (DI1) and the second semiconductor element (DI2) may be different types of semiconductor elements as described above. In addition, the connecting member (BR) may be embedded in the circuit board (100). In particular, the connecting member (BR) may be embedded in the circuit board (100). The circuit board (100) may be applied with various examples of circuit boards described below.

[0080] Additionally, the connecting member (BR) may include an upper wiring (BE) that is in contact with the electrode portion at the upper portion. The upper wiring (BE) may be electrically connected to the upper electrode portion. In addition, the upper wiring (BE) may be electrically connected to the first semiconductor element and the second semiconductor element at the upper portion through the upper electrode portion, thereby acting as a bridge.

[0081] In addition, the circuit board may include a conductive member (SB) for connection between the first and second semiconductor elements and the electrode portions disposed on the upper portion of the circuit board (100), particularly on the upper build-up layer, which is the upper build-up layer. In addition, the circuit board may further include a conductive member (SB) disposed between a connection member (BR) other than the build-up layer and the first and second semiconductor elements. In addition, the connection member (BR) may electrically connect between at least two semiconductor elements. However, the following description will be given as performing an electrical connection between two semiconductor elements.

[0082] Additionally, an underfill (UF) may be positioned between the circuit board (100) and the first and second semiconductor elements (DI1, DI2). The underfill (UF) may cover the conductive member (SB).

[0083] And when the connecting member (BR) does not include a via electrode, the via electrode of the core layer of the circuit board (100) may not vertically overlap with the connecting member (BR). However, when the connecting member (BR) includes a via electrode, it may vertically overlap with the via electrode of the core layer of the circuit board (100) and be electrically connected. The via electrode of the build-up layer may vertically overlap with the connecting member (BR). Furthermore, the connecting member (BR) and the via electrode of the build-up layer may be electrically connected. In addition, the connecting member (BR) may at least partially vertically overlap with the first and second semiconductor elements (DI1, DI2).

[0084] In addition, as described above, the connecting member (BR) may be an organic or inorganic connecting member. For example, the connecting member (BR) may be an inorganic connecting member, and when the connecting member (BR) includes a via electrode, it may be advantageous in transmitting power from the circuit board (100) to the first and second semiconductor elements (DI1, DI2).

[0085] FIG. 4 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, FIG. 5 is an enlarged view of K1 in FIG. 4, FIG. 6 is an enlarged view of K2 in FIG. 4, FIG. 7 is another example of FIG. 5, FIG. 8 is another example of FIG. 5, FIG. 9 is another example of FIG. 5, and FIG. 10 is another example of FIG. 5.

[0086] Referring to FIG. 4, a circuit board (100) according to an embodiment may include an insulating layer (110), an electrode portion (120), and a connecting member (BR).

[0087] In an embodiment, the insulating layer (110) may be provided in a structure in which multiple insulating layers are laminated. The electrode portion (120) may be disposed by being embedded in each insulating layer of the multiple insulating layers (110), thereby performing the function of transmitting signals and / or power from a main board (not shown) to a semiconductor element.

[0088] Furthermore, when the circuit board includes a core layer, it may include a build-up insulating portion laminated on the core layer. Specifically, as illustrated, the circuit board (100) may include a core layer (111), build-up insulating portions (112, 113), a core electrode portion (121), and build-up electrode portions (122, 123). Furthermore, the circuit board (100) may further include a protective layer (SR) and a bonding portion (BP). In addition, in the following embodiments of the present invention, the build-up insulating portions (112, 113) may include a plurality of insulating layers and may be provided in a structure in which a plurality of insulating layers are laminated. The build-up electrode portions (122, 123) may be disposed by being embedded in each layer (e.g., insulating layer) of the build-up insulating portions (112, 113), thereby performing a function of transmitting signals and / or power from a main board (not illustrated) to a semiconductor element.

[0089] And when the circuit board includes a core layer, it may include a core layer disposed within an insulating layer (110). Accordingly, the insulating layer (110) of the circuit board may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). The upper build-up layer (112) may be located above the core layer (111). And the lower build-up layer (113) may be located below the core layer (111).

[0090] And the electrode section (120) can be composed of a via electrode and a wiring section as described later.

[0091] As an example, the insulation layer (110) may be formed of a core layer (111) which is a core layer, and a build-up insulation portion (112, 113) which is formed of at least one insulation layer disposed above and below the core layer (111). Accordingly, the build-up insulation portion (112, 113) laminated on the core layer may include a plurality of vertically laminated insulation layers. The build-up insulation portion may include an upper build-up layer (112) and a lower build-up layer (113). As illustrated, the upper build-up layer (112) may be disposed above the core layer (111), and the lower build-up layer (113) may be disposed below the core layer (111). The upper build-up layer and / or the lower build-up layer may each be formed by laminating a plurality of insulation layers. In addition, the build-up layer (or build-up insulation portion) may be referred to as a build-up structure or a build-up insulation portion, etc. The following description will be made based on this.

[0092] As an example, the insulating layer (110) may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). In addition, a protective layer (SR) may be further disposed on the outer side of the insulating layer (110). This will be described later.

[0093] And the upper build-up layer (112) may be an 'upper build-up structure'. The lower build-up layer (113) may be a 'lower build-up structure'. In the present embodiment, the core layer (111) may be arranged at the center in the vertical direction of the insulating layer (110). When the build-up layers are laminated on both sides of the core layer (111), the core layer (111) may be located at the center of the insulating layer (110). That is, the upper build-up layer (112) may be arranged on the core layer (111), and the lower build-up layer (113) may be located below the core layer (111).

[0094] And the insulating layer (110) of the circuit board (100) may be rigid or flexible. For example, the insulating layer (110) of the circuit board (100) may include glass or plastic. For example, the insulating layer (110) of the circuit board or each insulating layer constituting the insulating layer (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer (110) of the circuit board may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer (110) of the circuit board may include sapphire. For example, the insulating layer (110) of the circuit board may include an optically isotropic film. For example, the insulating layer (110) of the circuit board may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer (110) of the circuit board may be formed of a material including a filler and an insulating resin. For example, the insulating layer (110) of the circuit board may have a structure in which a filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

[0095] The insulating layer (110) may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure will be described in more detail as follows.

[0096] In one embodiment, the insulating layer (110) may include a core layer (111) including a reinforcing member. Here, the core layer (111) may include the reinforcing member and have a thickness in a vertical direction (Y-axis direction or lamination direction) of tens to hundreds of micrometers. In addition, the upper build-up layer (112) and the lower build-up layer (113) may be disposed on the upper and lower sides of the core layer (111), respectively, and may include a plurality of layers that do not include the reinforcing member. The reinforcing member may also be referred to as a reinforcing fiber or glass fiber embedded in the core layer. The reinforcing member may refer to a glass fiber material extending along the horizontal direction (X-axis direction) of the insulating layer, and may have a different meaning from a filler that is spaced apart from each other. For example, the insulating layer (110) may be composed of a resin, a filler, and a reinforcing member (e.g., glass fiber), or may be composed of a resin and a filler.

[0097] The core layer (111) may be made of various insulating materials. For example, the core layer (111) may be a part of a copper clad laminate (CCL). Alternatively, the core layer may correspond to the copper clad laminate. In addition, the core layer (111) may be made of multiple layers, and the multiple layers may be made of the same or different materials. Furthermore, the core layer (111) may include a via electrode penetrating the upper and lower surfaces of the core layer (111).

[0098] And the upper build-up layer (112) or the lower build-up layer (113) can be provided with any insulating resin such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin can be used. The above-mentioned arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material or reinforcing member provided with glass fiber or aramid fiber. For example, when manufacturing an insulating layer (110), ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. can be used. For example, when the circuit board (100) is coreless, the insulating layer (110) can be provided by laminating ABF without a core layer.

[0099] Furthermore, the upper build-up layer (112) may be formed of a plurality of insulating layers that contact the core layer (111). The plurality of insulating layers may be formed of fillers of different sizes. For example, the filler size may decrease toward the top of the plurality of insulating layers. In addition, an upper electrode portion having a smaller width or pitch toward the upper insulating layer may be arranged among the plurality of insulating layers.

[0100] In addition, the wiring or electrode portion (120) according to the embodiment is arranged for electrical connection between a main board, etc. and a chip (or semiconductor element, die), and the electrode portion (120) includes a wiring portion (circuit pattern or circuit pattern layer, pad, pattern portion) and a via portion (or via electrode).

[0101] For example, the wiring portion of the electrode portion (120) may include a pattern and a pad on the upper surface of the insulating layer. Hereinafter, the wiring portion is described interchangeably with the terms 'circuit pattern' and 'pattern portion'. In addition, the electrode portion (120) may include a via portion or a via electrode penetrating the insulating layer. Accordingly, in the embodiment, the electrode portion (120) is described below as including a wiring portion (circuit pattern) and a via electrode in each insulating layer. In addition, the wiring portion in the electrode portion (120) may be designed in various forms for transmitting signals and / or power to and from the semiconductor element, and is arranged in each insulating layer of the laminated build-up insulating portions (112, 113).

[0102] In the electrode section (120), a via electrode (or via section) is arranged to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns arranged on each insulating layer of the build-up insulating section (112, 113). The via electrode can connect a plurality of circuit patterns (wiring sections) to each other. The via electrode may also be formed in multiple pieces like the wiring section. That is, the insulating layer may include a via hole for arranging the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and may be freely designed.

[0103] In the electrode portion (120), a wiring portion (circuit pattern) may be arranged on each insulating layer. And the circuit pattern may be electrically connected to the circuit pattern. In addition, the wiring portion (circuit pattern) may be connected to each via electrode. And the circuit patterns arranged on the upper and lower surfaces of the insulating layer in the build-up insulating portion (112, 113) may be electrically connected to a semiconductor element and / or a main board or substrate, etc. For example, the electrode portion (120) may be located on each layer (insulating layer) of the core layer (111), the upper build-up layer (112), and the lower build-up layer (113).

[0104] In an embodiment, the electrode portion (120) may include a core electrode portion (121), an upper electrode portion (122), and a lower electrode portion (123). The upper electrode portion (122) and the lower electrode portion (123) may be build-up layer electrode portions. In addition, the upper electrode portion (122) is disposed in each insulating layer in the upper build-up layer (112) and may be an 'upper build-up layer electrode portion'. In addition, the lower electrode portion (123) is disposed in each insulating layer in the lower build-up layer (113) and may be a 'lower build-up wiring portion electrode'.

[0105] The core electrode portion (121) may include a core wiring portion (121a) arranged on the upper and lower surfaces of the core layer (111) and a core via electrode (121b) penetrating the core layer (111).

[0106] The upper electrode portion (122) may include an upper wiring portion (122a), which is a wiring portion arranged on the upper and lower surfaces of each insulating layer of the upper build-up layer (112), and an upper via electrode (122b), which is a via electrode. The upper via electrode (122b) may penetrate each insulating layer of the upper build-up layer (112).

[0107] Furthermore, the lower electrode portion (123) may include a lower wiring portion (123a), which is a wiring portion arranged on the upper and lower surfaces of the lower build-up layer (113), and a lower via electrode (123b), which is a via electrode. In addition, the lower via electrode (123b) may penetrate each insulating layer of the lower build-up layer (113).

[0108] And in the embodiment, the wiring portion of the upper electrode portion (and / or the lower electrode portion) may include a wiring portion having a fine pitch and a general wiring portion having a pitch larger than the fine wiring portion.

[0109] The general wiring section may refer to wiring having the same width and spacing as the circuit pattern used in a conventional circuit board, and the fine wiring section may refer to fine wiring having a width and spacing narrower than the width and spacing of the pattern used in a conventional circuit board for interconnection between semiconductor devices, impedance matching, or formation of an inductor. For example, the line width of the fine wiring section may be several micrometers (㎛) or less, or the pitch may be several tens of ㎛ or less. For example, the width of the fine wiring section may be 30 ㎛ or less. For example, the pitch of the fine wiring section may be 55 ㎛ or less. A detailed description thereof will be provided later.

[0110] Additionally, the circuit board (100) according to the first embodiment may further include a protective layer (SR) and a bonding portion (BP).

[0111] Specifically, the protective layer (SR) can have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when bonding between the semiconductor element and / or the main board and the circuit board, the protective layer (SR) can be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals can be arranged at a high density. When the plurality of terminals and the pads of the circuit board are bonded, solder can be used, for example. When solder is used, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist that does not have good wettability with the solder can be arranged to solve this short circuit problem. In addition, the protective layer (SR) can be formed of a material having insulating properties for electrical connection. The protective layer (SR) can include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the protective layer (SR) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. The protective layer (SR) may have at least one opening for connection between a terminal of a semiconductor device and a pad of a circuit board. For example, in an embodiment, the protective layer (SR) may be formed of a filler and a resin, which are reinforcing members.

[0112] A protective layer (SR) may be disposed on an insulating layer (110). The protective layer (SR) may include a plurality of fillers. Specifically, the protective layer (SR) may include a first protective layer (SR1) disposed on an upper build-up layer (112) and a second protective layer (SR2) disposed under a lower build-up layer (113). The first protective layer (SR1) and the second protective layer (SR2) may be disposed spaced apart from each other along a stacking direction and may have different thicknesses in consideration of warpage of the circuit board. Hereinafter, the protective layer will be described based on the first protective layer (SR1).

[0113] The bonding portion (BP) may be disposed on the protective layer (SR). For example, the bonding portion (BP) may be disposed on the upper surface of the protective layer (SR). The bonding portion (BP) may be located outside the build-up electrode portions (122, 123). For example, in the upper build-up layer (112), the bonding portion (BP) may be located on the upper surface of the build-up electrode portions (122, 123). In addition, the bonding portion (BP) may include a pad portion (PP) disposed on the upper surface of the protective layer (SR) and a via portion (TP) penetrating the protective layer (SR). In an embodiment, the via portion (TP) and the pad portion (PP) may each include a plurality of protrusions or convex portions protruding toward the adjacent protective layer (SR). For example, on the first protective layer (SR1), the via portion (TP) and the pad portion (PP) may include a plurality of protrusions (or convex portions) protruding toward the first protective layer (SR1).

[0114] Furthermore, a metal layer may be additionally disposed on the bonding portion (BP) and electrically connected. Accordingly, the durability and reliability of the bonding portion (BP) may be further improved. For example, the metal layer may be formed of at least one metal layer. The metal layer may be formed of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or a combination thereof. Accordingly, the bonding strength between the metal layer and the bonding portion (BP) is improved, the corrosion resistance and durability of the bonding portion (BP) are improved, and the loss of electrical signals may also be minimized. The metal layer may be formed on the bonding portion (BP) by deposition, electroplating, or the like of various metals.

[0115] In addition, a semiconductor element may be arranged on the upper build-up layer (112). The semiconductor element may be electrically connected to the aforementioned micro-pattern, such as a micro-wiring portion. The circuit board may be arranged to have a high wiring density for connecting the semiconductor element and a signal. In addition, the micro-wiring portion, which is a micro-pattern, may provide a function of a line for signal connection between semiconductor elements, or may perform signal connection (e.g., provision to a lower substrate) for each semiconductor element. Accordingly, it may be provided to prevent the semiconductor element from becoming unnecessarily large, thereby improving the yield of the semiconductor element.

[0116] In addition, circuit boards can be divided into package substrates and interposers according to their function. The package substrate functions to mount semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of laminated insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of circuit boards with a high number of laminated layers, the yield of the circuit board can be improved by separating them into an interposer and a package substrate. In addition, as the terminal density of semiconductor devices increases, it may be difficult to implement pads on the package substrate with an area corresponding to the terminals of the semiconductor devices. Therefore, the interposer can act as a buffer between the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices.

[0117] The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0118] The circuit board (100) may include a connecting member (BR). The connecting member (BR) may be positioned within the build-up insulating portion (112, 113). A detailed description thereof will be provided later. Furthermore, with this configuration, a space for forming an electrode portion, such as in the upper build-up layer (112), can be easily secured. Accordingly, the circuit board according to the embodiment can provide easy connection between semiconductor elements and an improved input / output (I / O) count.

[0119] Additionally, in the embodiment, the core layer (111) in the circuit board (100) may not have a cavity. Similarly, the build-up insulation (112, 113) may not have a cavity that accommodates the connecting member (BR).

[0120] Additionally, the connecting member (BR) may be positioned within the core layer (111) of the circuit board (100) and may overlap with the core layer (111) in the horizontal direction (X-axis direction). For example, the connecting member (BR) may not be positioned in the upper build-up layer (112) or the lower build-up layer (113) of the circuit board (100).

[0121] For example, when a connecting member (BR) in a circuit board (100) is placed within a lower build-up layer (113), the physical distance between the connecting member (BR) and the upper element can be shortened. Furthermore, electrical connection can be accurately performed through the wiring portion of the build-up layer, thereby improving electrical reliability.

[0122] Since the circuit board (100) according to the embodiment can be used as an interposer, thinning is required, so that a connecting member (BR) can be embedded in the core layer (111).

[0123] Referring further to FIGS. 5 and 6, the upper build-up layer (112) may be formed of a plurality of insulating layers, for example, build-up layers.

[0124] As an example, the upper build-up layer (112) may include a first build-up layer (112a) and a second build-up layer (112b). The first build-up layer (112a) and the second build-up layer (112b) may be sequentially arranged in the stacking direction (Y-axis direction). For example, the first build-up layer (112a) may be arranged below the second build-up layer (112b). In addition, based on the circuit board having the core layer (111), the first build-up layer (112a) and the second build-up layer (112b) may be arranged on top of the core layer (111).

[0125] In addition, the connecting member (BR) may be disposed on the first build-up layer (112a). The connecting member (BR) may be disposed on the upper surface of the first build-up layer (112a). In addition, a wiring portion may be connected or a stopper portion may be disposed on the lower portion of the connecting member (BR) as illustrated. The wiring portion or the stopper portion may be located on the upper surface of the first build-up layer (112a). In this case, the wiring portion or the stopper portion may be located in a portion of the connecting member (BR). In addition, the wiring portion or the stopper portion may not be disposed on the lower portion of the connecting member (BR). For example, the connecting member (BR) may be in contact with the upper surface of the first build-up layer (112a).

[0126] The second build-up layer (112b) is disposed on the first build-up layer (112a) and may cover the connecting member (BR). The thickness (T2) of the second build-up layer (112b) may be different from the thickness (Ta) of the connecting member (BR). The thickness (T2) of the second build-up layer (112b) may be greater than the thickness (Ta) of the connecting member (BR).

[0127] The second build-up layer (112b) may have the largest thickness among the multiple build-up layers of the upper build-up layer (112). This may enhance compatibility with connecting members (BR) of various sizes. Furthermore, various circuit designs may be possible in the second build-up layer (112b). Furthermore, since there is no cavity structure, space for forming an electrode portion can be more easily secured. Accordingly, the circuit board may provide an improved input / output (I / O) count.

[0128] Additionally, the upper electrode portion (122) formed on the upper build-up layer (112) may include an upper wiring portion (122a) and an upper via electrode (122b) which is a via electrode. The upper wiring portion (122a) may be arranged on each build-up layer. The upper via electrode (122b) may penetrate each build-up layer.

[0129] Furthermore, the upper wiring portion (122a) may include a first wiring portion and a second wiring portion. The following description will be based on the second wiring portion (122a). In addition, the upper via electrode (122b) may include a first via electrode and a second via electrode. The following description will be based on the second via electrode (122b).

[0130] Furthermore, in the embodiment, the first electrode portion may include a first wiring portion and a first via electrode. The first wiring portion may be located on the upper surface of the first build-up layer (112a). The first via electrode may penetrate the first build-up layer (112a).

[0131] And the second electrode portion may include a second wiring portion (122a) and a second via electrode (122b). The second wiring portion (122a) may be located on the upper surface of the second build-up layer (122b). The second via electrode (122b) may penetrate the second build-up layer (122b).

[0132] The second via electrode (122b) may include a second-first via electrode (122b1) and a second-second via electrode (122b2). The second-first via electrode (122b1) may have a greater thickness than the second-second via electrode (122b2). In addition, the second-first via electrode (122b1) may be spaced apart from the connection member (BR) in the horizontal direction (X-axis direction). In addition, the second-first via electrode (122b1) may at least partially overlap the connection member (BR) in the horizontal direction (X-axis direction). For example, a lower surface of the second-first via electrode (122b1) may overlap the connection member (BR) in the horizontal direction (X-axis direction). In addition, the lower region of the second-first via electrode (122b1) may at least partially overlap with the connection member (BR) in the horizontal direction (X-axis direction). In addition, the second-first via electrode (122b1) may overlap with the lower surface of the connection member (BR) in the horizontal direction (X-axis direction). And the second-first via electrode (122b1) may not overlap with the connection member (BR) in the stacking direction (Y-axis direction) but may be misaligned. In this way, the second electrode portion may overlap with the connection member (BR) in the horizontal direction (X-axis direction). In particular, the second electrode portion may overlap with the lower surface of the connection member (BR) in the horizontal direction (X-axis direction). Furthermore, depending on the length in the vertical direction of the connection member (BR), the second electrode portion may overlap with the lower surface and the upper surface of the connection member (BR) in the horizontal direction (X-axis direction).

[0133] In addition, the second-second via electrode (122b2) may overlap with the connecting member (BR) in the stacking direction (Y-axis direction). And the second-second via electrode (122b2) may be electrically connected to the connecting member (BR). For example, the second-second via electrode (122b2) may be in contact with the upper wiring (BE) of the connecting member (BR). Furthermore, the second-second via electrode (122b2) may be located on the upper wiring (BE).

[0134] And as described above, a first protective layer (SR1) may be disposed on the upper build-up layer (112). And a lower build-up layer (113) may be disposed on the lower side of the core layer (111) or the upper build-up layer (112). And a second protective layer (SR2) may be disposed on the lower build-up layer (113). The second protective layer (SR2) may be disposed on the lower surface of the lower build-up layer (113).

[0135] In addition, in the embodiment, the lower build-up layer (113) may include a plurality of build-up layers (or insulating layers). At this time, in the embodiment, at least one of the plurality of build-up layers and the second protective layer (SR2) of the lower build-up layer (113) may have a different material from the upper build-up layer (112). For example, at least one of the plurality of build-up layers and the second protective layer (SR2) of the lower build-up layer (113) may be made of a material having lower stress than the upper build-up layer (112). For example, at least one of the plurality of build-up layers and the second protective layer (SR2) of the lower build-up layer (113) may include a photocurable material. In contrast, the upper build-up layer (112) may include a thermocurable material. For example, the upper build-up layer (112) may include ABF, and at least one of the plurality of build-up layers and the second protective layer (SR2) of the lower build-up layer (113) may include a solder resist, PID, etc.

[0136] In an embodiment, at least some of the plurality of build-up layers of the lower build-up layer (113) may be formed of a photocurable material. Alternatively, the second protective layer (SR2) other than the lower build-up layer (113) may include a photocurable material. Alternatively, some of the plurality of build-up layers of the lower build-up layer (113) and the second protective layer (SR2) may include a photocurable material.

[0137] With this configuration, as the connecting member (BR) is placed on the upper build-up layer (112), the difference in thermal expansion coefficients increases, and even if stress is concentrated due to the thickness of the second build-up layer, the stress can be alleviated through the aforementioned configuration. Furthermore, by reducing the stress difference, substrate deformation can be absorbed to a certain extent, so that peeling of each component can be easily suppressed.

[0138] In addition, the thickness (T2) of the second build-up layer (112b) is the largest in the upper build-up layer (112), and thus may be greater than the thickness (T1) of the first build-up layer (112a). Furthermore, the thickness (T2) of the second build-up layer (112b) may be greater than the thickness (T5) of the first protective layer (SR1).

[0139] And in the circuit board (100), the thickness (T0) of the core layer (111) may be the largest. The thickness (T0) of the core layer (111) may be greater than the thickness (T2) of the second build-up layer (112b). However, depending on the design, the thickness (T0) of the core layer (111) may be less than or equal to the thickness (T2) of the second build-up layer (112b).

[0140] In addition, the thickness (T3a, T3b, T3c) of each build-up layer of the lower build-up layer (113) may be smaller than the thickness (T0) of the core layer (111). In addition, the thickness (T3a, T3b, T3c) of each build-up layer of the lower build-up layer (113) may be smaller than the thickness (T2) of the second build-up layer (112b).

[0141] By this configuration, the stress relief effect can be improved for stress generated by the second build-up layer. In addition, warpage of the substrate can be prevented by stress relief.

[0142] Additionally, the thickness (T4) of the second protective layer (SR2) may be different from the thickness (T5) of the first protective layer (SR1). The thickness (T4) of the second protective layer (SR2) may be smaller than the thickness (T5) of the first protective layer (SR1).

[0143] By this configuration, flexibility can be improved at the bottom of the circuit board, thereby alleviating the stress concentrated in the second build-up layer due to the difference in thermal expansion coefficient. In addition, warping of the board due to the second build-up layer can be suppressed.

[0144] Additionally, as another example, the thickness (T4) of the second protective layer (SR2) may be greater than the thickness (T5) of the first protective layer (SR1). This configuration can enhance the rigidity of the lower portion of the circuit board. Furthermore, the thicker layer at the lower portion can easily suppress delamination between components.

[0145] Referring further to FIG. 7, the 2-1 via electrode (122b1) may have a convex portion or a concave groove on its outer surface. For example, the outer surface of the 2-1 via electrode (122b1) may have a convex portion (PR) that is convex outwardly. Correspondingly, the inner wall of the hole of the 2nd build-up layer (112b) may have a groove (GR). In addition, the 2nd build-up layer (112b) may have a plurality of convex portions (PR). A plurality of convex portions (PR) may be arranged along the stacking direction (Y-axis direction). In addition, a plurality of concave grooves may be arranged along the stacking direction (Y-axis direction) corresponding to these convex portions.

[0146] In contrast, the 2-2 via electrode (122b2) may have a structure extending along the stacking direction (Y-axis direction) and may have an inclined inner surface. For example, the outer surface of the 2-2 via electrode (122b2) may have a different structure from the outer surface of the 2-1 via electrode (122b1).

[0147] Referring further to FIG. 8, the outer surface (ES1) of the 2-1 via electrode (122b1) may have a first inclination angle (θ) with respect to the lower surface (BS1) of the 2-1 via electrode (122b1).

[0148] And the outer surface (ES2) of the 2nd via electrode (122b2) may have a second inclination angle (θ) with respect to the lower surface (BS2) of the 2nd via electrode (122b2).

[0149] And in the embodiment, the first inclination angle (θ) may be the same as or different from the second inclination angle (θ).

[0150] For example, the first slope angle (θ) may be different from the second slope angle (θ). For example, the first slope angle (θ) may be larger than the second slope angle (θ). By this configuration, even if the thickness of the 2-1 via electrode (122b1) is larger than the thickness of the 2-2 via electrode (122b2), the electrical connection between the lower first wiring portion and the 2-1 via electrode (122b1) can be accurately implemented.

[0151] Furthermore, the area of ​​the upper surface (US2) of the 2-2 via electrode (122b2) and the area of ​​the upper surface (US1) of the 2-1 via electrode (122b1) may be different from each other. For example, the area of ​​the upper surface (US1) of the 2-1 via electrode (122b1) can be minimized due to the difference in inclination angles described above. With this configuration, the formation of a fine pattern for electrical connection with an upper semiconductor element, etc. can be easily implemented.

[0152] In addition, the area of ​​the lower surface (BS1) of the 2-1 via electrode (122b1) may be different from the area of ​​the lower surface (BS2) of the 2-2 via electrode (122b2). For example, when the area of ​​the upper surface (US2) of the 2-2 via electrode (122b2) and the area of ​​the upper surface (US1) of the 2-1 via electrode (122b1) are the same, the area of ​​the lower surface (BS1) of the 2-1 via electrode (122b1) may be greater than or equal to the area of ​​the lower surface (BS2) of the 2-2 via electrode (122b2). Accordingly, an electrical connection between the first wiring portion and the 2-1 via electrode (122b1) can be accurately formed. Furthermore, the phenomenon of electrical reliability deterioration (e.g., short circuit, etc.) due to the increase in the area of ​​the lower surface (BS1) of the 2-1 via electrode (122b1) due to the thickness of the 2-1 via electrode (122b1) can be suppressed by the inclination angle and area.

[0153] Referring further to FIG. 9, the 2-1 via electrode (122b1) may be formed as a pillar on the first wiring portion. That is, after the 2-1 via electrode (122b1) is formed on the first build-up layer (112a), the second build-up layer (112b) may be covered. Accordingly, the 2-1 via electrode (122b1) may be formed by performing chemical plating and electroplating on the first build-up layer (112a).

[0154] Accordingly, the 2-1 via electrode (122b1) and the second wiring portion (122a) may each include multiple layers. For example, the 2-1 via electrode (122b1) may include a first layer (L1) and a second layer (L2) disposed on the first layer (L1).

[0155] And the second wiring section (122a) may include a third layer (L3) and a fourth layer (L4) disposed on the third layer (L3).

[0156] The first layer (L1) and the third layer (L3) may be chemical plating layers, and the second layer (L2) and the fourth layer (L4) may be electroplating layers.

[0157] At this time, the 2-2 via electrode (122b2) may not overlap with the first layer (L1) of the 2-1 via electrode (122b1) in the horizontal direction but may be misaligned. The 2-2 via electrode (122b2) may overlap with the second layer (L2) of the 2-1 via electrode (122b1) in the horizontal direction (X-axis direction).

[0158] In addition, unlike the 2-1 via electrode (122b1), the 2-2 via electrode (122b2) can be formed by plating or the like after the 2nd build-up layer (112b) is formed.

[0159] That is, the second-second via electrode (122b2) may include a fifth layer (L5) and a sixth layer (L6) on the fifth layer (L5).

[0160] The fifth layer (L5) may also be positioned on the upper surface of the second build-up layer (112b). Accordingly, the fifth layer (L5) may overlap with the second layer (L2) and the third layer (L3) in the horizontal direction (X-axis direction). In addition, the sixth layer (L6) formed on the upper portion of the fifth layer (L5) may overlap with the second layer (L2), the third layer (L3), and the fourth layer (L4) in the horizontal direction (X-axis direction).

[0161] Additionally, the fifth layer (L5) and the sixth layer (L6) may not overlap with the first layer (L1) in the horizontal direction (X-axis direction) but may be offset from it. For example, the fifth layer (L5) and the sixth layer (L6) may be spaced apart from the first layer (L1) in the stacking direction (Y-axis direction).

[0162] Furthermore, as described above, the outer surface of the 2-1 via electrode (122b1) may have a first inclination angle with respect to the lower surface of the 2-1 via electrode (122b1). And the outer surface of the 2-2 via electrode (122b2) may have a second inclination angle with respect to the lower surface of the 2-2 via electrode (122b2). And the first inclination angle may be greater than the second inclination angle. For example, the area ratio between the upper surface and the lower surface (e.g., upper surface / lower surface) of the 2-1 via electrode (122b1) may be smaller than the area ratio between the upper surface and the lower surface (e.g., upper surface / lower surface) of the 2-2 via electrode (122b2).

[0163] By this configuration, the formation of the 2-1 via electrode (122b1) can be easily performed. Furthermore, when forming a through hole of the second build-up layer (112b) having a large thickness, plating is not uniformly formed within the through hole of the second build-up layer (112b), and cracks and peeling may occur due to an increase in internal stress caused by a difference in thermal expansion coefficient.

[0164] In the embodiment, the formation of such through holes is not necessary, so that the occurrence of plating defects or faults is suppressed, and the problem of cracks or peeling in the build-up layer can also be resolved.

[0165] Referring further to FIG. 10, the 2-1 via electrode (122b1) may be formed as a pillar on the first wiring portion. That is, after the 2-1 via electrode (122b1) is formed on the first build-up layer (112a), the second build-up layer (112b) may be covered. Accordingly, the 2-1 via electrode (122b1) may be formed by performing chemical plating and electroplating on the first build-up layer (112a).

[0166] Furthermore, in the present embodiment, the second-1 via electrode (122b1) may include a first sub-via electrode (SVE1) and a second sub-via electrode (SVE2). The first sub-via electrode (SVE1) may be located below the second sub-via electrode (SVE2).

[0167] Furthermore, the inclination angle (θ) of the outer surface (ES1a) of the first sub-via electrode (SVE1) may be different from the inclination angle (θ) of the outer surface (ES1b) of the second sub-via electrode (SVE2). This inclination angle may be an angle with respect to the lower surface of each sub-electrode.

[0168] And the inclination angle (θ) of the outer surface (ES1a) of the first sub-via electrode (SVE1) may be greater than the inclination angle (θ) of the outer surface (ES1b) of the second sub-via electrode (SVE2).

[0169] For example, the first sub-via electrode (SVE1) may be formed as a pillar before laminating the second build-up layer (112b). And the second sub-via electrode (SVE2) may be formed after laminating the second build-up layer (112b). At this time, the second-second via electrode (122b2) may also be formed.

[0170] The second inclination angle (θ) of the outer surface (ES2) of the second-second via electrode (122b2) with respect to the lower surface (BS2) of the second-second via electrode (122b2) may be the same as the inclination angle (θ) of the outer surface (ES1b) of the second sub-via electrode (SVE2). Accordingly, the reliability of the substrate can be improved and the manufacturing process can be simplified.

[0171] Furthermore, the thickness (Tc) of the first sub-via electrode (SVE1) may be different from the thickness (Td) of the second sub-via electrode (SVe2). The thickness (Tc) of the first sub-via electrode (SVE1) may be smaller than the thickness (Td) of the second sub-via electrode (SVe2). Accordingly, the formation of a through hole in the second build-up layer (112b) can be prevented as much as possible, thereby improving the reliability of the circuit board.

[0172] Additionally, the thickness (Te) of the second-second via electrode (122b2) may be the same as or different from the thickness (Td) of the second sub-via electrode (SVe2).

[0173] For example, the thickness (Te) of the second-second via electrode (122b2) may be the same as the thickness (Td) of the second sub-via electrode (SVe2). Accordingly, the second-second via electrode (122b2) and the second sub-via electrode (SVE2) can be easily formed through the same process.

[0174] For example, the thickness (Te) of the second-second via electrode (122b2) may be smaller than the thickness (Td) of the second sub-via electrode (SVe2). Accordingly, by considering the aspect ratio of each via electrode, a fine pattern design for the second-second via electrode (122b2) can be easily implemented.

[0175] Figures 11 to 16 are drawings explaining a method for manufacturing a circuit board according to the first embodiment.

[0176] It should be noted that one or more steps may be combined to simplify and / or clarify the steps for providing or manufacturing a circuit board. In some implementations, the order of the processes may be changed or modified. Furthermore, in some implementations, one or more of the manufacturing methods may be replaced or substituted without departing from the spirit of the present disclosure. Different implementations may manufacture the board differently.

[0177] Referring to FIG. 11, a core layer (111) can be provided. The core layer (111) may be an insulating layer having a predetermined thickness or greater, as described above. In addition, the core layer (111) may include glass or glass fiber having a resin. However, the core layer (111) may also include different materials.

[0178] And a via hole or a through hole (111h) can be formed in the core layer (111). The through hole can be formed through the upper and lower surfaces of the core layer (111). The through hole or via hole can be formed by a method such as a laser drilling method, a punching method, an etching method (mechanical drilling, chemical etching, or any suitable mechanism).

[0179] Referring to FIG. 12, a core electrode portion (121) can be formed on a core layer (111). The electrode portion can be formed by a patterning process based on mask formation (exposure, curing, etc.), a stripping process, and / or a plating process. Furthermore, a via hole or a through hole can be formed in the upper build-up layer (112) and / or the lower build-up layer (113) to form the electrode portion. The via hole can be formed by a laser drilling method, a punching method, an etching method (mechanical drilling, chemical etching, or any suitable mechanism), etc.

[0180] For example, a plating process may be performed on a via hole formed in the core layer (111) to form a through electrode. Then, a core wiring portion may be formed on the upper and lower surfaces of the core layer (111). The core wiring portion may have a pattern using a mask or the like. Furthermore, the core wiring portion may be formed using an additive process, a subtractive process, a modified semi-additive process (MSAP), a semi-additive process (SAP), or the like, which are manufacturing processes for printed circuit boards. This may be equally applied to other wiring portions. Furthermore, a dummy electrode (not shown) may be disposed on the lower surface of the core layer (111). As a result, warping of the substrate with respect to the thick second build-up layer on the upper surface can be easily suppressed.

[0181] Furthermore, a build-up layer may be laminated on the core layer (111). For example, a build-up layer (112c) of an upper build-up layer (112) may be formed on the upper surface of the core layer (111). And a build-up layer (113c) of a lower build-up layer (113) may be formed on the lower surface of the core layer (111).

[0182] Referring to FIG. 13, additional build-up layers may be further laminated. For example, a first build-up layer (112a) may be further laminated on top of the core layer (111). Furthermore, a build-up electrode portion may also be formed in each build-up layer. The build-up electrode portion may be formed by a patterning process based on mask formation (exposure, curing, etc.), a stripping process, and / or a plating process, as described above.

[0183] Referring to Fig. 14, a connecting member (BR) may be mounted on the first wiring portion of the first build-up layer (112a). The first wiring portion and the connecting member (BR) may be electrically connected to each other. Additionally, the first wiring portion and the connecting member (BR) may not be in direct contact with each other or may not be connected to each other.

[0184] Referring to FIG. 15, a second build-up layer (112b) may be laminated on the first build-up layer (112a). The second build-up layer (112b) may cover the connecting member (BR).

[0185] At this time, as described above, the second wiring portion can be formed in various ways. For example, the second-first via electrode (122b1) can be formed before laminating the second build-up layer (112b). The second-first via electrode (122b1) can be formed as a pillar. In addition, the second build-up layer (112b) covering the second-first via electrode (122b1) and the connecting member (BR) can be formed.

[0186] Additionally, when the 2-1 via electrode (122b1) has a greater thickness than the 2nd build-up layer (112b), planarization may be performed on the 2-1 via electrode (122b1). In this case, the 2-1 via electrode (122b1) may not have a sub-via electrode having a different inclination angle.

[0187] In addition, the second-first via electrode (122b1) of the pillar may have a smaller thickness than the second build-up layer (112b). In this case, the second-first via electrode (122b1) may correspond to the first sub-via electrode. In addition, the second sub-via electrode and the second-second via electrode may be formed on the second build-up layer (112b).

[0188] In addition, a second wiring portion and a second via electrode can be formed after the second build-up layer (112b) is laminated.

[0189] Furthermore, the position of the connecting member (BR) can be easily adjusted by the aforementioned dummy electrodes and the like. For example, marks (e.g., alignment marks) for aligning the connecting member (BR) can be formed on the dummy electrodes (not shown). By this configuration, the connecting member (BR) can be positioned at a more precise position according to the design.

[0190] Referring to FIG. 16, a first protective layer (SR1) may be formed on the upper build-up layer (112) thereafter. A second protective layer (SR2) may be formed under the lower build-up layer (113). Furthermore, a via portion (TP) penetrating the protective layer (SR) may be formed.

[0191] Furthermore, semiconductor elements (DI1, DI2) may be stacked on the circuit board later.

[0192] Fig. 17 is a cross-sectional view of a circuit board according to the second embodiment, Fig. 18 is an enlarged view of K3 in Fig. 17, and Fig. 19 is another example of Fig. 18.

[0193] Referring to FIGS. 17 and 18, a circuit board (100A) according to the second embodiment may include an insulating layer (110), an electrode portion (120), and a connecting member (BR). Furthermore, the circuit board (100A) may further include a protective layer (SR) and a bonding portion (BP). As described above, the build-up electrode portions (122, 123) may be disposed to be embedded in each layer (e.g., an insulating layer) of the build-up insulating portions (112, 113), thereby functioning to transmit signals and / or power from a main board (not shown) to a semiconductor element. In addition, the connecting member (BR) may be located on an upper surface of one build-up layer of the upper build-up layer (112). In addition, the above-described contents may be equally applied to the circuit board, except for the contents described below.

[0194] In this example, the second build-up layer (112b) may include multiple sub-build-up layers. For example, the multiple sub-build-up layers may include a first sub-build-up layer (112ba), a second sub-build-up layer (112bb), and a third sub-build-up layer (112bc).

[0195] The first sub-build-up layer (112ba), the second sub-build-up layer (112bb), and the third sub-build-up layer (112bc) may be sequentially arranged in the stacking direction (Y-axis direction) on the first build-up layer (112a). For example, the second sub-build-up layer (112bb) may be arranged between the first sub-build-up layer (112ba) and the third sub-build-up layer (112bc).

[0196] And, at the boundary surface of the plurality of sub-build-up layers, the second-1 via electrode (122b1) may include a protrusion protruding outward. The protrusion may be positioned corresponding to the boundary surface of the plurality of sub-build-up layers.

[0197] Furthermore, the 2-2 via electrode (122b2) may overlap a portion of the boundary surface of a plurality of sub-build-up layers in the horizontal direction (X-axis direction). At this time, the 2-2 via electrode (122b2) may also include a protrusion protruding outward.

[0198] For example, the second-second via electrode (122b2) may include a protrusion corresponding to the boundary between the second sub-build-up layer (112bb) and the third sub-build-up layer (112bc).

[0199] Referring further to FIG. 19, as described above, the second build-up layer (112b) may include multiple sub-build-up layers. For example, the multiple sub-build-up layers may include a first sub-build-up layer (112ba), a second sub-build-up layer (112bb), and a third sub-build-up layer (112bc).

[0200] At this time, the outer surface of the second via electrode may be inclined relative to the lower surface. In addition, the area of ​​the upper surface of the second via electrode may be smaller than the area of ​​the lower surface. In addition, the area of ​​the second via electrode may decrease from the upper surface to the lower surface.

[0201] And, at the boundary surface of the plurality of sub-build-up layers, the second via electrode may have a step portion. For example, the second-first via electrode (122b1) may have a step portion (ST1, ST2) at the boundary surface of adjacent sub-build-up layers in the first sub-build-up layer (112ba), the second sub-build-up layer (112bb), and the third sub-build-up layer (112bc).

[0202] For example, the 2-1 via electrode (122b1) may have a first step portion (ST1) at the boundary between the first sub-build-up layer (112ba) and the second sub-build-up layer (112bb). In addition, the 2-1 via electrode (122b1) may have a second step portion (ST2) at the boundary between the second sub-build-up layer (112bb) and the third sub-build-up layer (112bc). By this configuration, the plating uniformity is improved, thereby improving the quality of the electrode portion, and the thermal stress is relieved, thereby suppressing cracking and peeling phenomena.

[0203] Fig. 20 is a cross-sectional view of a circuit board according to the third embodiment.

[0204] Referring to FIG. 20, a circuit board (100B) according to the third embodiment may include an insulating layer (210), a wiring layer (220), and a connecting member (BR).

[0205] In this example, the circuit board (100B) can be implemented by WLP (Wafer-Level Packaging). And the circuit boards according to the first and second embodiments described above can be implemented by PLP (Panel level Package).

[0206] Based on this, in this example, the insulating layer (210) of the circuit board can insulate between different layers of the wiring layer (220).

[0207] The insulating layer (210) may be made of an insulating material. For example, the insulating layer (210) may include SiO₂ (silicon oxide), SiN (silicon nitride), polyimide (PI), etc.

[0208] And the wiring layer (220) can perform signal transmission between chips or devices. The wiring layer (220) can have a fine wiring structure. For example, the wiring layer (220) can include Cu (copper), Al (aluminum), W (tungsten), etc.

[0209] The insulating layer (210) may be composed of multiple insulating layers. And the multiple wiring layers (220) may be located in the multiple insulating layers.

[0210] For example, the insulating layer (210) may include a first insulating layer (211), a second insulating layer (212) on top of the first insulating layer (211), and a third insulating layer (213) on top of the second insulating layer (212).

[0211] And the wiring layer (220) may include a first wiring layer (221), a second wiring section (222), and a third wiring section (223). And each wiring layer may include wiring on an insulating layer and a micro via electrode.

[0212] Furthermore, the via electrode of the first wiring layer (221) can penetrate the first insulating layer (211). And a connecting member (BR) can be positioned on the first insulating layer (211). The connecting member (BR) can be connected to the wiring of the first wiring layer (221).

[0213] In addition, the second insulating layer (212) may be positioned on the first insulating layer (211). The second insulating layer (212) may cover the connecting member (BR). The via electrode of the second wiring portion (222) may be smaller than the thickness of the connecting member (BR). Accordingly, the second insulating layer (212) may include a first upper surface overlapping the connecting member (BR) in the lamination direction, and a second upper surface overlapping or contacting the second wiring portion (222) in the lamination direction. The first upper surface may be positioned above the second upper surface in the lamination direction. And, an inclined surface may be positioned between the first upper surface and the second upper surface. That is, the upper surface of the second insulating layer (212) may include the first upper surface, the inclined surface, and the second upper surface. The inclined surface may not be vertical but may be inclined with respect to the first upper surface or the second upper surface. Furthermore, the area of ​​the second insulating layer (212) from the first upper surface to the second upper surface may increase. In addition, the inclined surface may be adjacent to the outermost surface of the connecting member (BR).

[0214] And the third insulating layer (213) can be positioned on top of the second insulating layer (212). Due to the structure of the second insulating layer (212) described above, the third insulating layer (213) can have a cavity (CV1) when flipped.

[0215] Furthermore, the gap between the slope and the connecting member (BR) can be reduced in the stacking direction.

[0216] In other words, the cavity (CV1) of the third insulating layer (213) can increase in width or area in the stacking direction.

[0217] By this configuration, a larger space can be secured for forming the third wiring section (223) located on the third insulating layer (213). That is, the space around the connecting member can be utilized as a circuit space. Accordingly, the circuit board can provide an improved input / output count.

[0218] Additionally, circuit elements can be easily interconnected with other packages (e.g., memory, logic chips, RF, etc.) by forming numerous output terminals on the top or bottom of the mounted element or chip. Furthermore, directivity can also be improved.

[0219] Figures 21 to 25 are drawings explaining a method for manufacturing a circuit board according to a third embodiment.

[0220] Referring to Fig. 21, a redistribution layer can be formed on a carrier board (CB). For example, an insulating layer and a wiring section can be additionally formed on the carrier board (CB).

[0221] Specifically, a wiring section can be formed by forming an insulating layer on a carrier board (CB), performing lithography patterning, etc., and then performing plating.

[0222] For example, by forming such an insulating layer and a wiring portion, a first insulating layer (211) and a first wiring portion 9221) can be formed.

[0223] Referring to Fig. 22, bonding of a connecting member (BR) may be performed on the first insulating layer (211). For example, the connecting member (BR) may be placed on a redistribution layer and bonding may be performed. Underfill, etc. may also be performed during die bonding.

[0224] Referring to Fig. 23, a second insulating layer (212) can be formed on the first insulating layer (211). For example, the insulating layer can be formed through coating or the like. The second insulating layer (212) can cover the connecting member (BR).

[0225] At this time, the second insulating layer (212) may have a slope adjacent to the edge of the connecting member (BR). In addition, the second insulating layer (212) may have a structure that protrudes upward in a region overlapping the connecting member (BR) in the lamination direction.

[0226] Referring to Fig. 24, a second wiring portion (222) can be formed on the second insulating layer (212). The wiring portion can be formed by performing plating and patterning processes as described above.

[0227] Referring to FIG. 25, the process of repeatedly laminating (e.g., coating) an insulating layer and plating and patterning can be performed. Thus, multiple insulating layers and multiple wiring sections can be formed.

[0228] Finally, the carrier board (CB) can be removed. The carrier board (CB) can be removed by mechanical, chemical, or other methods.

[0229] Afterwards, additional individual dicing can be performed.

[0230] Fig. 26 is a cross-sectional view showing a semiconductor package according to the first embodiment, Fig. 27 is a cross-sectional view showing a semiconductor package according to the second embodiment, and Fig. 28 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0231] In the various semiconductor packages described below, the circuit board described above may be located in some area or may correspond to one substrate.

[0232] Referring to FIG. 26, the semiconductor package of the first embodiment may include a second substrate (1200) and a semiconductor element (1300).

[0233] Furthermore, the semiconductor package may further include a first substrate and a connecting member (1210) described below.

[0234] The first substrate may mean or include a 'package substrate' or a 'circuit substrate'. In addition, the first substrate may be omitted. For example, the first substrate may provide a space to which at least one external substrate is coupled. The external substrate may mean a second substrate (1200) coupled on the first substrate. In addition, the external substrate may mean a main board included in an electronic device coupled to a lower portion of the first substrate.

[0235] Additionally, although not shown in the drawing, the first substrate may provide a space in which at least one semiconductor element is mounted.

[0236] The first substrate may include at least one build-up insulating portion and an electrode portion disposed on the at least one build-up insulating portion.

[0237] A second substrate (1200) can be placed on the first substrate.

[0238] The second substrate (1200) may be an interposer. For example, the second substrate (1200) may provide a space in which at least one semiconductor element is mounted. The second substrate (1200) may be connected to at least one semiconductor element (1300). For example, the second substrate (1200) may provide a space in which a first semiconductor element (1310) and a second semiconductor element (1320) are mounted. The second substrate (1200) may electrically connect the first semiconductor element (1310) and the second semiconductor element (1320), and electrically connect the first and second semiconductor elements (1310, 1320) and the first substrate. That is, the second substrate (1200) may perform a horizontal connection function between a plurality of semiconductor elements and a vertical connection function between the semiconductor element and the package substrate.

[0239] In addition, although the above-described example illustrates two semiconductor elements (1310, 1320) being arranged on the second substrate (1200), the present invention is not limited thereto. For example, one semiconductor element may be arranged on the second substrate (1200), or alternatively, three or more semiconductor elements may be arranged.

[0240] A second substrate (1200) may be placed between at least one semiconductor element (1300) and the first substrate.

[0241] In one embodiment, the second substrate (1200) may be an active interposer that functions as a semiconductor device. When the second substrate (1200) functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first substrate and may function as a plurality of logic chips. Having the function of a logic chip may mean having the functions of an active device and a passive device. Unlike passive devices, the characteristics of current and voltage may not be linear in the case of an active device, and the active interposer may have the function of an active device. In addition, the active interposer may perform the function of a corresponding logic chip while performing a signal transmission function between the second logic chip disposed thereon and the first substrate.

[0242] In another embodiment, the second substrate (1200) may be a passive interposer. For example, the second substrate (1200) may function as a signal relay between the semiconductor element (1300) and the first substrate, and may have passive element functions such as a resistor, a capacitor, and an inductor. For example, the number of terminals in the semiconductor element (1300) is gradually increasing due to reasons such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed. That is, the number of terminals provided in the semiconductor element (1300) is increasing, and accordingly, the width of the terminals or the spacing between the plurality of terminals is decreasing. At this time, the first substrate may be connected to the main board of the electronic device. Accordingly, in order for the electrodes provided in the first substrate to have a width and spacing for being connected to the semiconductor element (1300) and the main board, there is a problem that the thickness of the first substrate increases or the layer structure of the first substrate becomes complicated. Accordingly, the first embodiment can place a second substrate (1200) on the first substrate and the semiconductor element (1300). And the second substrate (1200) can include an electrode having a microscopic width and spacing corresponding to the terminal of the semiconductor element (1300).

[0243] The semiconductor device (1300) may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. The memory chip may be a stack memory such as HBM.

[0244] Meanwhile, the semiconductor package of the first embodiment may include a connecting portion.

[0245] For example, a semiconductor package may include a first connector (1410) positioned between a first substrate and a second substrate (1200). The first connector (1410) may electrically connect the second substrate (1200) to the first substrate while bonding them therebetween.

[0246] For example, the semiconductor package may include a second connection portion (1420) disposed between a second substrate (1200) and a semiconductor element (1300). The second connection portion (1420) may electrically connect the semiconductor element (1300) while bonding them to the second substrate (1200).

[0247] The semiconductor package may include a third connector (1430) disposed on the lower surface of the first substrate. The third connector (1430) may electrically connect the first substrate to the main board while connecting them therebetween.

[0248] At this time, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can electrically connect the plurality of components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) have the function of electrically connecting the plurality of components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as a part that is electrically connected rather than solder or wire.

[0249] The wire bonding method may refer to electrically connecting a plurality of components using a conductor such as gold (Au). In addition, the solder bonding method may electrically connect a plurality of components using a material including at least one of Sn, Ag, and Cu. In addition, the direct metal-to-metal bonding method may refer to directly bonding a plurality of components by applying heat and pressure between the plurality of components to recrystallize them without the use of solder, wires, conductive adhesives, etc. In addition, the direct metal bonding method may refer to a bonding method using a second connection portion (1420). In this case, the second connection portion (1420) may refer to a solder layer formed between the plurality of components by recrystallization.

[0250] Specifically, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the plurality of components by applying heat and pressure to the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430).

[0251] At this time, in at least one of the first substrate and the second substrate (1200), the electrodes on which the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) are arranged may be provided with a protrusion that protrudes outward away from the build-up insulation portion of the corresponding substrate. The protrusion may protrude outward from the first substrate or the second substrate (1200).

[0252] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode on which a second connection portion (1420) for coupling with a semiconductor element (1300) is arranged among the electrodes of the second substrate (1200). That is, as the pitch of the terminals of the semiconductor element (1300) becomes finer, a short circuit may occur between the plurality of second connection portions (1420) that are respectively connected to the plurality of terminals of the semiconductor element (1300) by a conductive adhesive such as solder. Therefore, in the embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portion (1420). Accordingly, the embodiment may include a protrusion in the electrode of the second substrate (1200) on which the second connecting portion (1420) is arranged to secure a degree of alignment, diffusion, and diffusion-preventing ability to prevent an intermetallic compound (IMC) formed between a conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the substrate.

[0253] Furthermore, the semiconductor package of the first embodiment may further include a connecting member (1210).

[0254] The connecting member (1210) may be referred to as a bridge substrate. For example, the connecting member (1210) may include a redistribution layer. The connecting member (1210) may have a function of horizontally electrically connecting a plurality of semiconductor devices to each other. For example, since the area that a semiconductor device should have is generally too large, the connecting member (1210) may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width or width of the circuit pattern, etc., a buffering function of the circuit pattern for electrical connection is required. The buffering function may mean having a size between the width or width of the circuit pattern of the semiconductor package and the width or width of the circuit pattern of the semiconductor device, and the redistribution layer may have a function of performing a buffering function.

[0255] In an embodiment, the connecting member (1210) may be an organic bridge. For example, the connecting member (1210) may include an organic material. For example, the connecting member (1210) may include an organic substrate instead of a silicon substrate. The connecting member (1210) may be embedded within the second substrate (1200).

[0256] For this purpose, a connecting member (1210) may be embedded within the second substrate (1200). The connecting member (1210) may horizontally connect a plurality of semiconductor elements arranged on the second substrate (1200).

[0257] The semiconductor package of the first embodiment may include a second substrate (1200) and a semiconductor element (1300). In this case, the semiconductor package of the first embodiment may have a structure in which the first substrate is omitted compared to the semiconductor package of the first embodiment.

[0258] That is, the second substrate (1200) of the first embodiment can function as a package substrate while also functioning as an interposer.

[0259] The first connecting portion (1410) arranged on the lower surface of the second substrate (1200) can connect the second substrate (1200) to the main board of the electronic device.

[0260] Referring to FIG. 27, the semiconductor package of the second embodiment may include a first substrate (1100) and a semiconductor element (1300).

[0261] At this time, the semiconductor package of the second embodiment may have a structure in which the second substrate (1200) is omitted compared to the semiconductor package of the first embodiment.

[0262] That is, the first substrate (1100) of the second embodiment can function as a package substrate while also connecting the semiconductor elements (1300) and the main board. To this end, the first substrate (1100) can include a connecting member (1110) for connecting between a plurality of semiconductor elements. The connecting member (1110) can be an organic bridge connecting between a plurality of semiconductor elements.

[0263] Referring to FIG. 28, the semiconductor package of the third embodiment may further include a third semiconductor element (1330) compared to the semiconductor package of the third embodiment. To this end, a fourth connecting portion may be further arranged on one surface of the first substrate (1100).

[0264] In this way, the semiconductor package of the third embodiment may have a structure in which semiconductor elements are mounted on the upper and lower sides, respectively. In this case, the third semiconductor element (1330) may have a structure in which it is placed on the lower surface of the second substrate (1200) in the aforementioned circuit board or semiconductor package.

[0265] And a connecting member (1110) can be embedded in the first substrate (1100). The connecting member (1110) can horizontally connect the first and second semiconductor elements (1310, 1320).

[0266] Additionally, the first substrate (1100) may include a conductive coupling portion (1450). The conductive coupling portion (1450) may further protrude from the first substrate (1100) toward the second semiconductor element (1320). The conductive coupling portion (1450) may be referred to as a bump, or alternatively, as a post. The conductive coupling portion (1450) may be positioned with a protruding structure on an electrode positioned on the uppermost side of the first substrate (1100).

[0267] A third semiconductor element (1330) may be placed on the conductive joint (1450). At this time, the third semiconductor element (1330) may be connected to the first substrate (1100) through the conductive joint (1450). In addition, a second connection (1420) may be placed between the first and second semiconductor elements (1310, 1320) and the third semiconductor element (1330).

[0268] Accordingly, the third semiconductor element (1330) can be electrically connected to the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0269] That is, the third semiconductor element (1330) can be connected to the first substrate (1100) through the conductive joint (1450), and can also be connected to the first and second semiconductor elements (1310, 1320) through the second connection (1420).

[0270] At this time, the third semiconductor element (1330) can receive a power signal and / or electric power through the conductive coupling portion (1450). In addition, the third semiconductor element (1330) can exchange communication signals with the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0271] The semiconductor package of the third embodiment can provide sufficient power for driving the third semiconductor element (1330) or enable smooth control of power operation by supplying a power signal and / or power to the third semiconductor element (1330) through the conductive joint (1450).

[0272] Accordingly, the embodiment can improve the driving characteristics of the third semiconductor element (1330). That is, the embodiment can solve the problem of insufficient power provided to the third semiconductor element (1330). Furthermore, the embodiment can provide at least one of the power signal, power, and communication signal of the third semiconductor element (1330) through different paths via the conductive coupling portion (1450) and the second connection portion (1420). Through this, the embodiment can solve the problem of loss of the communication signal caused by the power signal. For example, the embodiment can minimize mutual interference between the power signal and the communication signal.

[0273] Meanwhile, the third semiconductor element (1330) in the third embodiment may have a POP (Package On Package) structure in which a plurality of package substrates are stacked and may be placed on the first substrate (1100). For example, the third semiconductor element (1330) may be a memory package including a memory chip. And the memory package may be coupled on the conductive joint (1450). At this time, the memory package may not be connected to the first and second semiconductor elements (1310, 1320).

[0274] Furthermore, the semiconductor package of the modified example may include the first substrate (1100) and first and second semiconductor elements (1310, 1320) arranged on the first substrate (1100) as in the above-described example. Furthermore, the semiconductor package may include a first connection portion (1410) arranged between the first substrate (1100) and the first and second semiconductor elements (1310, 1320). That is, the semiconductor package may have a structure in which the second substrate and the second connection portion are omitted in the above-described example.

[0275] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0276] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0277] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0278] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. Core layer; An upper build-up layer including a first build-up layer and a second build-up layer arranged in a stacking direction on the core layer; A connecting member disposed on the first build-up layer; A second build-up layer disposed on the first build-up layer and covering the connecting member; A first electrode portion arranged on the first build-up layer; and A second electrode part disposed on the second build-up layer; A circuit board in which the second electrode portion overlaps horizontally with the lower surface of the connecting member.

2. In paragraph 1, A circuit board in which the second build-up layer has the greatest thickness in the upper build-up layer.

3. In paragraph 1, A circuit board wherein the thickness of the second build-up layer is greater than the thickness of the connecting member.

4. In paragraph 1, A first protective layer disposed on the upper build-up layer; a lower build-up layer disposed below the core layer; and A circuit board comprising a second protective layer disposed on the lower build-up layer.

5. In paragraph 4, A circuit board comprising a plurality of build-up layers of the lower build-up layer and at least one of the second protective layers comprising a photocurable material.

6. In paragraph 1, A circuit board including a second electrode portion, a second wiring portion disposed on the second build-up layer, and a second via electrode including a second-1 via electrode and a second-2 via electrode penetrating the second build-up layer.

7. In paragraph 6, The above 2-1 via electrode is a circuit board that overlaps the connecting member in the horizontal direction.

8. In paragraph 6, The above 2-2 via electrode is a circuit board electrically connected to the above connecting member.

9. In paragraph 6, A circuit board having an outer surface of the above-mentioned 2-1 via electrode having a concave groove.

10. In paragraph 6, The outer surface of the above 2-1 via electrode has a first inclination angle with respect to the lower surface of the above 2-1 via electrode, A circuit board in which the outer surface of the above-mentioned 2-2 via electrode has a second inclination angle with respect to the lower surface of the above-mentioned 2-2 via electrode.

11. In paragraph 6, A circuit board in which the area on the lower surface of the above-mentioned 2-1 via electrode is different from the area on the lower surface of the above-mentioned 2-2 via electrode.

12. In paragraph 6, A circuit board in which the above-mentioned second-first via electrode includes a first sub-via electrode and a second sub-via electrode disposed on the first sub-via electrode and having a different inclination angle from the outer surface of the first sub-via electrode.

13. In paragraph 12, The above second sub-via electrode is a circuit board having the same inclination angle with respect to the lower surface as the above second-2 via electrode.

14. In paragraph 12, A circuit board in which the thickness of the second sub-via electrode is the same as the thickness of the second-2 via electrode.

15. In paragraph 12, A circuit board in which the thickness of the first sub-via electrode is greater than the thickness of the second sub-via electrode.

16. In paragraph 6, A circuit board wherein the second build-up layer comprises a plurality of sub-build-up layers.

17. In paragraph 16, A circuit board wherein the plurality of sub-build-up layers include a first sub-build-up layer and a second sub-build-up layer disposed on the first sub-build-up layer.

18. In paragraph 17, A circuit board in which the second via electrode has a protrusion or step protruding outward from the boundary between the first sub-build-up layer and the second sub-build-up layer.

19. In paragraph 6, A circuit board including a first via electrode penetrating the first build-up layer and a first wiring portion disposed on the first build-up layer.

20. In paragraph 6, A circuit board in which the thickness of the above-mentioned 2-1 via electrode is greater than the thickness of the above-mentioned 2-2 via electrode.

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