Glass substrate and multilayer wiring substrate including same

Abstract

A glass substrate and a multilayer wiring substrate are provided. The glass substrate comprises a glass body and a through glass via (TGV) extending through the glass body. The surface roughness (Ra) of the side surface of the through glass via is 0.5 to 2 ㎛. The multilayer wiring substrate comprises: the glass substrate; and a wiring laminate laminated on the glass substrate.

Description

Glass substrate and multilayer wiring substrate including the same

[0001] The present invention relates to a glass substrate and a multilayer wiring board including the same. More specifically, the present invention relates to a glass substrate including a glass body and a conductor, and a multilayer wiring board including the same.

[0002] For example, a multilayer wiring board, such as a printed circuit board, is used to connect semiconductor chips such as an AP (Application Processor) chip and memory devices included in a smart phone to a circuit. The multilayer wiring board may include a plurality of insulating layers and a plurality of wiring layers repeatedly laminated therein. The AP chip or semiconductor chip can be mounted on the multilayer wiring board through soldering, wire connection, etc. using the outermost insulating layer and wiring layer.

[0003] Recently, as electronic components become more highly integrated, multilayer wiring boards may include a greater number of wiring layers. In this case, substrate warpage may occur due to differences in the coefficients of thermal expansion of the insulating and wiring layers. Furthermore, the heat generated during signal transmission to the AP chip or semiconductor chip may exacerbate this substrate warpage.

[0004] In addition, when passive elements such as capacitors, inductors, and resistors are included in the substrate, substrate warpage, substrate cracks, etc. may occur more easily due to differences in thermal expansion coefficients between the passive elements and the multilayer wiring substrate.

[0005] For example, Korean Patent Publication No. 10-2565119 discloses a wiring board with a built-in chip.

[0006] Meanwhile, when using glass as a substrate material, warpage can be suppressed, but the substrate can easily break or be damaged by external impact. Furthermore, defects can occur due to reduced adhesion between the conductor and the glass.

[0007] An object of the present invention is to provide a glass substrate having improved mechanical stability and electrical efficiency.

[0008] An object of the present invention is to provide a multilayer wiring board having improved mechanical stability and electrical efficiency.

[0009] 1. A glass substrate comprising a glass body; and a through glass via (TGV) penetrating the glass body, wherein the surface roughness (Ra) of a side surface of the through glass via is 0.5 μm to 2 μm.

[0010] 2. A glass substrate having a surface roughness (Ra) of the side surface of the through glass via in the above 1, of 0.8 ㎛ to 2 ㎛.

[0011] 3. A glass substrate in the above 1, wherein the diameter of the upper or lower surface of the through glass via is 25 ㎛ to 300 ㎛.

[0012] 4. A glass substrate in the above 3, wherein the diameter of the upper or lower surface of the through glass via is 30 ㎛ to 100 ㎛.

[0013] 5. In the above 1, including a plurality of the above through glass vias,

[0014] A glass substrate, wherein the distance between adjacent through-glass vias is 40 μm to 1,000 μm.

[0015] 6. In the above 1, the through glass via includes a via body and a conductive intermediary layer surrounding the side surface of the via body, a glass substrate.

[0016] 7. In the above 6, the conductive intermediary layer is a glass substrate, wherein the conductive intermediary layer includes at least one of titanium (Ti), tantalum (Ta), chromium (Cr), and nickel (Ni).

[0017] 8. A multilayer wiring board comprising a glass substrate of the above-described embodiments; and a wiring laminate disposed on an upper surface of the glass substrate and including repeatedly laminated wiring layers, insulating layers, and interlayer connection conductors.

[0018] 9. In the above 8, the wiring laminate is a multilayer wiring board having a passive element formed by the wiring layers, the interlayer connection conductors or the insulating layers.

[0019] 10. A multilayer wiring board according to the above 9, wherein the passive element includes at least one of a resistor, a capacitor, and an inductor.

[0020] 11. In the above 10, the register is a multilayer wiring board including a line pattern included in one of the wiring layers.

[0021] 12. In the above 10, the capacitor is a multilayer wiring board including first electrodes and second electrodes included in different levels of wiring layers among the wiring layers, and an insulating layer disposed between the first electrode and the second electrode among the insulating layers.

[0022] 13. In the above 10, the capacitor,

[0023] A multilayer wiring board comprising: first terminal electrodes and second terminal electrodes spaced apart from each other and included in the above wiring layers; first internal electrodes and second internal electrodes included in one layer of the interlayer connection conductors among the interlayer connection conductors, wherein one end of the first internal electrodes is connected to the first terminal electrode, and the other end of the second internal electrodes is connected to the second terminal electrode.

[0024] 14. A multilayer wiring board in the above 13, wherein the first internal electrodes and the second internal electrodes are alternately repeated within one of the insulating layers.

[0025] 15. In the above 10, the inductor includes a first coil part and a second coil part respectively included in different wiring layers among the wiring layers, and a coil via connecting the first coil part and the second coil part.

[0026] 16. In the above 15, the coil via is included in the interlayer connection conductor of one layer among the interlayer connection conductors, a multilayer wiring board.

[0027] 17. In the above 10, the inductor comprises a first terminal electrode and lower connection electrodes included in one of the wiring layers; a second terminal electrode and upper connection electrodes included in another of the wiring layers; and coil vias connected in a zigzag manner by the lower connection electrodes and the upper connection electrodes.

[0028] 18. A multilayer wiring board according to the above 17, wherein the coil vias are included in an interlayer connection conductor disposed within an insulating layer between the one wiring layer and the other wiring layer.

[0029] According to embodiments of the present invention, a wiring laminate can be laminated on a glass substrate. The glass substrate serves as a support substrate for the wiring laminate, and can suppress overall warpage of the multilayer wiring substrate.

[0030] According to embodiments of the present invention, a through glass via penetrating the glass body can be formed to electrically connect wiring layers included in the wiring laminate to the through glass via. Accordingly, electrical signal loss from the lower surface of the glass body to the upper surface of the wiring laminate can be reduced, and high-Q characteristics can be implemented.

[0031] According to exemplary embodiments, the surface roughness of the through glass via can be adjusted to improve adhesion between the glass body and the through glass via, while preventing crack propagation in the glass body.

[0032] According to exemplary embodiments, the wiring laminate may include passive components embedded therein. Therefore, the high-temperature SMT process for mounting passive components on the outer surface of the substrate can be omitted, thereby further preventing thermal damage and warpage of the substrate. Furthermore, the passive components can be designed utilizing the wiring layers included in the wiring laminate. Therefore, the manufacturing cost of the passive components can be reduced, while facilitating the design of a highly integrated circuit structure.

[0033] FIG. 1 is a schematic cross-sectional view showing a glass substrate according to exemplary embodiments.

[0034] FIG. 2 is a schematic plan view showing a glass substrate according to exemplary embodiments.

[0035] FIG. 3 is a schematic cross-sectional view showing a glass substrate according to exemplary embodiments.

[0036] FIG. 4 is a schematic cross-sectional view showing a multilayer wiring board according to exemplary embodiments.

[0037] FIG. 5 is a schematic cross-sectional view showing one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.

[0038] FIG. 6 is a schematic cross-sectional view showing one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.

[0039] FIG. 7 is a schematic perspective view illustrating implementation examples of passive components included in a multilayer wiring board according to exemplary embodiments.

[0040] FIG. 8 is a schematic plan view illustrating one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.

[0041] FIGS. 9 and 10 are schematic perspective and cross-sectional views, respectively, illustrating one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.

[0042] Embodiments of the present invention provide a glass substrate including a glass body. Embodiments of the present invention provide a multilayer wiring substrate including the glass substrate and a wiring laminate.

[0043] Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings. However, the following drawings attached to this specification illustrate preferred embodiments of the present invention and, together with the contents of the invention described above, serve to further understand the technical concept of the present invention. Therefore, the present invention should not be interpreted as being limited to the matters described in such drawings.

[0044] The terms “first”, “second”, “third”, “fourth”, “first”, “other”, “top”, “bottom”, etc. used in this application do not limit absolute positions or orders, but are used in a relative sense to distinguish different components or parts.

[0045] FIG. 1 is a schematic cross-sectional view showing a glass substrate according to exemplary embodiments.

[0046] Referring to FIG. 1, the glass substrate may include a glass body (105) and a through glass via (TGV) (110) penetrating the glass body (105).

[0047] The glass body (105) may be manufactured from a glass product or bare glass that substantially does not contain organic materials. For example, the term "glass body" as used in the present application may be used to mean excluding a structure in which glass particles or glass fibers are impregnated into an organic layer. In one embodiment, the glass body may include tempered glass.

[0048] In some embodiments, the glass body (105) may not include any vacancies or etched spaces (e.g., recesses, grooves, cavities, etc.) other than the through via holes for forming the through glass vias (110).

[0049] The dielectric constant of the glass body (105) may be 1 to 10 at 1 MHz, preferably 1 to 7, 1 to 5, or 1 to 3. The loss tangent (dielectric loss) of the glass body (105) may be 0.00005 to 0.001, for example, 0.0005 to 0.001. The thermal expansion coefficient of the glass body (105) may be 1*10 -6 / K to 10 -5 / K, for example, 1*10 -6 / K to 5*10 -6 / K could be.

[0050] The thickness of the glass body (105) may be 25 µm to 1,000 µm, 50 µm to 1,000 µm, 100 µm to 1,000 µm, or 500 µm to 1,000 µm. The thickness of the glass body (105) may be appropriately adjusted within the above range in consideration of the thickness and number of layers of the wiring laminate (WS) described later.

[0051] The through glass via (110) can extend as a single integral structure across the upper and lower surfaces of the glass body (105). The upper and lower surfaces of the through glass via (110) can be exposed to the upper and lower surfaces of the glass body (105), respectively.

[0052] For example, a through via hole (107) penetrating the upper and lower surfaces of the glass body (105) can be formed through laser drilling, etc. The through via hole can be filled with a metal material through a plating process (e.g., copper plating) to form a through glass via (110).

[0053] In some embodiments, the through glass via (110) may include a first portion (110-1) and a second portion (110-2). The first portion (110-1) and the second portion (110-2) may each have sidewalls that are inclined with respect to the thickness direction of the glass body (105). The second portion (110-2) may have a substantially reverse shape of the first portion (110-1). Accordingly, the adhesion of the through glass via (110) may be enhanced, and the phenomenon of the through glass via (110) falling off or falling off may be prevented.

[0054] The sidewall of the through glass via (110) may have a roughness surface (RS). According to exemplary embodiments, the surface roughness (Ra) of the roughness surface (RS) may be 0.5 μm to 2 μm.

[0055] When the surface roughness (Ra) of the roughness surface (RS) is less than 0.5 ㎛, sufficient adhesion between the side walls of the through glass via (110) and the through via hole (107) may not be secured. Accordingly, the phenomenon of the through glass via (110) falling off or detaching due to external mechanical or thermal shock can be prevented.

[0056] When the surface roughness (Ra) of the roughness surface (RS) exceeds 2㎛, cracks may occur inside the through glass via (110) and the glass body (105) due to the unevenness.

[0057] In some embodiments, the surface roughness (Ra) of the roughness surface (RS) may be 0.8 μm to 2 μm, preferably 1 μm to 2 μm, or 1.5 μm to 2 μm.

[0058] In the above illuminance range, sufficient adhesion can be more effectively secured while suppressing crack generation from the contact surface of the through glass via (110) and the glass body (105).

[0059] According to exemplary embodiments, preliminary through-via holes may be formed by performing laser drilling through the upper and / or lower surfaces of the glass body (105). In some embodiments, laser drilling may be performed simultaneously through the upper and lower surfaces of the glass body (105), respectively, to form preliminary through-via holes in the shape of opposite triangles or trapezoids facing each other in an hourglass shape.

[0060] An etchant (e.g., an acidic etchant such as hydrofluoric acid) may be supplied through the preliminary through-via hole to roughen the side surface of the preliminary through-via hole. Accordingly, a through-via hole (107) having a roughened surface (RS) may be formed.

[0061] Thereafter, a conductive material can be filled into the through-via hole (107) through the plating process described above to form a through-glass via (110). The roughness formed in the through-via hole (107) can be transferred to the through-glass via (110), thereby substantially sharing the roughness surface (RS).

[0062] According to exemplary embodiments, the surface roughness (Ra) of the roughness surface (RS) can be controlled by adjusting the laser intensity of the laser drilling, the concentration of the etchant, the temperature of the etchant, the contact time between the etchant and the side wall of the through via hole (107), etc.

[0063] In some embodiments, the diameter (diameter of the upper surface or lower surface) of the through glass via (110) or the through via hole (107) may be 25 μm to 300 μm, 30 μm to 200 μm, 30 μm to 100 μm, 30 μm to 80 μm, 30 μm to 70 μm, or 30 μm to 60 μm.

[0064] In some embodiments, the length of the through glass via (110), or the thickness of the glass body (105), may be 25 μm to 1,000 μm, 50 μm to 1,000 μm, 100 μm to 1,000 μm, 200 μm to 1,000 μm, 300 μm to 1,000 μm, 400 μm to 1,000 μm, or 500 μm to 1,000 μm.

[0065] Within the above-described diameter and thickness range, the adhesion of the through-glass via (110) can be enhanced and the breakage of the glass body (105) can be prevented through the formation of a roughness within the above-described range, while the electrical conductivity and high-frequency characteristics through the through-glass via (110) can be effectively implemented.

[0066] For example, if the diameter of the through-glass via (110) is excessively reduced, a sufficient contact area may not be secured. Accordingly, sufficient contact force may not be secured even within the above-described roughness range. Furthermore, if the diameter of the through-glass via (110) is excessively increased, micro-cracks in the glass body (105) may occur even within the above-described roughness range depending on the process conditions.

[0067] FIG. 2 is a schematic plan view showing a glass substrate according to exemplary embodiments.

[0068] Referring to FIG. 2, the glass substrate may include a plurality of through glass vias (110) and through via holes (107). For example, the plurality of through glass vias (110) may be repeatedly arranged along the row direction and the column direction.

[0069] The spacing distance (D1) between adjacent through-glass vias (110) or through-via holes (107) may be 40 μm to 1,000 μm. The spacing distance (D1) may be a horizontal distance between the centers of adjacent through-glass vias (110) or through-via holes (107). In the above range, concentration of local thermal expansion coefficient / bending stress of the glass substrate can be prevented. In one embodiment, the spacing distance (D1) may be 100 μm to 1,000 μm, or 100 μm to 800 μm.

[0070] FIG. 3 is a schematic cross-sectional view showing a glass substrate according to exemplary embodiments.

[0071] Referring to FIG. 3, the through glass via (110) may further include a conductive mediation layer (90). According to exemplary embodiments, the through glass via (110) may include a via body (115) and a conductive mediation layer (90) surrounding a side surface of the via body (115). The conductive mediation layer (90) may surround the entire side surface of the via body (115).

[0072] The via body (115) is formed by filling a conductive material through a plating process as described with reference to FIG. 1 and may correspond to a substantial through-glass (110).

[0073] The conductive intermediary layer (90) may include a metal having increased adhesion to the sidewall of the glass body (105) or the through via hole (107) compared to the via body (115). According to exemplary embodiments, the conductive intermediary layer (90) may include titanium (Ti), tantalum (Ta), chromium (Cr), nickel (Ni), or the like. These may be included alone or in combination of two or more. In one embodiment, the conductive intermediary layer (90) may include titanium (Ti).

[0074] According to exemplary embodiments, after forming the through via hole (107) as described above, a conductive mediation layer (90) may be formed through a deposition process such as a sputtering process. The conductive mediation layer (90) may be formed on the sidewall of the through via hole (107) and the upper and lower surfaces of the glass body (105).

[0075] Thereafter, a plating layer can be formed to fill the remaining portion of the through via hole (107) through a plating process (e.g., a copper plating process). The plating layer can also be formed on a portion of the conductive mediating layer (90) formed on the upper and lower surfaces of the glass body (105).

[0076] Thereafter, the conductive mediation layer (90) formed on the upper and lower surfaces of the glass body (105) and the conductive layer portion can be polished through a chemical mechanical polishing (CMP) process. Accordingly, a through glass via (110) formed within the through via hole (107) and including a via body (115) formed from the conductive mediation layer (90) and the plating layer can be formed.

[0077] The upper surface of the through glass via (110) may be positioned substantially coplanar with the upper surface of the glass body (105). The lower surface of the through glass via (110) may be positioned substantially coplanar with the lower surface of the glass body (105).

[0078] As illustrated in the dotted circle area of ​​FIG. 3, a first roughness surface (RS1) having the above-described roughness range may be included on the outer surface of the conductive mediation layer (90). As described above with reference to FIG. 1, the roughness formed on the side wall of the through via hole (107) may be transferred to the outer surface of the conductive mediation layer (90).

[0079] The inner surface of the conductive intermediary layer (90) can form a second roughness surface (RS2). Accordingly, the side surface of the via body (115) can share the second roughness surface (RS2).

[0080] When the conductive intermediary layer (90) covers the roughness surface of the through via hole (107), the surface roughness (Ra) of the second roughness surface (RS2) can be reduced compared to the surface roughness (Ra) of the first roughness surface (RS1). Accordingly, the occurrence of cracks within the via body (115) by the roughness surface can be suppressed, while also increasing the adhesion between the conductive intermediary layer (90) and the via body (115).

[0081] As described above, by bringing the conductive intermediary layer (90) into contact with the side surface of the through via hole (107), the overall adhesion of the through glass via (110) to the glass body (105) can be increased. Accordingly, even if shrinkage / expansion due to heat applied to the glass substrate (100) is repeated, detachment and peeling of the through glass via (110) can be prevented. In addition, detachment and peeling of the through glass via (110) can be prevented when the glass substrate (100) is bent. In addition, the conductive intermediary layer (90) can act as a facilitating layer for the plating process to improve the film quality and conductivity of the via body (115).

[0082] FIG. 4 is a schematic cross-sectional view showing a multilayer wiring board according to exemplary embodiments.

[0083] Referring to FIG. 4, the multilayer wiring board (200) (hereinafter, abbreviated as wiring board) may include the glass substrate (100) described above and a wiring laminate (WS) laminated on the glass substrate (100).

[0084] The glass substrate (100) has a low dielectric loss value and can be applied as a support substrate of a multilayer wiring board (200) to improve the low loss and high Q characteristics of the wiring board. In addition, the glass substrate (105) has a low coefficient of thermal expansion and can effectively suppress warpage occurring during high-temperature operation and build-up processes of the wiring board.

[0085] The wiring laminate (WS) may be an organic substrate including wiring layers. According to exemplary embodiments, the wiring laminate (WS) may include insulating layers (120) and wiring layers (130) that are repeatedly laminated from the upper surface of the glass substrate (100). According to exemplary embodiments, the wiring layers (130) and the insulating layers (120) may be build-up wiring layers and build-up insulating layers that are alternately and repeatedly laminated, respectively.

[0086] For example, the wiring layers (130) may include a first wiring layer (130a), a second wiring layer (130b), a third wiring layer (130c), a fourth wiring layer (130d), and a fifth wiring layer (130e). The insulating layers (120) may include a first insulating layer (120a), a second insulating layer (120b), a third insulating layer (120c), and a fourth insulating layer (120d).

[0087] According to exemplary embodiments, on the upper surface of the glass substrate (105), wiring layers (130) and insulating layers (120) may be alternately and repeatedly laminated in the following order: a first wiring layer (130a), a first insulating layer (120a), a second wiring layer (130b), a second insulating layer (120b), a third wiring layer (130c), a third insulating layer (120c), etc.

[0088] However, the number of wiring layers (130) and insulating layers (120) illustrated in FIG. 4 is only an example provided for convenience of explanation, and the number of layers and circuit design of the wiring laminate (WS) are not limited as illustrated in FIG. 4.

[0089] The wiring layers (130) can be formed by forming a conductive layer on the upper surface of the glass substrate (100) or on any one of the insulating layers (120), and then patterning the conductive layer through an etching process. The conductive layer can be formed through a deposition process such as a plating process or a sputtering process.

[0090] In some embodiments, the wiring layers (130) may be formed through a SAP process (Semi-Additive Process), an M-SAP process (Modified Semi-Additive Process), or a tenting process.

[0091] The wiring layers (130) may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, and preferably may include copper (Cu).

[0092] The insulating layers (120) may each be formed to cover the wiring layer (130). The insulating layers (120) may be formed using a photosensitive resin such as an acrylic resin and / or a thermosetting resin such as an epoxy resin.

[0093] The wiring laminate (WS) may further include interlayer connection conductors (140) that interconnect the wiring layers (120). The interlayer connection conductors (140) are disposed between wiring layers (130) of different levels and refer to conductors formed within the insulating layer (120).

[0094] In some embodiments, the interlayer interconnect conductor (140) may include interlayer vias that connect wiring layers (130) arranged at different levels.

[0095] In some embodiments, the interlayer interconnect conductor (140) may include a wiring-TGV via (140a) that interconnects the through-glass via (110) and the wiring layer (130) (e.g., the second wiring layer (130b)). The wiring-TGV via (140a) may be in direct contact with the through-glass via (110) and the second wiring layer (130b).

[0096] As described with reference to FIG. 3, the through glass via (110) may include a via body (115) and a conductive intermediary layer (90) surrounding the side surface of the via body (115).

[0097] In some embodiments, the interlayer interconnect conductor (140) may include an interlayer via (140b) that interconnects the upper and lower wiring layers (130) with each other.

[0098] According to embodiments of the present invention, a passive element may be included within the wiring laminate (WS). For example, the wiring laminate (WS) may be provided as an integrated passive device (IPD) substrate having the passive element built into it.

[0099] According to exemplary embodiments, the passive component may be implemented as an inherent component formed by the arrangement of wiring layers (130) and insulating layers (120) rather than being inserted into the wiring stack (WS) as a separate chip.

[0100] The passive components may include inductors, capacitors, resistors, and the like. In some embodiments, the passive components may include a first passive component (PE1), a second passive component (PE2), and a third passive component (PE3).

[0101] The first passive element (PE1), the second passive element (PE2), and the third passive element (PE3) may each be different types of passive elements. For example, the first passive element (PE1) may include a conductor pattern included in the second wiring layer (130b) and a conductor pattern included in the third wiring layer (130c), and the conductor patterns may face each other with the second insulating layer (120b) interposed therebetween. Accordingly, the first passive element (PE1) may be provided as a capacitor.

[0102] The second passive element (PE2) may include, for example, a line pattern having a relatively large length included in the fourth wiring layer (120d). Accordingly, the second passive element (PE2) may be provided as a resistor.

[0103] The third passive element (PE3) may include a coil in which at least two layers of wiring layers are connected through interlayer connecting conductors (140) (e.g., interlayer vias). Accordingly, the third passive element (PE3) may be provided as an inductor.

[0104] As described above, a passive component embedded in a wiring substrate (100) or a wiring laminate (WS) can be designed by utilizing the wiring layers (130), insulating layers (120), and / or interlayer connection conductors (140) included in the wiring laminate (WS). According to exemplary embodiments, the passive component may not include any other configuration / structure other than the wiring layer (130), insulating layer (120), and / or interlayer connection conductor (140).

[0105] Therefore, a separate, isolated chip-type passive element having a material different from that included in the wiring laminate (WS) is not included, and an increase in warpage due to differences in physical properties, such as the coefficient of thermal expansion, of the chip-type passive element can be prevented.

[0106] In addition, the integration density of passive components can be easily controlled by adjusting the line and space of the wiring layers (130). Accordingly, high integration density of passive components can be efficiently implemented, and an RF substrate can be effectively provided.

[0107] As described above, the passive element can be designed to be integrated with the wiring layer (130). Therefore, compared to a case where a separate chip is embedded, signal loss can be reduced and high Q characteristics can be enhanced.

[0108] According to exemplary embodiments, the wiring laminate (WS) and the glass substrate (100) may not include a chip-accommodating space, such as a cavity, recess, or through-hole, for inserting / embedding an electric element in the form of a chip (e.g., a passive element and an active element such as an IC chip), therein. Accordingly, mechanical defects, such as a decrease in substrate rigidity or warping due to the chip-accommodating space, can be prevented.

[0109] Through-glass vias (110) can be classified according to the conductive pattern included in the wiring laminate (WS) to which they are connected. In some embodiments, the through-glass vias (110) can include a first through-glass via (110a), a second through-glass via (110b), and a third through-glass via (110c).

[0110] Interlayer connection conductors (140) and wiring layers (130) may be alternately and sequentially laminated on the first through-glass via (110a) to form a common interconnect structure (CI). For example, the common interconnect structure (CI) may provide the shortest electrical signal path across the glass substrate (100) and the wiring laminate (WS) in the vertical direction or thickness direction of the wiring substrate (100).

[0111] The above-described wiring-TGV via (140a) may be laminated or in contact with the upper surface of the first through-glass via (110a). Wiring layers (120) and interlayer vias (140b) may be alternately and repeatedly laminated on the wiring-TGV via (140a) to form a common interconnect structure (CI).

[0112] The common interconnect structure (CI) may be provided as a substantially single pillar. For example, a virtual centerline vertically penetrating the first through-glass via (110a) may penetrate the entire common interconnect structure (CI).

[0113] The second through-glass via (110b) can be connected to a passive element. For example, it can be connected to the first passive element (PE1) through a wiring-TGV via (140a).

[0114] The third through-glass via (110c) may be connected to the wiring layer (120). For example, the third through-glass via (110c) may be electrically connected to the first wiring layer (130a) through a wiring-TGV via (140a) and an interlayer via (140b).

[0115] A lower wiring layer (190) and a lower insulating layer (180) can be laminated on the lower surface of the glass substrate (100). A lower wiring via (195) can be connected or in contact with the lower wiring layer (190).

[0116] The common interconnect structure (CI) may further include a TGV connecting via (197) that contacts the lower surface of the through glass via (110).

[0117] The wiring laminate (WS) may be provided as an upper wiring / insulating structure of the wiring board (100). The uppermost wiring layer (e.g., the fifth wiring layer (130e)) included in the wiring laminate (WS) may include a pad for mounting an electronic component. For example, an active component such as a semiconductor die, an AP chip, an IC chip, etc. may be mounted on the pad by soldering or wire bonding.

[0118] In some embodiments, the TGV connection via (197) and the lower wiring via (195) may be connected to the motherboard via conductive balls or soldering.

[0119] FIG. 5 is a schematic cross-sectional view illustrating an example implementation of a passive component included in a multilayer wiring board according to exemplary embodiments. For example, FIG. 5 illustrates an example implementation of a second passive component (PE2) provided as a resistor.

[0120] Referring to FIG. 5, a line pattern (132a) included in the wiring layers (130) may be placed on a lower insulating layer (e.g., a third insulating layer (120c)). An upper insulating layer (e.g., a fourth insulating layer (120d)) may be in direct contact with the line pattern (132a) and cover the line pattern (132a). Resistance may be adjusted depending on the length of the line pattern (132a), thereby providing a passive element that functions as a resistor.

[0121] A connection electrode (141) may be formed at each end of the line pattern (132a). The connection electrode (141) may penetrate the upper insulating layer and contact or be connected to the line pattern (132a). A terminal electrode (132b) may be formed on the upper insulating layer and contact or be connected to the connection electrode (141).

[0122] The line pattern (132a) is included as a configuration of one of the wiring layers (130), and can be formed at the same level with substantially the same material and the same process as the wiring layer (130). The terminal electrode (132b) is also included as a configuration of one of the wiring layers (130) (e.g., the uppermost wiring layer (e.g., the fifth wiring layer (130e))) among the wiring layers (130), and can be formed at the same level with substantially the same material and the same process as the wiring layer (130).

[0123] The connecting electrode (141) is included as a component of one layer of the interlayer connecting conductor (140) among the interlayer connecting conductors (140), and can be formed at the same level using substantially the same material and the same process as the interlayer connecting conductor (140).

[0124] FIG. 6 is a schematic cross-sectional view illustrating an example implementation of a passive component included in a multilayer wiring board according to exemplary embodiments. For example, FIG. 6 illustrates an example implementation of a first passive component (PE1) provided as a capacitor.

[0125] Referring to Fig. 6, the first electrode (131) and the second electrode (133) can be placed facing each other with an insulating layer (120) therebetween. Accordingly, a passive element of a MIM (Metal-Insulator-Metal) capacitor structure can be implemented.

[0126] The first electrode (131) and the second electrode (133) are each included as a component of one of the wiring layers (130), and can be formed at the same level using substantially the same material and the same process as the wiring layer (130).

[0127] As illustrated in Fig. 6, the first electrode (131) and the second electrode (133) may each be connected to an interlayer connection conductor (140) (see the first passive element (PE1)). The interlayer connection conductor (140) connected to the first electrode (131) and the second electrode (133) may be provided as a terminal electrode or an external electrode.

[0128] Figure 7 is a schematic perspective view illustrating implementation examples of passive components included in a multilayer wiring board according to exemplary embodiments. Figure 7 illustrates one implementation example of a capacitor as a passive component.

[0129] Referring to FIG. 7, one of the wiring layers (130) may be provided as a first terminal electrode (134) (or a first external electrode), and one of the wiring layers (130) may be provided as a second terminal electrode (136) (or a second external electrode). In one embodiment, the first terminal electrode (134) and the second terminal electrode (136) may be included in a wiring layer (130) of the same level. Alternatively, the first terminal electrode (134) and the second terminal electrode (136) may be included in wiring layers (130) of different levels.

[0130] Internal electrodes may be distributed within the insulating layer (120). For example, first internal electrodes (142) and second internal electrodes (144) may be alternately repeated in the horizontal direction.

[0131] One end of the first internal electrodes (142) can be in contact with or connected to the first terminal electrode (134). The other end of the second internal electrodes (144) (the ends opposite to the one end of the first internal electrodes (152)) can be in contact with or connected to the second terminal electrode (136).

[0132] A capacitance can be formed in the insulating layer (120) portion between the first internal electrode (142) and the second internal electrode (144) that are adjacent to each other. Accordingly, a passive element having a multilayer capacitor structure can be implemented.

[0133] The first internal electrodes (142) and the second internal electrodes (144) are included as a configuration of one layer of the interlayer connection conductor (140) among the interlayer connection conductors (140), and can be formed at the same level using substantially the same material and the same process as the interlayer connection conductor (140).

[0134] FIG. 8 is a schematic plan view illustrating an example implementation of a passive component included in a multilayer wiring board according to exemplary embodiments. For example, FIG. 8 illustrates an example implementation of a third passive component (PE3) provided as an inductor.

[0135] Referring to FIG. 8, a first coil part (138) is disposed on a lower insulating layer (not shown) (e.g., a second insulating layer (120b)), and an upper insulating layer (not shown) (e.g., a third insulating layer (120c)) may be in contact with the first coil part (138) and cover the first coil part (138). A second coil part (139) may be disposed on the upper insulating layer.

[0136] The first coil section (138) and the second coil section (139) can be connected to each other by a coil via (not shown) penetrating the upper insulating layer. Accordingly, a coil-shaped inductor having multiple turns can be implemented.

[0137] The first coil portion (138) and the second coil portion (139) are each included as a configuration of one of the wiring layers (130), and can be formed at the same level using substantially the same material and the same process as the wiring layer (130).

[0138] The above coil via is included as a component of one layer of the interlayer connection conductor (140) among the interlayer connection conductors (140), and can be formed at the same level with substantially the same material and the same process as the interlayer connection conductor (140).

[0139] Terminal electrodes (not shown) may be contacted or connected to the ends of the first coil portion (138) and the second coil portion (139), respectively. The terminal electrodes are included as a component of one layer of the interlayer connection conductors (140) among the interlayer connection conductors (140), and may be formed at the same level using substantially the same material and the same process as the interlayer connection conductor (140).

[0140] FIGS. 9 and 10 are schematic perspective and cross-sectional views, respectively, illustrating one embodiment of a passive component included in a multilayer wiring board according to exemplary embodiments. For example, FIG. 10 is a cross-sectional view taken vertically or in the thickness direction along line II' of FIG. 9.

[0141] Referring to FIGS. 9 and 10, one of the wiring layers (130) may include a first terminal electrode (135) (or a first external electrode) and lower connection electrodes (135a). The upper wiring layer (130) may include a second terminal electrode (137) (or a second external electrode) and upper connection electrodes (137a) with an insulating layer (120) therebetween relative to the first terminal electrode (135) and lower connection electrodes (135a).

[0142] Coil vias (145) may be distributed within the insulating layer (120). The coil vias (145) are included as a component of one layer of the interlayer connection conductors (140) among the interlayer connection conductors (140), and may be formed at the same level using substantially the same material and the same process as the interlayer connection conductor (140).

[0143] A first terminal electrode (135) and a second terminal electrode (137) may be connected through coil vias (145) and connection electrodes (135a, 137a) to form a coil-shaped inductor. According to exemplary embodiments, neighboring coil vias (145) in the width direction may be connected to each other by an upper connection electrode (137a), and neighboring coil vias (145) in a diagonal direction with respect to the width direction may be connected to each other by a lower connection electrode (135a). Accordingly, a conductor may be repeated in a zigzag pattern across the lower and upper layers to form a coil.

[0144] The multilayer wiring board (200) described above can be applied as a circuit board for highly integrated electronic devices such as smart phones, PCs, semiconductor packages, etc. A glass substrate (100) and a passive component-embedded wiring laminate can be combined to provide a thin circuit board with low loss, high Q, and high speed.

[0145] Hereinafter, preferred embodiments are presented to help understand the present invention, but these embodiments are only illustrative of the present invention and do not limit the scope of the appended claims. It is obvious to those skilled in the art that various changes and modifications to the embodiments are possible within the scope and technical idea of ​​the present invention, and it is also natural that such changes and modifications fall within the scope of the appended claims.

[0146] Examples and Comparative Examples

[0147] Example 1

[0148] A 50 μm diameter through-glass via (110) was formed through copper plating within a 1 mm thick glass body (105). Specifically, a preliminary through-glass via hole was formed in the glass body (105) through UV Pico laser drilling (laser power: 20 W / 1.5 sec). A 20% concentration hydrofluoric acid solution was brought into contact with the preliminary through-via hole at 25°C for 60 minutes to form a through-via hole having a roughness surface (Rs). A Ti layer was deposited on the through-via hole through a sputtering process to form a conductive mediating layer. Thereafter, a plating layer was formed through copper plating, and a through-glass via was formed through a CMP process.

[0149] Other Examples and Comparative Examples

[0150] Through-glass vias were formed by changing the diameter of the through-glass via (through-via hole) and the spacing between adjacent vias, or by controlling the laser power, concentration of the hydrofluoric acid solution, temperature, and contact time, etc., to change the surface roughness (Ra) as described in Table 1.

[0151] Surface roughness was measured using the KEYENCE Laser Microscope VK-1000 model based on KSBISO4287.

[0152] In Example 18, the conductive intermediary layer was omitted and the through-via hole was filled with a plating layer to form a through-glass via.

[0153] Experimental example

[0154] (1) Cross-cut peeling test

[0155] The adhesion of the glass body and through-glass vias was evaluated by cross-cut testing. Specifically, cross-sections including through-glass vias were cut into grid units according to the ASTMD 3359 (Method B) standard, and the peel strength of the through-glass vias was evaluated on a scale from 0B to 5B using tape (Nitto Tape 50B).

[0156] (2) Crack evaluation

[0157] During the above peeling test experiment, the occurrence of cracks in the glass body was evaluated according to the criteria below.

[0158] ◎: No cracks on the glass body at the peeling surface

[0159] ○: Fine cracks appear on the outside of the glass body in some cases when peeling off.

[0160] △: When peeled, micro cracks occur on the entire outside of the glass body.

[0161] X: Crack propagation clearly observed from the peeling surface into the glass body

[0162] (3) Coating property evaluation

[0163] After coating the conductive mediator layer, the area ratio of the portion coated by the conductive mediator layer to the total sidewall area of ​​the through via hole was measured and evaluated as follows.

[0164] ◎: Coating of more than 95% of the sidewall area of ​​the through via hole

[0165] ○: Coating of 90% or more and less than 95% of the sidewall area of ​​the through via hole

[0166] △: Coating of 80% or more and less than 90% of the sidewall area of ​​the through via hole

[0167] X: Coating of 80% or more and less than 90% of the through via hole sidewall area

[0168] The evaluation results are shown in Table 1 below.

[0169] ClassificationSurface roughness (Ra, ㎛)Via diameter (㎛)Via spacing (㎛)Peeling strengthCrack occurrenceCoating propertyExample 10.550505B◎◎Example 20.850505B◎◎Example 31.050505B◎◎Example 41.550505B◎◎Example 51.850505B◎◎Example 6250505B◎◎Example 71.020504B◎△Example 81.025505B◎○Example 91.030505B◎○Example 101.040505B◎○Example 111.080505B◎◎Example 121.01001005B◎◎Example 131.02002005B○◎Example 141.03003005B○◎Example 151.03503505B△◎Example 161.050305B△◎Example 171.050405B○◎Example 180.550503B◎◎Comparative Example 10.450503B◎◎Comparative Example 20.150502B◎◎Comparative Example 32.150504B△△Comparative Example 42.550502B△X

[0170] Referring to Table 1, the surface roughness (Ra) was adjusted according to the exemplary embodiments described above, thereby improving the adhesion of the through-glass via and suppressing cracks in the glass body.

[0171] In Example 7, the peel strength decreased somewhat as the via diameter decreased. In Example 15, as the via diameter increased, some microcracks in the glass body at the peel surface were observed.

[0172] In Example 16, where the spacing between vias was reduced, microcracks in the glass body were observed due to the increase in the number of vias.

[0173] In Example 18, where the conductive intermediary layer was omitted, the peel strength was somewhat reduced compared to other examples.

Claims

1. Glass body; and Includes a through glass via (TGV) penetrating the glass body, A glass substrate having a surface roughness (Ra) of the side surface of the above-mentioned through glass via of 0.5 ㎛ to 2 ㎛.

2. A glass substrate according to claim 1, wherein the surface roughness (Ra) of the side surface of the through glass via is 0.8 µm to 2 µm.

3. A glass substrate according to claim 1, wherein the diameter of the upper or lower surface of the through glass via is 25 µm to 300 µm.

4. A glass substrate according to claim 3, wherein the diameter of the upper or lower surface of the through glass via is 30 µm to 100 µm.

5. In claim 1, a plurality of through glass vias are included, A glass substrate, wherein the distance between adjacent through-glass vias is 40 μm to 1,000 μm.

6. A glass substrate according to claim 1, wherein the through glass via comprises a via body and a conductive intermediary layer surrounding a side surface of the via body.

7. A glass substrate according to claim 6, wherein the conductive intermediary layer comprises at least one of titanium (Ti), tantalum (Ta), chromium (Cr), and nickel (Ni).

8. The glass substrate of claim 1; and A multilayer wiring board comprising a wiring laminate including repeatedly laminated wiring layers, insulating layers and interlayer connection conductors, which is disposed on the upper surface of the glass substrate.

9. In claim 8, the wiring laminate is a multilayer wiring board having a passive element formed by the wiring layers, the interlayer connection conductors, or the insulating layers.

10. A multilayer wiring board according to claim 9, wherein the passive element includes at least one of a resistor, a capacitor, and an inductor.

11. A multilayer wiring board according to claim 10, wherein the register includes a line pattern included in one of the wiring layers.

12. A multilayer wiring board according to claim 10, wherein the capacitor includes first electrodes and second electrodes respectively included in different levels of wiring layers among the wiring layers, and an insulating layer disposed between the first electrode and the second electrode among the insulating layers.

13. In claim 10, the capacitor, A first terminal electrode and a second terminal electrode spaced apart from each other and included in the above wiring layers; Among the interlayer connecting conductors, first internal electrodes and second internal electrodes are included in one layer of the interlayer connecting conductors, A multilayer wiring board, wherein one end of the first internal electrodes is connected to the first terminal electrode, and the other end of the second internal electrodes is connected to the second terminal electrode.

14. A multilayer wiring board according to claim 13, wherein the first internal electrodes and the second internal electrodes are alternately repeated within one of the insulating layers.

15. A multilayer wiring board according to claim 10, wherein the inductor comprises a first coil portion and a second coil portion respectively included in different wiring layers among the wiring layers, and a coil via connecting the first coil portion and the second coil portion.

16. A multilayer wiring board according to claim 15, wherein the coil via is included in one layer of the interlayer connection conductors among the interlayer connection conductors.

17. In claim 10, the inductor First terminal electrodes and lower connection electrodes included in one of the above wiring layers; Second terminal electrodes and upper connection electrodes included in another wiring layer among the above wiring layers; A multilayer wiring board comprising coil vias connected in a zigzag manner by the lower connecting electrodes and the upper connecting electrodes.

18. A multilayer wiring board according to claim 17, wherein the coil vias are included in an interlayer connection conductor disposed within an insulating layer between the one wiring layer and the other wiring layer.

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