Circuit board and semiconductor package comprising same

Abstract

The present invention provides a circuit board comprising: a core layer including a through hole; and a connection member disposed on the inner side of the through hole of the core layer, wherein an inner wall surface of the core layer forming the through hole includes a stepped portion, and the connection member is disposed on the stepped portion.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to mount more semiconductor chips on a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices such as mobile devices, servers, and PCs, along with the adoption of High Bandwidth Memory (HBM), have led to larger semiconductor chip areas and the attachment of multiple semiconductor chips to a single package substrate to shorten the electrical connection distance between them, thereby increasing the size of the package. Furthermore, as the functions required for application processors increase, there is a growing need for separate processor chips for each function, and circuit boards capable of mounting these processor chips are required.

[0005] At this time, for the above application processor, even when it is separated into two processor chips by function, the number of terminals (Input / Output) provided in each processor chip is increasing.

[0006] Furthermore, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and faster communication speeds, the number of terminals on processor chips is steadily increasing due to the increase in power and signal capacity. Consequently, the area, thickness, and circuit pattern density of circuit boards are also increasing. Furthermore, increased circuit board area and thickness can make product miniaturization difficult, leading to reliability issues such as board warping and increased product price.

[0007] Furthermore, there is a recent trend toward thicker core layers in circuit boards to prevent problems such as warpage. However, utilizing thick core layers can lead to difficulties in forming via electrodes on the core layer, such as yield, density of the spacing between via electrodes, and productivity.

[0008] In addition, increasing the density of circuit patterns is more advantageous in terms of product price, reliability such as warpage, and product miniaturization than increasing the area and thickness of the circuit board. Therefore, there is a recent trend to prevent problems such as warpage of the circuit board by providing a thick core layer of the circuit board. However, when using a thick core layer, there may be difficulties in the yield, density of the spacing between via electrodes, and productivity in forming the via electrodes of the core layer. In addition, the number (or count) of terminals (input / output, IO) provided on each processor chip is increasing, and the number of chips mounted on the board is also increasing. Accordingly, it is also necessary to increase the input / output count of the circuit board to correspond to the increase in the terminals of the chip and the increase in the number of chips.

[0009] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, in which stress balance is easily achieved and warpage is prevented even when multiple elements are positioned on the upper portion of the circuit board, by positioning the core material corresponding to an area where a connecting member is mounted in the core layer.

[0010] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved reliability by facilitating heat dissipation upward through the difference in thickness between the first resin material and the second resin material, thereby improving heat dissipation efficiency, and further improving stress balance through the difference in thickness between the upper build-up layer and the lower build-up layer.

[0011] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved electrical reliability by easily realizing positional alignment and fixation between a connecting member and a core layer through a bonding member arranged on a mounting surface of a core layer, thereby preventing tilting of the connecting member even during a thermal process, etc.

[0012] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, in which stress balance is easily achieved and warpage is prevented even when multiple elements are positioned on the upper portion of the circuit board by having an asymmetrical structure in which the core material in the core layer is biased to one side (e.g., the upper portion).

[0013] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved reliability by facilitating heat dissipation upward through the difference in thickness between the first resin material and the second resin material, thereby improving heat dissipation efficiency, and further improving stress balance through the difference in thickness between the upper build-up layer and the lower build-up layer.

[0014] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, which improves the input / output count of the circuit board through a cavity disposed in some insulating layers.

[0015] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, in which electrical connection between a semiconductor element or chip mounted in a cavity and the board is easy and reliability is improved by forming an inlet portion on the inner surface of an insulating layer having a cavity.

[0016] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, which can easily perform desmear through an inlet portion of the insulating layer to protect the inner surface of the insulating layer and suppress electrical connection between semiconductor elements and electrodes.

[0017] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, which further improve the input / output count by forming a circuit pattern or a circuit pattern layer on the upper portion of the lead portion on the inner surface of the insulating layer.

[0018] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0019] A circuit board according to an embodiment of the present invention includes a core layer including a through hole; and a connecting member disposed inside the through hole of the core layer; wherein an inner wall surface of the core layer forming the through hole includes a step portion, and the connecting member is disposed on the step portion.

[0020] The core layer may further include an upper build-up layer disposed on top of the core layer and within the through hole, and the core layer may include a core material and a first resin material and a second resin material that are disposed asymmetrically with respect to the core material.

[0021] The above through hole may include a first region disposed at a lower portion of the connecting member and a second region positioned above the first region and at least partially overlapping the connecting member in a horizontal direction.

[0022] The thickness of the first resin material may be smaller than the thickness of the second resin material.

[0023] The first resin material and the core material may overlap the second region in a horizontal direction.

[0024] A portion of the second resin material may overlap the second region in a horizontal direction.

[0025] The second resin material may have a thickness in a region horizontally overlapping with the second region that is smaller than a thickness in a region horizontally overlapping with the first region.

[0026] The above first region can overlap the above second resin material in a horizontal direction.

[0027] The width of the first region may be smaller than the width of the connecting member.

[0028] The above step portion may be positioned between the first region and the second region.

[0029] The width of the second region may be greater than the width of the connecting member.

[0030] The inner wall surface of the above-mentioned through hole has a first inner wall surface located in the first region and a second inner wall surface located in the second region, and the first inner wall surface can be positioned spaced apart from the inner side of the second inner wall surface.

[0031] The above through hole may include a mounting surface disposed between the first inner wall surface and the second inner wall surface.

[0032] It may further include a bonding member arranged on the above-mentioned mounting surface.

[0033] The width of the first region may be smaller than the width of the second region.

[0034] The core layer includes a lower region and an upper region disposed on the lower region, wherein the lower region overlaps with the first region in a horizontal direction, and the upper region can overlap with the second region in the horizontal direction.

[0035] The thickness of the lower region and the thickness of the upper region may be different.

[0036] The first resin material and the core material may be located in the upper region, and the second resin material may be located in the lower region.

[0037] In addition, a circuit board according to an embodiment includes a core layer including a cavity; a bridge substrate disposed in the cavity; an upper build-up layer disposed on top of the core layer and within the cavity; and a lower build-up layer disposed under the core layer; wherein the core layer includes a core material, a first resin material disposed on top of the core material, and a second resin material disposed under the core material, and the first resin material and the second resin material have different thicknesses, and the thickness of the upper build-up layer and the thickness of the lower build-up layer are different.

[0038] The thickness of the upper build-up layer may be less than the thickness of the lower build-up layer.

[0039] The thickness of the first resin material may be smaller than the thickness of the second resin material.

[0040] The shortest distance from the core material to the lower surface of the upper build-up layer may be smaller than the shortest distance from the core material to the upper surface of the lower build-up layer.

[0041] A first protective layer disposed on the upper build-up layer;

[0042] It may include a second protective layer disposed below the lower build-up layer.

[0043] The thickness of the upper build-up layer may be greater than the thickness of any one of the lower build-up layer, the first protective layer, and the second protective layer.

[0044] The lower build-up layer, the first protective layer and the second protective layer may have the same thickness.

[0045] The thickness of the lower build-up layer may be smaller than the thickness of any one of the upper build-up layer, the first protective layer, and the second protective layer.

[0046] The upper build-up layer, the first protective layer, and the second protective layer may have the same thickness.

[0047] The thickness of the core material may be smaller than the total thickness of the first resin material and the second resin material.

[0048] A circuit board according to an embodiment includes a first insulating layer; and a second insulating layer disposed on the first insulating layer, the second insulating layer including a first build-up layer, and a second build-up layer disposed between the first build-up layer and the first insulating layer, the first build-up layer and the second build-up layer each including a first through hole and a second through hole, the first through hole and the second through hole overlapping in a stacking direction, and a width of the first through hole being smaller than a width of the second through hole.

[0049] The second insulating layer may include an edge portion outside the first through hole and the second through hole.

[0050] The second insulating layer includes an inlet portion that is misaligned with the first through hole in the stacking direction, and the inlet portion can overlap at least partially with the first build-up layer in the stacking direction.

[0051] It may include a first core wiring portion arranged on the first insulating layer; and a build-up wiring portion arranged on the second insulating layer.

[0052] The above-mentioned lead portion may overlap at least partially with the above-mentioned build-up wiring portion in the stacking direction.

[0053] The distance between the above-mentioned inlet portions in the vertical direction of the stacking direction may be 100 um to 200 um.

[0054] At least a portion of the above first core wiring portion may be exposed by the second through hole.

[0055] The edge portion may have a distance from the center of the first through hole in the first build-up layer that is smaller than a distance from the center of the second through hole in the second build-up layer.

[0056] The edge portion may increase in distance from the center of the first through hole in the first build-up layer along the stacking direction.

[0057] The edge portion may have a distance that decreases along the stacking direction from the center of the second through hole in the second build-up layer.

[0058] The side surface of the second through hole may have a curved surface.

[0059] The second insulating layer includes a dummy layer disposed inside, and the dummy layer can be exposed by the lead-in portion.

[0060] The above dummy layer may be located outside the second through hole.

[0061] The above first insulating layer and the above first core wiring portion may be a copper-clad laminate.

[0062] A package substrate according to an embodiment includes a circuit board; a semiconductor element connected to the circuit board; and a connection portion connecting the semiconductor element and the circuit board, wherein the circuit board includes a first insulating layer; and a second insulating layer disposed on the first insulating layer, wherein the second insulating layer includes a first build-up layer and a second build-up layer disposed between the first build-up layer and the first insulating layer, wherein the first build-up layer and the second build-up layer each include a first through hole and a second through hole, wherein the first through hole and the second through hole overlap in a stacking direction, and a width of the first through hole is smaller than a width of the second through hole.

[0063] An embodiment of the present invention implements a circuit board and a semiconductor package including the same, in which stress balance is easily achieved and warpage is prevented even when multiple elements are positioned on the upper portion of the circuit board, by positioning the core material corresponding to an area where a connecting member is mounted in the core layer.

[0064] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved reliability by facilitating heat dissipation upward through the difference in thickness between the first resin material and the second resin material, thereby improving heat dissipation efficiency, and further improving stress balance through the difference in thickness between the upper build-up layer and the lower build-up layer.

[0065] In addition, the embodiment facilitates alignment and fixation between a connecting member and a core layer through a bonding member disposed on a mounting surface of a core layer, thereby preventing tilting of the connecting member even during a thermal process, etc., thereby enabling implementation of a circuit board and a semiconductor package including the same with improved electrical reliability.

[0066] In addition, the embodiment can implement a circuit board and a semiconductor package including the same in which stress balance is easily achieved and warpage is prevented even when multiple elements are positioned on the upper part of the circuit board by having an asymmetrical structure in which the core material in the core layer is biased to one side (e.g., the upper part).

[0067] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved reliability by facilitating heat dissipation upward through the difference in thickness between the first resin material and the second resin material, thereby improving heat dissipation efficiency, and further improving stress balance through the difference in thickness between the upper build-up layer and the lower build-up layer.

[0068] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, which improves the input / output count of the circuit board through a cavity disposed in some insulating layers.

[0069] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, in which electrical connection between a semiconductor element or chip mounted in a cavity and the substrate is easy and reliability is improved by forming an inlet portion on the inner surface of an insulating layer having a cavity.

[0070] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, which can easily perform desmear through the lead-in portion of the insulating layer to protect the inner surface of the insulating layer and suppress electrical connection between semiconductor elements and electrodes.

[0071] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, which further improve the input / output count by forming a circuit pattern or a circuit pattern layer on the upper portion of the lead portion on the inner side of the insulating layer.

[0072] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0073] Figure 1 is a plan view of a package substrate according to an embodiment of the present invention.

[0074] Figure 2 is a perspective view of a package substrate according to an embodiment of the present invention;

[0075] Figure 3 is a drawing taken along line II' in Figure 1,

[0076] Figure 4 is a cross-sectional view of a circuit board according to the first embodiment of the present invention.

[0077] Figure 5 is an enlarged view of part K1 in Figure 4,

[0078] Figure 6 is an enlarged view of the K2 portion in Figure 4,

[0079] Figure 7 is an enlarged view of a portion of a part of Figure 6,

[0080] Figure 8 is an enlarged view of part K3 in Figure 4,

[0081] Fig. 9 is a modified example of Fig. 6,

[0082] Figures 10 to 16 are drawings explaining a method for manufacturing a circuit board according to the first embodiment of the present invention.

[0083] Fig. 17 is a cross-sectional view of a circuit board according to the second embodiment,

[0084] Figure 18 is an enlarged view of part K4 in Figure 18,

[0085] Figure 19 is an enlarged view of part K5 in Figure 18,

[0086] Figure 20 is a cross-sectional view of a circuit board according to a third embodiment of the present invention.

[0087] Figure 21 is an enlarged view of K6 in Figure 20,

[0088] Figure 22 is an enlarged view of K7 in Figure 20,

[0089] Fig. 23 is a modified example of Fig. 22,

[0090] Fig. 24 is another modified example of Fig. 22,

[0091] Fig. 25 is another modified example of Fig. 22,

[0092] Fig. 26 is another modified example of Fig. 22,

[0093] Figures 27 to 33 are drawings explaining a method for manufacturing a circuit board according to a third embodiment of the present invention.

[0094] Fig. 34 is a drawing of a circuit board according to the fourth embodiment,

[0095] Figure 35 is an enlarged view of a portion of Figure 34.

[0096] Fig. 36 is a plan view of a circuit board according to the fourth embodiment.

[0097] Fig. 37 is a modified example of Fig. 36,

[0098] Figures 38 to 40 are flowcharts for a method of manufacturing a circuit board according to the fourth embodiment.

[0099] Fig. 41 is a drawing of a circuit board according to the fifth embodiment,

[0100] Figure 42 is an enlarged view of a portion of Figure 41.

[0101] Fig. 43 is a drawing of a circuit board according to the sixth embodiment.

[0102] Figure 44 is an enlarged view of a portion of Figure 43.

[0103] Fig. 45 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0104] Fig. 46 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0105] Fig. 47 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0106] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0107] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0108] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0109] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0110] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0111] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0112] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as a "first component," and similarly, a first component may also be referred to as a "second component." The terms "and / or" include a combination of multiple related items described herein or any of multiple related items described herein. These terms are only used to distinguish the component from other components and are not limited by the nature, order, or sequence of the component.

[0113] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0114] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0115] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0116] Additionally, the expression that configuration A is positioned between configurations B and C should also include the meaning that configuration A is positioned so that it overlaps configurations B and C at least partially in the horizontal and / or vertical directions.

[0117] Expressions referring to directions include horizontal directions, vertical directions, and include a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as a first horizontal direction (X-axis), a second horizontal direction (Y-axis), and a vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of overlapping along the horizontal direction should also include the meaning of overlapping along the first horizontal direction and / or overlapping along the second horizontal direction.

[0118] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0119] Furthermore, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood only as being in "direct contact" with a component B, it is described as being in "direct contact."

[0120] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0121] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0122] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may include a circuit board and semiconductor elements, and the semiconductor elements may be mounted on the circuit board.

[0123] A semiconductor device may include active components and / or passive components. An active component may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of components are integrated into a single chip. A semiconductor chip may be a logic chip, a memory chip, or the like. A logic chip may be a non-memory chip such as a central processor (CPU), a graphics processor (GPU), or a field programmable gate array (FPGA). For example, a logic chip may be an application processor (AP) chip that includes at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set that includes a specific combination of the above-mentioned components.

[0124] The memory chip may be a stacked memory such as HBM. Additionally, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0125] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0126] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is obvious that the electronic device may be any other electronic device that processes data.

[0127] FIG. 1 is a plan view of a package substrate according to an embodiment of the present invention, FIG. 2 is a perspective view of a package substrate according to an embodiment of the present invention, and FIG. 3 is a view taken along line II' in FIG. 1.

[0128] Referring to FIGS. 1 to 3, a package substrate according to an embodiment may include a main substrate in addition to semiconductor elements (DI1, DI2) and a circuit substrate (100). For example, the main substrate may be an FPGA substrate. In particular, the circuit substrate according to the first embodiment may be a substrate having a built-in connecting member.

[0129] The circuit board of the embodiment may include a first semiconductor element (DI1), a second semiconductor element (DI2), and a connecting member (BR). The first semiconductor element (DI1) and the second semiconductor element (DI2) may include a logic chip or a memory chip as described above. In addition, the first semiconductor element (DI1) and the second semiconductor element (DI2) may be different types of semiconductor elements as described above. In addition, the connecting member (BR) may be embedded in the circuit board (100). In particular, the connecting member (BR) may be embedded in a through hole of the circuit board (100). Various examples of circuit boards described below may be applied to the circuit board (100).

[0130] Additionally, the connecting member (BR) may include an upper wiring (BE) that is in contact with a third electrode portion (Fig. 5, 123) at the upper portion. The upper wiring (BE) may be electrically connected to the third electrode portion. In addition, the upper wiring (BE) may be electrically connected to the first semiconductor element and the second semiconductor element at the upper portion through the third electrode portion, thereby functioning as a bridge.

[0131] In addition, the circuit board may include a conductive member (SB) for connection between the first and second semiconductor elements and the electrode portions disposed on the upper portion of the circuit board (100), particularly on the upper build-up layer, which is the upper build-up layer. In addition, the circuit board may further include a conductive member (SB) disposed between a connection member (BR) other than the build-up layer and the first and second semiconductor elements. In addition, the connection member (BR) may electrically connect between at least two semiconductor elements. However, the following description will be given as performing an electrical connection between two semiconductor elements.

[0132] Additionally, an underfill (UF) may be positioned between the circuit board (100) and the first and second semiconductor elements (DI1, DI2). The underfill (UF) may cover the conductive member (SB).

[0133] And when the connecting member (BR) does not include a via electrode, the via electrode of the core layer of the circuit board (100) may not vertically overlap with the connecting member (BR). However, when the connecting member (BR) includes a via electrode, it may vertically overlap with the via electrode of the core layer of the circuit board (100) and be electrically connected. The via electrode of the build-up layer may vertically overlap with the connecting member (BR). Furthermore, the connecting member (BR) and the via electrode of the build-up layer may be electrically connected. In addition, the connecting member (BR) may at least partially vertically overlap with the first and second semiconductor elements (DI1, DI2).

[0134] In addition, as described above, the connecting member (BR) may be an organic or inorganic connecting member. For example, the connecting member (BR) may be an inorganic connecting member, and when the connecting member (BR) includes a via electrode, it may be advantageous in transmitting power from the circuit board (100) to the first and second semiconductor elements (DI1, DI2).

[0135] FIG. 4 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, FIG. 5 is an enlarged view of a portion K1 in FIG. 4, FIG. 6 is an enlarged view of a portion K2 in FIG. 4, FIG. 7 is an enlarged view of a portion of a certain area in FIG. 6, FIG. 8 is an enlarged view of a portion K3 in FIG. 4, and FIG. 9 is a modified example of FIG. 6.

[0136] Referring to FIG. 4, the circuit board (100) according to the first embodiment may include an insulating layer (110), an electrode portion (120), and a connecting member (BR).

[0137] In an embodiment, the insulating layer (110) may be provided in a structure in which multiple insulating layers are laminated. The electrode portion (120) may be disposed by being embedded in each insulating layer of the multiple insulating layers (110), thereby performing the function of transmitting signals and / or power from a main board (not shown) to a semiconductor element.

[0138] Furthermore, when the circuit board includes a core layer, it may include a build-up insulating portion laminated on the core layer. Specifically, as illustrated, the circuit board (100) may include a core layer (111), build-up insulating portions (112, 113), a core electrode portion (121), and build-up electrode portions (122, 123). Furthermore, the circuit board (100) may further include a protective layer (SR) and a bonding portion (BP). In addition, in the following embodiments of the present invention, the build-up insulating portions (112, 113) may include a plurality of insulating layers and may be provided in a structure in which a plurality of insulating layers are laminated. The build-up electrode portions (122, 123) may be disposed by being embedded in each layer (e.g., insulating layer) of the build-up insulating portions (112, 113), thereby performing a function of transmitting signals and / or power from a main board (not illustrated) to a semiconductor element.

[0139] And when the circuit board includes a core layer, it may include a core layer disposed within an insulating layer (110). Accordingly, the insulating layer (110) of the circuit board may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). The upper build-up layer (112) may be located above the core layer (111). And the lower build-up layer (113) may be located below the core layer (111).

[0140] And the electrode section (120) can be composed of a via electrode and a wiring section as described later.

[0141] In addition, as an embodiment, the insulating layer (110) may be formed of a core layer (111) which is a core layer, and a build-up insulating portion (112, 113) which is formed of at least one insulating layer disposed above and below the core layer (111). Accordingly, the build-up insulating portion (112, 113) laminated on the core layer may include a plurality of vertically laminated insulating layers. The build-up insulating portion may include an upper build-up layer (112) and a lower build-up layer (113). As illustrated, the upper build-up layer (112) may be disposed above the core layer (111), and the lower build-up layer (113) may be disposed below the core layer (111). The upper build-up layer and / or the lower build-up layer may each be formed by laminating a plurality of insulating layers. In addition, the build-up layer (or build-up insulating portion) may be referred to as a build-up structure or a build-up insulating portion, etc. The following description will be made based on this.

[0142] As an example, the insulating layer (110) may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). In addition, a protective layer (SR) may be further disposed on the outer side of the insulating layer (110). This will be described later.

[0143] And the upper build-up layer (112) may be an 'upper build-up structure'. The lower build-up layer (113) may be a 'lower build-up structure'. In the present embodiment, the core layer (111) may be arranged at the center in the vertical direction of the insulating layer (110). When the build-up layers are laminated on both sides of the core layer (111), the core layer (111) may be located at the center of the insulating layer (110). That is, the upper build-up layer (112) may be arranged on the core layer (111), and the lower build-up layer (113) may be located below the core layer (111).

[0144] And the insulating layer (110) of the circuit board (100) may be rigid or flexible. For example, the insulating layer (110) of the circuit board (100) may include glass or plastic. For example, the insulating layer (110) of the circuit board or each insulating layer constituting the insulating layer (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer (110) of the circuit board may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer (110) of the circuit board may include sapphire. For example, the insulating layer (110) of the circuit board may include an optically isotropic film. For example, the insulating layer (110) of the circuit board may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer (110) of the circuit board may be formed of a material including a filler and an insulating resin. For example, the insulating layer (110) of the circuit board may have a structure in which a filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

[0145] The insulating layer (110) may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure will be described in more detail as follows.

[0146] In one embodiment, the insulating layer (110) may include a core layer (111) including a reinforcing member. Here, the core layer (111) may include the reinforcing member and have a thickness in a vertical direction (Y-axis direction or lamination direction) of tens to hundreds of micrometers. In addition, the upper build-up layer (112) and the lower build-up layer (113) may be disposed on the upper and lower sides of the core layer (111), respectively, and may include a plurality of layers that do not include the reinforcing member. The reinforcing member may also be referred to as a reinforcing fiber or glass fiber embedded in the core layer. The reinforcing member may refer to a glass fiber material extending along the horizontal direction (X-axis direction) of the insulating layer, and may have a different meaning from a filler that is spaced apart from each other. For example, the insulating layer (110) may be composed of a resin, a filler, and a reinforcing member (e.g., glass fiber), or may be composed of a resin and a filler.

[0147] The core layer (111) may be made of various insulating materials. For example, the core layer (111) may be a part of a copper clad laminate (CCL). Alternatively, the core layer may correspond to the copper clad laminate. In addition, the core layer (111) may be made of multiple layers, and the multiple layers may be made of the same or different materials. Furthermore, the core layer (111) may include a via electrode penetrating the upper and lower surfaces of the core layer (111).

[0148] And the upper build-up layer (112) or the lower build-up layer (113) can be provided with any insulating resin such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin can be used. The above-mentioned arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material or reinforcing member provided with glass fiber or aramid fiber. For example, when manufacturing an insulating layer (110), ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. can be used. For example, when the circuit board (100) is coreless, the insulating layer (110) can be provided by laminating ABF without a core layer.

[0149] In addition, the wiring or electrode portion (120) according to the embodiment is arranged for electrical connection between a main board, etc. and a chip (or semiconductor element, die), and the electrode portion (120) includes a wiring portion (circuit pattern or circuit pattern layer, pad, pattern portion) and a via portion (or via electrode).

[0150] For example, the wiring portion of the electrode portion (120) may include a pattern and a pad on the upper surface of the insulating layer. Hereinafter, the wiring portion is described interchangeably with the terms 'circuit pattern' and 'pattern portion'. In addition, the electrode portion (120) may include a via portion or a via electrode penetrating the insulating layer. Accordingly, in the embodiment, the electrode portion (120) is described below as including a wiring portion (circuit pattern) and a via electrode in each insulating layer. In addition, the wiring portion in the electrode portion (120) may be designed in various forms for transmitting signals and / or power to and from the semiconductor element, and is arranged in each insulating layer of the laminated build-up insulating portions (112, 113).

[0151] In the electrode section (120), a via electrode (or via section) is arranged to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns arranged on each insulating layer of the build-up insulating section (112, 113). The via electrode can connect a plurality of circuit patterns (wiring sections) to each other. The via electrode may also be formed in multiple pieces like the wiring section. That is, the insulating layer may include a via hole for arranging the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and may be freely designed.

[0152] In the electrode portion (120), a wiring portion (circuit pattern) may be arranged on each insulating layer. And the circuit pattern may be electrically connected to the circuit pattern. In addition, the wiring portion (circuit pattern) may be connected to each via electrode. And the circuit patterns arranged on the upper and lower surfaces of the insulating layer in the build-up insulating portion (112, 113) may be electrically connected to a semiconductor element and / or a main board or substrate, etc. For example, the electrode portion (120) may be located on each layer (insulating layer) of the core layer (111), the upper build-up layer (112), and the lower build-up layer (113).

[0153] In an embodiment, the electrode portion (120) may include a core electrode portion (121), an upper electrode portion (122), and a lower electrode portion (123). The upper electrode portion (122) and the lower electrode portion (123) may be build-up layer electrode portions. In addition, the upper electrode portion (122) is disposed in each insulating layer in the upper build-up layer (112) and may be an 'upper build-up layer electrode portion'. In addition, the lower electrode portion (123) is disposed in each insulating layer in the lower build-up layer (113) and may be a 'lower build-up wiring portion electrode'.

[0154] The core electrode portion (121) may include a core wiring portion (121a) arranged on the upper and lower surfaces of the core layer (111) and a core via electrode (121b) penetrating the core layer (111).

[0155] The upper electrode portion (122) may include an upper wiring portion (122a), which is a wiring portion arranged on the upper and lower surfaces of each insulating layer of the upper build-up layer (112), and an upper via electrode (122b), which is a via electrode. The upper via electrode (122b) may penetrate each insulating layer of the upper build-up layer (112).

[0156] Furthermore, the lower electrode portion (123) may include a lower wiring portion (123a), which is a wiring portion arranged on the upper and lower surfaces of the lower build-up layer (113), and a lower via electrode (123b), which is a via electrode. In addition, the lower via electrode (123b) may penetrate each insulating layer of the lower build-up layer (113).

[0157] And in the embodiment, the wiring portion of the upper electrode portion (and / or the lower electrode portion) may include a wiring portion (first wiring portion) having a fine pitch and a wiring portion (second wiring portion) having a pitch larger than the first wiring portion.

[0158] The second wiring portion may refer to a wiring having the same width and spacing as a circuit pattern used in a conventional circuit board, and the first wiring portion may refer to a fine wiring having a width and spacing narrower than the width and spacing of a pattern used in a conventional circuit board for interconnection between semiconductor devices, impedance matching, or formation of an inductor. For example, the line width of the first wiring portion may be several micrometers (㎛) or less, or the pitch may be several tens of ㎛ or less. For example, the width of the first wiring portion may be 30 ㎛ or less. For example, the pitch of the first wiring portion may be 55 ㎛ or less. A detailed description thereof will be provided later.

[0159] Additionally, the circuit board (100) according to the first embodiment may further include a protective layer (SR) and a bonding portion (BP).

[0160] Specifically, the protective layer (SR) can have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when bonding between the semiconductor element and / or the main board and the circuit board, the protective layer (SR) can be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals can be arranged at a high density. When the plurality of terminals and the pads of the circuit board are bonded, solder can be used, for example. When solder is used, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist that does not have good wettability with the solder can be arranged to solve this short circuit problem. In addition, the protective layer (SR) can be formed of a material having insulating properties for electrical connection. The protective layer (SR) can include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the protective layer (SR) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. The protective layer (SR) may have at least one opening for connection between a terminal of a semiconductor device and a pad of a circuit board. For example, in an embodiment, the protective layer (SR) may be formed of a filler and a resin, which are reinforcing members.

[0161] A protective layer (SR) may be disposed on an insulating layer (110). The protective layer (SR) may include a plurality of fillers. Specifically, the protective layer (SR) may include a first protective layer (SR1) disposed on an upper build-up layer (112) and a second protective layer (SR2) disposed under a lower build-up layer (113). The first protective layer (SR1) and the second protective layer (SR2) may be disposed spaced apart from each other along a stacking direction and may have different thicknesses in consideration of warpage of the circuit board. Hereinafter, the protective layer will be described based on the first protective layer (SR1).

[0162] The bonding portion (BP) may be disposed on the protective layer (SR). For example, the bonding portion (BP) may be disposed on the upper surface of the protective layer (SR). The bonding portion (BP) may be located outside the build-up electrode portions (122, 123). For example, in the upper build-up layer (112), the bonding portion (BP) may be located on the upper surface of the build-up electrode portions (122, 123). In addition, the bonding portion (BP) may include a protrusion (PP) disposed on the upper surface of the protective layer (SR) and a via portion (TP) penetrating the protective layer (SR). In an embodiment, the via portion (TP) and the protrusion (PP) may each include a plurality of protrusions or convex portions protruding toward the adjacent protective layer (SR). For example, on the first protective layer (SR1), the via portion (TP) and the protrusion portion (PP) may include a plurality of protrusions (or convex portions) protruding toward the first protective layer (SR1).

[0163] Furthermore, a metal layer may be additionally disposed on the bonding portion (BP) and electrically connected. Accordingly, the durability and reliability of the bonding portion (BP) may be further improved. For example, the metal layer may be formed of at least one metal layer. The metal layer may be formed of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or a combination thereof. Accordingly, the bonding strength between the metal layer and the bonding portion (BP) is improved, the corrosion resistance and durability of the bonding portion (BP) are improved, and the loss of electrical signals may also be minimized. The metal layer may be formed on the bonding portion (BP) by deposition, electroplating, or the like of various metals.

[0164] In addition, a semiconductor element may be arranged on the upper build-up layer (112). The semiconductor element may be electrically connected to the first wiring portion, which is the aforementioned micro-pattern. The circuit board may be arranged to have a high wiring density for connecting the semiconductor element and signals. In addition, the first wiring portion, which is the micro-pattern, may provide a function of a line for signal connection between the semiconductor elements, or may perform signal connection (e.g., provision to the lower substrate) for each semiconductor element. Accordingly, it may be provided to prevent the semiconductor element from becoming unnecessarily large, thereby improving the yield of the semiconductor element.

[0165] In addition, circuit boards can be divided into package substrates and interposers according to their function. The package substrate functions to mount semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of laminated insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of circuit boards with a high number of laminated layers, the yield of the circuit board can be improved by separating them into an interposer and a package substrate. In addition, as the terminal density of semiconductor devices increases, it may be difficult to implement pads on the package substrate with an area corresponding to the terminals of the semiconductor devices. Therefore, the interposer can act as a buffer between the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices.

[0166] The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0167] In addition, in the embodiment, the core layer (111) may include a through hole (CV). That is, the circuit board (100) may include a core layer (111) including a through hole (CV). In the embodiment, the through hole (CV) may be expressed in various ways, such as a 'groove', a 'recess', a hole, a 'via', etc. Furthermore, the through hole (CV) may have various shapes, such as a plane, a circle, a square, etc. Furthermore, the inner wall of the through hole (CV) or the inner side of the core layer (111) may have a structure in which the width or diameter increases from the center or the central portion toward the upper surface of the core layer (111), and the width or diameter increases toward the lower surface of the core layer (111). Alternatively, the inner wall of the through hole (CV) or the inner side of the core layer (111) may only have a structure in which the width or diameter increases from the center or central portion toward the upper surface of the core layer (111), or the width or diameter increases toward the lower surface of the core layer (111).

[0168] The through-hole (CV) may have various shapes depending on the shape of the element (e.g., connecting member) mounted inside. For example, the shape of the connecting member may generally be rectangular with respect to the plane perpendicular to the stacking direction. Correspondingly, the through-hole (CV) may also have a rectangular shape with respect to the plane perpendicular to the stacking direction. However, for easy mounting of the connecting member (BR), it may have various shapes.

[0169] Additionally, the circuit board (100) may include a connecting member (BR) and a bonding member (BM).

[0170] The connecting member (BR) can be positioned within the through hole (CV). That is, a mounting space for the connecting member (BR) and the like can be easily secured in the upper build-up layer (112) through the through hole (CV). In addition, a lower electrode portion (123) having a smaller line width than the upper electrode portion (122) outside the through hole (CV) can be easily placed above the through hole (CV). Accordingly, the circuit board according to the first embodiment can provide easy connection between semiconductor elements and an improved input / output (I / O) count.

[0171] According to an embodiment, the connecting member (BR) may be embedded in the through hole (CV) of the core layer (111). That is, according to an embodiment, the core layer (111) may be provided to prevent warpage while the circuit board (100) is made thinner, and at this time, the connecting member (BR) may be embedded in the core layer (111). In addition, as described above, since the connecting member (BR) is arranged in the core layer (111), the reliability of the circuit board is maintained by mounting the connecting member, and mounting of various connecting members (BR) can be performed.

[0172] Accordingly, when the connecting member (BR) is embedded in the upper build-up layer (112), a dummy electrode can be placed on the upper surface of the upper build-up layer. Accordingly, the connecting member (BR) can be mounted within a limited height within the upper build-up layer (112). Furthermore, when the length (thickness) of the connecting member (BR) increases in the stacking direction, problems such as peeling or cracking occurring at the boundary between the plurality of insulating layers may exist as a through hole is formed in the upper build-up layer (112), which is a plurality of insulating layers. Therefore, by mounting the connecting member (BR) in the core layer (111) as in the embodiment, the connecting member (BR) can be easily mounted regardless of whether the size of the connecting member (BR) is large or small, and since a via penetrating the boundary between the plurality of insulating layers for mounting the connecting member is not formed, the reliability of the circuit board can be improved.

[0173] Since the circuit board (100) according to the embodiment can be used as an interposer, thinning is required, so that a connecting member (BR) can be embedded in the core layer (111).

[0174] In addition, the upper build-up layer (112) may be disposed on the core layer (111), and a portion thereof may be disposed within the through hole (CV) of the core layer (111). Accordingly, a portion of the lower surface of the upper build-up layer (112) may be in contact with the upper surface of the lower build-up layer (113), and may form the same surface. This may be implemented within the through hole (CV).

[0175] The circuit board (100) may further include a bonding member (BM) disposed between the stopper portion (ST) and the connecting member (BR). The bonding member (BM) may be in contact with the stopper portion (ST) and the connecting member (BR). The bonding member (BM) may be disposed on the stopper portion (ST). In addition, the bonding member (BM) may be disposed within the through hole (CV). The bonding member (BM) may be disposed at a stepped portion of the through hole (CV). Accordingly, the bonding member (BM) may overlap the through hole (CV) in a horizontal direction (X-axis direction). In addition, the bonding member (BM) may be positioned on the lower surface (BS) of the core layer (111).

[0176] Furthermore, the joining member (BM) may overlap with the stopper member (ST) and the connecting member (BR) in the vertical direction or the stacking direction (Y-axis direction). A portion of the stopper member (ST) may not overlap with the joining member (BM) in the stacking direction (Y-axis direction) but may be misaligned.

[0177] By means of this joint member (BM), the position of the connecting member (BR) on the stopper portion (ST) can be adjusted more precisely. That is, the alignment error of the connecting member (BR) is reduced, and thus the deterioration of electrical reliability and structural reliability due to the alignment error can be prevented.

[0178] Additionally, the circuit board (100) may further include a stopper portion (ST).

[0179] The stopper part (ST) may be placed on the lower surface of the core layer (111). However, a connecting member may be mounted in the through hole described later through various members (e.g., a film) without the stopper part (ST). In addition, the stopper part (ST) may be a dummy electrode. Hereinafter, the stopper part (ST) is described interchangeably with the stopper part (ST).

[0180] Referring further to FIGS. 5 and 47, in an embodiment, the core layer (111) may include a core material (CO), a first resin material (RL1), and a second resin material (RL2). In an embodiment, the first resin material (RL1) may be positioned above the core material (CO). And the second resin material (RL2) may be positioned below the core material (CO). For example, the core material (CO) may be a plurality of fibers. In this case, the first resin material (RL1) may refer to an upper region of the fibers at the uppermost part of the core material (CO). In addition, the second resin material (RL2) may refer to a lower region of the fibers at the lowest part of the core material (CO). The following description will be based on this. However, the first resin material (RL1) may refer to a fiber located in the center of the core material (CO) or an upper region based on the center of the core material, and the second resin material (RL2) may refer to a fiber located in the center of the core material (CO) or a lower region based on the center of the core material. In addition, the first resin material (RL1) and the second resin material (RL2) are described based on one horizontal direction.

[0181] The core material (CO) is a region forming the center of the core layer (111) and can determine mechanical strength and electrical properties. For example, the core material (CO) of the core layer (111) can include epoxy, glass fiber, metal, ceramic, etc.

[0182] The first resin material (RL1) and the second resin material (RL2) may be positioned on the core material (CO). The first resin material (RL1) and the second resin material (RL2) are made of resin and may include, for example, epoxy, polyimide, Teflon, etc. The first resin material (RL1) and the second resin material (RL2) may determine the flexibility, adhesion, insulation, etc. of the core layer (111).

[0183] In an embodiment, the core layer (111) may have an asymmetrical structure with respect to a virtual line (VL) which is a bisector in the stacking direction (Y-axis direction).

[0184] For example, the core material (CO) of the core layer (111) may be positioned asymmetrically with respect to the virtual line (VL). For example, with respect to the virtual line (VL), the distance between the uppermost part of the virtual line (VL) and the core material (CO) may be different from the distance between the lowermost part of the virtual line (VL) and the core material (CO). For example, with respect to the virtual line (VL), the distance between the uppermost part of the virtual line (VL) and the core material (CO) may be greater than the distance between the lowermost part of the virtual line (VL) and the core material (CO). That is, the core material (CO) may be positioned adjacent to one side of the core layer (111). For example, the core material (CO) may be positioned adjacent to the upper side compared to the lower side of the core layer (111). Accordingly, in the core layer (111), a plurality of core materials (CO) may be positioned on the upper side with respect to the virtual line (VL).

[0185] In addition, the first resin material (RL1) and the second resin material (RL2) may be positioned asymmetrically with respect to the core material or the virtual line (VL). In an embodiment, the thickness (T1) of the first resin material (RL1) may be different from the thickness (T2) of the second resin material (RL2). For example, the thickness (T1) of the first resin material (RL1) may be smaller than the thickness (T2) of the second resin material (RL2). In addition, the shortest distance (T11) from the core material (CO) to the lower surface of the upper build-up layer (112) may be smaller than the shortest distance (T22) from the core material (CO) to the upper surface of the lower build-up layer (113).

[0186] In this way, when the core material (CO) within the core layer (111) has an asymmetrical structure in the lamination direction, a difference in the thermal expansion coefficients between the upper and lower portions of the core layer (111) may occur. For example, a difference in the thermal expansion coefficients between the upper and lower portions of the core layer (111) may occur based on the virtual line (VL). In addition, since the core material (CO) is positioned or concentrated at the upper portion of the core layer (111), stress may be concentrated at the lower portion of the core layer (111). For example, thermal stress and mechanical stress may be concentrated at the lower portion of the core layer (111). At this time, a through hole (CV) and a connecting member (BR), etc. may be disposed on the upper portion of the core layer (111). In addition, a semiconductor element, etc. may be further disposed on the upper portion of the core layer (111). Accordingly, the thickness of the second resin material (RL2) may be formed to be greater than the thickness of the first resin material (RL1), so that stress concentration due to various elements, fine patterns, etc. at the upper portion of the core layer (111) may be compensated for. In other words, the stress balance of the core layer (111) can be maintained by adjusting the thickness between the first resin material and the second resin material, thereby minimizing deformation of the circuit board.

[0187] In addition, since the core material (CO) is arranged on the upper side of the core layer (111), heat generated in the circuit board can be easily dissipated. In particular, the heat for the connecting member (BR) mounted in the through hole (CV) of the core layer (111) and the semiconductor element on the upper side can be brought closer to the core material (CO) of the core layer (111). In other words, the distance between the heat source and the core material (CO) can be reduced. Accordingly, the heat dissipation path through the first resin material (RL1) on the upper side of the core material (CO) within the core layer (111) is reduced, so that heat can be easily dissipated upward, and heat dissipation of the circuit board can be easily achieved. In particular, when the core material (CO) includes a high thermal conductivity material, the heat dissipation efficiency of the circuit board can be further improved.

[0188] In addition, the thickness of the core material (CO) may be smaller than the total thickness of the first resin material (RL1) and the second resin material (RL2). And the thickness of the core material (CO) may be different from the thickness of the first resin material (RL1) or the second resin material (RL2). For example, the thickness of the core material (CO) may be larger than the thickness of the first resin material (RL1). In addition, the thickness of the core material (CO) may be larger or smaller than the thickness of the second resin material (RL2). By this configuration, the mechanical strength of the core layer can be improved, and the structural stability and electrical properties can also be improved.

[0189] Additionally, the core layer (111) may have a step portion. The step portion may be located on the inside. In particular, the step portion may be located on the inner wall of the through hole (CV).

[0190] Accordingly, as an example, the through hole (CV) may include a first region (AR1) and a second region (AR2). The second region (AR2) may be located above the first region (AR1). In addition, the connecting member (BR) may be more easily mounted in the through hole due to the step portion described above on the inner wall of the through hole (CV). That is, the step portion may be located between the first region (AR1) and the second region (AR2).

[0191] In response to the step formed on the inner wall of the through hole (CV), the core layer (111) may include an upper region (UA) and a lower region (BA). The upper region (UA) may be located on the lower region (BA).

[0192] The upper region (UA) may correspond to the second region (AR2) of the through hole (CV). The upper region (UA) may overlap with the second region (AR2) in the horizontal direction (X-axis direction). The lower region (BA) may correspond to the first region (AR1) of the through hole (CV). The lower region (BA) may overlap with the first region (AR1) in the horizontal direction (X-axis direction).

[0193] Additionally, the core material (CO) and the first resin material (RL1) may be positioned in the upper region (UA). And the second resin material (RL2) may be positioned in the lower region (BA).

[0194] Accordingly, the thickness (T3) of the lower region (BA) may be smaller than the thickness (T4) of the upper region (UA). By this configuration, the thickness of the first region (AR1) may be smaller than the thickness of the second region (AR2).

[0195] And a connecting member (BR) may be positioned in the second region (AR2). The connecting member (BR) may be positioned on the first region (AR1). Accordingly, the connecting member (BR) may overlap a part of the first region (AR1) in the vertical direction (Y-axis direction). In addition, the connecting member (BR) may not overlap with the first region (AR1) in the horizontal direction (X-axis direction) but may be misaligned. And the connecting member (BR) may overlap with the second region (AR2) in the horizontal direction (X-axis direction). In addition, the connecting member (BR) may not overlap with the second region (AR2) in the vertical direction (Y-axis direction) but may be misaligned.

[0196] In this way, a connecting member (BR) can be mounted within the second region (AR2). Accordingly, at least a portion of the second region (AR2) can overlap the connecting member (BR) in the horizontal direction (X-axis direction).

[0197] In addition, the first resin material (RL1) and the core material (CO) may be positioned in the upper region (UA) and may overlap with the second region (AR2) in the horizontal direction (X-axis direction). And the second resin material (RL2) may be positioned in the lower region (BA) and may overlap with the first region (AR1) in the horizontal direction (X-axis direction). Furthermore, a part of the second resin material (RL2) may be positioned in the upper region (UA). A part of the second resin material (RL2) may overlap with the second region (AR2) in the horizontal direction (X-axis direction).

[0198] By this configuration, since the connecting member (BR) is positioned in the second region (AR2) and the core material (CO) overlaps the connecting member (BR) in the horizontal direction (X-axis direction), the bending phenomenon of the circuit board can be easily suppressed even when the connecting member (BR) is mounted in the through hole (CV).

[0199] In addition, in the case of the second resin material (RL2), the thickness (T2a) in the region overlapping the second region (AR2) in the horizontal direction (X-axis direction) may be different from the thickness (T2b) in the region overlapping the first region (AR1) in the horizontal direction (X-axis direction). For example, in the second resin material (RL2), the thickness (T2a) in the region overlapping the second region (AR2) in the horizontal direction (X-axis direction) may be smaller than the thickness (T2b) in the region overlapping the first region (AR1) in the horizontal direction (X-axis direction). By this configuration, the position of the core material in the core layer (111) can be formed corresponding to the connecting member, while suppressing the bending phenomenon, and the mounting of the connecting member can be implemented more accurately through the lower region (BA).

[0200] Also, for example, in a region where the second resin material (RL2) overlaps the second region (AR2) in the horizontal direction (X-axis direction), the thickness (T2a) may be smaller than the thickness of the core material (CO). Furthermore, in a region where the second resin material (RL2) overlaps the second region (AR2) in the horizontal direction (X-axis direction), the thickness (T2a) may correspond to the thickness (T1) of the first resin material (RL1). In addition, in a region where the second resin material (RL2) overlaps the second region (AR2) in the horizontal direction (X-axis direction), the thickness (T2a) may be different from the thickness (T1) of the first resin material (RL1). For example, when multiple semiconductor devices are arranged on the upper portion of a circuit board, in a region where the second resin material (RL2) overlaps the second region (AR2) in the horizontal direction (X-axis direction), the thickness (T2a) may be larger than the thickness (T1) of the first resin material (RL1). This compensates for the stress on the various elements placed on top, thereby balancing the overall stress within the circuit board.

[0201] Referring further to Fig. 6, the width (W2) in the horizontal direction (X-axis direction) of the first region (AR1) may be different from the width (W1) in the horizontal direction (X-axis direction) of the second region (AR2). The width (W2) in the horizontal direction (X-axis direction) of the first region (AR1) may be smaller than the width (W1) in the horizontal direction (X-axis direction) of the second region (AR2). By this configuration, a step portion for mounting the connecting member (BR) may be formed.

[0202] Additionally, the length (W3) of the connecting member (BR) in the horizontal direction (X-axis direction) may be different from the length of the first region (AR1) or the second region (AR2) in the horizontal direction (X-axis direction). For example, the length (W3) of the connecting member (BR) in the horizontal direction (X-axis direction) may be greater than the length (W2) of the first region (AR1) in the horizontal direction (X-axis direction). As a result, the connecting member (BR) may be settled on the lower region (BA) within the upper region (UA).

[0203] Additionally, the length (W3) in the horizontal direction (X-axis direction) of the connecting member (BR) may be smaller than the length (W1) in the horizontal direction (X-axis direction) of the second region (AR2). Accordingly, the connecting member (BR) can be easily accommodated within the second region (AR2).

[0204] Referring further to Fig. 7, the through hole (CV) may include an inner wall or an inner wall surface. In an embodiment, the inner wall surface of the through hole (CV) may include a first inner wall surface (IS1) and a second inner wall surface (IS2). The first inner wall surface (IS1) may be located on the inner side of the second inner wall surface (IS2). Alternatively, the first inner wall surface (IS1) may be located adjacent to the center of the through hole (CV) relative to the second inner wall surface (IS2).

[0205] Furthermore, the through hole (CV) may include a seating surface (SS) disposed between the first inner wall surface (IS1) and the second inner wall surface (IS2). The seating surface (SS) may be in contact with the first inner wall surface (IS1) and the second inner wall surface (IS2). The first inner wall surface (IS1) and the second inner wall surface (IS2) may be surfaces perpendicular to the seating surface (SS). At least a portion of the seating surface (SS) may face the lower surface of the connecting member (BR). Alternatively, at least a portion of the seating surface (SS) may be positioned below the lower surface of the connecting member (BR). For example, the seating surface (SS) may overlap the connecting member (BR) in a vertical direction (Y-axis direction). In addition, the first inner wall surface (IS1) may overlap the connecting member (BR) in a vertical direction (Y-axis direction). In contrast, the second inner wall surface (IS2) may be spaced apart from the connecting member (BR) in the horizontal direction (X-axis direction). And the second inner wall surface (IS2) may be misaligned with the connecting member (BR) in the vertical direction (Y-axis direction) and may not overlap.

[0206] In addition, the bonding member (BM) may be positioned between the seating surface (SS) and the connecting member (BR). The bonding member (BM) may be disposed within the through hole (CV). Accordingly, the bonding member (BM) may overlap the through hole (CV) in a horizontal direction (X-axis direction). In particular, the bonding member (BM) may overlap the second region (AR2) in a horizontal direction (X-axis direction). In addition, a part of the bonding member (BM) may overlap the first region (AR1) in a horizontal direction.

[0207] And the bonding member (BM) can be made of various materials having bonding strength. The bonding member (BM) can include a die attached film (DAF), etc.

[0208] In addition, the joining member (BM) can be positioned on the seating surface (SS). The joining member (BM) can be in contact with the seating surface (SS) and a portion of the first inner wall surface (IS1). And the joining member (BM) can be in contact with a lower surface and a portion of a side surface of the connecting member (BR). By this configuration, the position of the connecting member (BR) within the through hole (CV) can be easily adjusted. Accordingly, the connecting member (BR) can be positioned at a more precise position according to the design within the through hole (CV). For example, the position of the connecting member (BR) can be adjusted so that the center of the connecting member (BR) is at the center of the through hole (CV).

[0209] Furthermore, the joining member (BM) may include a first extension region (BUA), a middle region (BMA), and a second extension region (BBA). The first extension region (BUA) may be a region that is in contact with an outer surface of the connecting member (BR) and overlaps horizontally. And the middle region (BMA) may be a region located between the connecting member (BR) and the first region (or the seating surface). The middle region (BMA) may overlap with the upper region in the horizontal direction. And the second extension region (BBA) may overlap with the first region (AR1) in the horizontal direction (X-axis direction) and may be in contact with the first inner wall surface (IS1). Accordingly, the first extension region (BUA) may be located above the middle region (BMA). The second extension region (BBA) may be located below the middle region (BMA).

[0210] Furthermore, the first outer side (ES1) of the first extension area (BUA) may be adjacent to the outer side of the connecting member (BR). Furthermore, the first outer side (ES1) of the first extension area (BUA) may be positioned above the joining member (BM).

[0211] And the middle region (BMA) may include a second outer side (ES2) located on the outside and a third outer side (ES3) located on the inside. The second outer side (ES2) may be located on the outside of the first outer side (ES1). And the second outer side (ES2) may be located adjacent to the second inner wall surface (IS2). And the third outer side (ES3) may be located at the innermost side of the joining member (BM). The second outer side (ES2) and the third outer side (ES3) may be horizontally spaced apart from each other. The second outer side (ES3) and the third outer side (ES3) may horizontally overlap with the second region (AR2) and may be horizontally misaligned with and not overlap with the connecting member (BR). And the fourth outer side surface (ES4) is the outer side surface of the second extension area (BBA) and can overlap with the first area (AR1) in the horizontal direction (X-axis direction). The fourth outer side surface (ES4) can be located lower than the first outer side surface (ES1), the second outer side surface (ES2), and the third outer side surface (ES3). The second outer side surface (ES2) and the third outer side surface (ES3) can be located in the area between the first outer side surface (ES1) and the fourth outer side surface (ES4).

[0212] In addition, the joint member (BM) may be horizontally misaligned with and may not overlap the first resin material (RL1) in the X-axis direction. In addition, the joint member (BM) may or may not overlap the core material (CO) in the X-axis direction. For example, the joint member (BM) may at least partially overlap the core material (CO) in the X-axis direction. For example, the first extension area (BUA) of the joint member (BM) may overlap the core material (CO) in the horizontal direction. In addition, the joint member (BM) may overlap the second resin material (RL2) in the X-axis direction. The joint member (BM) may overlap the middle area (BMA) in the X-axis direction. And the joint member (BM) may also overlap the second extension area (BBA) in the X-axis direction.

[0213] Also, referring further to FIG. 8, in an embodiment, the upper build-up layer (112) and the lower build-up layer (113) may have different thicknesses. In an embodiment, the relationship in thickness between the upper build-up layer (112) and the lower build-up layer (113) may correspond to the relationship in thickness between the first resin material (RL1) and the second resin material (RL2).

[0214] For example, the thickness (Ta) of the upper build-up layer (112) may be smaller than the thickness (Tb) of the lower build-up layer (113). In other words, the upper build-up layer (112) in contact with the first resin material (RL1) may be formed to have a thicker thickness than the lower build-up layer (113) in contact with the second resin material (RL2).

[0215] By this configuration, stress balance can be easily maintained in the circuit board (100). In addition, heat can be easily dissipated upwards through the difference in thickness between the first resin material (RL1) and the second resin material (RL2), and stress concentrated downwards can be compensated for through the difference in thickness between the upper build-up layer and the lower build-up layer. Accordingly, in addition to stress balance, the difference in thermal expansion can be reduced, thereby inducing uniform thermal deformation. In particular, warpage of the circuit board in a high-temperature environment such as reflow can be more easily suppressed. Furthermore, by securing the thickness of the lower build-up layer (113), mechanical strength is improved, so that delamination or cracking between layers can be suppressed. Furthermore, durability against external impact can also be improved.

[0216] Additionally, the upper build-up layer (112) and the lower build-up layer (113) may have different filler contents. As described above, the filler includes silica, alumina, etc., and as the filler proportion increases, the mechanical strength of the build-up layer increases and mechanical stress may further increase. Furthermore, however, as the filler content increases, thermal stress may be alleviated.

[0217] Accordingly, for example, the filler ratio of the lower build-up layer (113) can be smaller than the filler ratio of the upper build-up layer (112). Accordingly, the reliability of the circuit board can be improved by increasing the mechanical stress of the lower portion while alleviating the thermal stress of the upper portion. Furthermore, shock absorption, thermal expansion, and stress concentration can be effectively compensated for by adjusting the filler content and thickness. For example, since an increase in the filler content causes a concentration of stress, stress relief can be implemented by increasing the filler content in the upper build-up layer (112) or increasing the thickness of the lower build-up layer (113).

[0218] Referring to FIG. 9, the circuit board may further include a device (DI3) positioned in the first region (AR1). The device (DI3) may include the semiconductor device described above.

[0219] The element (DI3) can be overlapped with the first region (AR1) and the lower region (BA) in the horizontal direction (X-axis direction). And the element (DI3) can be located below the connecting member (BR). The element (DI3) can be overlapped with the connecting member (BR) in the vertical direction (Y-axis direction). The element (DI3) can further include a connecting electrode (CE) connected to the connecting member (BR). The connecting electrode (CE) can be located between the element (DI3) and the connecting member (BR).

[0220] The connecting electrode (CE) can overlap with the bonding member (BM) or the second region (AR2) in the horizontal direction (X-axis direction). In addition, the connecting electrode (CE) can overlap with the element (DI3) and the connecting member (BR) in the vertical direction (Y-axis direction) to perform an electrical connection between the element (DI3) and the connecting member (BR). Accordingly, an electrical connection can be made between another semiconductor element on the connecting member (BR) and the element (DI3). At this time, the element (DI3) can have a thickness smaller than the thickness of the connecting member (BR) in order to be accommodated in the first region (AR1).

[0221] FIGS. 10 to 16 are drawings explaining a method for manufacturing a circuit board according to a first embodiment of the present invention.

[0222] It should be noted that one or more steps may be combined to simplify and / or clarify the steps for providing or manufacturing a circuit board. In some implementations, the order of the processes may be changed or modified. Furthermore, in some implementations, one or more of the manufacturing methods may be replaced or substituted without departing from the spirit of the present disclosure. Different implementations may manufacture the board differently.

[0223] Referring to FIG. 10, a core layer (111) can be provided. The core layer (111) may be an insulating layer having a predetermined thickness or greater, as described above. In addition, the core layer (111) may include glass or glass fiber having a resin. However, the core layer (111) may also include different materials.

[0224] Referring to FIG. 11, a via hole or a through hole (111h) can be formed in the core layer (111). The through hole can be formed through the upper and lower surfaces of the core layer (111). The through hole or via hole can be formed by a method such as a laser drilling method, a punching method, an etching method (mechanical drilling, chemical etching, or any suitable mechanism).

[0225] Referring to Fig. 12, a core electrode portion (121) can be formed on a core layer (111). The electrode portion can be formed by a patterning process based on mask formation (exposure, curing, etc.), a stripping process, and / or a plating process.

[0226] For example, a plating process may be performed on a via hole formed in a core layer (111) to form a through electrode. In addition, a core wiring portion may be formed on the upper and lower surfaces of the core layer (111). The core wiring portion may have a pattern using a mask or the like. Furthermore, the core wiring portion may be formed using an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are manufacturing processes for printed circuit boards. This may be equally applied to other wiring portions.

[0227] Furthermore, a stopper part (ST) may be arranged on the lower surface of the core layer (111). However, a connecting member may be mounted in the through hole described later through various members (e.g., a film) without the stopper part (ST). And the stopper part (ST) may be a dummy electrode. In addition, after the through hole (CV) is formed, a member (e.g., a film) may be arranged on the lower surface of the core layer (111). The above-described member (e.g., a film) may overlap with the through hole (CV) in a vertical direction. And a connecting member (BR) may be settled on the member (e.g., a film).

[0228] Referring to Fig. 13, a through hole (CV) can be formed in a region of the core layer (111) by various methods such as a laser method, a punching method, and an etching method. The through hole (CV) can be easily formed by a stopper part (ST). The through hole (CV) can penetrate the core layer (111). However, the present invention is not limited thereto, and the through hole (CV) can penetrate up to a part of the core layer (111). That is, the through hole (CV) can be a hole or a groove.

[0229] Furthermore, in forming the through hole (CV), the various methods described above may be performed multiple times. Accordingly, the through hole (CV) may have a step portion. For example, the through hole (CV) may include a first region (AR1) and a second region (AR20). The second region (AR2) may be located on the first region (AR1). The width (or area) of the first region (AR1) may be smaller than the width (or area) of the second region (AR2). Accordingly, as described above, a mounting surface or support region for mounting a connecting member may be formed. The lower region (BA) of the core layer (111) may be formed to vertically overlap at least a portion of the connecting member.

[0230] Referring to Fig. 14, a connecting member (BR) can be mounted in a through hole (CV) of a core layer (111). The connecting member (BR) can be mounted on a lower region of the core layer (111). In addition, when mounting the connecting member (BR), a bonding member (BM) can be positioned on a lower region (mounting surface) of the core layer (111). Accordingly, the connecting member (BR) can be firmly coupled to the core layer (111) through the bonding member (BM). Furthermore, since the connecting member (BR) comes into contact with the bonding member (BM) on the lower region, positional alignment can be easily implemented. In other words, misalignment due to thermal deformation, etc. can be prevented compared to when mounted on a bonding or build-up layer such as a film.

[0231] Referring to Fig. 15, an upper build-up layer (112) can be formed on top of the core layer (111) and within the through hole (CV). Additionally, a lower build-up layer (113) can be formed on the bottom of the core layer (111).

[0232] In addition, before forming the upper build-up layer (112), underfilling may be performed to fix the position of the connecting member (BR) in the through hole (CV). For example, a filling member (FI) may be further applied within the through hole (CV). Accordingly, the filling member (FI) may improve the bonding strength between the core layer (111) and the connecting member (BR). The filling member (FI) may refer to underfill, etc. As a result, the circuit board may be protected from impact, dropping, and vibration. In addition, deformation due to differences in thermal expansion between other components, such as the connecting member (BR) and the core layer (111), may be reduced. The filling member (FI) may include epoxy, etc.

[0233] However, as described above, the upper build-up layer (112) can be applied within the through hole (CV), and this is illustrated as a reference.

[0234] Referring to FIG. 16, a via hole or through hole may be formed in the upper build-up layer (112) and / or the lower build-up layer (113). The via hole may be formed by a laser drilling method, a punching method, an etching method (mechanical drilling, chemical etching, or any suitable mechanism), etc.

[0235] Additionally, an upper electrode portion (122) may be formed on the upper build-up layer (112). And a lower electrode portion (123) may be formed on the lower build-up layer (113). The upper electrode portion (122) and the lower electrode portion (123) may be formed by a patterning process based on mask formation (exposure, curing, etc.), a stripping process, and / or a plating process.

[0236] And the upper wiring part of the upper electrode part (122) may be formed on the upper surface of the upper build-up layer (112), and the lower wiring part of the lower electrode part (123) may be formed on the lower surface of the lower build-up layer (113). Each wiring part may have a pattern by a mask or the like. Furthermore, the wiring part may be formed by an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are manufacturing processes of a printed circuit board.

[0237] Thereafter, a first protective layer (SR1) may be formed on the upper build-up layer (112). A second protective layer (SR2) may be formed under the lower build-up layer (113). Furthermore, a via (TP) penetrating the protective layer (SR) may be formed.

[0238] Fig. 17 is a cross-sectional view of a circuit board according to the second embodiment, Fig. 18 is an enlarged view of part K4 in Fig. 18, and Fig. 19 is an enlarged view of part K5 in Fig. 18.

[0239] Referring to FIGS. 17 to 19, a circuit board (100A) according to the second embodiment may include an insulating layer (110), an electrode portion (120), and a connecting member (BR). Furthermore, the circuit board (100A) may further include a protective layer (SR) and a bonding portion (BP). As described above, the build-up electrode portions (122, 123) may be disposed embedded in each layer (e.g., an insulating layer) of the build-up insulating portions (112, 113), thereby functioning to transmit signals and / or power from a main board (not shown) to a semiconductor element. In addition, the connecting member (BR) may be positioned within a through hole (CV) formed in a core layer (111) of the insulating layer (110).

[0240] Additionally, the bonding member may be positioned between the connecting member (BR) and the lower region of the core layer (111). The foregoing may be equally applicable to the circuit board, except for the following description.

[0241] In this example, the core layer (111) may include a core material (CO), a first resin material (RL1), and a second resin material (RL2). In an embodiment, the first resin material (RL1) may be positioned above the core material (CO). And the second resin material (RL2) may be positioned below the core material (CO). And the core material (CO) may be composed of multiple fibers. In this case, the first resin material (RL1) may refer to the upper fiber region at the top of the core material (CO). In addition, the second resin material (RL2) may refer to the lower fiber region at the bottom of the core material (CO).

[0242] In the core layer (111), the core material (CO) may not be located at the center in the stacking direction (Y-axis direction). That is, since the core material (CO) is not located at the center in the core layer (111), the core layer (111) may have an asymmetrical structure with respect to the core material (CO).

[0243] Additionally, the first resin material (RL1) and the second resin material (RL2) can also be positioned asymmetrically with respect to the core material (CO).

[0244] And as described above, the core layer (111) may have a step portion. The step portion may be located on the inner side of the core layer (111). In particular, the step portion may be formed on the inner wall of the through hole (CV).

[0245] The through hole (CV) may include a first region (AR1) and a second region (AR2). The second region (AR2) may be positioned above the first region (AR1). Furthermore, the aforementioned step portion on the inner wall of the through hole (CV) allows the connecting member (BR) to be more easily mounted in the through hole.

[0246] In response to the step formed on the inner wall of the through hole (CV), the core layer (111) may include an upper region (UA1) and a lower region (BA1). The upper region (UA1) may be located on the lower region (BA1).

[0247] In this example, the thickness (T6) of the first resin material (RL1) in the vertical direction (Y-axis direction) and the thickness (T5) of the second resin material (RL2) in the vertical direction (Y-axis direction) may be different from each other. For example, the thickness (T6) of the first resin material (RL1) in the vertical direction (Y-axis direction) may be smaller than the thickness (T5) of the second resin material (RL2) in the vertical direction (Y-axis direction). Furthermore, the core material (CO) and the second resin material (RL2) may be positioned in the lower area (BA1). Accordingly, the core material (CO) and the second resin material (RL2) may overlap with the first area (AR1) in the horizontal direction (X-axis direction). In addition, the first resin material (RL1) may overlap with the second area (AR2) in the horizontal direction, and may partially overlap with the first area (AR1) in the horizontal direction.

[0248] Furthermore, the thickness (T7) of the lower region (BA1) in the core layer (111) may be different from the thickness (T8) of the upper region (UA1). The thickness (T7) of the lower region (BA1) in the core layer (111) may be greater than the thickness (T8) of the upper region (UA1).

[0249] In particular, a device (DI3) may be arranged in a first region (AR1), and a connecting member (BR) may be positioned in a second region (AR2). In addition, a thickness (T9) of the device (DI3) may be smaller than a thickness (T10) of the connecting member (BR). In this structure, the thickness of the region (first region) where the device (DI3) is arranged may be set to be larger than the thickness of the region (second region) where the connecting member (BR) is arranged. Accordingly, the reliability of the circuit board can be improved.

[0250] The element (DI3) may further include a connection electrode (CE) connected to the connection member (BR). The connection electrode (CE) may be located between the element (DI3) and the connection member (BR).

[0251] Additionally, the element (DI3) and the connecting member (BR) can be connected and joined to each other via the connecting electrode (CE). For positional alignment, the connecting member (BM) can be positioned on the core material (CO) or the lower region (BA1) and can be in contact with the connecting member (BR).

[0252] Additionally, in this example, the width (W2) in the horizontal direction (X-axis direction) of the first region (AR1) may be different from the width (W1) in the horizontal direction (X-axis direction) of the second region (AR2). The width (W2) in the horizontal direction (X-axis direction) of the first region (AR1) may be smaller than the width (W1) in the horizontal direction (X-axis direction) of the second region (AR2). By this configuration, a step portion for mounting the connecting member (BR) may be formed.

[0253] Additionally, the length (W3) of the connecting member (BR) in the horizontal direction (X-axis direction) may be different from the length of the first region (AR1) or the second region (AR2) in the horizontal direction (X-axis direction). For example, the length (W3) of the connecting member (BR) in the horizontal direction (X-axis direction) may be greater than the length (W2) of the first region (AR1) in the horizontal direction (X-axis direction). As a result, the connecting member (BR) may be settled on the lower region (BA) within the upper region (UA).

[0254] Additionally, the length (W3) in the horizontal direction (X-axis direction) of the connecting member (BR) may be smaller than the length (W1) in the horizontal direction (X-axis direction) of the second region (AR2). Accordingly, the connecting member (BR) can be easily accommodated within the second region (AR2).

[0255] In addition, the length (W4) of the element (DI3) in the horizontal direction (X-axis direction) may be greater than the width (W2) of the first region (AR1) in the horizontal direction (X-axis direction). And, the length (W4) of the element (DI3) in the horizontal direction (X-axis direction) may be less than the width (W1) of the second region (AR2) in the horizontal direction (X-axis direction). Furthermore, the length (W4) of the element (DI3) in the horizontal direction (X-axis direction) may be less than the width (W2) of the first region (AR1) in the horizontal direction (X-axis direction).

[0256] Additionally, in this example, the upper build-up layer (112) and the lower build-up layer (113) may have different thicknesses. In an embodiment, the relationship between the thicknesses of the upper build-up layer (112) and the lower build-up layer (113) may correspond to the relationship between the thicknesses of the first resin material (RL1) and the second resin material (RL2).

[0257] For example, the thickness (Ta') of the upper build-up layer (112) may be greater than the thickness (Tb') of the lower build-up layer (113). In other words, the upper build-up layer (112) in contact with the first resin material (RL1) may be formed to have a thinner thickness than the lower build-up layer (113) in contact with the second resin material (RL2). By this configuration, even if the thickness of the first resin material on the upper side is increased due to the thicker element (DI3) being placed at the lower side of the circuit board (100A), the difference in thickness between the upper build-up layer and the lower build-up layer can be compensated for. Accordingly, the balance in stress can be maintained, thereby improving the reliability of the circuit board.

[0258] Additionally, as described above, the upper build-up layer (112) and the lower build-up layer (113) may have different filler contents.

[0259] Thus, for example, the filler ratio of the lower build-up layer (113) can be greater than the filler ratio of the upper build-up layer (112). Accordingly, the reliability of the circuit board can be improved as the mechanical stress of the upper portion increases. Furthermore, by adjusting the filler content and thickness, shock absorption, thermal expansion, and stress concentration can be effectively compensated for.

[0260] FIG. 20 is a cross-sectional view of a circuit board according to a third embodiment of the present invention, FIG. 21 is an enlarged view of K6 in FIG. 20, FIG. 22 is an enlarged view of K7 in FIG. 20, FIG. 23 is a modified example of FIG. 22, FIG. 24 is another modified example of FIG. 22, FIG. 25 is another modified example of FIG. 22, and FIG. 26 is another modified example of FIG. 22.

[0261] Referring to FIG. 20, a circuit board (100B) according to the third embodiment may include an insulating layer (110), an electrode portion (120), and a bridge board (BR).

[0262] In an embodiment, the insulating layer (110) may be provided in a structure in which multiple insulating layers are laminated. The electrode portion (120) may be disposed by being embedded in each insulating layer of the multiple insulating layers (110), thereby performing the function of transmitting signals and / or power from a main board (not shown) to a semiconductor element.

[0263] Furthermore, when the circuit board includes a core layer, it may include a build-up insulating portion laminated on the core layer. Specifically, as illustrated, the circuit board (100B) may include a core layer (111), build-up insulating portions (112, 113), a core electrode portion (121), and build-up electrode portions (122, 123). Furthermore, the circuit board (100B) may further include a protective layer (SR) and a bonding portion (BP). In addition, in the following embodiments of the present invention, the build-up insulating portions (112, 113) may include a plurality of insulating layers and may be provided in a structure in which a plurality of insulating layers are laminated. The build-up electrode portions (122, 123) may be disposed by being embedded in each layer (e.g., insulating layer) of the build-up insulating portions (112, 113), thereby performing a function of transmitting signals and / or power from a main board (not illustrated) to semiconductor devices.

[0264] And when the circuit board includes a core layer, it may include a core layer disposed within an insulating layer (110). Accordingly, the insulating layer (110) of the circuit board may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). The upper build-up layer (112) may be located above the core layer (111). And the lower build-up layer (113) may be located below the core layer (111).

[0265] And the electrode section (120) can be composed of a via electrode and a wiring section as described later.

[0266] As an example, the insulation layer (110) may be formed of a core layer (111) which is a core layer, and a build-up insulation portion (112, 113) which is formed of at least one insulation layer disposed above and below the core layer (111). Accordingly, the build-up insulation portion (112, 113) laminated on the core layer may include a plurality of vertically laminated insulation layers. The build-up insulation portion may include an upper build-up layer (112) and a lower build-up layer (113). As illustrated, the upper build-up layer (112) may be disposed above the core layer (111), and the lower build-up layer (113) may be disposed below the core layer (111). The upper build-up layer and / or the lower build-up layer may each be formed by laminating a plurality of insulation layers. In addition, the build-up layer (or build-up insulation portion) may be referred to as a build-up structure or a build-up insulation portion, etc. The following description will be made based on this.

[0267] As an example, the insulating layer (110) may include a core layer (111), an upper build-up layer (112), and a lower build-up layer (113). In addition, a protective layer (SR) may be further disposed on the outer side of the insulating layer (110). This will be described later.

[0268] And the upper build-up layer (112) may be an 'upper build-up structure'. The lower build-up layer (113) may be a 'lower build-up structure'. In the present embodiment, the core layer (111) may be arranged at the center in the vertical direction of the insulating layer (110). When the build-up layers are laminated on both sides of the core layer (111), the core layer (111) may be located at the center of the insulating layer (110). That is, the upper build-up layer (112) may be arranged on the core layer (111), and the lower build-up layer (113) may be located below the core layer (111).

[0269] And the insulating layer (110) of the circuit board (100B) may be rigid or flexible. For example, the insulating layer (110) of the circuit board (100B) may include glass or plastic. For example, the insulating layer (110) of the circuit board or each insulating layer constituting the insulating layer (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer (110) of the circuit board may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer (110) of the circuit board may include sapphire. For example, the insulating layer (110) of the circuit board may include an optically isotropic film. For example, the insulating layer (110) of the circuit board may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer (110) of the circuit board may be formed of a material including a filler and an insulating resin. For example, the insulating layer (110) of the circuit board may have a structure in which a filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

[0270] The insulating layer (110) may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure will be described in more detail as follows.

[0271] In one embodiment, the insulating layer (110) may include a core layer (111) including a reinforcing member. Here, the core layer (111) may include the reinforcing member and have a thickness in a vertical direction (Y-axis direction or lamination direction) of tens to hundreds of micrometers. In addition, the upper build-up layer (112) and the lower build-up layer (113) may be disposed on the upper and lower sides of the core layer (111), respectively, and may include a plurality of layers that do not include the reinforcing member. The reinforcing member may also be referred to as a reinforcing fiber or glass fiber embedded in the core layer. The reinforcing member may refer to a glass fiber material extending along the horizontal direction (X-axis direction) of the insulating layer, and may have a different meaning from a filler that is spaced apart from each other. For example, the insulating layer (110) may be composed of a resin, a filler, and a reinforcing member (e.g., glass fiber), or may be composed of a resin and a filler.

[0272] The core layer (111) may be made of various insulating materials. For example, the core layer (111) may be a part of a copper clad laminate (CCL). Alternatively, the core layer may correspond to the copper clad laminate. In addition, the core layer (111) may be made of multiple layers, and the multiple layers may be made of the same or different materials. Furthermore, the core layer (111) may include a via electrode penetrating the upper and lower surfaces of the core layer (111).

[0273] And the upper build-up layer (112) or the lower build-up layer (113) can be provided with any insulating resin such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin can be used. The above-mentioned arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material or reinforcing member provided with glass fiber or aramid fiber. For example, when manufacturing an insulating layer (110), ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. can be used. For example, when the circuit board (100B) is coreless, the insulating layer (110) can be provided by laminating ABF without a core layer.

[0274] In addition, the wiring or electrode portion (120) according to the embodiment is arranged for electrical connection between a main board, etc. and a chip (or semiconductor element, die), and the electrode portion (120) includes a wiring portion (circuit pattern or circuit pattern layer, pad, pattern portion) and a via portion (or via electrode).

[0275] For example, the wiring portion of the electrode portion (120) may include a pattern and a pad on the upper surface of the insulating layer. Hereinafter, the wiring portion is described interchangeably with the terms 'circuit pattern' and 'pattern portion'. In addition, the electrode portion (120) may include a via portion or a via electrode penetrating the insulating layer. Accordingly, in the embodiment, the electrode portion (120) is described below as including a wiring portion (circuit pattern) and a via electrode in each insulating layer. In addition, the wiring portion in the electrode portion (120) may be designed in various forms for transmitting signals and / or power to and from the semiconductor element, and is arranged in each insulating layer of the laminated build-up insulating portions (112, 113).

[0276] In the electrode section (120), a via electrode (or via section) is arranged to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns arranged on each insulating layer of the build-up insulating section (112, 113). The via electrode can connect a plurality of circuit patterns (wiring sections) to each other. The via electrode may also be formed in multiple pieces like the wiring section. That is, the insulating layer may include a via hole for arranging the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and may be freely designed.

[0277] In the electrode portion (120), a wiring portion (circuit pattern) may be arranged on each insulating layer. And the circuit pattern may be electrically connected to the circuit pattern. In addition, the wiring portion (circuit pattern) may be connected to each via electrode. And the circuit patterns arranged on the upper and lower surfaces of the insulating layer in the build-up insulating portion (112, 113) may be electrically connected to a semiconductor element and / or a main board or substrate, etc. For example, the electrode portion (120) may be located on each layer (insulating layer) of the core layer (111), the upper build-up layer (112), and the lower build-up layer (113).

[0278] In an embodiment, the electrode portion (120) may include a core electrode portion (121), an upper electrode portion (122), and a lower electrode portion (123). The upper electrode portion (122) and the lower electrode portion (123) may be build-up layer electrode portions. In addition, the upper electrode portion (122) is disposed in each insulating layer in the upper build-up layer (112) and may be an 'upper build-up layer electrode portion'. In addition, the lower electrode portion (123) is disposed in each insulating layer in the lower build-up layer (113) and may be a 'lower build-up wiring portion electrode'.

[0279] The core electrode portion (121) may include a core wiring portion (121a) arranged on the upper and lower surfaces of the core layer (111) and a core via electrode (121b) penetrating the core layer (111).

[0280] The upper electrode portion (122) may include an upper wiring portion (122a), which is a wiring portion arranged on the upper and lower surfaces of each insulating layer of the upper build-up layer (112), and an upper via electrode (122b), which is a via electrode. The upper via electrode (122b) may penetrate each insulating layer of the upper build-up layer (112).

[0281] Furthermore, the lower electrode portion (123) may include a lower wiring portion (123a), which is a wiring portion arranged on the upper and lower surfaces of the lower build-up layer (113), and a lower via electrode (123b), which is a via electrode. In addition, the lower via electrode (123b) may penetrate each insulating layer of the lower build-up layer (113).

[0282] And in the embodiment, the wiring portion of the upper electrode portion (and / or the lower electrode portion) may include a wiring portion (first wiring portion) having a fine pitch and a wiring portion (second wiring portion) having a pitch larger than the first wiring portion.

[0283] The second wiring portion may refer to a wiring having the same width and spacing as a circuit pattern used in a conventional circuit board, and the first wiring portion may refer to a fine wiring having a width and spacing narrower than the width and spacing of a pattern used in a conventional circuit board for interconnection between semiconductor devices, impedance matching, or formation of an inductor. For example, the line width of the first wiring portion may be several micrometers (㎛) or less, or the pitch may be several tens of ㎛ or less. For example, the width of the first wiring portion may be 30 ㎛ or less. For example, the pitch of the first wiring portion may be 55 ㎛ or less. A detailed description thereof will be provided later.

[0284] Additionally, the circuit board (100B) according to the third embodiment may further include a protective layer (SR) and a bonding portion (BP).

[0285] Specifically, the protective layer (SR) can have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when bonding between the semiconductor element and / or the main board and the circuit board, the protective layer (SR) can be provided with a solder resist, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals can be arranged at a high density. When the plurality of terminals and the pads of the circuit board are bonded, solder can be used, for example. When solder is used, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist that does not have good wettability with the solder can be arranged to solve this short circuit problem. In addition, the protective layer (SR) can be formed of a material having insulating properties for electrical connection. The protective layer (SR) can include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the protective layer (SR) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. The protective layer (SR) may have at least one opening for connection between a terminal of a semiconductor device and a pad of a circuit board. For example, in an embodiment, the protective layer (SR) may be formed of a filler and a resin, which are reinforcing members.

[0286] A protective layer (SR) may be disposed on an insulating layer (110). The protective layer (SR) may include a plurality of fillers. Specifically, the protective layer (SR) may include a first protective layer (SR1) disposed on an upper build-up layer (112) and a second protective layer (SR2) disposed under a lower build-up layer (113). The first protective layer (SR1) and the second protective layer (SR2) may be disposed spaced apart from each other along a stacking direction and may have different thicknesses in consideration of warpage of the circuit board. Hereinafter, the protective layer will be described based on the first protective layer (SR1).

[0287] The bonding portion (BP) may be disposed on the protective layer (SR). For example, the bonding portion (BP) may be disposed on the upper surface of the protective layer (SR). The bonding portion (BP) may be located outside the build-up electrode portions (122, 123). For example, in the upper build-up layer (112), the bonding portion (BP) may be located on the upper surface of the build-up electrode portions (122, 123). In addition, the bonding portion (BP) may include a protrusion (PP) disposed on the upper surface of the protective layer (SR) and a via portion (TP) penetrating the protective layer (SR). In an embodiment, the via portion (TP) and the protrusion (PP) may each include a plurality of protrusions or convex portions protruding toward the adjacent protective layer (SR). For example, on the first protective layer (SR1), the via portion (TP) and the protrusion portion (PP) may include a plurality of protrusions (or convex portions) protruding toward the first protective layer (SR1).

[0288] Furthermore, a metal layer may be additionally disposed on the bonding portion (BP) and electrically connected. Accordingly, the durability and reliability of the bonding portion (BP) may be further improved. For example, the metal layer may be formed of at least one metal layer. The metal layer may be formed of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or a combination thereof. Accordingly, the bonding strength between the metal layer and the bonding portion (BP) is improved, the corrosion resistance and durability of the bonding portion (BP) are improved, and the loss of electrical signals may also be minimized. The metal layer may be formed on the bonding portion (BP) by deposition, electroplating, or the like of various metals.

[0289] In addition, a semiconductor element may be arranged on the upper build-up layer (112). The semiconductor element may be electrically connected to the first wiring portion, which is the aforementioned micro-pattern. The circuit board may be arranged to have a high wiring density for connecting the semiconductor element and signals. In addition, the first wiring portion, which is the micro-pattern, may provide a function of a line for signal connection between the semiconductor elements, or may perform signal connection (e.g., provision to the lower substrate) for each semiconductor element. Accordingly, it may be provided to prevent the semiconductor element from becoming unnecessarily large, thereby improving the yield of the semiconductor element.

[0290] In addition, circuit boards can be divided into package substrates and interposers according to their function. The package substrate functions to mount semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of laminated insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of circuit boards with a high number of laminated layers, the yield of the circuit board can be improved by separating them into an interposer and a package substrate. In addition, as the terminal density of semiconductor devices increases, it may be difficult to implement pads on the package substrate with an area corresponding to the terminals of the semiconductor devices. Therefore, the interposer can act as a buffer between the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices.

[0291] The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0292] In addition, in the embodiment, the core layer (111) may include a cavity (CV). That is, the circuit board (100B) may include a core layer (111) including a cavity (CV). In the embodiment, the cavity (CV) may be expressed in various ways, such as a 'groove', a 'recess', a hole, a 'via', etc. Furthermore, the cavity (CV) may have various shapes, such as a flat surface, a circle, a square shape, etc. Furthermore, the inner wall of the cavity (CV) or the inner side of the core layer (111) may have a structure in which the width or diameter increases from the center or the central portion toward the upper surface of the core layer (111), and the width or diameter increases toward the lower surface of the core layer (111). Alternatively, the inner wall of the cavity (CV) or the inner side of the core layer (111) may only have a structure in which the width or diameter increases from the center or central portion toward the upper surface of the core layer (111), or the width or diameter increases toward the lower surface of the core layer (111).

[0293] And the cavity (CV) can have various shapes depending on the shape of the element (e.g., bridge substrate) mounted inside. For example, the shape of the bridge substrate can generally be rectangular with respect to the plane perpendicular to the stacking direction. Correspondingly, the cavity (CV) can also have a rectangular shape with respect to the plane perpendicular to the stacking direction. However, for easy mounting of the bridge substrate (BR), it can have various shapes.

[0294] The bridge substrate (BR) can be positioned within the cavity (CV). That is, through the cavity (CV), a mounting space for the bridge substrate (BR) and the like can be easily secured on the upper build-up layer (112). In addition, a lower electrode portion (123) having a smaller line width than the upper electrode portion (122) outside the cavity (CV) can be easily placed on the upper portion of the cavity (CV). Accordingly, the circuit board according to the embodiment can provide easy connection between semiconductor elements and an improved input / output (I / O) count.

[0295] According to an embodiment, the bridge substrate (BR) is positioned within the cavity (CV) of the core layer (111), but may be embedded within the upper build-up layer disposed on the core layer (111). That is, according to an embodiment, the core layer (111) may be provided to prevent warpage while the circuit board (100B) is thinned, and at this time, the bridge substrate (BR) may be embedded within the core layer (111), but when the circuit board (100B) is designed to have a high multi-layer structure for signal integrity and power integrity, the bridge substrate (BR) may be embedded within the upper build-up layer to shorten the electrical length between the first and second semiconductor elements (DI1, DI2) and the bridge substrate (BR). Since the circuit board (100B) according to the embodiment can be used as an interposer, thinning is required, and thus the bridge substrate (BR) is embedded within the core layer (111), but is not limited thereto. That is, it is equipped with a circuit board (100B) rather than an interposer, so that a bridge board (BR) can be embedded in the upper build-up layer. In addition, the upper build-up layer (112) can be arranged on the core layer (111), and a part of it can be arranged in the cavity (CV) of the core layer (111). Accordingly, a part of the lower surface of the upper build-up layer (112) can be in contact with the upper surface of the lower build-up layer (113), and they can form the same plane. This can be implemented in the cavity (CV).

[0296] Furthermore, a stopper portion (ST) may be further arranged on the lower surface of the core layer (111). However, the bridge substrate may be mounted in the cavity described below using various materials (e.g., films) without the stopper portion (ST). In addition, the stopper portion (ST) may be a dummy electrode.

[0297] Referring further to FIG. 21, in the embodiment, the core layer (111) may include a core material (CO), a first resin material (RL1), and a second resin material (RL2).

[0298] The first resin material (RL1) may be positioned above the core material (CO). And the second resin material (RL2) may be positioned below the core material (CO). For example, the core material (CO) may be composed of multiple fibers. In this case, the first resin material (RL1) may refer to the upper fiber region of the uppermost part of the core material (CO). In addition, the second resin material (RL2) may refer to the lower fiber region of the lowest part of the core material (CO). The following description will be based on this. However, the first resin material (RL1) may refer to the upper region based on the fiber located in the center of the core material (CO) or the center of the core material, and the second resin material (RL2) may refer to the lower region based on the fiber located in the center of the core material (CO) or the center of the core material. In addition, the first resin material (RL1) and the second resin material (RL2) are described based on one horizontal direction.

[0299] The core material (CO) is a region forming the center of the core layer (111) and can determine mechanical strength and electrical properties. For example, the core material (CO) of the core layer (111) can include epoxy, glass fiber, metal, ceramic, etc.

[0300] The first resin material (RL1) and the second resin material (RL2) may be positioned on the core material (CO). The first resin material (RL1) and the second resin material (RL2) are made of resin and may include, for example, epoxy, polyimide, Teflon, etc. The first resin material (RL1) and the second resin material (RL2) may determine the flexibility, adhesion, insulation, etc. of the core layer (111).

[0301] In an embodiment, the core layer (111) may have an asymmetrical structure with respect to a virtual line (VL) which is a bisector in the stacking direction (Y-axis direction).

[0302] For example, the core material (CO) of the core layer (111) may be positioned asymmetrically with respect to the virtual line (VL). For example, with respect to the virtual line (VL), the distance (La) between the uppermost part of the virtual line (VL) and the core material (CO) may be different from the distance (Lb) between the lowermost part of the virtual line (VL) and the core material (CO). For example, with respect to the virtual line (VL), the distance (T1) between the uppermost part of the virtual line (VL) and the core material (CO) may be greater than the distance (T2) between the lowermost part of the virtual line (VL) and the core material (CO).

[0303] In addition, the first resin material (RL1) and the second resin material (RL2) may be positioned asymmetrically with respect to the core material or the virtual line (VL). In an embodiment, the thickness (T1) of the first resin material (RL1) may be different from the thickness (T2) of the second resin material (RL2). For example, the thickness (T1) of the first resin material (RL1) may be smaller than the thickness (T2) of the second resin material (RL2). In addition, the shortest distance (T11) from the core material (CL) to the lower surface of the upper build-up layer (112) may be smaller than the shortest distance (T22) from the core material (CL) to the upper surface of the lower build-up layer (113).

[0304] Accordingly, in the core layer (111), the core material (CO) can be positioned in large numbers on the upper side with respect to the virtual line (VL).

[0305] In this way, when the core material (CO) within the core layer (111) has an asymmetrical structure in the lamination direction, a difference in the thermal expansion coefficients between the upper and lower portions of the core layer (111) may occur. For example, a difference in the thermal expansion coefficients between the upper and lower portions of the core layer (111) may occur based on the virtual line (VL). In addition, since the core material (CO) is positioned or concentrated at the upper portion of the core layer (111), stress may be concentrated at the lower portion of the core layer (111). For example, thermal stress and mechanical stress may be concentrated at the lower portion of the core layer (111). At this time, a cavity (CV) and a bridge substrate (BR), etc. may be disposed on the upper portion of the core layer (111). In addition, semiconductor elements, etc. may be further disposed at the upper portion of the core layer (111). Accordingly, the thickness of the second resin material (RL2) is formed to be greater than the thickness of the first resin material (RL1), so that stress concentration due to various elements, fine patterns, etc. on the upper side of the core layer (111) can be compensated. In other words, by adjusting the thickness between the first resin material and the second resin material, the stress balance of the core layer (111) can be maintained, so that deformation of the circuit board can be minimized.

[0306] However, since the core material (CO) is arranged on the upper side of the core layer (111), heat generated in the circuit board can be easily dissipated. In particular, the heat for the bridge substrate (BR) mounted in the cavity (CV) of the core layer (111) and the semiconductor element on the upper side can be brought closer to the core material (CO) of the core layer (111). In other words, the distance between the heat source and the core material (CO) can be reduced. Accordingly, the heat dissipation path through the first resin material (RL1) on the upper side of the core material (CO) within the core layer (111) is reduced, so that heat can be easily dissipated upward, and heat dissipation of the circuit board can be easily achieved. In particular, when the core material (CO) includes a high thermal conductivity material, the heat dissipation efficiency of the circuit board can be further improved.

[0307] Additionally, the thickness of the core material (CO) may be smaller than the total thickness of the first resin material (RL1) and the second resin material (RL2). Furthermore, the thickness of the core material (CO) may be larger than the thickness of the first resin material (RL1) or the thickness of the second resin material (RL2). With this configuration, the mechanical strength of the core layer can be enhanced, and structural stability and electrical properties can also be improved.

[0308] Referring further to FIG. 22, in the embodiment, the upper build-up layer (112) and the lower build-up layer (113) may have different thicknesses.

[0309] As an example, the relationship between the thicknesses of the upper build-up layer (112) and the lower build-up layer (113) may correspond to the relationship between the thicknesses of the first resin material (RL1) and the second resin material (RL2).

[0310] For example, the thickness (Ta) of the upper build-up layer (112) may be smaller than the thickness (Tb) of the lower build-up layer (113). In other words, the upper build-up layer (112) in contact with the first resin material (RL1) may be formed to have a thicker thickness than the lower build-up layer (113) in contact with the second resin material (RL2).

[0311] By this configuration, stress balance can be easily maintained in the circuit board (100B). In addition, heat can be easily dissipated upwards through the difference in thickness between the first resin material (RL1) and the second resin material (RL2), and stress concentrated downwards can be compensated for through the difference in thickness between the upper build-up layer and the lower build-up layer. Accordingly, in addition to stress balance, the difference in thermal expansion can be reduced, so that uniform thermal deformation can be induced. In particular, warpage of the circuit board in a high-temperature environment such as reflow can be more easily suppressed. Furthermore, by securing the thickness of the lower build-up layer (113), mechanical strength is improved, so that delamination or cracking between layers can be suppressed. Furthermore, durability against external impact can also be improved.

[0312] Table 1 below shows the results of measuring the degree of warpage for various examples in which the thickness (Ta) of the upper build-up layer (112) and the thickness (Tb) of the lower build-up layer (113) were changed.

[0313] Example 1 Example 2 Example 3 Example 4 Ta (Upper) 15㎛ 15㎛ 20㎛ 20㎛ Tb (Lower) 15㎛ 20㎛ 15㎛ 20㎛ Warpage degree +5.89㎜ +4.46㎜ +8.05㎜ +6.63㎜

[0314] As shown in Table 1, when the thickness (Ta) of the upper build-up layer (112) is greater than the thickness (Tb) of the lower build-up layer (113), the warpage phenomenon is significantly improved compared to other cases (smaller or equal cases). In addition, in the embodiment, the first protective layer (SR1) may be laminated on the upper build-up layer (112) and may be in contact with the upper build-up layer (112). And the second protective layer (SR2) may be laminated on the lower build-up layer (113) and may be in contact with the lower build-up layer (113). In addition, the upper build-up layer (112) and the lower build-up layer (113) may have different filler contents. As described above, the filler includes silica, alumina, etc., and when the proportion of the filler increases, the mechanical strength in the build-up layer increases and the mechanical stress may further increase. Furthermore, however, when the content of the filler increases, the thermal stress may be alleviated.

[0315] Accordingly, for example, the filler ratio of the lower build-up layer (113) can be smaller than the filler ratio of the upper build-up layer (112). Accordingly, the reliability of the circuit board can be improved by increasing the mechanical stress of the lower portion while alleviating the thermal stress of the upper portion. Furthermore, shock absorption, thermal expansion, and stress concentration can be effectively compensated for by adjusting the filler content and thickness. For example, since an increase in the filler content causes a concentration of stress, stress relief can be implemented by increasing the filler content in the upper build-up layer (112) or increasing the thickness of the lower build-up layer (113).

[0316] And the first protective layer (SR1) and the second protective layer (SR2) may have the same or different thicknesses. For example, the thickness (Tc) of the first protective layer (SR1) and the thickness (Td) of the second protective layer (SR2) may be different from each other. For example, the thickness (Tc) of the first protective layer (SR1) may be smaller than the thickness (Td) of the second protective layer (SR2).

[0317] That is, the thickness (Tc) of the first protective layer (SR1) and the thickness (Td) of the second protective layer (SR2) may correspond to the relationship in magnitude between the thicknesses of the first resin material (RL1) and the second resin material (RL2). In addition, the thickness (Tc) of the first protective layer (SR1) and the thickness (Td) of the second protective layer (SR2) may be opposite to the relationship in magnitude between the thickness (Ta) of the upper build-up layer (112) and the thickness (Tb) of the lower build-up layer (113).

[0318] Accordingly, the circuit board (100B) can have high mechanical strength through the thickness of the second protective layer (SR2). Furthermore, the stress concentrated downward can be partially alleviated based on the core layer (111), etc.

[0319] In addition, in an embodiment, a circuit board may be provided in which the thicknesses of the upper build-up layer (112), the lower build-up layer (113), the first protective layer (SR1), and the second protective layer (SR2) are adjusted to be the same or different from each other. Accordingly, the circuit board may have more stress relief and an improved warpage suppression effect.

[0320] Table 2 below shows the results of measuring the degree of warpage for various examples in which the thickness (Ta) of the upper build-up layer (112), the thickness (Tb) of the lower build-up layer (113), the thickness (Tc) of the first protective layer (SR1), and the thickness (Td) of the second protective layer (SR2) were changed.

[0321] Example 5 Example 6 Example 7 Example 8 Example 9 Tc (Upper) 15㎛ 15㎛ 20㎛ 15㎛ 15㎛ Ta (Upper) 15㎛ 20㎛ 15㎛ 15㎛ 15㎛ Tb (Lower) 15㎛ 15㎛ 15㎛ 15㎛ 10㎛ Td (Lower) 15㎛ 15㎛ 15㎛ 10㎛ 15㎛ Warpage degree +2.28㎜ +1.09㎜ +3.88㎜ +3.33㎜ +1.22㎜

[0322] As shown in Table 2, it can be seen that adjusting the thickness of the upper build-up layer (112) and the lower build-up layer (113) greatly improves the warpage phenomenon. This is explained in the following examples with reference to FIGS. 23 to 26. Referring to FIG. 23, in the circuit board of the present example, the upper build-up layer (112) and the first protective layer (SR1) can be sequentially laminated in the lamination direction (Y-axis direction) on top of the core layer (111). In addition, the second protective layer (SR2) and the lower build-up layer (113) can be sequentially laminated in the lamination direction (Y-axis direction) on the bottom of the core layer (111). Accordingly, the second protective layer (SR2), the lower build-up layer (113), the core layer (111), the upper build-up layer (112), and the first protective layer (SR1) can be sequentially stacked in the stacking direction (Y-axis direction). In this example, the thickness (Ta) of the upper build-up layer (112) can be greater than the thickness of at least one of the lower build-up layer (113), the first protective layer (SR1), and the second protective layer (SR2).

[0323] For example, the thickness (Ta) of the upper build-up layer (112) may be the largest among the lower build-up layer (113), the first protective layer (SR1), and the second protective layer (SR2). In other words, the thickness (Ta) of the upper build-up layer (112) may be larger than the thickness (Tb) of the lower build-up layer (113), the thickness (Tc) of the first protective layer (SR1), and the thickness (Td) of the second protective layer (SR2).

[0324] By this configuration, the bending phenomenon of the circuit board (100B) can be suppressed more effectively.

[0325] At this time, as described above, the position of the core material in the core layer (111) can be positioned symmetrically or asymmetrically with respect to the virtual line.

[0326] Furthermore, the thickness (Tb) of the lower build-up layer (113), the thickness (Tc) of the first protective layer (SR1), and the thickness (Td) of the second protective layer (SR2) may be the same or different from each other.

[0327] For example, when the thickness (Ta) of the upper build-up layer (112) is greater than the thickness (Tc) of the first protective layer (SR1), the thickness (Tc) of the first protective layer (SR1) may be equal to or different from the thickness (Tb) of the lower build-up layer (113). Furthermore, the thickness (Tc) of the first protective layer (SR1) may also be equal to or different from the thickness (Td) of the second protective layer (SR2).

[0328] In addition, for example, if the distance (T1) between the uppermost part of the virtual line (VL) and the core material (CO) is greater than the distance (T2) between the lowermost parts, the core material (CO) may be positioned relatively tilted downward. In this case, the thickness (Ta) of the upper build-up layer (112) formed on the upper part of the core layer (111) may be greater than the thickness (Tb) of the lower build-up layer (113), and the thickness (Tc) of the first protective layer (SR1) may also be formed to be greater than the thickness (Td) of the second protective layer (SR2). This configuration may increase the structural rigidity of the upper build-up layer (112), thereby contributing to the stable formation of a high-density circuit pattern. In addition, the heat dissipation performance may be improved by expanding the heat dissipation path of the upper wiring portion. Furthermore, since the upper part of the circuit board has a relatively thick structure, the warping phenomenon may be suppressed.

[0329] In addition, as another example, when the distance (T1) between the uppermost part of the virtual line (VL) and the core material (CO) is smaller than the distance (T2) between the lowermost parts, the core material (CO) may be positioned relatively tilted upward. Accordingly, the thickness (Tb) of the lower build-up layer (113) formed under the core layer (111) may be larger than the thickness (Ta) of the upper build-up layer (112), and the thickness (Td) of the second protective layer (SR2) may also be formed to be larger than the thickness (Tc) of the upper protective layer (the first protective layer (SR1)).

[0330] This structure can increase the mechanical strength of the lower build-up layer (113), thereby enhancing the structural stability of the entire substrate and improving the reliability of the lower interface soldered to the substrate. In addition, by thickening the lower wiring layer, the current capacity can be increased, thereby improving power integrity.

[0331] In addition, as another example, even if the distance (T1) between the uppermost portions of the virtual line (VL) and the core material (CO) is greater than the distance (T2) between the lowermost portions, the thickness distribution of the protective layer may be applied differently from the above-described. For example, the thickness (Ta) of the upper build-up layer (112) may be greater than the thickness (Tb) of the lower build-up layer (113), but the thickness (Tc) of the upper protective layer (the first protective layer (SR1)) may be less than the thickness (Td) of the second protective layer (SR2). Such a structure can protect a layer (e.g., a signal layer) disposed on the upper portion of the substrate, while forming the second protective layer (SR2) thick to strengthen the solder mask function and prevent soldering failures. In addition, the thickening of the second protective layer can increase the environmental durability at the bottom.

[0332] In addition, as a modified example, even if the distance (T1) between the uppermost portions of the virtual line (VL) and the core material (CO) is smaller than the distance (T2) between the lowermost portions, the first protective layer (SR1) may be formed thicker than the second protective layer (SR2). That is, the thickness (Tb) of the lower build-up layer (113) may be larger than the thickness (Ta) of the upper build-up layer (112), but the protective layer thickness may be set in the opposite direction in response to the thickness of the build-up layer. Accordingly, the thickness (Tc) of the first protective layer (SR1) may be larger than the thickness (Td) of the second protective layer (SR2). By this configuration, the circuit board is more effectively protected from the external environment (moisture, chemical exposure), and the EMI (Electromagnetic Interference) shielding effect can also be improved.

[0333] In addition, the position of the core material (CO) may be arranged asymmetrically with respect to the virtual line (VL). That is, the thicknesses of the first resin material and the second resin material may be different. In addition, when the thicknesses of the build-up insulation parts (112, 113) are the same, only the thickness of the protective layer may be different. That is, even if the thickness (Ta) of the upper build-up layer (112) and the thickness (Tb) of the lower build-up layer (113) are the same, the thickness (Tc) of the first protective layer (SR1) and the thickness (Td) of the second protective layer (SR2) may be different from each other. This configuration can improve signal protection or soldering reliability in a specific area while maintaining the physical rigidity of the substrate in a balanced manner.

[0334] Referring to FIG. 24, in the circuit board of the present example, an upper build-up layer (112) and a first protective layer (SR1) may be sequentially stacked in a stacking direction (Y-axis direction) on top of a core layer (111). In addition, a second protective layer (SR2) and a lower build-up layer (113) may be sequentially stacked in a stacking direction (Y-axis direction) below the core layer (111). Accordingly, the second protective layer (SR2), the lower build-up layer (113), the core layer (111), the upper build-up layer (112), and the first protective layer (SR1) may be sequentially stacked in a stacking direction (Y-axis direction).

[0335] In this example, in addition to the upper build-up layer (112), the lower build-up layer (113), the first protective layer (SR1), and the second protective layer (SR2) may have the same thickness.

[0336] For example, the lower build-up layer (113), the first protective layer (SR1), and the second protective layer (SR2) may have the same thickness, and the thickness of each of the lower build-up layer (113), the first protective layer (SR1), and the second protective layer (SR2) may be different from the thickness (Ta) of the upper build-up layer (112). Since the lower build-up layer (113), the first protective layer (SR1), and the second protective layer (SR2) have the same thickness except for the first layer, the stress balance of the entire circuit board can be maintained. As a result, the substrate warpage phenomenon can be suppressed, and the durability of the circuit board can be improved.

[0337] Furthermore, as in Example 6 of Table 2, the bending phenomenon can be suppressed more effectively.

[0338] Referring to FIG. 25, in the circuit board of the present example, an upper build-up layer (112) and a first protective layer (SR1) may be sequentially stacked in a stacking direction (Y-axis direction) on top of a core layer (111). In addition, a second protective layer (SR2) and a lower build-up layer (113) may be sequentially stacked in a stacking direction (Y-axis direction) below the core layer (111). Accordingly, the second protective layer (SR2), the lower build-up layer (113), the core layer (111), the upper build-up layer (112), and the first protective layer (SR1) may be sequentially stacked in a stacking direction (Y-axis direction).

[0339] In this example, the thickness (Tb) of the lower build-up layer (113) may be smaller than the thickness of at least one of the upper build-up layer (112), the first protective layer (SR1), and the second protective layer (SR2). For example, the thickness (Tb) of the lower build-up layer (113) may be smaller than the thickness (Ta) of the upper build-up layer (112).

[0340] And in this example, the upper build-up layer (112), the first protective layer (SR1), and the second protective layer (SR2) may have different or the same thicknesses.

[0341] In particular, as described above, the core layer (111) may have various positions of the core material within the core layer (111). For example, in the core layer (111), the core material may be positioned adjacent to the lower build-up layer (113) compared to the upper build-up layer (112). Accordingly, stress relief can be easily implemented by making the thickness of the lower build-up layer (113) described above greater than that of the other layers.

[0342] Referring to FIG. 26, in the circuit board of the present example, an upper build-up layer (112) and a first protective layer (SR1) may be sequentially stacked in a stacking direction (Y-axis direction) on top of a core layer (111). In addition, a second protective layer (SR2) and a lower build-up layer (113) may be sequentially stacked in a stacking direction (Y-axis direction) below the core layer (111). Accordingly, the second protective layer (SR2), the lower build-up layer (113), the core layer (111), the upper build-up layer (112), and the first protective layer (SR1) may be sequentially stacked in a stacking direction (Y-axis direction).

[0343] In this example, the thickness (Tb) of the lower build-up layer (113), the thickness (Tc) of the first protective layer (SR1), and the thickness (Td) of the second protective layer (SR2) may be the same. That is, the thicknesses of the remaining layers, except for the upper build-up layer (112), may be the same.

[0344] At this time, the core material in the core layer (111) may be positioned adjacent to the upper portion. As a result, the core material may be concentrated in the upper portion of the core layer (111), and stress may be concentrated on the lower side.

[0345] In this example, since the first protective layer (SR1), the lower build-up layer (113), and the second protective layer (SR2) have the same thickness, stress balance can be maintained throughout the circuit board. This suppresses substrate warpage, and improves the durability of the circuit board.

[0346] Figures 27 to 33 are drawings explaining a method for manufacturing a circuit board according to an embodiment of the present invention.

[0347] It should be noted that one or more steps may be combined to simplify and / or clarify the steps for providing or manufacturing a circuit board. In some implementations, the order of the processes may be changed or modified. Furthermore, in some implementations, one or more of the manufacturing methods may be replaced or substituted without departing from the spirit of the present disclosure. Different implementations may manufacture the board differently.

[0348] Referring to Fig. 27, a core layer (111) can be provided. The core layer (111) may be an insulating layer having a predetermined thickness or more as described above. In addition, the core layer (111) may include glass or glass fiber having a resin. However, the core layer (111) may also include different materials.

[0349] Referring to FIG. 28, a via hole or a through hole (111h) can be formed in the core layer (111). The through hole can be formed through the upper and lower surfaces of the core layer (111). The through hole or via hole can be formed by a method such as a laser drilling method, a punching method, an etching method (mechanical drilling, chemical etching, or any suitable mechanism).

[0350] Referring to Fig. 29, a core electrode portion (121) can be formed on a core layer (111). The electrode portion can be formed by a patterning process based on mask formation (exposure, curing, etc.), a stripping process, and / or a plating process.

[0351] For example, a plating process may be performed on a via hole formed in a core layer (111) to form a through electrode. In addition, a core wiring portion may be formed on the upper and lower surfaces of the core layer (111). The core wiring portion may have a pattern using a mask or the like. Furthermore, the core wiring portion may be formed using an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are manufacturing processes for printed circuit boards. This may be equally applied to other wiring portions.

[0352] Furthermore, a stopper portion (ST) may be arranged on the lower surface of the core layer (111). However, the bridge substrate may be mounted in the cavity described below using various materials (e.g., films) without the stopper portion (ST). In addition, the stopper portion (ST) may be a dummy electrode.

[0353] Referring to Fig. 30, a cavity (CV) can be formed in a region of the core layer (111) by various methods such as a laser method, a punching method, and an etching method. The cavity (CV) can be easily formed by a stopper part (ST). The cavity (CV) can penetrate the core layer (111). However, the present invention is not limited thereto, and the cavity (CV) can penetrate up to a part of the core layer (111). That is, the cavity (CV) can be a hole or a groove.

[0354] Referring to Fig. 31, a bridge substrate (BR) may be mounted in a cavity (CV) of a core layer (111). The bridge substrate (BR) may be mounted on a stopper portion (ST). Alternatively, if the stopper portion (ST) does not exist, a member (e.g., a film) may be placed on the lower surface of the core layer (111) after the cavity (CV) is formed. The above-described member (e.g., a film) may overlap the cavity (CV) in a vertical direction. In addition, the bridge substrate (BR) may be mounted on the member (e.g., a film).

[0355] Referring to Fig. 32, an upper build-up layer (112) can be formed above the core layer (111) and within the cavity (CV). Additionally, a lower build-up layer (113) can be formed below the core layer (111).

[0356] In addition, before forming the upper build-up layer (112), underfilling may be performed to fix the position of the bridge substrate (BR) in the cavity (CV). For example, a filling material (F1) may be further applied within the cavity (CV). Accordingly, the filling material (F1) may improve the bonding strength between the core layer (111) and the bridge substrate (BR). As a result, the circuit board may be protected from impact, dropping, and vibration. In addition, deformation due to differences in thermal expansion between other components, such as the bridge substrate (BR) and the core layer (111), may be reduced. The filling material (F1) may include epoxy, etc.

[0357] However, as described above, the upper build-up layer (112) can be applied within the cavity (CV), and this is illustrated as a reference.

[0358] Referring to FIG. 33, a via hole or through hole may be formed in the upper build-up layer (112) and / or the lower build-up layer (113). The via hole may be formed by a laser drilling method, a punching method, an etching method (mechanical drilling, chemical etching, or any suitable mechanism), etc.

[0359] Additionally, an upper electrode portion (122) may be formed on the upper build-up layer (112). And a lower electrode portion (123) may be formed on the lower build-up layer (113). The upper electrode portion (122) and the lower electrode portion (123) may be formed by a patterning process based on mask formation (exposure, curing, etc.), a stripping process, and / or a plating process.

[0360] And the upper wiring part of the upper electrode part (122) may be formed on the upper surface of the upper build-up layer (112), and the lower wiring part of the lower electrode part (123) may be formed on the lower surface of the lower build-up layer (113). Each wiring part may have a pattern by a mask or the like. Furthermore, the wiring part may be formed by an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are manufacturing processes of a printed circuit board.

[0361] Thereafter, a first protective layer (SR1) may be formed on the upper build-up layer (112). A second protective layer (SR2) may be formed under the lower build-up layer (113). Furthermore, a via (TP) penetrating the protective layer (SR) may be formed.

[0362] Fig. 34 is a drawing of a circuit board according to the fourth embodiment, Fig. 35 is an enlarged view of a portion of Fig. 34, Fig. 36 is a plan view of a circuit board according to the fourth embodiment, and Fig. 37 is a modified example of Fig. 36.

[0363] Referring to FIGS. 34 and 35, a circuit board (100C) according to an embodiment may include an insulating layer (110) and an electrode portion (120). In the embodiment described below, the circuit board includes an insulating layer (110) and a wiring or electrode portion (120). The insulating layer (110) includes an upper surface for mounting a semiconductor element, a lower surface corresponding to the upper surface, and a lower surface for connecting the circuit board (CB) to a main board, etc., and may have a structure in which a plurality of insulating layers are laminated between the upper surface and the lower surface. The upper build-up layer (112) constituting the upper surface of the circuit board and the lower build-up layer (112) constituting the lower surface of the circuit board may be referred to as an outer laminated region, and the region laminated between the upper insulating layer and the lower insulating layer may be referred to as an inner laminated region.

[0364] The wiring or electrode portion (120) is arranged for electrical connection between the main board, etc. and the semiconductor element (SD), and includes a circuit pattern (or circuit pattern layer), pad, and via electrode. The wiring may correspond to the electrode portion or electrode. And the circuit pattern may be designed in various forms for signal and / or power transmission with the semiconductor element (SD), and is arranged within each vertically stacked insulating layer (110).

[0365] Via electrodes (121b, 122b) are arranged to penetrate a portion of each insulating layer to vertically connect circuit patterns arranged on each vertically stacked insulating layer. That is, the insulating layer may include a via hole for arranging the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but the present invention is not limited thereto and may be freely designed.

[0366] The pads (121a, 122a) may include an outer pad (122a) arranged in the outer stacking region and an inner pad (121a) arranged in the inner stacking region. The outer pad (122a) functions to be bonded to a semiconductor device (SD) and / or a main board or substrate (CB). Currently, it can be bonded with solder, wire, conductive adhesive, etc., but may be arranged with a width larger than the width of the circuit pattern to solve problems such as securing yield. However, the present invention is not limited thereto, and may have the same width as the width of the circuit pattern depending on the technical limitations of the bonding process. The inner pad (121a) functions to connect the via electrode and the circuit pattern. When the via electrode is arranged with a width wider than the circuit pattern, a pad with a width wider than the circuit pattern is provided for positional alignment during the manufacturing process of the via electrode to be arranged on each circuit pattern. Accordingly, each via electrode may have an upper surface that is flush with the lower surface of the upper pad that is in direct contact with the via electrode, and a lower surface that is flush with the upper surface of the lower pad that is in direct contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean flat surfaces, and it should be understood that even concave or convex surfaces that may appear depending on various processes may be present.

[0367] The circuit board may further include a protective layer (SR). The protective layer (SR) may function to protect the pad from external moisture or contaminants, and may be formed of a solder resist, for example, to prevent a short circuit problem when bonding the semiconductor device and / or the main board to the circuit board. Specifically, the semiconductor device and / or the main board, etc. have multiple terminals for connecting the circuit board. In addition, the multiple terminals may be arranged at a high density. When the multiple terminals and the pads of the circuit board are bonded, solder may be used, for example. When solder is used, a solder short circuit problem may occur between terminals with a high density, and thus, a solder resist that does not have good wettability with the solder may be arranged to solve this short circuit problem. In addition, the protective layer (SR) may be formed of a material that has insulating properties for electrical connection. Accordingly, the protective layer (SR) may be referred to as an 'insulating layer' and may be a component of the above-described insulating layer (110).

[0368] And the build-up layer (112) or the protective layer (SR) located in the outer laminated area of ​​the circuit board may have an opening (OP). That is, when the protective layer (SR) is not provided, the build-up layer (112) may have an opening (OP), and when the protective layer (SR) is provided, the protective layer (SR) may have an opening (OP). It may be electrically connected to other semiconductor elements, a circuit board, etc. through the opening (OP).

[0369] Circuit boards can be divided into package boards and interposers based on their function. The package board serves the function of mounting semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, to improve the yield of circuit boards with a high number of layers, the yield of the circuit board can be improved by separating them into an interposer and a package board. In addition, as the terminal density of semiconductor devices increases, it can be difficult to implement pads on the package board with an area corresponding to the terminals of the semiconductor devices. Therefore, the pad size of the package board can act as a buffer between the size of the pad and the fine pattern size of the terminals of the semiconductor devices.

[0370] The package substrate and interposer described above can be classified into core substrates and coreless substrates, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0371] The insulating layer of the circuit board is formed of any insulating resin, such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin, such as PID (Photo Imageable Dielectric) resin, can be used. The aforementioned optional insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, a reinforcing material such as glass fiber or aramid fiber can be included.

[0372] In a circuit board (100C) according to an embodiment, the build-up layer (112) may include a first build-up layer (112a) and a second build-up layer (112b).

[0373] The second build-up layer (112b) may be positioned between the first build-up layer (112a) and the core layer (111). For example, in the lamination direction, the first build-up layer (112a) may be positioned on top of the second build-up layer (112b).

[0374] Each layer of the build-up layer (112) may include a through hole. The first build-up layer (112a) may include a first through hole (CV1). The second build-up layer (112b) may include a second through hole (CV2).

[0375] Furthermore, the first through hole (CV1) may overlap the second through hole (CV2) in the stacking direction. And the width (W1,3) of the first through hole (CV1) may be smaller than the width (W2) of the second through hole (CV2). For example, the maximum width (W1,3) of the first through hole (CV1) may be smaller than the maximum width (W2) of the second through hole (CV2).

[0376] These first through-holes (CV1) and second through-holes (CV2) can form a cavity (CV). That is, the cavity (CV) can be an area or recess formed by the first through-holes (CV1) and the second through-holes (CV2). Alternatively, the build-up layer (112) of the circuit board (100C) includes the cavity (CV), and the cavity (CV) can include the first through-holes (CV1) and the second through-holes (CV2). In the circuit board of the embodiment according to the present invention, the circuit pattern layer can be a concept including the circuit pattern and pad described in FIG. 1.

[0377] First, the insulating layer (110) may be formed of an insulating material. The insulating layer (110) may be formed of at least one layer. When the insulating layer (110) has a multi-layer structure, the insulating layers (110) of the multiple layers may include the same insulating material, but are not limited thereto. For example, at least one insulating layer (110) among the multiple layers of insulating layers (110) may include an insulating material different from at least one other insulating layer (110).

[0378] The insulating layer (110) of the circuit board may be rigid or flexible. For example, the insulating layer (110) of the circuit board may include glass or plastic. For example, the insulating layer (110) of the circuit board may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer (110) of the substrate may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer (110) of the circuit board may include sapphire. For example, the insulating layer (110) of the substrate may include an optically isotropic film. For example, the insulating layer (110) of the substrate may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), photoisotropic polycarbonate (PC), or photoisotropic polymethyl methacrylate (PMMA). For example, the insulating layer (110) of the substrate may be formed of a material including a filler and an insulating resin. For example, the insulating layer (110) of the substrate may have a structure in which a filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

[0379] The insulating layer (110) may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure will be described in more detail as follows.

[0380] In one embodiment, the insulating layer (110) may include a core layer including a reinforcing member, or may be provided as a coreless layer. Here, the core layer (110) may refer to an insulating layer including a reinforcing member and having a thickness in the lamination direction (X-axis direction) exceeding 30 μm. In addition, the insulating layer may include a plurality of layers that are respectively disposed on the upper and lower portions of the core layer and do not include a reinforcing member. In this case, the circuit board may be a core board. The reinforcing member may also be referred to as a reinforcing fiber or glass fiber.

[0381] Reinforcing member may mean a glass fiber material extending along the horizontal direction of the insulation layer and may have a different meaning from the spaced filler.

[0382] In another embodiment, the insulating layer (110) of the substrate may be a coreless substrate that does not include a core layer. For example, the insulating layer (110) of the substrate may include an organic material that does not include a reinforcing member that has excellent processability, enables slimming of the substrate, and enables miniaturization of the electrode portion of the substrate. For example, the insulating layer (110) of the substrate may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the insulating layer (110) may include a plurality of layers composed of ABF.

[0383] As an example, the insulating layer (110) may include a core layer (111) and a build-up layer (112). The build-up layer (112) may be disposed on the core layer (111).

[0384] The core layer (111) may be a core layer. Alternatively, the core layer (111) may correspond to a portion of a copper-clad laminate.

[0385] And the core layer (111) may include an insulating material as an inner laminated region in the circuit board (100C). The core layer (111) may be formed of a plurality of layers, and the plurality of layers may be formed of the same or different materials. In addition, the core layer (111) may be positioned between upper and lower build-up layers (112). The build-up layers (112) may be arranged on the upper and lower surfaces of the core layer (111).

[0386] In addition, a circuit board according to an embodiment of the present invention may include a build-up structure and an electrode portion (in addition to a protective layer). The build-up structure may be formed of a plurality of insulating layers. In particular, the circuit board includes a build-up structure, and when a core layer is present, the build-up structure may include an upper build-up layer, a core layer, and a lower build-up layer. In addition, when the core layer is not present, the build-up structure may include an upper build-up layer and a lower build-up layer based on the aforementioned expansion direction, etc. That is, the upper build-up layer and the lower build-up layer may be distinguished by a structure in which the expansion directions of via holes within the layers are opposite to each other. For example, the width or area of ​​the via hole may increase (increase) as it goes upward in the upper build-up layer. And the width or area of ​​the via hole may decrease (increase) as it goes upward in the lower build-up layer. In addition, each build-up layer may correspond to an insulating layer other than the core layer. In addition, each build-up layer may be formed of at least one insulating layer.

[0387] Furthermore, the build-up layer may be a different layer from the protective layer. For example, the top / bottom surface of the build-up layer (or insulating layer) corresponds to the top / bottom surface of the build-up layer (insulating layer) positioned at the top, and does not refer to the top / bottom surface of the protective layer. In other words, the top surface of the insulating layer of the circuit board refers to the top / bottom surface of the build-up layer, not the protective layer.

[0388] Accordingly, in the circuit board according to the present embodiment, the core layer (111) is a core layer, the upper build-up layer may include a build-up layer (112) arranged on top of the core layer (111), and the lower build-up layer may include a build-up layer (112) arranged under the core layer (111).

[0389] The core layer (111) and the core electrode portion (121) may not be easily removed by etching during cavity formation or by etching in the desmear process described below. That is, even if a cavity (CV) is formed in the build-up layer (112) or a desmear process is performed, the core layer (111) and the core electrode portion (121) may easily remain.

[0390] Additionally, the build-up layer (112) may be disposed on the core layer (111) and the first core wiring portion (121a). The build-up layer (112) may correspond to an outer laminated area in the circuit board (110A).

[0391] The build-up layer (112) may be composed of at least one layer. As illustrated, the build-up layer (112) may be composed of multiple layers. As an example, the build-up layer (112) may include a first build-up layer (112a) and a second build-up layer (112b). In addition, the build-up layer (112) may include ABF (Ajinomoto Build-up Film) as described above, or prepreg (PPG) including glass fiber.

[0392] The build-up layer (112) can be located on at least one of the upper and lower surfaces of the core layer (111). The following description is based on the stacking direction (X-axis direction).

[0393] Additionally, as described above, a third insulating layer (not shown) may be further disposed on the build-up layer (112). That is, in addition to the illustrated build-up layer (112), an additional insulating layer may be further formed on the build-up layer (112).

[0394] The electrode portion (120) may include a core electrode portion (121) and a build-up electrode portion (122). The core electrode portion (121) may be located in the core layer (111). The build-up electrode portion (122) may be located in the build-up layer (112).

[0395] The core electrode portion (121) may include a first core wiring portion (121a) and a core via electrode (121b). The build-up electrode portion (122) may include a build-up wiring portion (122a) and a build-up via electrode (122b). As described above, each circuit pattern layer may mean including a pad and / or trace of the electrode portion and a circuit pattern. The via electrode may mean an electrode that is connected to a circuit pattern layer and penetrates the build-up layer. For example, the via electrode may be disposed between a plurality of circuit pattern layers disposed on different layers.

[0396] The first core wiring portion (121a) may be arranged on the core layer (111). The first core wiring portion (121a) may be arranged on the upper and lower surfaces of the core layer (111). The core via electrode (121b) may penetrate the core layer (111) and come into contact with the first core wiring portion (121a).

[0397] The build-up wiring portion (122a) can be arranged on the build-up layer (112). The build-up wiring portion (122a) can be arranged on the upper and lower surfaces of the build-up layer (112). The build-up via electrode (122b) can penetrate the build-up layer (112) and come into contact with the build-up wiring portion (122a).

[0398] In this way, the first core wiring portion (121a) and the build-up wiring portion (122a) can be positioned on the core layer (111) and the build-up layer (112). And as described above, since the circuit pattern layer is a concept including a circuit pattern and a pad, the circuit pattern layer can be positioned within each insulating layer and may not be directly connected to the via electrode. However, each circuit pattern layer can be electrically connected to any one of the via electrodes.

[0399] In addition, the core layer (111) and the build-up layer (112) may include vias or via holes (V1, V2). The via holes may include a first via hole (V1) penetrating the core layer (111) and a second via hole (V2) penetrating the build-up layer (112). In addition, via electrodes of the electrode portion may be positioned in the via holes (V1, V2). For example, a core via electrode (121b) may be positioned in the first via hole (V1). A second through electrode (122b) may be positioned in the second via hole (V2).

[0400] As an example, the first via hole (V1) of the core layer (111) and the second via hole (V2) of the build-up layer (112) may have an inclined surface along the stacking direction. That is, the adjacent first via hole (V1) and second via hole (V2) may have an area that increases or decreases in one direction. For example, the area of ​​the first via hole (V1) and the second via hole (V2) may increase along the stacking direction based on the upper region of the circuit board (100C). Here, the upper region of the circuit board (100C) corresponds to an area on the stacking direction side among the regions that bisect the core layer (111) in the stacking direction.

[0401] In addition, since the build-up layer (112) is composed of a plurality of insulating layers, the second via holes (V2) may also be provided in a plurality. Each of the plurality of second via holes (V2) may have an area that increases or decreases in one direction. Based on the upper region of the circuit board (100C), the area of ​​the plurality of second via holes (V2) may increase along the stacking direction.

[0402] Additionally, the build-up layer (112) may cover at least a portion of the first core wiring portion (121a). Additionally, the third insulating layer (not shown) may cover at least a portion of the build-up wiring portion (122a). The third insulating layer (not shown) may include an opening (OP) for electrical connection with a semiconductor element, an interposer, etc. The build-up wiring portion (122a) may be exposed by the opening (OP).

[0403] The build-up layer (112) may include a cavity (CV) formed by a first through-hole (CV1) and a second through-hole (CV2). The build-up layer (112) may include the cavity (CV) and an edge portion (EG) outside the cavity (CV). The edge portion (EG) may be located outside the first through-hole (CV1) and the second through-hole (CV2) in the build-up layer (112). The edge portion (EG) may correspond to an 'edge portion', a 'wall portion', a 'side wall', etc. Furthermore, a build-up electrode portion (122) may be located in the edge portion (EG).

[0404] A cavity (CV) composed of a first through hole (CV1) and a second through hole (CV2) may be located within a build-up layer (112). The cavity (CV) may be located on a core layer (111) and a core electrode portion (121). In addition, the first through hole (CV1) and the second through hole (CV2) may be located on the core layer (111) and the core electrode portion (121).

[0405] In addition, the second through hole (CV2) of the build-up layer (112) according to the embodiment may include a protruding area that is misaligned with the first through hole (CV1) in the stacking direction. In other words, the build-up layer (112) may have an inner wall or a groove inner wall in which the cavity (CV) is formed. At this time, the protruding area may correspond to the 'indentation portion' of the inner wall of the build-up layer (112) in which the cavity (CV) is formed. That is, the protruding area may be the indentation portion (G). Hereinafter, the protruding area and the indentation portion (G) of the aforementioned second through hole (CV2) will be described interchangeably. For example, the indentation portion (G) may be an area that protrudes outward from the side of the first through hole (CV1) in the second through hole (CV2). The indentation portion (G) may not overlap with the first through hole (CV1) in the stacking direction. In addition, the build-up layer (112) may include an inlet portion (G) that is convex toward the outside of the cavity (CV). In addition, the second build-up layer (112b) may overlap at least partially with the first build-up layer (112a) in the lamination direction. The inlet portion (G) according to the embodiment may be positioned adjacent to the core layer (111). In addition, the inlet portion (G) may correspond to a portion where the second through hole (CV2) extends toward the outside, the edge portion, or the build-up electrode portion in an area adjacent to the core layer (111).

[0406] The inlet portion (G) according to the embodiment may be located on the inner surface (EGS) of the edge portion (EG) exposed by the first through hole (CV1) and the second through hole. For example, the inlet portion (G) may be formed on the inner surface (EGS) of the edge portion (EG) exposed by the cavity (CV). Alternatively, the inlet portion (G) may be located on the inner surface of the cavity (CV) corresponding to the inner surface (EGS) of the edge portion (EG).

[0407] In addition, the lead-in portion (G) may be located in a portion adjacent to the core layer (111) as described above in the build-up layer (112) or the edge portion (EG). For example, the lead-in portion (G) may be located in a lower region, not a region (upper region) on the stacking direction side, among the bisected regions of the build-up layer (112) along the stacking direction. By this configuration, when a bridge is embedded in the cavity (CV) through the lead-in portion (G) and covered with an insulating layer such as ABF, the bonding strength to the bridge may be improved. Accordingly, the reliability of the circuit board may be improved. Furthermore, the electrical reliability of the exposed first core wiring portion (121a, 121E) electrically connected to the semiconductor element or chip may be improved. In addition, the lead-in portion (G) may easily secure the flatness of the surface of the region where the semiconductor element or chip is settled by the eddy current of the cleaning material, or cleaning may be performed more easily. Furthermore, after a semiconductor element or chip is mounted within a cavity (CV) by the lead-in portion (G), underfilling or other operations can be easily performed. Furthermore, when molding is performed on a circuit board, underfilling or molding can be performed on the lead-in portion (G), thereby improving the structural reliability of the circuit board.

[0408] Furthermore, the lead-in portion (G) may be positioned only in the lower region described above. Alternatively, the lead-in portion (G) may be positioned in both the upper region and the lower region. When the lead-in portion (G) is positioned only in the lower region, a space for positioning the build-up electrode portion can be easily secured. Conversely, when the lead-in portion (G) is positioned in both the upper region and the lower region, the locking of the cleaning material during desmear or cleaning can be more easily achieved. Furthermore, the lead-in portion (G) may also increase the separation distance between the semiconductor element or chip and the inner surface (EGS). Therefore, electrical connection to the semiconductor element or chip becomes easier, and the reliability of the electrical connection can also be improved.

[0409] Since the lead-in portion (G) has a structure that protrudes outward from the inner surface (EGS) of the build-up layer (112), it can overlap at least partially with the first build-up layer (112a) in the stacking direction (X-axis direction). By this configuration, the flatness of the inner surface (EGS) of the cavity (CV) or the build-up layer (112) can be improved. As a result, the electrical reliability of a semiconductor element or chip mounted in the cavity (CV) can be improved. Furthermore, the reliability of the build-up layer (112) and the build-up electrode portion can be improved.

[0410] In addition, by securing a mounting space for semiconductor elements or chips within the cavity (CV) and arranging the build-up electrode portion (122) in the edge portion (EG), a circuit pattern with a small line width can be easily arranged within the build-up layer (112). As a result, the circuit board according to the embodiment can provide an improved input / output (I / O) count.

[0411] Furthermore, in the circuit board (100C) according to the embodiment, the lead-in portion (G) may overlap (OV) at least partially with the build-up wiring portion (122a (122V)) in the stacking direction. That is, the circuit pattern or pad of the build-up wiring portion may be located in an area of ​​the build-up layer (112) where the lead-in portion (G) is not disposed. For example, a portion of the build-up wiring portion may be located on the upper portion of the build-up layer (112). However, the build-up wiring portion may be spaced apart from the lead-in portion (G) to suppress the phenomenon in which the build-up wiring portion is exposed by the lead-in portion (G). As a result, the input / output (I / O) count may be further improved. Meanwhile, in some cases, the build-up wiring portion may be in contact with the lead-in portion (G) and a portion of the build-up wiring portion may be exposed by the lead-in portion (G). As described, the lead-in portion (G) may be located outside the cavity (CV) and may also be spaced apart from a semiconductor element or chip within the cavity (CV). Accordingly, even if a portion of the build-up wiring section is exposed by the lead-in section (G), electrical issues may not occur significantly.

[0412] In addition, the inlet portion (G) may have a distance (d) of 100 um to 200 um in the vertical direction of the stacking direction. If the distance (d) described above is less than 100 um, the fixing force for a bridge or the like mounted within the cavity can be significantly improved when embedded. In addition, if the distance (d) described above is greater than 200 um, there is a problem of voids being formed due to the cleaning material.

[0413] And at least a part of the first core wiring portion (121a) may be exposed by the cavity (CV). At least a part of the first core wiring portion (121a) may be exposed by the second through hole (CV2). In addition, the first core wiring portion (121a) exposed by the second through hole (CV2) may be located inside the inlet portion (G). The first core wiring portion (121a (121E)) exposed by the cavity (CV) may be located inside the inlet portion (G). For example, the first core wiring portion (121E) exposed by the cavity (CV) may be located adjacent to the center or central axis (CA) of the cavity (CV) with respect to the inlet portion (G). Accordingly, the first core wiring portion (121E) to be exposed may be surrounded by the inlet portion (G).

[0414] Additionally, a portion of the core layer (111) may be exposed by the cavity (CV). The exposed core layer (111E) may be located inside the lead-in portion (G). For example, the exposed core layer (111E) may be surrounded by the lead-in portion (G). Furthermore, the exposed core layer (111E) may face a mounted semiconductor element or chip, which will be described later. Furthermore, the exposed core layer (111E) may be located below the lead-in portion (G).

[0415] By this configuration, semiconductor elements or chips can be easily placed within the cavity (CV), and electrical connection between the semiconductor elements and the core electrode portion can also be easily made.

[0416] Furthermore, the upper surface of the core layer (111) may be further exposed by the lead-in portion (G). The exposed core layer (111E') may be located outside the core layer (111E) exposed by the cavity (CV). For example, the exposed core layer (111E') may overlap the lead-in portion (G) in a lower layer direction. This makes it possible to easily secure a space for electrical connection between the semiconductor element or chip and the core electrode portion, while also reducing the risk of short circuits.

[0417] Additionally, a first core wiring section may be further arranged on the exposed core layer (111E'). With this configuration, additional terminals for electrical connection between the semiconductor element or chip mounted in the cavity and the electrode section can be secured. In other words, the number of input / output terminals for the semiconductor element or chip can be secured.

[0418] As an example, the build-up layer (112) may be formed of a plurality of insulating layers as described above. In particular, the lead-in portion (G) may overlap the second build-up layer (112b) in a vertical direction relative to the lamination direction. Accordingly, while easily performing locking of the cleaning material by the lead-in portion (G), a space for forming a build-up electrode portion may also be secured in the build-up layer (112) above the lead-in portion (G).

[0419] The inlet portion (G) may have a structure extending toward the edge portion (EG). In other words, the inlet portion (G) may have a structure extending outward based on the central axis (CA) of the cavity (CV). Alternatively, the inlet portion (G) may have a structure extending outward based on the central axis (CA) of the first through hole (CV1) and / or the second through hole (CV2). Accordingly, the edge portion (EG) may have a distance (W1) from the center (CA) of the first through hole (CV1) (or cavity (CV)) in the first build-up layer (112a) smaller than a distance (W2) from the center (CA) of the first through hole (CV1) (or cavity (CV)) in the second build-up layer (112b). In various embodiments of the present invention, the center or central axis of the cavity (CV) corresponds to the centers or central axes of the first and second through holes.

[0420] And the edge portion (EG) may decrease in the distance (W2) from the center (CA) of the first and second through-holes (or cavities (CV)) in the second build-up layer (112b) in the opposite direction to the stacking direction or the direction toward the first insulating layer. Alternatively, the edge portion (EG) may have different distances from the center (CA) of the cavity (CV) at both ends adjacent to the through-hole (G) of the second build-up layer (112b). For example, the edge portion (EG) may have a greater distance from the center (CA) of the cavity (CV) at one end (lower end) adjacent to the first insulating layer among the upper or lower ends of the through-hole (G) in the second build-up layer (112b) than at the other end (upper end). Additionally, the edge portion (EG) may be spaced such that the distance from the center (CA) of the second through hole (or cavity (CV)) in the second build-up layer (112b) decreases along the stacking direction. With this configuration, the locking of the cleaning material during desmearing can be more effectively achieved.

[0421] In addition, in the present embodiment, the edge portion (EG) may be the same or maintained along the stacking direction at a distance from the center (CA) of the first through hole (or cavity (CV)) in the first build-up layer (112a). Here, maintenance means a range within 10%. With this configuration, the build-up layer (112) may have sufficient space on the upper portion of the inlet portion (G) to allow circuit patterns or pads to be arranged. Accordingly, an increase in the number of inputs and outputs may be achieved.

[0422] Furthermore, the inner surface (EGS) of the build-up layer (112) may be positioned closer to the center (CA) of the first and second through holes (or cavities (CV)) in the first build-up layer (112a) than in the second build-up layer (112b). This allows for the design of additional circuit patterns in the first build-up layer (112a). Accordingly, the input / output (I / O) count may increase.

[0423] Additionally, from another perspective, the build-up layer (112) may have a cavity (CV) penetrating the build-up layer (112). Furthermore, the cavity (CV) may have a maximum area, region, or diameter (r1) at the lower portion. In other words, the area of ​​the cavity (CV) may be maximum at the lower portion in a plane perpendicular to the stacking direction by the aforementioned inlet portion (G). In an embodiment, the area of ​​the cavity (CV) may be largest at the lowermost portion of the inner surface of the cavity (CV).

[0424] Referring further to Fig. 36, the cavity (CV) may be located on the inner side of the edge portion (EG) and may be surrounded by the edge portion (EG). Furthermore, the inlet portion (G) may have a structure that extends or protrudes outwardly from the inner side (EGS) of the edge portion (EG) or toward the edge portion (EG). In particular, in order to improve the cleaning effect for the first insulating layer and the first core wiring portion exposed by the cavity (CV), the inlet portion (G) may have a structure that further extends outwardly toward the first insulating layer. That is, the distance of the inlet portion (G) from the center (CA) of the cavity (CV) may increase as it goes downward. This will be described later.

[0425] The cavity (CV) can have various shapes depending on the shape of the semiconductor device or chip mounted inside. For example, the shape of the semiconductor device or chip can generally be rectangular with respect to the plane perpendicular to the stacking direction. Correspondingly, the cavity (CV) can also have a rectangular shape with respect to the plane perpendicular to the stacking direction.

[0426] A portion (111E) of the first insulating layer may be exposed by the second through hole (CV2) (or cavity (CV)). A portion (121E) of the first core wiring portion (121a) may be exposed by the second through hole (CV2) (or cavity (CV)). The lead-in portion (G) may be formed along an edge of the second through hole (or cavity (CV)). For example, the lead-in portion (G) may be arranged continuously or discontinuously along the inner surface (EGS) of the cavity (CV). The lead-in portion (G) may have a curvature in an area where adjacent edges meet. In an embodiment, the lead-in portion (G2) or the second through hole (CV2) may have a curved outer surface. That is, the outer surface of the second through hole (CV2) may have a curvature. Accordingly, during desmear or washing, the locking of the cleaning agent may not be concentrated in certain areas. Therefore, washing can be performed evenly.

[0427] In addition, a build-up electrode portion may be positioned on the upper portion of the lead portion (G) as illustrated. For example, a part (122V) of the build-up wiring portion (122a) may be positioned on the upper portion of the lead portion (G). Accordingly, the build-up wiring portion (122a) (or the build-up electrode portion) and the lead portion (G) may overlap at least partially in the stacking direction. Accordingly, despite the formation of the lead portion (G), a space in which a plurality of circuit patterns or pads can be arranged within the build-up layer (112) can be easily secured. Accordingly, an increase in the input / output (I / O) count can be facilitated.

[0428] As a variation, referring further to FIG. 37, the lead-in portion (G) may not overlap with the build-up electrode portion (122) in the stacking direction. That is, the lead-in portion (G) may be spaced apart from the build-up electrode portion (122) in a direction perpendicular to the stacking direction. For example, the lead-in portion (G) may not overlap with the build-up wiring portion (122a) in the stacking direction. By this configuration, a spaced area between the build-up electrode portion (122) and the cavity (CV) can be secured. Therefore, exposure of the build-up electrode portion (122) by the cavity can be easily prevented, thereby improving the electrical reliability of the circuit board.

[0429] As a variation, the circuit board may include a cavity (CV) penetrating the build-up layer (112) and partially penetrating the core layer (111). Accordingly, the cavity (CV) may be located inside the core layer (111) and the build-up layer (112). In this variation, the lead-in portion (G) may also be located in the second insulating layer (1112) and / or the core layer (111) corresponding to the position of the cavity (CV). Depending on the position, the lead-in portion (G) may be located in the first insulating layer, or in the first and second insulating layers. Accordingly, the lead-in portion (G) may overlap the first insulating layer in a direction perpendicular to the lamination direction. In addition, the lead-in portion (G) may overlap the first and second insulating layers in a direction perpendicular to the lamination direction.

[0430] The core electrode portion may be exposed by the cavity (CV). In particular, the first core wiring portion may be exposed by the cavity. In addition, a portion of the core via electrode may also be exposed by the cavity. In this case, the filling material (or filling layer) filled by the underfill may be in contact with both the first core wiring portion and the core via electrode.

[0431] Figures 38 to 40 are flowcharts for a method of manufacturing a circuit board according to the fourth embodiment.

[0432] Referring to Fig. 38, a copper-clad laminate having copper foil on both sides including a core layer (111) is prepared. Then, a via hole or via holes can be formed in the core layer (111). The via holes can be formed by a method such as a laser drilling method, a punching method, or an etching method.

[0433] And a core via electrode can be formed within the first via hole. Afterwards, a first core wiring portion can be formed on the upper portion of the core layer (111) through patterning.

[0434] And a build-up layer (112) can be laminated on both sides of the core layer (111). And a via hole can be formed for the second insulating layer and a second through-electrode can be formed. However, one area of ​​the build-up layer (112) can be formed only of the insulating layer without a build-up electrode portion. This area can correspond to the area of ​​the cavity described above.

[0435] Each circuit pattern layer can be formed by a manufacturing process of a printed circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP).

[0436] Furthermore, the pattern can be formed by a dry film or the like.

[0437] Referring to FIG. 39, a cavity (CV) may be formed on the inside of the build-up layer (112) in the above-described area by a laser method, a punching method, an etching method, or the like. The cavity (CV) may penetrate the central area of ​​the build-up layer (112). The cavity (CV) may be surrounded by a build-up electrode portion. A portion of the core layer (111) and the core electrode portion (121) may be exposed by the cavity (CV).

[0438] Referring to Fig. 40, an inlet portion (G) may be further formed on the lower portion of the inner surface (side surface of the cavity (CV)) of the edge portion exposed by the cavity (CV). That is, the inlet portion (G) may correspond to an undercut in which a portion of the inner surface of the build-up layer (112) is removed. A portion of the first insulating layer may be further exposed by this inlet portion (G).

[0439] Afterwards, clearing can be performed within the cavity (CV) using a desmear treatment. The desmear treatment can be performed using a cleaning agent to smear the remaining insulating layer, circuit pattern layer, etc. For example, the desmear treatment can be performed using a cleaning agent or a desmear chemical. The cleaning agent can include NMP, H2SO4, NaMnO4, etc. However, the present invention is not limited to these materials.

[0440] According to an embodiment, the bonding strength of a device mounted within a cavity is improved by the introduction portion (G), and cleaning can be facilitated. As a result, the electrical reliability of the exposed first core wiring portion electrically connected to the semiconductor device or chip can be improved. In addition, the flatness of the surface of the area where the semiconductor device or chip is settled can be easily secured by the eddy current of the cleaning material by the introduction portion (G), and the insulation layer can be protected. Furthermore, the inner surface of the second insulation layer, etc. can be additionally roughened by the desmear to improve the adhesion.

[0441] Fig. 41 is a drawing of a circuit board according to the fifth embodiment, and Fig. 42 is an enlarged view of a portion of Fig. 41.

[0442] Referring to FIGS. 41 and 42, a circuit board (100D) according to the fifth embodiment may include an insulating layer (110) and an electrode portion (120). Except for the contents described below, the above-described contents may be equally applied.

[0443] The build-up layer (112) may include a cavity (CV).

[0444] The edge portion (EG) may be a distance (W5) from the center (CA) of the first through hole (or cavity (CV)) in the first build-up layer (112a) greater than or less than the distance (W6) from the center (CA) of the second through hole (or cavity) in the second build-up layer (112b).

[0445] More specifically, according to an embodiment, the edge portion (EG) may increase in a distance (W5) from the center (CA) of the cavity (CV) in the first build-up layer (112a) along the stacking direction or in the opposite direction toward the first build-up layer. For example, the edge portion (EG) may have a smaller distance from the center (CA) of the second through hole (or cavity (CV)) at one end adjacent to the first insulating layer among both ends in the second build-up layer (112b) than at the other end. In other words, the inner surface (EGS) of the edge portion (EG) may be arranged to be inclined in the first build-up layer (112a).

[0446] In addition, the edge portion (EG) may have a distance (W6) that decreases along the stacking direction from the center (CA) of the second through hole (or cavity (CV)) in the second build-up layer (112b). For example, the edge portion (EG) may have a greater distance from the center (CA) of the cavity (CV) at one end adjacent to the first insulating layer among both ends of the edge portion (EG) in the second build-up layer (112b) than at the other end. However, the present invention is not limited to this shape, and the inner surface (EGS) of the edge portion (EG) in the second build-up layer (112b) may have the same or similar distance from the center (CA) along the stacking direction.

[0447] Furthermore, as described above, the inner surface (EGS) of the first build-up layer (112a) may have a structure that is not parallel to the central axis, but rather inclined with respect to the central axis. With this configuration, processing using a laser or the like can be easily performed when forming the cavity (CV). Furthermore, the distance between the build-up electrode portion of the second insulating layer and the semiconductor element or chip (electrical element) mounted within the cavity (CV) can be easily secured.

[0448] The edge portion (EG) may decrease in distance from the center (CA) of the second through-hole (or cavity (CV)) in the second build-up layer (112b) along the stacking direction or the opposite direction toward the first insulating layer. For example, the edge portion (EG) may have a shorter distance from the center (CA) of the cavity (CV) at one end of the second build-up layer (112b) adjacent to the first insulating layer than at the other end. In addition, the edge portion (EG) may decrease in distance from the center (CA) of the second through-hole (or cavity (CV)) in the second build-up layer (112b) along the stacking direction. By this configuration, the locking of the cleaning material can be performed more effectively during desmearing.

[0449] Fig. 43 is a drawing of a circuit board according to the sixth embodiment, and Fig. 44 is an enlarged view of a portion of Fig. 43.

[0450] Referring to FIGS. 43 and 44, a circuit board (100E) according to the sixth embodiment may include an insulating layer (110) and an electrode portion (120). Except for the contents described below, the above-described contents may be equally applied.

[0451] The build-up layer (112) may include a dummy layer (DE) disposed therein. The dummy layer (DE) corresponds to the circuit pattern layer, but may be a dummy electrode. That is, the dummy layer (DE) may not be electrically connected.

[0452] In addition, the dummy layer (DE) may be positioned corresponding to the inlet portion (G). Accordingly, the dummy layer (DE) may be positioned within the second build-up layer (112b). Additionally, the dummy layer (DE) may be positioned outside the cavity (CV). Accordingly, the dummy layer (DE) may not overlap with the cavity (CV) in the lamination direction. Additionally, the dummy layer (DE) may surround the cavity (CV).

[0453] In addition, the dummy layer (DE) may be positioned on the outside of the lead-in portion (G). Therefore, the dummy layer (DE) may surround the outside of the lead-in portion (G). Furthermore, the dummy layer (DE) may be arranged along the edge of the lead-in portion (G) and may have a closed-loop or open-loop shape in a plane (a plane perpendicular to the stacking direction). A portion of the dummy layer (DE) may be exposed by the lead-in portion (G). Therefore, the dummy layer (DE) may simultaneously perform the functions of protecting the inner surface of the second insulating layer and performing stop etching. The electrical reliability of the circuit board may be improved by the dummy layer (DE).

[0454] The dummy layer (DE) may overlap at least partly with the build-up electrode portion in the stacking direction. However, as described above, the dummy layer (DE) may be spaced apart from the build-up electrode portion as a dummy electrode.

[0455] Additionally, the dummy layer (DE) may be formed to correspond to the shape of the inner surface of the inlet portion. Furthermore, the dummy layer (DE) may have a different shape from the inner surface of the inlet portion (G). Accordingly, a portion of the dummy layer (DE) may be exposed by the inlet portion (G).

[0456] Additionally, the dummy layer (DE) may partially overlap (OV1) the build-up electrode portion in the stacking direction. However, since the dummy layer (DE) is a dummy electrode, the dummy layer (DE) may be spaced apart from the build-up electrode portion for electrical insulation.

[0457] As a variation, the dummy layer (DE) may be positioned on the core layer (111). For example, the dummy layer (DE) may be positioned on the upper surface of the core layer (111) such as the first core wiring portion. For example, the dummy layer (DE) may correspond to a pad or trace disposed on the upper surface of the core layer (111). However, even in this case, the dummy layer (DE) may be disposed adjacent to the lead-in portion (G). Furthermore, the dummy layer (DE) may not be electrically connected to the pad or electrode portion of the outer stacking region. In addition, the dummy layer (DE) may at least partially overlap the lead-in portion (G) in a direction perpendicular to the stacking direction. As such, the role of stop etching can be performed as described above. Furthermore, even if the dummy layer (DE) is exposed by the lead-in portion (G), a deterioration in electrical reliability can be prevented.

[0458] Fig. 45 is a cross-sectional view showing a semiconductor package according to the first embodiment, Fig. 46 is a cross-sectional view showing a semiconductor package according to the second embodiment, and Fig. 47 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0459] In the various semiconductor packages described below, the circuit board described above may be located in some area or may correspond to one substrate.

[0460] Referring to FIG. 45, the semiconductor package of the first embodiment may include a second substrate (1200) and a semiconductor element (1300).

[0461] Furthermore, the semiconductor package may further include a first substrate and a connecting member (1210) described below.

[0462] The first substrate may mean or include a 'package substrate' or a 'circuit substrate'. The first substrate may be omitted. For example, the first substrate may provide a space to which at least one external substrate is coupled. The external substrate may mean a second substrate (1200) coupled on the first substrate. In addition, the external substrate may mean a main board included in an electronic device coupled to a lower portion of the first substrate.

[0463] Additionally, although not shown in the drawing, the first substrate may provide a space in which at least one semiconductor element is mounted.

[0464] The first substrate may include at least one build-up insulating portion and an electrode portion disposed on the at least one build-up insulating portion.

[0465] A second substrate (1200) can be placed on the first substrate.

[0466] The second substrate (1200) may be an interposer. For example, the second substrate (1200) may provide a space in which at least one semiconductor element is mounted. The second substrate (1200) may be connected to at least one semiconductor element (1300). For example, the second substrate (1200) may provide a space in which a first semiconductor element (1310) and a second semiconductor element (1320) are mounted. The second substrate (1200) may electrically connect the first semiconductor element (1310) and the second semiconductor element (1320), and electrically connect the first and second semiconductor elements (1310, 1320) and the first substrate. That is, the second substrate (1200) may perform a horizontal connection function between a plurality of semiconductor elements and a vertical connection function between the semiconductor element and the package substrate.

[0467] In addition, although the above-described example illustrates two semiconductor elements (1310, 1320) being arranged on the second substrate (1200), the present invention is not limited thereto. For example, one semiconductor element may be arranged on the second substrate (1200), or alternatively, three or more semiconductor elements may be arranged.

[0468] A second substrate (1200) may be placed between at least one semiconductor element (1300) and the first substrate.

[0469] In one embodiment, the second substrate (1200) may be an active interposer that functions as a semiconductor device. When the second substrate (1200) functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first substrate and may function as a plurality of logic chips. Having the function of a logic chip may mean having the functions of an active device and a passive device. Unlike passive devices, the characteristics of current and voltage may not be linear in the case of an active device, and the active interposer may have the function of an active device. In addition, the active interposer may perform the function of a corresponding logic chip while performing a signal transmission function between the second logic chip disposed thereon and the first substrate.

[0470] In another embodiment, the second substrate (1200) may be a passive interposer. For example, the second substrate (1200) may function as a signal relay between the semiconductor element (1300) and the first substrate, and may have passive element functions such as a resistor, a capacitor, and an inductor. For example, the number of terminals in the semiconductor element (1300) is gradually increasing due to reasons such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed. That is, the number of terminals provided in the semiconductor element (1300) is increasing, and accordingly, the width of the terminals or the spacing between the plurality of terminals is decreasing. At this time, the first substrate may be connected to the main board of the electronic device. Accordingly, in order for the electrodes provided in the first substrate to have a width and spacing for being connected to the semiconductor element (1300) and the main board, there is a problem that the thickness of the first substrate increases or the layer structure of the first substrate becomes complicated. Accordingly, the first embodiment can place a second substrate (1200) on the first substrate and the semiconductor element (1300). And the second substrate (1200) can include electrodes having a microscopic width and spacing corresponding to the terminals of the semiconductor element (1300).

[0471] The semiconductor device (1300) may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. The memory chip may be a stack memory such as HBM.

[0472] Meanwhile, the semiconductor package of the first embodiment may include a connecting portion.

[0473] For example, a semiconductor package may include a first connector (1410) positioned between a first substrate and a second substrate (1200). The first connector (1410) may electrically connect the second substrate (1200) to the first substrate while bonding them therebetween.

[0474] For example, the semiconductor package may include a second connection portion (1420) disposed between a second substrate (1200) and a semiconductor element (1300). The second connection portion (1420) may electrically connect the semiconductor element (1300) while bonding them to the second substrate (1200).

[0475] The semiconductor package may include a third connector (1430) disposed on the lower surface of the first substrate. The third connector (1430) may electrically connect the first substrate to the main board while connecting them therebetween.

[0476] At this time, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can electrically connect the plurality of components using at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) have the function of electrically connecting the plurality of components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as a part that is electrically connected rather than solder or wire.

[0477] The wire bonding method may refer to electrically connecting a plurality of components using a conductor such as gold (Au). In addition, the solder bonding method may electrically connect a plurality of components using a material including at least one of Sn, Ag, and Cu. In addition, the direct metal-to-metal bonding method may refer to directly bonding a plurality of components by applying heat and pressure between the plurality of components to recrystallize them without the use of solder, wires, conductive adhesives, etc. In addition, the direct metal bonding method may refer to a bonding method using a second connection portion (1420). In this case, the second connection portion (1420) may refer to a solder layer formed between the plurality of components by recrystallization.

[0478] Specifically, the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) can be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the plurality of components by applying heat and pressure to the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430).

[0479] At this time, in at least one of the first substrate and the second substrate (1200), the electrodes on which the first connection portion (1410), the second connection portion (1420), and the third connection portion (1430) are arranged may be provided with a protrusion that protrudes outward away from the build-up insulation portion of the corresponding substrate. The protrusion may protrude outward from the first substrate or the second substrate (1200).

[0480] The protrusion may be referred to as a bump. The protrusion may also be referred to as a post. The protrusion may also be referred to as a pillar. Preferably, the protrusion may refer to an electrode on which a second connection portion (1420) for coupling with a semiconductor element (1300) is arranged among the electrodes of the second substrate (1200). That is, as the pitch of the terminals of the semiconductor element (1300) becomes finer, a short circuit may occur between the plurality of second connection portions (1420) that are respectively connected to the plurality of terminals of the semiconductor element (1300) by a conductive adhesive such as solder. Therefore, in the embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portion (1420). Accordingly, the embodiment may include a protrusion in the electrode of the second substrate (1200) on which the second connecting portion (1420) is arranged to secure a degree of alignment, diffusion, and diffusion-preventing ability to prevent an intermetallic compound (IMC) formed between a conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the substrate.

[0481] Furthermore, the semiconductor package of the first embodiment may further include a connecting member (1210).

[0482] The connecting member (1210) may be referred to as a bridge substrate. For example, the connecting member (1210) may include a redistribution layer. The connecting member (1210) may have a function of horizontally electrically connecting a plurality of semiconductor devices to each other. For example, since the area that a semiconductor device should have is generally too large, the connecting member (1210) may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width or width of the circuit pattern, etc., a buffering function of the circuit pattern for electrical connection is required. The buffering function may mean having a size between the width or width of the circuit pattern of the semiconductor package and the width or width of the circuit pattern of the semiconductor device, and the redistribution layer may have a function of performing a buffering function.

[0483] In an embodiment, the connecting member (1210) may be an organic bridge. For example, the connecting member (1210) may include an organic material. For example, the connecting member (1210) may include an organic substrate instead of a silicon substrate. The connecting member (1210) may be embedded within the second substrate (1200).

[0484] To this end, the second substrate (1200) may include a through hole, and the connecting member (1210) may be placed within the through hole of the second substrate (1200). The connecting member (1210) may horizontally connect a plurality of semiconductor elements placed on the second substrate (1200).

[0485] The semiconductor package of the first embodiment may include a second substrate (1200) and a semiconductor element (1300). In this case, the semiconductor package of the first embodiment may have a structure in which the first substrate is omitted compared to the semiconductor package of the first embodiment.

[0486] That is, the second substrate (1200) of the first embodiment can function as a package substrate while also functioning as an interposer.

[0487] The first connecting portion (1410) arranged on the lower surface of the second substrate (1200) can connect the second substrate (1200) to the main board of the electronic device.

[0488] Referring to FIG. 46, the semiconductor package of the second embodiment may include a first substrate (1100) and a semiconductor element (1300).

[0489] At this time, the semiconductor package of the second embodiment may have a structure in which the second substrate (1200) is omitted compared to the semiconductor package of the first embodiment.

[0490] That is, the first substrate (1100) of the second embodiment can function as a package substrate while also connecting the semiconductor elements (1300) and the main board. To this end, the first substrate (1100) can include a connecting member (1110) for connecting between a plurality of semiconductor elements. The connecting member (1110) can be an organic bridge connecting between a plurality of semiconductor elements.

[0491] Referring to FIG. 47, the semiconductor package of the third embodiment may further include a third semiconductor element (1330) compared to the semiconductor package of the third embodiment. To this end, a fourth connecting portion may be further arranged on one surface of the first substrate (1100).

[0492] In this way, the semiconductor package of the third embodiment may have a structure in which semiconductor elements are mounted on the upper and lower sides, respectively. In this case, the third semiconductor element (1330) may have a structure in which it is placed on the lower surface of the second substrate (1200) in the aforementioned circuit board or semiconductor package.

[0493] And a connecting member (1110) can be embedded in the first substrate (1100). The connecting member (1110) can horizontally connect the first and second semiconductor elements (1310, 1320).

[0494] Additionally, the first substrate (1100) may include a conductive coupling portion (1450). The conductive coupling portion (1450) may further protrude from the first substrate (1100) toward the second semiconductor element (1320). The conductive coupling portion (1450) may be referred to as a bump, or alternatively, as a post. The conductive coupling portion (1450) may be positioned with a protruding structure on an electrode positioned on the uppermost side of the first substrate (1100).

[0495] A third semiconductor element (1330) may be placed on the conductive joint (1450). At this time, the third semiconductor element (1330) may be connected to the first substrate (1100) through the conductive joint (1450). In addition, a second connection (1420) may be placed between the first and second semiconductor elements (1310, 1320) and the third semiconductor element (1330).

[0496] Accordingly, the third semiconductor element (1330) can be electrically connected to the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0497] That is, the third semiconductor element (1330) can be connected to the first substrate (1100) through the conductive joint (1450), and can also be connected to the first and second semiconductor elements (1310, 1320) through the second connection (1420).

[0498] At this time, the third semiconductor element (1330) can receive a power signal and / or electric power through the conductive coupling portion (1450). In addition, the third semiconductor element (1330) can exchange communication signals with the first and second semiconductor elements (1310, 1320) through the second connection portion (1420).

[0499] The semiconductor package of the third embodiment can provide sufficient power for driving the third semiconductor element (1330) or enable smooth control of power operation by supplying a power signal and / or power to the third semiconductor element (1330) through the conductive joint (1450).

[0500] Accordingly, the embodiment can improve the driving characteristics of the third semiconductor element (1330). That is, the embodiment can solve the problem of insufficient power provided to the third semiconductor element (1330). Furthermore, the embodiment can provide at least one of the power signal, power, and communication signal of the third semiconductor element (1330) through different paths via the conductive coupling portion (1450) and the second connection portion (1420). Through this, the embodiment can solve the problem of loss of the communication signal caused by the power signal. For example, the embodiment can minimize mutual interference between the power signal and the communication signal.

[0501] Meanwhile, the third semiconductor element (1330) in the third embodiment may have a POP (Package On Package) structure in which a plurality of package substrates are stacked and may be placed on the first substrate (1100). For example, the third semiconductor element (1330) may be a memory package including a memory chip. And the memory package may be coupled on the conductive joint (1450). At this time, the memory package may not be connected to the first and second semiconductor elements (1310, 1320).

[0502] Furthermore, the semiconductor package of the modified example may include the first substrate (1100) and first and second semiconductor elements (1310, 1320) arranged on the first substrate (1100) as in the above-described example. Furthermore, the semiconductor package may include a first connection portion (1410) arranged between the first substrate (1100) and the first and second semiconductor elements (1310, 1320). That is, the semiconductor package may have a structure in which the second substrate and the second connection portion are omitted in the above-described example.

[0503] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0504] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0505] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0506] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. Core layer including through holes; and including a connecting member arranged inside the through hole of the core layer; The inner wall surface of the core layer forming the through hole includes a step portion, The above connecting member is a circuit board arranged on the step portion.

2. In paragraph 1, Further comprising an upper build-up layer disposed on the upper portion of the core layer and within the through hole; A circuit board comprising a core layer and a first resin material and a second resin material asymmetrically arranged with respect to the core material.

3. In paragraph 2, A circuit board including a first region disposed below the connecting member, and a second region located above the first region and at least partially overlapping the connecting member in a horizontal direction, wherein the through hole is a first region disposed below the connecting member, and a second region located above the first region and at least partially overlapping the connecting member in a horizontal direction.

4. In paragraph 2, A circuit board wherein the thickness of the first resin material is smaller than the thickness of the second resin material.

5. In paragraph 3, A circuit board in which the first resin material and the core material overlap horizontally with the second region.

6. In paragraph 3, A circuit board in which a portion of the second resin material overlaps horizontally with the second region.

7. In paragraph 3, A circuit board in which the second resin material has a thickness in an area that horizontally overlaps the second area, and is smaller than a thickness in an area that horizontally overlaps the first area.

8. In paragraph 3, A circuit board in which the first region overlaps the second resin material in a horizontal direction.

9. In paragraph 3, A circuit board wherein the width of the first region is smaller than the width of the connecting member.

10. In paragraph 3, A circuit board wherein the step portion is positioned between the first region and the second region.

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