Radio frequency front-end bus optimization in a power management circuit

Abstract

Radio frequency front-end (RFFE) bus optimization in a power management circuit is provided. Herein, an RFFE bus circuit is optiized to provide an RFFE standard-compliant mechanism for cancelling a timer(s) configured to fire an event trigger(s). As a result, it is possible to provide the optimized RFFE bus circuit in a power management circuit to configure and control multiple timers according to various operating scenarios.

Description

RADIO FREQUENCY FRONT-END BUS OPTIMIZATION IN A POWER MANAGEMENT CIRCUITRelated Applications

[0001] This application claims the benefit of U.S. provisional patent application serial number 63 / 570,882, filed on March 28, 2024, and U.S. provisional patent application serial number 63 / 651 ,189, filed on May 23, 2024, the disclosures of which are hereby incorporated herein by reference in their entireties.Field of the Disclosure

[0002] The technology of the disclosure relates generally to optimizing a radio frequency frontend (RFFE) bus for usage in a power management circuit.Background

[0003] Mobile communication devices have become increasingly common in current society. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

[0004] The redefined user experience requires higher data rates offered by wireless communication technologies, such as Wi-Fi, long-term evolution (LTE), and fifth-generation new-radio (5G-NR). To achieve the higher data rates in mobile communication devices, sophisticated power amplifiers may be employed to increase output power of radio frequency (RF) signals (e.g., maintaining sufficient energy per bit) communicated by mobile communication devices.

[0005] Figure 1 is a schematic diagram of an exemplary power management circuit 10 wherein a power amplifier circuit 12 is configured to amplify an RF signal 14 based on a voltage Vcc supplied by a power management integrated circuit (PMIC) 16. The power management circuit 10 includes a transceiver circuit 18. The transceiver circuit 18 is configured to generate the RF signal 14and a target voltage VTGT that tracks time-variant power of the RF signal 14. The PMIC 16, in turn, generates the voltage Vcc in accordance with the target voltage VTGT such that the voltage Vcc can follow the time-variant power of the RF signal 14 to thereby help the power amplifier circuit 12 achieve better efficiency and linearity.

[0006] The transceiver circuit 18 can be configured to provide the target voltage VTGT and other parameters to the PMIC 16 via a radio frequency frontend (RFFE) bus 20, with the transceiver circuit 18 functioning as a main circuit (a.k.a. master) and the PMIC 16 functioning as a subordinate circuit (a.k.a. slave). The RFFE 20, as defined by the MIPI® alliance RFFE specification, can support a standard event trigger mechanism whereby the transceiver circuit 18 can configure a timer in the PMIC 16 for firing a specific event (e.g., changing the voltage Vcc from one level to another). However, the RFFE specification does not provide a method to cancel the timer once the timer is defined. In this regard, it is desirable to enhance the standard event trigger mechanism such that the transceiver circuit 18 can cancel the timer via the RFFE bus 20.

[0007] Aspects disclosed in the detailed description include radio frequency front-end (RFFE) bus optimization in a power management circuit. Herein, an RFFE bus circuit is optimized to provide an RFFE standard-compliant mechanism for cancelling a timer(s) configured to fire an event trigger(s). As a result, it is possible to provide the optimized RFFE bus circuit in a power management circuit to configure and control multiple timers according to various operating scenarios.

[0008] In one aspect, an RFFE bus circuit is provided. The RFFE bus circuit includes an RFFE bus. The RFFE bus is coupled to a main circuit. The RFFE bus circuit also includes multiple subordinate circuits. Each of the multiple subordinate circuits is coupled to the RFFE bus. Each of the multiple subordinate circuits is configured to receive a respective one of multiple timer setup telegrams including a respective one of multiple timer values. Each of themultiple subordinate circuits is also configured to receive a respective one of multiple high-level command (HLC) telegrams each including multiple data bytes. Each of the multiple subordinate circuits is also configured to initiate a respective timer to the respective one of the multiple timer values at a start of a first one of the multiple data bytes in the respective one of the multiple HLC telegrams. Each of the multiple subordinate circuits is also configured to receive a timer control flag in one of the multiple data bytes comprised in the respective one of the multiple HLC telegrams. Each of the multiple subordinate circuits is also configured to stop the respective timer immediately when the timer control flag is set to a false value.

[0009] In another aspect, a wireless device is provided. The wireless device includes a transceiver circuit and an RFFE bus coupled to the transceiver circuit. The wireless device also includes a PMIC. The PMIC includes a tracker circuit and a voltage circuit. Each of the tracker circuit and the voltage circuit is coupled to the RFFE bus. Each of the tracker circuit and the voltage circuit is configured to receive a respective one of multiple timer setup telegrams including a respective one of multiple timer values. Each of the tracker circuit and the voltage circuit is also configured to receive a respective one of multiple HLC telegrams each including multiple data bytes. Each of the tracker circuit and the voltage circuit is also configured to initiate a respective timer to the respective one of the multiple timer values at a start of a first one of the multiple data bytes in the respective one of the multiple HLC telegrams. Each of the tracker circuit and the voltage circuit is also configured to receive a timer control flag in one of the multiple data bytes comprised in the respective one of the multiple HLC telegrams. Each of the tracker circuit and the voltage circuit is also configured to stop the respective timer immediately when the timer control flag is set to a false value.

[0010] In another aspect, a method for optimizing an RFFE bus is provided. The method includes receiving a respective one of multiple timer setup telegrams comprising a respective one of multiple timer values. The method also includes receiving a respective one of multiple HLC telegrams each comprising multipledata bytes. The method also includes initiating a respective timer to the respective one of the multiple timer values at a start of a first one of the multiple data bytes in the respective one of the multiple HLC telegrams. The method also includes receiving a timer control flag in one of the multiple data bytes comprised in the respective one of the multiple HLC telegrams. The method also includes stopping the respective timer immediately when the timer control flag is set to a false value.

[0011] Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings.Brief Description of the Drawings

[0012] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0013] Figure 1 is a schematic diagram of an exemplary existing power management circuit wherein a transceiver circuit communicates with a power management integrated circuit (PMIC) based on a radio frequency front-end (RFFE) bus structure as defined by the Ml PI® alliance;

[0014] Figure 2 is a schematic diagram of an exemplary RFFE bus circuit that can be optimized according to embodiments of the present disclosure;

[0015] Figure 3 is a schematic diagram illustrating an optimized event trigger scheme in the RFFE bus circuit of Figure 2;

[0016] Figure 4 is a schematic diagram of an exemplary power management circuit configured to support the optimized event trigger scheme of Figure 3;

[0017] Figure 5 is a schematic diagram providing an exemplary illustration as to how the power management circuit of Figure 4 can support the optimized event trigger scheme of Figure 3;

[0018] Figures 6A and 6B are schematic diagrams illustrating exemplary operating scenarios of the power management circuit of Figure 4 based on the optimized event trigger scheme of Figure 3;

[0019] Figure 7 is a schematic diagram of an exemplary communication device wherein the power management circuit of Figure 4 can be provided; and

[0020] Figure 8 is a flowchart of an exemplary process for optimizing the RFFE bus circuit of Figure 2.Detailed Description

[0021] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0022] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directlyover" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0024] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0027] Aspects disclosed in the detailed description include radio frequency front-end (RFFE) bus optimization in a power management circuit. Herein, an RFFE bus circuit is optimized to provide an RFFE standard-compliantmechanism for cancelling a timer(s) configured to fire an event trigger(s). As a result, it is possible to provide the optimized RFFE bus circuit in a power management circuit to configure and control multiple timers according to various operating scenarios.

[0028] Figure 2 is a schematic diagram of an exemplary RFFE bus circuit 22 that can be optimized according to embodiments of the present disclosure. The RFFE bus circuit 22 includes a main circuit 24 and multiple subordinate circuits 26(1 )-26(N). The main circuit 24 is coupled to the subordinate circuits 26(1 )- 26(N) via an RFFE bus 28, which is a two-wire serial bus that includes a data line 30 and a clock line 32 for communicating a bidirectional data signal SDATA and a clock signal SCLK, respectively.

[0029] Each of the subordinate circuits 26(1 )-26(N) includes a respective one of multiple register banks REGMAP-1 -REGMAP-N. In a non-limiting example, each of the register banks REGMAP-1 -REGMAP-N can include up to two hundred fifty-six (256) 8-bit registers labeled as REG

[0000] -REG

[0255] . Using the register banks REGMAP-1 -REGMAP-N, the main circuit 24 can set a respective timer to trigger a specific event in each of the subordinate circuits 26(1 )-26(N).

[0030] In an embodiment, the RFFE bus circuit 22 can be configured according to an optimized event trigger scheme to not only provide the main circuit 24 with the ability to coordinate multiple timers among the subordinate circuits 26(1 )-26(N) but also allow the main circuit 24 to selectively cancel any of the timers. As such, the RFFE bus circuit 22 can provide a much-needed enhancement to the standard event trigger mechanism as defined in the RFFE specification.

[0031] Figure 3 is a schematic diagram providing an exemplary illustration of the optimized event trigger scheme in the RFFE bus circuit 22 of Figure 2. Common elements between Figures 2 and 3 are shown therein with common element numbers and will not be re-described herein. For the sake of simplicity, the optimized event trigger scheme is illustrated herein based on the subordinate circuits 26(1 ) and 26(2). Understandably, the operating principles of theoptimized event trigger scheme illustrated herein can be applicable to an additional number of the subordinate circuits 26(1 )-26(N).

[0032] In a non-limiting example, the subordinate circuits 26(1 ) and 26(2) are uniquely identified by universal subordinate identifications (USIDs) “1 1 ” and “12,” respectively. To set up timers in the subordinate circuits 26(1 ) and 26(2), the main circuit 24 first communicates a pair of timer setup telegrams 34, 36 to the subordinate circuits 26(1 ), 26(2), respectively. Notably, the main circuit 24 can only provide the timer setup telegrams 34, 36 sequentially because the RFFE bus 28 is a serial bus.

[0033] The timer setup telegram 34 includes the USID (USID = “1 1 ”) of the subordinate circuit 26(1 ) and a timer value T1 1 . In a non-limiting example, the timer value T1 1 is written into a selected one of the registers REG

[0000] - REG

[0255] (e.g., REG

[0057] ) in the register bank REGMAP-1 . Similarly, the timer setup telegram 36 includes the USID (USID = “12”) of the subordinate circuit 26(2) and a timer value T12. In a non-limiting example, the timer value T12 is written into a selected one of the registers REG

[0000] -REG

[0255] (e.g., REG

[0059] ) in the register bank REGMAP-2.

[0034] After providing the timer setup telegrams 34, 36, the main circuit 24 communicates a pair of high-level command (HLC) telegrams 38, 40 to the subordinate circuits 26(1 ) and 26(2), respectively. Like the timer setup telegrams 34, 36, the main circuit 24 can only provide the HLC telegrams 38, 40 sequentially because the RFFE bus 28 is a serial bus. In an embodiment, the main circuit 24 is configured to communicate the HLC telegrams 38, 40 in an identical sequential order as the timer setup telegrams 34, 36. In other words, since the timer setup telegram 34 is communicated before the timer setup telegram 36, the HLC telegram 38 will likewise be communicated before the HLC telegram 40. Understandably, the main circuit 24 may also communicate the HLC telegrams 38, 40 in a different order from the timer setup telegrams 34, 36.

[0035] In an embodiment, each of the HLC telegrams 38, 40 includes multiple data bytes B0-B3, so encoded to carry multiple high-level configuration commands. Each of the data bytes B0-B3 includes eight binary bits b0-b7.Herein, each of the subordinate circuits 26(1 ) and 26(2) may be configured to initiate a respective timer to the respective timer values T11 and T12 upon receiving the first data byte BO (e.g., upon receiving b7 of the first data byte BO).

[0036] Herein, b7 in the third data byte B2 is designated as a timer control flag whereby the main circuit 24 can cancel the respective timer in the subordinate circuits 26(1 ) and 26(2). More specifically, b7 in the third data byte B2 of the HLC telegram 38 can be used to cancel the respective timer in the subordinate circuit 26(1 ), whereas b7 in the third data byte B2 of the HLC telegram 40 can be used to cancel the respective timer in the subordinate circuit 26(2).

[0037] In an embodiment, the respective timer in the subordinate circuits 26(1 ) and 26(2) will be cancelled immediately (e.g., after b7 in the third data byte B2) when b7 in the third data byte B2 is set to a false value (e.g., binary “0”). Accordingly, each of the subordinate circuits 26(1 ) and 26(2) will fire up respective HLC event triggers HLC1 1 EVT and HLC12EVT immediately upon receiving bO of the fourth data byte B3 in the respective HLC telegrams 38, 40. In other words, when the respective timer in the subordinate circuit 26(1 ) is cancelled, the subordinate circuit 26(1 ) will fire up the HLC event trigger HLC1 1 EVT right after receiving bO in the fourth data byte B3 in the HLC telegram 38. Likewise, when the respective timer in the subordinate circuit 26(2) is cancelled, the subordinate circuit 26(2) will fire up the HLC event trigger HLC12EVT right after receiving bO in the fourth data byte B3 in the HLC telegram 40.

[0038] In contrast, the respective timer in the subordinate circuits 26(1 ) and 26(2) will be kept alive when b7 in the third data byte B2 is set to a true value (e.g., binary “1 ”). Accordingly, each of the subordinate circuits 26(1 ) and 26(2) will fire up the respective HLC event triggers HLC1 1 EVT and HLC12EVT at an expiration of the respective timer. As an example, the timer value T1 1 for setting up the respective timer in the subordinate circuit 26(1 ) can be so determined to cause the subordinate circuit 26(1 ) to fire up the respective HLC event trigger HLC1 1 EVT anytime during the HLC telegram 40. Thus, by setting the timer value T11 to be equal to an entire duration of the HLC telegram 40, thesubordinate circuits 26(1 ) and 26(2) can fire up the HLC event triggers HLC1 1 EVT and HLC12EVT simultaneously.

[0039] In an alternative embodiment, the timer control flag may be provided in bO in the fourth data byte B3. Accordingly, each of the subordinate circuits 26(1 ) and 26(2) can have more time (e.g., from b7 in the third data byte B2 to bO in the fourth data byte B3) to decide what to do in response to the timer control flag. The corresponding actions of the subordinate circuits 26(1 ) and 26(2) may remain the same as described above with the timer control flag provided in bO in the third data byte B2.

[0040] In an embodiment, the firing of the HLC event trigger HLC1 1 EVT causes the subordinate circuit 26(1 ) to interpret the high-level configuration commands carried in the HLC telegram 38 into specific low-level configuration parameters and store the low-level configuration parameters in predesignated ones of the registers REG

[0000] -REG

[0255] in the respective register bank REGMAP-1 . Accordingly, the subordinate circuit 26(1 ) can carry out a specific action(s) based on the low-level configuration parameters.

[0041] Similarly, the firing of the HLC event trigger HLC12EVT causes the subordinate circuit 26(2) to interpret the high-level configuration commands carried in the HLC telegram 40 into specific low-level configuration parameters and store the low-level configuration parameters in predesignated ones of the registers REG

[0000] -REG

[0255] in the respective register bank REGMAP-2. Accordingly, the subordinate circuit 26(2) can carry out a specific action(s) based on the low-level configuration parameters.

[0042] The RFFE bus circuit 22 can be provided in various electrical circuits to enable serial communications based on the optimized event trigger scheme of Figure 3. In one embodiment, Figure 4 is a schematic diagram of an exemplary power management circuit 42 configured to support the optimized event trigger scheme of Figure 3.

[0043] Herein, the power management circuit 42 includes a transceiver circuit 44 that is configured to function as the main circuit 24 in the RFFE bus circuit 22 of Figure 2. The power management circuit 42 also includes a powermanagement integrated circuit (PMIC) 46 and a distributed PMIC (DPMIC) 48. In an embodiment, the PMIC 46 is configured to supply a voltage Vcc, which can be an envelope tracking (ET) voltage or an average power tracking (APT) voltage, to a power amplifier circuit 50. The DPMIC 48 is configured to supply a distributed voltage VCC-D, which can also be an ET voltage or an APT voltage, to a distributed power amplifier circuit 52. Herein, the PMIC 46 is provided closer to the power amplifier circuit 50 than to the distributed power amplifier circuit 52 to help reduce trace inductance that can potentially distort the voltage Vcc at the power amplifier circuit 50. Likewise, the DPMIC 48 is provided closer to the distributed power amplifier circuit 52 than to the power amplifier circuit 50 to help reduce trace inductance that can potentially distort the distributed voltage VCC-D at the distributed power amplifier circuit 52.

[0044] The PMIC 46 includes a tracker circuit 54 and a voltage circuit 56. The tracker circuit 54 is coupled to a voltage output 58 via a first switch Si and configured to provide a low-frequency current IDC to the voltage output 58 when the first switch Si is closed. The voltage circuit 56, on the other hand, is configured to generate the voltage Vcc at the voltage output 58.

[0045] Herein, each of the tracker circuit 54 and the voltage circuit 56 is configured to function as a respective one of the subordinate circuits 26(1 )-26(N) in the RFFE bus circuit 22 of Figure 2. In a non-limiting example, the tracker circuit 54 and the voltage circuit 56, which are uniquely identified by USIDs “1 1 ” and “12,” respectively, are coupled to the transceiver circuit 44 via a first RFFE bus 60. Like the subordinate circuits 26(1 )-26(N), the tracker circuit 54 includes a respective register bank REGMAP-1 and the voltage circuit 56 includes a respective register bank REGMAP-2. Herein, each of the register banks REGMAP-1 and REGMAP-2 includes multiple registers REG

[0000] -REG

[0255] .

[0046] In a mode of operation, the tracker circuit 54 and the voltage circuit 56 are coupled to the voltage output 58 simultaneously to provide the low-frequency current IDC and the voltage Vcc to the power amplifier circuit 50 at the same time. In this regard, Figure 5 is a schematic diagram providing an exemplary illustration as to how the transceiver circuit 44 can configure the tracker circuit 54 and thevoltage circuit 56 based on the optimized event trigger scheme of Figure 3. Common elements between Figures 3, 4, and 5 are shown therein with common element numbers and will not be re-described herein.

[0047] Herein, the timer setup telegram 34 is addressed to the tracker circuit 54, wherein the timer value T11 is set to a total duration TTOTAL of the HLC telegrams 38 and 40. The timer setup telegram 36 is addressed to the voltage circuit 56, wherein the timer value T12 can be set to any value.

[0048] The HLC telegram 38 is addressed to the tracker circuit 54, wherein the timer control flag in b7 of the third data byte B2 is set to the true value (binary “1 ”). Accordingly, the tracker circuit 54 will initiate the timer at a start (corresponding to b7 of the first data byte BO) of the HLC telegram 38 and fire up the respective HLC event trigger HLC1 1 EVT at the expiration of the timer.

[0049] The HLC telegram 40 is addressed to the voltage circuit 56, wherein the timer control flag in b7 of the third data byte B2 is set to the false value (binary “0”). Accordingly, the voltage circuit 56 will cancel the timer and fire up the respective HLC event trigger HLC12EVT at an end (corresponding bO of the fourth data byte B3) of the HLC telegram 40. Because the timer value T11 is set to the total duration TTOTAL of the HLC telegrams 38 and 40, the HLC event triggers HLC11 EVT and HLC12EVT are thus fired simultaneously.

[0050] In an embodiment, the firing of the HLC event trigger HLC1 1 EVT causes the tracker circuit 54 to derive a set of current generation parameters from the data bytes B0-B3 in the HLC telegram 38 to thereby provide the low- frequency current IDC. The tracker circuit 54 may store the derived current generation parameters in any of the registers REG

[0000] -REG

[0255] in the register bank REGMAP-1 . The firing of the HLC event trigger HLC12EVT, on the other hand, causes the voltage circuit 56 to derive a set of voltage generation parameters from the data bytes B0-B3 in the HLC telegram 40 to thereby generate the voltage Vcc. The voltage circuit 56 may store the derived voltage generation parameters in any of the registers REG

[0000] -REG

[0255] in the register bank REGMAP-2.

[0051] With reference back to Figure 4, the DPMIC 48 includes a distributed tracker circuit 62 and a distributed voltage circuit 64. The distributed tracker circuit 62 is coupled to a distributed voltage output 66 via a second switch S2 and configured to provide a distributed low-frequency current IDC-D to the distributed voltage output 66 when the second switch S2 is closed. The distributed tracker circuit 62 is also coupled to the voltage output 58 via a third switch S3 and configured to provide the distributed low-frequency current IDC-D to the voltage output 58 when the third switch S3 is closed. The distributed voltage circuit 64, on the other hand, is configured to generate the distributed voltage VCC-D at the distributed voltage output 66.

[0052] Herein, each of the distributed tracker circuit 62 and the distributed voltage circuit 64 is configured to function as a respective one of the subordinate circuits 26(1 )-26(N) in the RFFE bus circuit 22 of Figure 2. In a non-limiting example, the distributed tracker circuit 62 and the distributed voltage circuit 64, which are uniquely identified by USIDs “13” and “14,” respectively, are coupled to the transceiver circuit 44 via a second RFFE bus 68. Like the subordinate circuits 26(1 )-26(N), the distributed tracker circuit 62 includes a respective register bank REGMAP-D1 and the distributed voltage circuit 64 includes a respective register bank REGMAP-D2. Herein, each of the register banks REGMAP-D1 and REGMAP-D2 includes multiple registers REG

[0000] -REG

[0255] .

[0053] The transceiver circuit 44 can be further configured to control the distributed tracker circuit 62 and the distributed voltage circuit 64 based on the same optimized event trigger scheme as described above. Moreover, since the first RFFE bus 60 and the second RFFE bus 68 are operating independently of each other, the transceiver circuit 44 can coordinate timer setup telegrams and HLC telegrams communicated over the first RFFE bus 60 and the second RFFE bus 68 to enable more concurrent operating scenarios. Figures 6A and 6B are schematic diagrams illustrating various concurrent operating scenarios in the power management circuit of Figure 4.

[0054] In one example, the third switch S3 can be closed to couple the distributed tracker circuit 62 to the voltage output 58. In this regard, as illustratedin Figure 6A, the voltage circuit 56 and the distributed tracker circuit 62 can be configured according to the optimized event trigger scheme to concurrently fire up the HLC event trigger. In the meantime, the first switch Si and the second switch S2 may remain open.

[0055] In another example, the first switch Si and the third switch S3 can be closed to couple the tracker circuit 54 and the distributed tracker circuit 62 to the voltage output 58 concurrently. In this regard, as illustrated in Figure 6B, the tracker circuit 54, the voltage circuit 56, and the distributed tracker circuit 62 can be configured according to the optimized event trigger scheme to concurrently fire up the HLC event trigger. In the meantime, the second switch S2 may remain open.

[0056] The power management circuit 42 of Figure 4 can be provided in a communication device to support the embodiments described above. In this regard, Figure 7 is a schematic diagram of an exemplary communication device 100 wherein the power management circuit 42 of Figure 4 can be provided.

[0057] Herein, the communication device 100 can be any type of communication device, such as mobile terminal, smart watch, tablet, computer, navigation device, access point, base station (e.g., eNB, gNB), and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, Ultrawideband (UWB), and near field communications. The communication device 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 1 12, and user interface circuitry 1 14. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 1 12 and through the antenna switching circuitry 110 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitizationcircuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0058] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0059] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 1 12 through the antenna switching circuitry 110. The multiple antennas 1 12 and the replicated transmit and receive circuitries 106, 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0060] In an embodiment, the transmit circuitry 106 can be configured to function as the transceiver circuit 44 in Figure 4, whereas the PMIC 46 and the DPMIC 48 can be provided in between the transmit circuitry 106 and the antenna switching circuitry 1 10.

[0061] The RFFE bus circuit 22 of Figure 2 can be optimized based on a process. In this regard, Figure 8 is a flowchart of an exemplary process 200 for optimizing the RFFE bus circuit 22 of Figure 2.

[0062] Herein, the process 200 includes receiving the respective one of the timer setup telegrams 34, 36 including the respective one of the timer values T1 1 , T12 (step 202). The process 200 also includes receiving the respective oneof the HLC telegrams 38, 40 each comprising the data bytes B0-B3 (step 204). The process 200 also includes initiating the respective timer to the respective one of the timer values T1 1 , T12 at the start of the first one of the data bytes (BOBS) in the respective one of the HLC telegrams (38, 40) (step 206). The process 200 also includes receiving the timer control flag in one of the data bytes B0-B3 comprised in the respective one of the of HLC telegrams (38, 40) (step 208). The process 200 also includes stopping the respective timer immediately when the timer control flag is set to the false value “0” (step 210).

[0063] Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

ClaimsWhat is claimed is:1 . A radio frequency frontend (RFFE) bus circuit comprising: an RFFE bus coupled to a main circuit; and a plurality of subordinate circuits each coupled to the RFFE bus and configured to: receive a respective one of a plurality of timer setup telegrams comprising a respective one of a plurality of timer values; receive a respective one of a plurality of high-level command (HLC) telegrams each comprising multiple data bytes; initiate a respective timer to the respective one of the plurality of timer values at a start of a first one of the multiple data bytes in the respective one of the plurality of HLC telegrams; receive a timer control flag in one of the multiple data bytes comprised in the respective one of the plurality of HLC telegrams; and stop the respective timer immediately when the timer control flag is set to a false value.

2. The RFFE bus circuit of claim 1 , wherein the multiple data bytes in each of the plurality of HLC telegrams comprise a first data byte, a second data byte, a third data byte, and a fourth data byte, and the timer control flag is carried in a first bit of the third data byte.

3. The RFFE bus circuit of claim 1 , wherein the multiple data bytes in each of the plurality of HLC telegrams comprise a first data byte, a second data byte, a third data byte, and a fourth data byte, and the timer control flag is carried in a first bit of the fourth data byte.

4. The RFFE bus circuit of claim 1 , wherein each of the plurality of subordinate circuits is further configured to fire a respective HLO event trigger at an end of the respective one of the plurality of HLC telegrams when the timer control flag is set to the false value.

5. The RFFE bus circuit of claim 4, wherein each of the plurality of subordinate circuits is further configured to fire the respective HLC event trigger at an expiration of the respective timer when the timer control flag is set to a true value.

6. The RFFE bus circuit of claim 1 , wherein the main circuit is configured to communicate the plurality of timer setup telegrams before the plurality of HLC telegrams.

7. The RFFE bus circuit of claim 6, wherein the main circuit is further configured to communicate the plurality of HLC telegrams in a same sequential order as the plurality of timer setup telegrams.

8. A wireless device comprising a power management circuit, the power management circuit comprises: a transceiver circuit and a radio frequency frontend (RFFE) bus coupled to the transceiver circuit; and a power management integrated circuit (PMIC) comprising: a tracker circuit and a voltage circuit each coupled to the RFFE bus and configured to: receive a respective one of a plurality of timer setup telegrams comprising a respective one of a plurality of timer values; receive a respective one of a plurality of high-level command (HLC) telegrams each comprising multiple data bytes;initiate a respective timer to the respective one of the plurality of timer values at a start of a first one of the multiple data bytes in the respective one of the plurality of HLC telegrams; receive a timer control flag in one of the multiple data bytes comprised in the respective one of the plurality of HLC telegrams; and stop the respective timer immediately when the timer control flag is set to a false value.

9. The wireless device of claim 8, wherein each of the tracker circuit and the voltage circuit is further configured to fire a respective HLC event trigger at an end of the respective one of the plurality of HLC telegrams when the timer control flag is set to the false value.

10. The wireless device of claim 9, wherein each of the tracker circuit and the voltage circuit is further configured to fire the respective HLC event trigger at an expiration of the respective timer when the timer control flag is set to a true value.1 1 . The wireless device of claim 10, wherein: the tracker circuit is configured to: derive a set of current generation parameters from the respective one of the plurality of HLC telegrams when the respective HLC event trigger is fired; and generate a low-frequency current based on the set of current generation parameters; and the voltage circuit is configured to: derive a set of voltage modulation parameters from the respective one of the plurality of HLC telegrams when the respective HLC event trigger is fired; andgenerate a voltage based on the set of voltage modulation parameters.

12. The wireless device of claim 8, wherein the transceiver circuit is configured to communicate the plurality of timer setup telegrams before the plurality of HLC telegrams.

13. The wireless device of claim 12, wherein the transceiver circuit is further configured to communicate the plurality of HLC telegrams in a same sequential order as the plurality of timer setup telegrams.

14. A method for optimizing a radio frequency frontend (RFFE) bus comprising: receiving a respective one of a plurality of timer setup telegrams comprising a respective one of a plurality of timer values; receiving a respective one of a plurality of high-level command (HLC) telegrams each comprising multiple data bytes; initiating a respective timer to the respective one of the plurality of timer values at a start of a first one of the multiple data bytes in the respective one of the plurality of HLC telegrams; receiving a timer control flag in one of the multiple data bytes comprised in the respective one of the plurality of HLC telegrams; and stopping the respective timer immediately when the timer control flag is set to a false value.

15. The method of claim 14, wherein the multiple data bytes in each of the plurality of HLC telegrams comprise a first data byte, a second data byte, a third data byte, and a fourth data byte, and the timer control flag is carried in a first bit of the third data byte.

16. The method of claim 14, wherein the multiple data bytes in each of the plurality of HLC telegrams comprise a first data byte, a second data byte, a third data byte, and a fourth data byte, and the timer control flag is carried in a first bit of the fourth data byte.

17. The method of claim 14, further comprising firing a respective HLC event trigger at an end of the respective one of the plurality of HLC telegrams when the timer control flag is set to the false value.

18. The method of claim 17, further comprising firing the respective HLC event trigger at an expiration of the respective timer when the timer control flag is set to a true value.

19. The method of claim 14, further comprising communicating the plurality of timer setup telegrams before the plurality of HLC telegrams.

20. The method of claim 19, further comprising communicating the plurality of HLC telegrams in a same sequential order as the plurality of timer setup telegrams.

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