Die to wafer bonding method and apparatus with thermal contact die shape control

Abstract

Aspects of the present disclosure provide an apparatus that heats a semiconductor structure while holding the semiconductor structure. For example, the apparatus can include a semiconductor structure holding device that is configured to hold the semiconductor structure. The apparatus can also include a heating device that is configured to generate a certain pattern of heat. The heating device can be integrated with the semiconductor structure holding device such that when the semiconductor structure holding device is holding the semiconductor structure, the certain pattern of heat generated by the heating device can be applied to the semiconductor structure.

Description

DIE TO WAFER BONDING METHOD AND APPARATUS WITH THERMAL CONTACT DIE SHAPE CONTROLCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This present disclosure claims the benefit of U.S. Nonprovisional Application No. 18 / 622,694, filed on March 29, 2024, which is incorporated herein by reference in its entirety.FIELD OF THE INVENTION

[0002] The present disclosure relates to semiconductor fabrication, and, more particularly, to die to die / wafer bonding method and apparatus with thermal contact die shape control.BACKGROUND

[0003] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0004] A typical semiconductor device can be comprised of over 70 individual layers. Each level requires multiple process steps including, but not limited to, thin film deposition, lithography and etches to form the desired structures. Non-uniform wafer stresses induced through these operations result from the patterning of thin films and are amplified via multiple temperature cycling processes, fundamentally distorting the wafer grid and creating unique wafer shapes throughout the entire integration. Current die to die / wafer bonding methods cannot handle (on an industrial scale) other distortions than just magnification, whereas the actual distortions due to lithography and warping include also dipole, quadrupole and higher order terms. There is no reliable solution to match the shape and side of a (distorted) die to the receiving bonding location.SUMMARY

[0005] Aspects of the present disclosure provide an apparatus that heats a semiconductor structure while holding the semiconductor structure. For example, the apparatus can include a semiconductor structure holding device that is configured to hold the semiconductor structure. The apparatus can also include a heating device that is configured to generate acertain pattern of heat (or a 2D temperature profile). The heating device can be integrated with the semiconductor structure holding device such that when the semiconductor structure holding device is holding the semiconductor structure, the certain pattern of heat generated by the heating device can be applied to the semiconductor structure.

[0006] In an embodiment, the certain pattern of heat generated by the heating device can be transferred through the semiconductor structure holding device and applied to the semiconductor structure. In some embodiments, the semiconductor structure holding device can be a gripper. In an embodiment, the gripper can include aluminum nitride (AIN). In another embodiment, the gripper can include siliconized silicon carbide (SiSiC).

[0007] In an embodiment, the heating device can include a plurality of heating units that are controlled to generate heat independently. For example, the heating units can be arranged in a matrix. In an embodiment, at least one of the heating units can include a Peltier element. In another embodiment, at least one of the heating units can include a resistive element. For example, the resistive element can include one or more resistors that are configured to receive currents and generate heat. In some embodiments, the at least one of the heating units can further include a temperature sensor that is configured to sense a temperature of the at least one of the heating units. In various embodiments, the heating device can further include a heat sink that is thermally coupled to the heating units.

[0008] Aspects of the present disclosure also provide a method that can bond a first semiconductor structure to a second semiconductor structure, while the shape of the first semiconductor structure is fixed in time by a sacrificial carrier substrate. For example, the method can include applying a certain pattern of heat to a first semiconductor structure to shape the first semiconductor structure and bonding a first surface of the shaped first semiconductor structure to a carrier substrate. In an embodiment, the carrier substrate can have a lower thermal conductivity than the first semiconductor structure.

[0009] In an embodiment, the carrier substrate can include silicon oxide (SiOx). In another embodiment, the carrier substrate can include silicon nitride (SiNx).

[0010] In an embodiment, the method can further include bonding a second surface of the shaped first semiconductor structure to a second semiconductor structure and removing the carrier substrate. In another embodiment, the method can further include providing a plurality of heating units that are configured to generate heat independently and controlling the heating units to generate the certain pattern of heat. For example, each of the heating units can generate heat that causes a corresponding displacement field to the semiconductor structure, and the certain pattern of heat is applied based on a combination of thedisplacement fields caused by the heating units. In some embodiments, the method can further include providing a semiconductor structure holding device that is configured to hold the first semiconductor structure and controlling the semiconductor structure holding device to hold the first semiconductor structure. In various embodiments, the first surface of the shaped first semiconductor structure is bonded to the carrier substrate after 300ms since the certain pattern of heat was applied to the first semiconductor structure.

[0011] Note that this summary section does not specify every embodiment and / or incrementally novel aspect of the present disclosure or claimed invention. Instead, this summary only provides a preliminary discussion of different embodiments and corresponding points of novelty. For additional details and / or possible perspectives of the invention and embodiments, the reader is directed to the Detailed Description section and corresponding figures of the present disclosure as further discussed below.BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Various embodiments of this disclosure that are proposed as examples will be described in detail with reference to the following figures, wherein like numerals reference like elements, and wherein:

[0013] FIG. 1 A shows a top view of a semiconductor structure with no distortion;

[0014] FIGs. 1B-1F show top views of semiconductor structures with various distortion;

[0015] FIG. 2 is a functional block diagram of an exemplary wafer processing system for controlling and adapting the dimension of a die that may be distorted and bonding the shaped die to a target die (or wafer) according to some embodiments of the present disclosure;

[0016] FIG. 3 is a flow chart of an exemplary method that bonds a shaped die to a target semiconductor structure, e.g., a wafer or die, with the shape of the shaped die being fixed in time, according to some embodiments of the present disclosure;

[0017] FIGs. 4A-4G are schematic diagrams illustrating the wafer processing system implementing the method according to some embodiments of the present disclosure;

[0018] FIG. 5A is a schematic diagram and a side view of an exemplary apparatus that includes a heating device and a gripper that are integrated with each other according to some embodiments of the present disclosure;

[0019] FIG. 5B is a side view of the apparatus;

[0020] FIGs. 6A and 6B are a side view and a circuit diagram of an exemplary heating device, respectively, according to some embodiments of the present disclosure; and

[0021] FIG. 7 illustrates how heat generated by each of a plurality of heating units of the heating device that are arranged in a matrix distorts or causes displacement to a die when a heating unit is put at a defined temperature difference with the other heating units according to some embodiments of the present disclosure.DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed. Further, spatially relative terms, such as “top,” “bottom,” “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0023] The order of discussion of the different steps as described herein has been presented for clarity sake. In general, these steps can be performed in any suitable order. Additionally, although each of the different features, techniques, configurations, etc. herein may be discussed in different places of this disclosure, it is intended that each of the concepts can be executed independently of each other or in combination with each other. Accordingly, the present invention can be embodied and viewed in many different ways.

[0024] As sizes of semiconductor devices scale according to Moore’s law, the use of advanced packaging, e.g., three-dimensional (3D) vertical stacking based on hybrid bonding, is becoming the next step to increase performance of such a semiconductor device. High density interconnection between two or more 3D vertically stacked semiconductor devicesensures high performance in combination with a smaller form factor. A reliable interconnection between two vertically stacked semiconductor devices requires a position accuracy of the interconnects in the nanometer range. Unlike overlay in an optical system, where stage and lens manipulation can be used to improve overlay, in hybrid bonding distortion of the semiconductor device has to be controlled and corrected by dimensional shaping of the semiconductor device. With the shrinking size of microelectronics, also the electrical contact pads are shrinking, and, at the same time, the number of contact pads is increasing due to rising circuit complexity. One way to cope with this development is to do direct die to die bonding, for instance, memory to logic. With the coming generations of microchips, also these contact pads become so small that conventional methods are insufficient to secure that all contact pads of both dies are lined up correctly for a functional end result.

[0025] The present disclosure provides means to control and adapt the dimension and shape of a (singulated) die using thermal expansion of the material thereof by thermal manipulation introduced by a heating matrix. In an embodiment, the required thermal XY pattern generated by the heating matrix can be calculated or estimated to deform the die in XY to match the receiving bond location. In another embodiment, an intermediate step can be introduced where the shaped die can be placed (e.g., with its backside surface) on a sacrificial carrier substrate that is made of, for example, silicon oxide (SiOx), SiOxiNitride and silicon nitride (SiNx), that freezes the shape of the die mechanically at ambient temperature and conditions, then the stack of the shaped die and the sacrificial carrier can be placed on a target die (or wafer) at ambient conditions, and the sacrificial carrier can then be removed, e.g., by polish or laser process.

[0026] FIG. 1 A shows a top view of a semiconductor structure (or a semiconductor device, e.g., a wafer or die) 190A with no distortion. As more layers (or tiers) of semiconductor components and signal wiring structures are formed, the semiconductor structure 190 A may become a semiconductor structure with distortion. For example, during the formation of the semiconductor components and the signal wiring structures, the semiconductor structure 190A may become a semiconductor structure 190B that has symmetrically scaled distortion (as shown in FIG. IB), become a semiconductor structure 190C that has trapezoidal distortion (as shown in FIG. 1C), or become a semiconductor structure 190D that has shear distortion (as shown in FIG. ID). The semiconductor structure 190A may also become a semiconductor structure that has symmetrically radial distortion. For example, the semiconductor structure 190A may become a semiconductor structure 190E that has barrel (negative) distortion (as shown in FIG. IE) or become a semiconductor structure 190F that has pincushion (positive) distortion (as shown in FIG. IF). Aspects of the present disclosure provide methods andapparatuses that can correct at least these distorted semiconductor structures 190B-190F via thermal expansion control, but higher order corrections are not excluded.

[0027] FIG. 2 is a functional block diagram of an exemplary wafer processing system 200 for controlling and adapting the dimension, e.g., XY dimension, of a die that may be distorted and bonding the shaped die to a target die (or wafer) according to some embodiments of the present disclosure. In an embodiment, the distorted die may be obtained by singulating a distorted semiconductor structure, e.g., the semiconductor structures 190B-190F. Typical die sizes are 26mm x 33mm in width and length in maximum, with a typical thickness of 800 microns and thinner, even down to for instance 50 microns. Bulk or carrier material can be silicon, but also for instance silicon oxide (SiOx) or silicon nitride (SiNx). The active circuits, e.g., the semiconductor components and the signal wiring structures, can be embedded in this bulk or carrier, or placed on top of this bulk or carrier die.

[0028] The wafer processing system 200 can include metrology equipment, e.g., a (XY) distortion measurement device 210. In an embodiment, the distortion measurement device 210 can be configured to measure a semiconductor structure that may be distorted (e.g., the semiconductor structures 190B-190F) and a distorted die that may be obtained by singulating the semiconductor structure, to identify a distortion measurement, e.g., an XY distortion measurement, of the semiconductor structure. In an embodiment, the distortion measurement device 210 can use optical (e.g., using a scanning laser technique) (e.g., optical interferometers), acoustic and other mechanisms (e.g., capacitive sensors) to measure the XY deviations of the semiconductor structure, e.g., by determining alignment mark registration, overlay mark registration or reference grid registration on the semiconductor structure, or algorithmically based on die shape metrology, and store the XY deviations by (x, y) coordinates to identify the XY distortion measurement of the semiconductor structure. In some embodiments, the XY distortion measurement can include raw distortion data or be represented as a distortion signature with relative values.

[0029] The wafer processing system 200 can further include a heating device 220 that is configured to generate a certain pattern of heat (or a certain thermal XY pattern or profile, or a temperature profile) according to the XY distortion measurement of the semiconductor structure, e.g., the distorted die. In an embodiment, the certain pattern of heat can be applied to the distorted die to deform, correct or modify the XY distortion of the distorted die. In some embodiments, the heating device 220 can include a plurality of heating units that have an arrangement corresponding to the certain pattern of heat and are controlled independently to generate different temperature ranges of heat. For example, the heating units can be arrangedin a matrix. Accordingly, the distorted die can be heated in different regions that correspond to the certain pattern of heat, which corresponds to the XY distortion measurement of the distorted die, and the (XY) dimension of the distorted die can thus be corrected or modified. Main issue here is that continuous heating will result in ever rising of the temperature, and all locally deposited heat will flow away laterally, causing the distortion pattern to be of a dynamic nature. Also, a (single) pulsed deposition will only result in a shortly lived distorted shape. This limits the available time for placement and bonding before the shape dissipates (fades). A way around this is to create a balance between heating and cooling. Light energy can be added in the center of a cell, where as cooling-contact can remove the heat at the edge of a cell. The heat resistance from center to edge will result in a stable temperature difference and local expansion of the cell.

[0030] The wafer processing system 200 can further include a semiconductor structure holding device (e.g., a gripper, a clamper, and so on) 230 that is configured to pick up, hold and grip a wafer (or a die), e.g., a semiconductor structure. For example, the gripper 230 can be a vacuum gripper 230. In operation, a negative pressure can be created inside a hose and a vacuum head to cause suction cups or ceramic pads to stick to the surface of the wafer.

[0031] In an embodiment, the wafer processing system 200 can further include other components, such as a wafer chuck 251 for a wafer to be placed thereon, a coating device 252 configured to coat a working surface and / or backside surface of the wafer with a photosensitive material e.g., a photoresist layer) or a heat sensitive material, a development device 253 configured to develop a latent pattern in the photoresist layer, an etching device 254 configured to use plasma or vapor-phase etching or wet etching to etch the photoresist layer, a polishing device 255 configured to polish (e.g., chemical-mechanical polishing, CMP) a semiconductor structure, and a bonding device 256 configured to bonding a die or wafer to a wafer or die that is placed on the wafer chuck 251. In some embodiments, the wafer processing system 200 can further include a robot 257 that can be coupled to the gripper 230 and configured to transfer the wafer or die, which is gripped by the gripper 230, among different treatment modules, where the distortion measurement device 210, the heating device 220, the wafer chuck 251, the coating device 252, the development device 253, the etching device 254, the polishing device 255 and / or the bonding device 256 may be installed, for various processing. In an embodiment, due to variations in the surface layering of the die, a light absorption layer may be needed to ensure correct in-coupling of the light energy into the die.

[0032] In an embodiment, the wafer processing system 200 can further include a controller 240 that is coupled to the distortion measurement device 210, the heating device 220, thegripper 230, the wafer chuck 251, the coating device 252, the development device 253, the etching device 254, the polishing device 255, the bonding device 256 and the robot 257 and configured to control the operations thereof. For example, the controller 240 can be configured to control the gripper 230 to grip a semiconductor structure (e.g., a distorted die), to control the distortion measurement device 210 to measure the semiconductor structure (e.g., the distorted die) to identify the XY distortion measurement of the distorted die, to control the heating device 220 to generate and apply to the distorted die a certain pattern of heat that corresponds to the XY distortion measurement of the distorted die to deform, correct or modify the XY dimension of the distorted die, and to control the bonding device 256 to bond the shaped die to a target wafer or die that is placed on the wafer chuck 251.

[0033] The thermal shaping of the distorted die by the heating device 220 suffers from the time frame mismatch of bringing to the desired shape and the timeframe of fixating the shaped die in a desired target location (wafer or die) by bonding. This is caused by either the heatspreading of a thermal profile, e.g., the thermal XY profile, in the shaped die after the shaped die is released from the gripper 230 or the heatloss by contact between the shaped die and the target wafer or die. For example, bonding timeframe of a complete die at ambient conditions is about 0.5 to 1 second in maximum, during which the heating device 220 does not heat the shaped die and the shapeloss of the shaped die occurs. As the heating device 220 sets a desired temperature profile (which can be maintained as long as the die is in contact) during the bonding process, the bonding contact to the wafer causes heatloss (transfer to the wafer) and the release from the gripper disallow resupply of the lost heat. This causes highly dynamical and difficult to predict temperature profile and there for a difficult to predict shape. Improvement may be made by slowing the shapeloss by heatloss down and speeding up the bonding process. Typical timeframes for the shapeloss are in the order of 300ms to 600ms, when the receiving target location is made of bulk silicon.

[0034] The present disclosure introduces an intermediate step where the shaped die is placed (e.g., with its backside surface) on a sacrificial carrier substrate first. In an embodiment, the sacrificial carrier substrate can be made of a low thermal conductivity material, such as silicon oxide (SiOx) and silicon nitride (SiNx), which has a lower thermal conductivity than a silicon (Si) or germanium (Ge) wafer or die. Therefore, the heatloss (or heattransfer) of the shaped die to the sacrificial carrier substrate can be minimized and the shape of the shaped die can thus be fixed in time mechanically by the sacrificial carrier substrate.

[0035] FIG. 3 is a flow chart of an exemplary method 300 that can bond a shaped die to a target semiconductor structure, e.g., a wafer or die, while the shape of the shaped die is fixedin time by a sacrificial carrier substrate, according to some embodiments of the present disclosure. In various embodiments, some of the steps of the method 300 shown can be performed concurrently or in a different order than shown, can be substituted by other method steps, or can be omitted. Additional method steps can also be performed as desired. Aspects of the method 300 can be implemented by a wafer processing system, such as the wafer processing system 200 illustrated in and described with respect to the preceding figures, e.g., FIG. 2. FIG. 4 is a schematic diagram illustrating the wafer processing system 200 implementing the method 300 according to some embodiments of the present disclosure. The method 300 starts with step S310, at which a die that is to be reshaped / distorted / deformed can be provided. For example, a distorted die 490 can be provided and gripped by the gripper 230, to be bonded to a sacrificial carrier substrate 491, as shown in FIG. 4A. In an embodiment, the distorted die 490 can be provided by singulating a distorted semiconductor structure, e.g., the semiconductor structures 190B-190F. The method 300 can proceed to step S320.

[0036] At step S320, the distorted die 490 can be measured to identify an XY distortion measurement of the distorted die 490. For example, the controller 240 can be used to control the distortion measurement device 210 to measure the distorted die 490 to identify the XY distortion measurement of the distorted die 490. The method 300 can proceed to step S330.

[0037] At step S330, the dimension of the distorted die 490 can be deformed, corrected or modified to form a shaped die 490. For example, the controller 240 can be used to control the heating device 220 to generate a certain pattern of heat according to the distortion measurement of the distorted die 490 to correct or modify the dimension of the distorted die 490 to form the shaped die 490. In an embodiment, the controller 240 can control the heating units of the heating device 220 independently to generate different temperatures of heat that correspond to the XY distortion measurement of the distorted die 490. Accordingly, the distorted die 490 can be heated in different regions that correspond to the certain pattern of heat, which corresponds to the XY distortion measurement of the distorted die 490, and the dimension of the distorted die 490 can thus be corrected or modified to form the shaped die 490. The method 300 can proceed to step S340.

[0038] At step S340, the shaped die 490, which is gripped by the gripper 230, can be bonded to the sacrificial carrier substrate 491, as shown in FIG. 4B. For example, after a range of time from between 300ms to 3000ms (or between 300ms to 1500ms, 1000ms or 500ms) since the heating device 220 generated the certain pattern of heat, the carrier substrate 491 can be placed on the wafer chuck 251, and the controller 240 can be used to control the bonding device 225 to bond the shaped die 490, which is gripped by the gripper 230, to the carrier substrate 491.In an embodiment, the carrier substrate 491 can be made of a low thermal conductivity material, e.g., silicon oxide (SiOx) and silicon nitride (SiNx), which has lower thermal conductivity than the shaped die 490, which is made of silicon (Si) or germanium (Ge). Therefore, the heatloss (or heattransfer) of the shaped die 490 to the sacrificial carrier substrate 491 can be minimized and the shape of the shaped die 490 can thus be fixed in time mechanically by the sacrificial carrier substrate 491. The method 300 can proceed to step S350.

[0039] At step S350, the shaped die 490, which is bonded to the sacrificial carrier substrate 491, can be released from the gripper 230, as shown in FIG. 4C. For example, the controller 240 can be used to control the gripper 230, e.g., by stopping creating the negative pressure inside the hose and the vacuum head of the vacuum gripper 230, to release the shaped die 490, which is bonded to the sacrificial carrier substrate 491 and the shape of which is fixed in time mechanically by the sacrificial carrier substrate 491 at ambient temperature and conditions. The method 300 can proceed to step S360.

[0040] At step S360, the shaped die 490 can be flipped over and the carrier substrate 491, which is bonded to the shaped die 490, can be gripped by the gripper 230, for the shaped die 490 to be bonded to a target wafer (or die) 492, as shown in FIG. 4D. For example, the controller 240 can be used to control the robot 257 to flip the shaped die 490 over and to control the gripper 230 to grip the carrier substrate 491. The method 300 can proceed to step S370.

[0041] At step S370, the shaped die 490 can be bonded to the target wafer 492, as shown in FIG. 4E. For example, the controller 240 can be used to control the bonding device 256 to bond the shaped die 490, the shape of which is fixed in time mechanically by the carrier substrate 491, to the target wafer 492. Accordingly, the electrical connections, e.g., contact pads, of both the shaped die 490 and the target wafer 492 can be aligned with each other. The method 300 can proceed to step S380.

[0042] At step S380, the carrier substrate 491 can be released from the gripper 230, as shown in FIG. 4F. For example, the controller 240 can be used to control the gripper 230, e.g., by stopping creating the negative pressure inside the hose and the vacuum head of the vacuum gripper 230, to release the carrier substrate 491, which is bonded to the shaped die 490 to freeze the shape of the shaped die 490 mechanically at ambient temperature and conditions. The method 300 can proceed to step S390.

[0043] At step S390, the sacrificial carrier substrate 491 can be removed, as shown in FIG. 4G. For example, the controller 240 can be used to control the polishing device 255 to polish and remove the sacrificial carrier substrate 491. As another example, the sacrificial carrier substrate 491 can also be removed by a laser process.

[0044] The thermal shaping of a distorted die (or wafer) in order to form a shaped die, such as the shaped die 490, relies on creating a temperature profile in the lateral direction (XY). Due to the lateral heat conduction, the natural tendency is that this temperature profile will even out to an even or uniform temperature. The present disclosure provides means to impose and maintain a temperature profile applied to a die accurate enough and long enough to create the desired shape and size for the contact pads on both components aligned during die to die (or die to wafer) bonding. Various implementations can be realized, and a characteristic of the present disclosure is the integration of a heating device with a gripper that can pick up, hold and place a (singulated) die that may be distorted. In an embodiment, the heating device can have a plurality of heating units that are arranged in a matrix. Therefore, the heating device can keep on heating the (singulated) die with a certain pattern of heat while the semiconductor structure holding device 230 is holding (e.g., the gripper 230 is gripping) the die and maintaining the desired shape and size of the die until the die is bonded to a sacrificial carrier substrate and / or a target die or wafer.

[0045] FIG. 5 A is a schematic diagram of an exemplary apparatus 500 that includes a heating device 520 (e.g., the heating device 220) and a gripper (or a gripper of plate) 530 (e.g., the gripper 230) that are integrated with each other according to some embodiments of the present disclosure. FIG. 5B is a side view of the apparatus 500. In an embodiment, the gripper 530 can be configured to grip a (singulated, distorted) die 590 (shown in FIG. 5B), e.g., the distorted die 490, that is disposed thereon, and the heating device 520 can be thermally coupled to the gripper 530 and configured to generate a certain pattern of heat (or a certain thermal XY pattern or profile), which can be transferred through the gripper 530 and applied to the singulated distorted die 590 to deform, correct or modify the dimension (e.g., XY distortion) of the distorted die 590 to form a shaped die.

[0046] In an embodiment, the gripper 530 can include a vacuum gripper. In operation, a negative pressure P can be created by a vacuum pump (not shown) and introduced through a hose (not shown) via a gripper hole 531 to fill channels or trenches 533 to cause suction cups or ceramic pads 532 to stick to the surface of the distorted die 590. In an embodiment, the ceramic pads 532 can be arranged in a matrix (e.g., 5x5, 5x7, etc.). In another embodiment, the ceramic pads 532 can be separated from one another, e.g., by the trenches 533. Therefore, the heat transferred to one of the ceramic pads 532 does not affect and is not affected by the remaining ceramic pads 532.

[0047] As the heat generated by the heating device 520 can be transferred through the gripper 530 and applied to the distorted die 590, the gripper 530 can be made of a material that has heatconductivity high enough to transfer heat from the heating device 520 to the distorted die 590 disposed on the gripper 530, but low enough to minimize lateral flow of heat. The lateral spread of the heat can be prevented by surrounding the heating units of the heating device 520 with cooling elements (in practice, copper pillars). The lateral heat conduction may blur the XY-temperature pattern. For example, the gripper 530 may be made of aluminum nitride (AIN) or siliconized silicon carbide (SiSiC). For a die size of 25mm x 35mm in width and length, the gripper 530 may be 2.5mm in total thickness and the ceramic pads 532 arranged in a 5x7 matrix may be 0.35mm in thickness and less than 5mm x 5mm in width and length. The trenches 533 between the ceramic pads 532 can prevent lateral spread and can act as channels for evacuation. In some embodiments, each of the ceramic pads 532 may be as small as 2mm x 2mm in width and length in order to get enough XY resolution in the temperature (distortion) pattern.

[0048] In an embodiment, the heating device 520 can include a plurality of heating units 521 that are arranged in a matrix, each of heating units 521 corresponding to one of the ceramic pads 532. The heating device 520 can be configured to generate a certain pattern of heat, which can be transferred through the gripper 530 and applied to the distorted die 590. Accordingly, the heating units 521 can have an arrangement corresponding to the certain pattern of heat (or a 2D temperature profile) and be controlled independently, e.g., by the controller 240, to generate different temperature ranges of heat. For example, the heating units 521 can be arranged in a matrix (e.g., 5x5, 5x7, etc.). Accordingly, the distorted die 590 can be heated in different regions that correspond to the certain pattern of heat, which corresponds to the XY distortion measurement of the distorted die 590, and the (XY) dimension of the distorted die 590 can thus be corrected or modified.

[0049] The size and shape matching of two dies (or one die and one wafer) that have to be bonded will rely on precise and accurate temperature control. For a typical die size of 26mm x 33mm in width and length, a IK deviation will result in a size mismatch of ca lOOnm, and a lOOmK mismatch will result in a size mismatch of ca lOnm, and so on. Therefore, the desired temperature profile will need to be superimposed on a carefully controlled base (or reference) temperature. In an embodiment, the base of the heating device 520 can be placed on top of a well-designed heat sink 522 that can be maintained to a well-chosen reference temperature (e.g., 20°C). In an embodiment, the heating device 520 can also include a plurality of leads or legs (e.g., made of copper), e.g., first and second copper legs 523a and 523b, that are configured to electrically couple the heat sink 522 to the heating units 521. In an embodiment, the first and second copper legs 523a and 523b can be 1.5mm in length. The leads or legs can act as electrical connections but also as a heat conduction to prevent that locally generated heat doesnot reach the neighboring heating units, thereby allowing for local temperature control per heating unit. The length and thickness of the legs as well as the placement (heating unit size) can determine the heatflow balance and the reachable maximum heating unit temperature.

[0050] FIGs. 6A and 6B are a side view and a circuit diagram of an exemplary heating device 620, e.g., the heating device 520, respectively, according to some embodiments of the present disclosure. The heating device 620 can include a plurality of heating units 621, e.g., the heating units 521, that are arranged in a matrix (e.g., 5x5, 5x7, etc.). In an embodiment, the heating units 621 can include resistive (joule heating or Ohm resistance) or Peltier elements (Peltier heating).

[0051] As shown in FIGs. 6A and 6B, each of the heating units 621 can include one or more resistive elements 627-629, e.g., first to third resistors 627-629, that act as heating resistors that receive currents and generate heat. In an embodiment, the first to third resistors 627-629 can be connected in parallel. In another embodiment, the first to third resistors 627-629 can be connected in series, as shown in FIG. 6B. For example, the second resistor 628 can be serially connected between the first resistor 627 and the third resistor 629, one end of the first resistor 627 that is not connected to the second resistor 628 can be connected to a first lead or leg (e.g., made of copper) 623a, and one end of the third resistor 629 that is not connected to the second resistor 628 can be connected to a second lead or leg (e.g., made of copper) 623b.

[0052] Additionally, each of the heating units 621 can further include a temperature sensor 626, acting as a measuring resistor, that is configured to sense the temperature of the heating unit 621, so that the balance between delivered heat by the heating elements (i.e., the first to third resistors) 627-629 and removed heat by a gripper integrated therewith, e.g., the gripper 530, can be established to generate the desired stable temperature pattern. In an embodiment, the temperature sensor 626 can be physical (like a positive temperature coefficient (PTC) or a negative temperature coefficient (NTC) thermistor) or via infra-red imaging. Therefore, the precise temperature per heating unit 621 in the (e.g., 5x5 or 5x7) heating matrix (e.g., the heating device 620) needs to be determined, e.g., by the controller 240 based on the distortion measurement of the distorted die 590 identified by the distortion measurement device 210, to create the desired local expansion to the distorted die 590. The dimension of the distorted die 590 will have to be corrected or modified such that all of the contact pads on the respective die will meet and make accurate electrical contact. Typically, this match should be better than 20nm rms.

[0053] FIG. 7 illustrates how the heat generated by each of a plurality of heating units (e.g., the heating units 621) of a heating device (e.g., the heating device 620) that are arranged in amatrix (e.g., a 5^7 matrix), distorts or causes displacement to a die according to some embodiments of the present disclosure. The dimension of the die, e.g., the distorted die 590, can be corrected or modified based on a combination (e.g., a linear combination) of the distortions created by the individual heating units 621. For example, in a 5x7 heating matrix (e.g., the heating units 521 shown in FIGs. 5A and 5B), the distortion field of the die caused by any of the heating units [1,1], [1, 2], . . ., [2, 1], . . ., [7, 4] and [7, 5], e.g., the heating unit [2, 3], can be determined. This will be a vector field of displacements {u, v} for each location on the die. The displacement fields (called displacement primitives) caused by different heating units will be different from each other. For example, the displacement field caused by the heating unit [1, 4] will be different than that caused by the heating unit [2, 3],

[0054] In operation, metrology equipment, e.g., the (XY) distortion measurement device 210 can be controlled, e.g., by the controller 240, to measure a die that may be distorted, e.g., the distorted die 590, to identify a distortion measurement, e.g., an XY distortion measurement, of the distorted die 590, and the heating device 620 (the heating units 621) can be controlled to generate a certain pattern of heat based on the distortion measurement, which is transferred through the gripper 630 and applied to the distorted die 590. In an embodiment, the displacement fields caused by the heating units 621 can be summed linearly, and the temperature (and the heat generated) per heating unit 621 can be seen as a weight function for the displacement field per heating unit 621. For example, the displacement field (i.e., displacement primitive) caused by the heating unit [x, y] is {u, v}[X, y], and the total distortion [x, y] will be the sum (over XY) of dT[x, y]x{u, v}[X, y], where dT(x, y) can be solved via a matrix inversion operation, e.g., a least squares method.

[0055] The displacements caused by the individual heating units 621 can be estimated theoretically, or can be measured or preferably be simulated by finite element method (FEM) to take specific mechanical construction in account.

[0056] In the preceding description, specific details have been set forth, such as a particular geometry of a processing system and descriptions of various components and processes used therein. It should be understood, however, that techniques herein may be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation and not limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. Nevertheless, embodiments may be practiced without such specific details.Components having substantially the same functional constructions are denoted by like reference characters, and thus any redundant descriptions may be omitted.

[0057] Various techniques have been described as multiple discrete operations to assist in understanding the various embodiments. The order of description should not be construed as to imply that these operations are necessarily order dependent. Indeed, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0058] “ Substrate” or “target substrate” as used herein generically refers to an object being processed in accordance with the invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a dielectric layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying dielectric layer or overlying dielectric layer, patterned or un-pattemed, but rather, is contemplated to include any such dielectric layer or base structure, and any combination of dielectric layers and / or base structures. The description may reference particular types of substrates, but this is for illustrative purposes only.

[0059] Those skilled in the art will also understand that there can be many variations made to the operations of the techniques explained above while still achieving the same objectives of the invention. Such variations are intended to be covered by the scope of this disclosure. As such, the foregoing descriptions of embodiments of the invention are not intended to be limiting. Rather, any limitations to embodiments of the invention are presented in the following claims.

Claims

WHAT IS CLAIMED IS:

1. An apparatus, comprising: a semiconductor structure holding device configured to hold a semiconductor structure; and a heating device configured to generate a certain pattern of heat, wherein the heating device is integrated with the semiconductor structure holding device such that when the semiconductor structure holding device is holding the semiconductor structure, the certain pattern of heat generated by the heating device is applied to the semiconductor structure.

2. The apparatus of claim 1, wherein the certain pattern of heat generated by the heating device is transferred through the semiconductor structure holding device and applied to the semiconductor structure.

3. The apparatus of claim 2, wherein the semiconductor structure holding device is a gripper.

4. The apparatus of claim 3, wherein the gripper includes aluminum nitride (AIN) or siliconized silicon carbide (SiSiC).

5. The apparatus of claim 1, wherein the heating device includes a plurality of heating units that are controlled to generate heat independently.

6. The apparatus of claim 5, wherein the heating units are arranged in a matrix.

7. The apparatus of claim 5, wherein at least one of the heating units includes a Peltier element.

8. The apparatus of claim 5, wherein at least one of the heating units includes a resistive element.

9. The apparatus of claim 8, wherein the resistive element includes one or more resistors that are configured to receive currents and generate heat.

10. The apparatus of claim 9, wherein the at least one of the heating units further includes a temperature sensor that is configured to sense a temperature of the at least one of the heating units.

11. The apparatus of claim 7, further comprising cooling units surrounding the heating units to localize heat transferring.

12. The apparatus of claim 6, wherein the heating device further includes a heat sink that is thermally coupled to the heating units.

13. A method, comprising: applying a certain pattern of heat to a first semiconductor structure to shape the first semiconductor structure; and bonding a first surface of the shaped first semiconductor structure to a carrier substrate, wherein the carrier substrate has a lower thermal conductivity than the first semiconductor structure.

14. The method of claim 13, wherein the carrier substrate includes silicon Oxi- Nitride.

15. The method of claim 13, wherein the carrier substrate includes silicon oxide (SiOx) or silicon nitride (SiNx).

16. The method of claim 13, further comprising: bonding a second surface of the shaped first semiconductor structure to a second semiconductor structure; and removing the carrier substrate.

17. The method of claim 13, further comprising: providing a plurality of heating units that are configured to generate heat independently; and controlling the heating units to generate the certain pattern of heat.

18. The method of claim 17, wherein each of the heating units generates heat that causes a corresponding displacement field to the semiconductor structure, and the certain pattern of heat is applied based on a combination of the displacement fields caused by the heating units.

19. The method of claim 13, further comprising: providing a semiconductor structure holding device that is configured to hold the first semiconductor structure; and controlling the semiconductor structure holding device to hold the first semiconductor structure.

20. The method of claim 19, wherein the first surface of the shaped first semiconductor structure is bonded to the carrier substrate after 300ms since the certain pattern of heat was applied to the first semiconductor structure.

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