Algorithm engine, security chip, electronic device and encryption method

Abstract

Disclosed in the present application are an algorithm engine, a security chip, an electronic device and an encryption method, which are applied to SM9. The algorithm engine comprises: an input circuit, which is used for acquiring an input of a preset algorithm in SM9; an operational circuit, which is used for performing an operation on the preset algorithm according to the input, so as to obtain the operation result of the preset algorithm; and an output circuit, which is used for outputting the operation result. The preset algorithm is decomposed into a plurality of algorithm steps, and each of the plurality of algorithm steps comprises m operations; and the operational circuit comprises n identical operational subcircuit groups for performing the m operations in each algorithm step, m and n being integers greater than 1, and m being greater than or equal to n. In the solution, at least n operations among the m operations in the same algorithm step can be executed by the n operational subcircuit groups, and the m operations do not need to be executed in sequence, such that the operation speed is fast, the operation efficiency can be improved, the operation time can be reduced, and the operation performance of the algorithm engine is effectively improved.

Description

Algorithm engine, security chip, electronic device and encryption method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority based on Chinese patent application 202410391029.0 filed on April 1, 2024, and all of its contents are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of information security technology, and in particular to an algorithm engine, a security chip, an electronic device, and an encryption method. Background Art

[0004] In the information age, people have higher requirements for information encryption. The SM9 (Modular Multiplication Encryption Algorithm) is a Chinese-developed identification encryption algorithm. Compared to traditional public-key encryption, identification encryption derives its public key from an identity identifier, avoiding complex exchange processes and improving wireless network throughput.

[0005] The SM9 algorithm is based on elliptic curve operations on an extended field. Its core algorithm is the calculation of bilinear pairings, mainly including modular addition, modular multiplication and modular inverse operation modules on the base field, quadratic extended field, quartic extended field and twelfth extended field, point addition and multiple point operation modules on the base field and quadratic extended field, Miller algorithm module, modular exponentiation module on the twelfth extended field and final modular exponentiation module.

[0006] Traditional SM9 circuit designs often include all the submodules required for the SM9 functional algorithm, including base-domain modular addition and subtraction modules, base-domain modular multiplication modules, base-domain modular inversion modules, base-domain point addition modules, base-domain point doubling modules, quadratic extended-domain point addition modules, quadratic extended-domain point doubling modules, 12th-order extended-domain modular multiplication modules, 12th-order extended-domain modular exponentiation modules, and bilinear pairing modules. Since operations on the extended domain are all based on operations on lower-level domains, for example, a 12th-order extended-domain modular multiplication operation is decomposed into four extended-domain operations, then further decomposed into quadratic extended-domain operations, and finally decomposed into modular operations on the base domain. Modular operations on the base domain cannot be computed in parallel. Therefore, traditional SM9 circuits often require a large hardware footprint and are time-consuming to implement, seriously impacting the performance of the SM9 algorithm and its hardware adoption.

[0007] Summary of the Invention

[0008] This application provides at least one algorithm engine, a security chip, an electronic device, and an encryption method.

[0009] In a first aspect, the present application provides an algorithm engine, applied to SM9, comprising:

[0010] An input circuit, used to obtain input of a preset algorithm in the SM9;

[0011] an operation circuit, configured to operate the preset algorithm according to the input to obtain an operation result of the preset algorithm;

[0012] An output circuit, configured to output the operation result;

[0013] The preset algorithm is decomposed into a plurality of algorithm steps, and each of the plurality of algorithm steps includes m operations;

[0014] The operation circuit includes n identical operation sub-circuit groups for performing the m operations in each algorithm step, wherein m and n are integers greater than 1, and m is greater than or equal to n.

[0015] In some embodiments, when m is equal to n, the n operation sub-circuit groups simultaneously perform the m operations in each algorithm step.

[0016] In some embodiments, each of the n operator sub-circuit groups includes:

[0017] a base-field modular addition and subtraction subcircuit and a base-field modular multiplier subcircuit, wherein the base-field modular addition and subtraction subcircuit is used to perform a base-field modular addition or a base-field modular subtraction operation, and the base-field modular multiplier circuit is used to perform a base-field modular multiplication operation; and / or

[0018] A secondary extended-range modular addition and subtraction subcircuit and a secondary extended-range modular multiplier circuit, wherein the secondary extended-range modular addition and subtraction subcircuit is used to perform a secondary extended-range modular addition or secondary extended-range modular subtraction operation, and the secondary extended-range modular multiplier circuit is used to perform a secondary extended-range modular multiplication operation.

[0019] In some embodiments, the SM9 includes a bilinear pairing operation, a twelve-order extended-field modular exponentiation operation, a quadratic extended-field point addition operation, a quadratic extended-field point doubling operation, a base-field point addition operation, and a base-field point doubling operation;

[0020] The preset algorithm includes an algorithm of at least one of the bilinear pairing operation, the twelve-fold extended-range modular exponentiation operation, the quadratic extended-range point addition operation, the quadratic extended-range point doubling operation, the base-range point addition operation, and the base-range point doubling operation.

[0021] In some embodiments, the operation result is at least part of the step results of the multiple algorithm steps.

[0022] In some embodiments, the preset algorithm includes a first algorithm and a second algorithm, the first algorithm is decomposed into a first number of algorithm steps, the second algorithm is decomposed into a second number of algorithm steps, and the first number and the second number are different.

[0023] In some embodiments, operating the preset algorithm according to the input to obtain an operation result of the preset algorithm includes:

[0024] The input is converted from an affine coordinate system to a Jacobi weighted mapping coordinate system, so as to operate the preset algorithm according to the input to obtain an operation result of the preset algorithm.

[0025] A second aspect of the present application provides a security chip, including the algorithm engine in the first aspect.

[0026] A third aspect of the present application provides an electronic device, comprising the security chip in the second aspect.

[0027] A fourth aspect of the present application provides an encryption method, applied to SM9, comprising:

[0028] Performing a calculation operation on the preset algorithm in the SM9 to achieve encryption, wherein the calculation operation is implemented by an algorithm engine, and the algorithm engine includes:

[0029] An input circuit, used to obtain input of a preset algorithm in the SM9;

[0030] an operation circuit, configured to operate the preset algorithm according to the input to obtain an operation result of the preset algorithm;

[0031] An output circuit, configured to output the operation result;

[0032] The preset algorithm is decomposed into a plurality of algorithm steps, and each of the plurality of algorithm steps includes m operations;

[0033] The operation circuit includes n identical operation sub-circuit groups for performing the m operations in each algorithm step, wherein m and n are integers greater than 1, and m is greater than or equal to n.

[0034] In some embodiments, when m is equal to n, the n operation sub-circuit groups simultaneously perform the m operations in each algorithm step.

[0035] In some embodiments, each of the n operator sub-circuit groups includes:

[0036] a base-field modular addition and subtraction subcircuit and a base-field modular multiplier subcircuit, wherein the base-field modular addition and subtraction subcircuit is used to perform a base-field modular addition or a base-field modular subtraction operation, and the base-field modular multiplier circuit is used to perform a base-field modular multiplication operation; and / or

[0037] A secondary extended-range modular addition and subtraction subcircuit and a secondary extended-range modular multiplier circuit, wherein the secondary extended-range modular addition and subtraction subcircuit is used to perform a secondary extended-range modular addition or secondary extended-range modular subtraction operation, and the secondary extended-range modular multiplier circuit is used to perform a secondary extended-range modular multiplication operation.

[0038] In some embodiments, the SM9 includes a bilinear pairing operation, a twelve-order extended-field modular exponentiation operation, a quadratic extended-field point addition operation, a quadratic extended-field point doubling operation, a base-field point addition operation, and a base-field point doubling operation;

[0039] The preset algorithm includes an algorithm of at least one of the bilinear pairing operation, the twelve-fold extended-range modular exponentiation operation, the quadratic extended-range point addition operation, the quadratic extended-range point doubling operation, the base-range point addition operation, and the base-range point doubling operation.

[0040] In some embodiments, the operation result is at least part of the step results of the multiple algorithm steps.

[0041] In some embodiments, the preset algorithm includes a first algorithm and a second algorithm, the first algorithm is decomposed into a first number of algorithm steps, the second algorithm is decomposed into a second number of algorithm steps, and the first number and the second number are different.

[0042] In some embodiments, operating the preset algorithm according to the input to obtain an operation result of the preset algorithm includes:

[0043] The input is converted from an affine coordinate system to a Jacobi weighted mapping coordinate system, so as to operate the preset algorithm according to the input to obtain an operation result of the preset algorithm.

[0044] In the above solution, the algorithm engine includes an input circuit, an operation circuit, and an output circuit. The operation circuit is used to operate the preset algorithm according to the input to obtain the operation result of the preset algorithm. Each of the multiple algorithm steps of the preset algorithm includes m operations, and the operation circuit includes n identical operation sub-circuit groups, which are used to perform the m operations in each algorithm step. Wherein, m and n are both integers greater than 1, and m is greater than or equal to n. Therefore, at least n of the m operations in the same algorithm step can be executed simultaneously by n operation sub-circuit groups, and the m operations do not need to be executed sequentially, which makes the operation speed faster, can improve the operation efficiency, save operation time, and thus can effectively improve the operation performance of the algorithm engine.

[0045] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and, together with the specification, are used to illustrate the technical solutions of the present application.

[0047] FIG1 is a schematic diagram of the framework of the algorithm engine provided in an embodiment of the present application.

[0048] FIG. 2 is a first schematic diagram of a framework of an operator sub-circuit group of the algorithm engine shown in FIG. 1 .

[0049] FIG3 is a second schematic diagram of a framework of the operator sub-circuit group of the algorithm engine shown in FIG1 .

[0050] FIG. 4 is a third schematic diagram of a framework of the operator sub-circuit group of the algorithm engine shown in FIG. 1 .

[0051] FIG5 is a schematic diagram of the framework of the security chip provided in an embodiment of the present application.

[0052] FIG6 is a schematic diagram of the framework of the electronic device provided in an embodiment of the present application.

[0053] FIG7 is a flowchart of the encryption method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] The following describes the embodiments of the present application in detail with reference to the accompanying drawings.

[0055] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0056] The term "and / or" in this article is simply a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects are in an "or" relationship. In addition, "many" in this article means two or more than two. In addition, the term "at least one" in this article means any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0057] Please refer to Figure 1, which is a schematic diagram of the framework of the algorithm engine provided in an embodiment of the present application. The algorithm engine 1 is applied to SM9, and SM9 is an identification cryptographic algorithm. The algorithm engine 1 includes an input circuit 10, an operation circuit 20, and an output circuit 30. The input circuit 10 is used to obtain the input of the preset algorithm in SM9; the operation circuit 20 is used to operate the preset algorithm according to the input to obtain the operation result of the preset algorithm; the output circuit 30 is used to output the operation result. Among them, the preset algorithm is decomposed into multiple algorithm steps, and each of the multiple algorithm steps includes m operations. The operation circuit 20 includes the same n operation sub-circuit groups 21, which are used to perform m operations in each algorithm step. Both m and n are integers greater than 1, and m is greater than or equal to n.

[0058] The arithmetic circuit 20 is electrically connected to the input circuit 10 and the output circuit 30. The input circuit 10 is used to obtain the input of the preset algorithm in the SM9 and send the input to the arithmetic circuit 20. The arithmetic circuit 20 is used to calculate the preset algorithm corresponding to the input to obtain the calculation result of the preset algorithm and send the calculation result to the output circuit 30. The output circuit 30 is used to output the calculation result.

[0059] In this embodiment, SM9 may include a bilinear pairing operation and a twelve-times extended-domain modular exponentiation operation, and the preset algorithm may include an algorithm in the bilinear pairing operation and an algorithm in the twelve-times extended-domain modular exponentiation operation. The bilinear pairing operation may include the gU, V(Q) algorithm, the gV, V(Q) algorithm, and the f q The power algorithm, the twelve-times extended-field modular exponentiation operation may include four-times extended-field modular multiplication algorithm.

[0060] gU,V(Q) algorithm, gV,V(Q) algorithm, f q The power algorithm and the quartic extended-field modular multiplication algorithm are both decomposed into multiple algorithm steps, each of which includes m operations, and the number of operations in each algorithm step is the same. Where m can be 2, 3, 4, or 5, and is not limited here.

[0061] f q Taking the power algorithm as an example, f q The power algorithm is decomposed into 6 algorithm steps, each of which includes 2 operations, that is, m is equal to 2. q The specific decomposition method of the power algorithm will be described in detail below.

[0062] In some feasible embodiments, the number of operations in each algorithm step of the same preset algorithm may not be the same. For example, a preset algorithm is decomposed into three algorithm steps, two of the three algorithm steps may each include m operations, and the remaining algorithm step may include m-1 operations or m+1 operations.

[0063] In this embodiment, the operation circuit 20 includes n identical operation sub-circuit groups 21 for performing m operations in each algorithm step, wherein n can be 2, 3, 4 or 5, which is not limited here.

[0064] For example, n operator sub-circuit groups 21 first simultaneously perform n operations out of the m operations in the current algorithm step. Then, n operator sub-circuit groups 21 simultaneously perform mn operations out of the m operations in the current algorithm step. After all m operations in the current algorithm step have been performed, n operator sub-circuit groups 21 perform the m operations of the next algorithm step according to the above rules until the calculation result of the preset algorithm is obtained. When n operator sub-circuit groups 21 simultaneously perform n operations out of the m operations in the algorithm step, each of the n operator sub-circuit groups 21 performs one operation.

[0065] In this embodiment, m is greater than n, or m is equal to n.

[0066] When m is equal to n, the number of operations in each algorithm step in the preset algorithm is the same as the number of operation sub-circuit groups 21 in the operation circuit 20 .

[0067] For example, if m equals n equals 2, then f q Taking the power algorithm as an example, f q Each algorithm step in the power algorithm includes two operations. Accordingly, the operation circuit 20 includes two identical operation sub-circuit groups 21. Then the operation circuit 20 calculates the value of the input pair f according to the input pair f. q When the power algorithm is operated, the two operation sub-circuit groups simultaneously perform the two operations of the first algorithm step, and then simultaneously perform the two operations of the second algorithm step, and so on, until the two operation sub-circuit groups simultaneously perform the two operations of the sixth algorithm step, and obtain f q The result of the power algorithm.

[0068] When m is greater than n, the number of operations in each algorithm step in the preset algorithm is greater than the number of operation sub-circuit groups 21 in the operation circuit 20 .

[0069] For example, if m is equal to 3 and n is equal to 2, taking a certain algorithm A as an example, algorithm A is decomposed into two algorithm steps, each of which includes three operations; and the operation circuit 20 includes two identical operation sub-circuit groups 21. Then, when the operation circuit 20 operates on the algorithm A according to the input, the two operation sub-circuit groups 21 first simultaneously perform the two operations in the first algorithm step, and then any one of the two operation sub-circuit groups 21 performs the remaining operation in the first algorithm step. Then, the two operation sub-circuit groups 21 first simultaneously perform the two operations in the second algorithm step, and then any one of the two operation sub-circuit groups 21 performs the remaining operation in the second algorithm step to obtain the operation result of algorithm A.

[0070] Compared with the prior art in which m operations in an algorithm step are performed sequentially, when m is equal to n, the m operations in an algorithm step can be completed simultaneously, so that the operation speed of the preset algorithm can be increased by m times; when m is greater than n, the n operations in an algorithm step can be completed simultaneously, so that the operation speed of the preset algorithm can be increased, even by n times.

[0071] In the technical solution of the above embodiment, the algorithm engine includes an input circuit, an operation circuit, and an output circuit. The operation circuit is used to operate the preset algorithm according to the input to obtain the operation result of the preset algorithm. Each of the multiple algorithm steps of the preset algorithm includes m operations, and the operation circuit includes n identical operation sub-circuit groups, which are used to perform the m operations in each algorithm step. Wherein, m and n are both integers greater than 1, and m is greater than or equal to n. Therefore, at least n of the m operations of the same algorithm step can be executed by n operation sub-circuit groups at the same time, and the m operations do not need to be executed sequentially, so that the operation speed is faster, the operation efficiency can be improved, and the operation time can be saved, thereby effectively improving the operation performance of the algorithm engine.

[0072] In some embodiments, when m is equal to n, the n operation sub-circuit groups 21 simultaneously perform m operations in each algorithm step.

[0073] In this embodiment, when m is equal to n, n operator subcircuit groups 21 simultaneously perform m operations in each algorithm step. One operator subcircuit group 21 performs one operation. m and n can both be 2, 3, 4, or 5, and are not limited here.

[0074] In the technical solution of the above embodiment, when m is equal to n, the n operator sub-circuit groups can simultaneously perform m operations in each algorithm step, and the n operator sub-circuit groups can execute each algorithm step in sequence, thereby improving the operation efficiency and saving operation events.

[0075] In some feasible embodiments, when m is greater than n, the n operation sub-circuit groups 21 may first simultaneously perform n operations out of the m operations, and then simultaneously perform the remaining mn operations.

[0076] In some embodiments, each of the n operator sub-circuit groups 21 includes a base-field modular addition and subtraction sub-circuit 211 and a base-field modular multiplication sub-circuit 212, and / or a secondary extended-field modular addition and subtraction sub-circuit 213 and a secondary extended-field modular multiplication sub-circuit 214. The base-field modular addition and subtraction sub-circuit 211 is configured to perform a base-field modular addition or subtraction operation, and the base-field modular multiplication sub-circuit 212 is configured to perform a base-field modular multiplication operation. The secondary extended-field modular addition and subtraction sub-circuit 213 is configured to perform a secondary extended-field modular addition or subtraction operation, and the secondary extended-field modular multiplication sub-circuit 214 is configured to perform a secondary extended-field modular multiplication operation.

[0077] In this embodiment, each operator circuit group 21 may include a base-domain modulo addition and subtraction subcircuit 211 and a base-domain modulo multiplier circuit 212 (as shown in FIG2 ), may include a secondary extended-domain modulo addition and subtraction subcircuit 213 and a secondary extended-domain modulo multiplier circuit 214 (as shown in FIG3 ), or may include a base-domain modulo addition and subtraction subcircuit 211, a base-domain modulo multiplier circuit 212, a secondary extended-domain modulo addition and subtraction subcircuit 213, and a secondary extended-domain modulo multiplier circuit 214 (as shown in FIG4 ).

[0078] Each operation includes any one of base field modular addition, base field modular subtraction, base field modular multiplication, quadratic extended field modular addition, quadratic extended field modular subtraction, and quadratic extended field modular multiplication.

[0079] It is understood that when the operator subcircuit group 21 includes the base-field modular addition and modular subtraction subcircuit 211 and the base-field modular multiplication subcircuit 212, the operator subcircuit group 21 can simultaneously perform base-field modular addition and base-field modular multiplication operations, or simultaneously perform base-field modular subtraction and base-field modular multiplication operations. When the operator subcircuit group 21 includes the secondary extended-field modular addition and modular subtraction subcircuit 213 and the secondary extended-field modular multiplication subcircuit 214, the operator subcircuit group 21 can simultaneously perform secondary extended-field modular addition and secondary extended-field modular multiplication operations, or simultaneously perform secondary extended-field modular subtraction and secondary extended-field modular multiplication operations. In other words, one operator subcircuit group 21 can perform two operations simultaneously, i.e., perform two calculations simultaneously.

[0080] In the technical solution of the above embodiment, when each of the n operator circuit groups includes a base-domain modular addition and subtraction circuit and a base-domain modular multiplication circuit, the operation circuit includes n base-domain modular addition and subtraction circuits and n base-domain modular multiplication circuits; when each of the n operator circuit groups includes a quadratic extended-domain modular addition and subtraction circuit and a quadratic extended-domain modular multiplication circuit, the operation circuit includes n quadratic extended-domain modular addition and subtraction circuits and n quadratic extended-domain modular multiplication circuits; when each of the n operator circuit groups includes a base-domain modular addition and subtraction circuit, a base-domain modular multiplication circuit, a quadratic extended-domain modular addition and subtraction circuit, and a quadratic extended-domain modular multiplication circuit, the operation circuit includes n base-domain modular addition and subtraction circuits, n base-domain modular multiplication circuits, n quadratic extended-domain modular addition and subtraction circuits, and n quadratic extended-domain modular multiplication circuits. The arrangement of the subcircuits in the operation circuit can greatly increase the operation speed of the operation circuit while minimizing the increase in the circuit area of ​​the algorithm engine.

[0081] This application only describes the portion of the operation circuit 20 related to the circuit improvement of the algorithm engine 1. The operation circuit 20 may also include other circuits, such as a core algorithm subcircuit (not shown), an intermediate operation subcircuit (not shown), and a basic operation subcircuit (not shown). Of course, the operation circuit 20 of this application may also be part of the core algorithm subcircuit, the intermediate operation subcircuit, or the basic operation subcircuit.

[0082] The basic operator circuit may include n operator circuit groups 21 and a base-field modular inverse subcircuit (not shown). Each operator circuit group 21 in the basic operator circuit includes a base-field modular addition and subtraction subcircuit 211 and a base-field modular multiplication subcircuit 212.

[0083] The intermediate operator circuit may include n operator circuit groups 21, a quadratic extended-range modular division subcircuit (not shown), a quartic extended-range modular addition and subtraction subcircuit (not shown), a quartic extended-range modular multiplication circuit (not shown), a quartic extended-range modular division subcircuit (not shown), a twelfth extended-range modular multiplication circuit (not shown), and a twelfth extended-range modular inversion subcircuit (not shown). Each operator circuit group 21 in the intermediate operator circuit includes a quadratic extended-range modular addition and subtraction subcircuit 213 and a quadratic extended-range modular multiplication circuit 214.

[0084] The core algorithm subcircuit may include a bilinear pairing subcircuit (not shown in the figure), a twelve-fold extended-domain modular multiplication subcircuit (not shown in the figure), a twelve-fold extended-domain modular exponentiation subcircuit (not shown in the figure), a base-domain point addition subcircuit (not shown in the figure), a base-domain doubling subcircuit (not shown in the figure), a quadratic extended-domain point addition subcircuit (not shown in the figure), and a quadratic extended-domain doubling subcircuit (not shown in the figure).

[0085] It can be understood that the basic operator circuit includes n operator subcircuit groups 21 , or the intermediate operator circuit includes n operator subcircuit groups 21 , or both the basic operator circuit and the intermediate operator circuit include n operator subcircuit groups 21 .

[0086] In some feasible embodiments, the algorithm engine 1 further includes a command parsing circuit (not shown), which is electrically connected to the input circuit 10 and the operation circuit 20 respectively.

[0087] The input includes input signals and input parameters. The input signal is used to indicate the operation type. The command parsing circuit can send the input parameters to the core algorithm subcircuit, intermediate operation subcircuit or basic operation subcircuit of the operation circuit 20 according to the value of the current input signal.

[0088] Specifically, the input circuit 10 obtains the input of the preset algorithm in SM9 and sends the input to the command parsing circuit; the command parsing circuit parses the input signal in the input to obtain a parsing result, and sends the input parameters in the input to the operation circuit 20 according to the parsing result; the operation circuit 20 is used to operate the corresponding preset algorithm according to the input parameters to obtain the operation result of the preset algorithm, and send the operation result to the output circuit 30; the output circuit 30 is used to output the operation result.

[0089] In some feasible embodiments, the algorithm engine 1 includes an input circuit 10, a command parsing circuit, an operation circuit 20 and an output circuit 30. The operation circuit 20 includes a core algorithm subcircuit, an intermediate operation subcircuit and a basic operation subcircuit. The basic operator circuits include two base-field modular addition and modular subtraction circuits 211, two base-field modular multiplier circuits 212 and one base-field modular inversion circuit; the intermediate operator circuits include two quadratic extended-field modular addition and modular subtraction circuits 213, two quadratic extended-field modular multiplier circuits 214, one quadratic extended-field modular division circuit, one quartic extended-field modular addition and modular subtraction circuit, one quartic extended-field modular multiplier circuit, one quartic extended-field modular division circuit, one twelfth extended-field modular multiplier circuit and one twelfth extended-field modular inversion circuit; the core algorithm subcircuit includes one bilinear pairing subcircuit, one twelfth extended-field modular multiplier circuit, one twelfth extended-field modular power subcircuit, one base-field point addition subcircuit, one base-field multiplication subcircuit, one quadratic extended-field point addition subcircuit and one quadratic extended-field multiplication subcircuit.

[0090] In some embodiments, SM9 includes bilinear pairing operation, twelve-times extended-field modular exponentiation operation, quadratic extended-field point addition operation, quadratic extended-field point doubling operation, base-field point addition operation and base-field point doubling operation, and the preset algorithm includes an algorithm of at least one of the bilinear pairing operation, twelve-times extended-field modular exponentiation operation, quadratic extended-field point addition operation, quadratic extended-field point doubling operation, base-field point addition operation and base-field point doubling operation.

[0091] In this embodiment, SM9 includes bilinear pairing operation, twelve-times extended-range modular exponentiation operation, quadratic extended-range point addition operation, quadratic extended-range point doubling operation, base-range point addition operation, and base-range point doubling operation. The preset algorithms may include the gU, V(Q) algorithm, gV, V(Q) algorithm, and f in the bilinear pairing operation. q The power algorithm may include the fourth extended-field modular multiplication algorithm in the twelve extended-field modular exponentiation operation, may include at least one of the quadratic extended-field point addition algorithm in the quadratic extended-field point addition operation, the quadratic extended-field point doubling algorithm in the quadratic extended-field point doubling operation, the base-field point addition algorithm in the base-field point addition operation, and the base-field point doubling algorithm in the base-field point doubling operation, and may also include the gU, V(Q) algorithm, the gV, V(Q) algorithm, and the f in the bilinear pairing operation. q The exponentiation algorithm, the quartic extended-field modular multiplication algorithm in the twelve-fold extended-field modular exponentiation operation, the quadratic extended-field point addition algorithm in the quadratic extended-field point addition operation, the quadratic extended-field point doubling algorithm in the quadratic extended-field point doubling operation, the base-field point addition algorithm in the base-field point addition operation, and the base-field point doubling algorithm in the base-field point doubling operation. The quartic extended-field modular multiplication algorithm is derived by decomposing the twelve-fold extended-field modular exponentiation operation.

[0092] Among them, since bilinear pairing operations and twelve-times extended-field modular exponentiation operations are necessary operations in the digital signature algorithm, key exchange protocol, key encapsulation mechanism and encryption algorithm, the algorithm engine 1 can complete the digital signature algorithm, key exchange protocol, key encapsulation mechanism and encryption algorithm specified in the SM9 identification cryptographic algorithm.

[0093] In the technical solution of the above embodiment, since the bilinear pairing operation and the twelve-times extended-field modular exponentiation operation in SM9 are necessary in the digital signature algorithm, key exchange protocol, key encapsulation mechanism and encryption algorithm, and are the most time-consuming operations among all core algorithms, the preset algorithm includes the algorithm in the bilinear pairing operation and / or the twelve-times extended-field modular exponentiation operation, which can greatly improve the computing performance of the digital signature algorithm, key exchange protocol, key encapsulation mechanism and encryption and decryption using the SM9 identification algorithm. At the same time, the quadratic extended-field point addition operation, the quadratic extended-field doubling operation, the base-field point addition operation and the base-field doubling operation are the basic operations in SM9. Therefore, the preset algorithm includes the algorithm in at least one of the quadratic extended-field point addition operation, the quadratic extended-field doubling operation, the base-field point addition operation and the base-field doubling operation, which can also improve the computing speed of SM9, improve computing efficiency, save computing time, and effectively improve the computing performance of the algorithm engine 1.

[0094] In some embodiments, a preset algorithm is operated according to the input to obtain the operation result of the preset algorithm, including: converting the input from an affine coordinate system to a Jacobi weighted projection coordinate system, and operating the preset algorithm according to the input to obtain the operation result of the preset algorithm.

[0095] In this embodiment, when the calculation circuit 20 calculates the preset algorithm based on the input, it can convert the input from the affine coordinate system to the Jacobian weighted projection coordinate system, and calculate the preset algorithm in the Jacobian weighted projection coordinate system. The calculation result can include the co-output in the Jacobian weighted projection coordinate system.

[0096] Specifically, the embodiment of the present application performs bilinear pairing operations on the gU, V(Q) algorithm, gV, V(Q) algorithm, and f q The power algorithm and the four-times extended-field modular multiplication algorithm in the twelve-times extended-field modular exponentiation operation are deeply decomposed and reconstructed to obtain algorithm steps corresponding to each preset algorithm.

[0097] The decomposition of the gU,V(Q) algorithm is shown in Table 1. The operation circuit 20 includes two identical operator circuit groups 21. The two identical operator circuit groups 21 each include a quadratic extended-range modulo addition and subtraction subcircuit 213 and a quadratic extended-range modulo multiplication circuit 214.

[0098] Table 1 Decomposition of gU,V(Q) algorithm

[0099] The gU,V(Q) algorithm is decomposed into 13 algorithm steps: Step 1, Step 2, Step 3, Step 4, Step 5, Step 6, Step 7, Step 8, Step 9, Step 10, Step 11, Step 12, and Step 13. Among them, Step 1, Step 2, Step 3, Step 4, Step 5, Step 6, Step 7, Step 8, Step 9, Step 10, Step 11, and Step 12 each include 2 operations, and Step 13 includes 1 operation.

[0100] The input of the gU,V(Q) algorithm includes U, V and Q, and the calculation results of the gU,V(Q) algorithm include Rx, Ry, Rz, g_1_2, g_3_4 and g_11_12. U includes Ux, Uy and Uz; V includes Vx, Vy and Vz; Q includes Qx and Qy. Among them, U and V are elements on the quadratic extension field, Q is an element on the base field; g_1_2, g_3_4 and g_11_12 are the co-outputs in the Jacobi weighted projection coordinate system. The elements on the base field are 256-bit numbers, and the elements on the quadratic extension field are composed of two elements on the base field. Rx=(Uz 3 ·Vy-Uy) 2 -(Uz 2 Vx-Ux) 3 -2·Ux·(Uz2 Vx-Ux) 2 Ry={Ux·(Uz 2 Vx-Ux) 2 -[(Uz 3 ·Vy-Uy) 2 -(Uz 2 Vx-Ux) 3 -2Ux(Uz 2 Vx-Ux) 2 ]}·(U z 3 ·Vy-Uy)-Uy·(Uz 2 Vx-Ux) 3 Rz=Uz·(Uz 2 ·Vx-Ux). g_1_2=Uz·(Uz 2 ·Vx-Ux)·Qy·{1,0}. g_3_4=Vx·(Uz 3 ·Vy-Uy)-Vy·Uz·(Uz 2 ·Vx-Ux). g_11_12=Qx·(Uy-Uz 3 ·Vy).

[0101] Since U and V are elements on the quadratic extended domain, the operations of the algorithm steps in the gU,V(Q) algorithm are all performed by the quadratic extended domain modular addition and modular subtraction subcircuit 213 and the quadratic extended domain modular multiplication subcircuit 214. For example, the operation Uz in Step 1 2 The operation Uz in Step 3 is performed by the quadratic extended-domain modular multiplier circuit 214. 2 Vx-Ux is performed by the secondary extended-range modulus-addition-modulus-subtraction subcircuit 213 .

[0102] It can be understood that, when performing the operations of quadratic extended-domain modular addition, quadratic extended-domain modular subtraction, and quadratic extended-domain modular multiplication according to the above algorithm steps, any two of the three operations can be performed simultaneously, thereby nearly doubling the operation speed of the gU,V(Q) algorithm.

[0103] The decomposition of the gV,V(Q) algorithm is shown in Table 2. The operation circuit 20 includes two identical operator circuit groups 21. The two identical operator circuit groups 21 each include a quadratic extended-range modulo addition and subtraction subcircuit 213 and a quadratic extended-range modulo multiplication circuit 214.

[0104] Table 2 gV,V(Q) algorithm decomposition

[0105] The gV,V(Q) algorithm is decomposed into 15 algorithm steps: Step 1, Step 2, Step 3, Step 4, Step 5, Step 6, Step 7, Step 8, Step 9, Step 10, Step 11, Step 12, Step 13, Step 14, and Step 15. Among them, Step 1, Step 2, Step 3, Step 4, Step 5, Step 6, Step 7, Step 8, Step 9, Step 10, Step 11, Step 12, Step 13, and Step 14 each include 2 operations, and Step 15 includes 1 operation.

[0106] The inputs to the gV,V(Q) algorithm include V and Q. The results of the gV,V(Q) algorithm include Rx, Ry, Rz, g_1_2, g_3_4, and g_11_12. V includes Vx, Vy, and Vz, and Q includes Qx and Qy. V is an element on the quadratic extension domain, and Q is an element on the base domain. g_1_2, g_3_4, and g_11_12 are the co-outputs in the Jacobi weighted projection coordinate system. Rx = 9Vx 4 -4VxVy 2 Ry=3Vx 2 ·(VxVy 2 -9Vx 4 )-8Vy 4 . Rz=2VyVz. g_1_2=2VyVz 3 Qy·{1,0}. g_3_4=3Vx 3 -2Vy 2 g_11_12=-3Vx 2 VZ 2 Qx.

[0107] Since V is an element on the quadratic extended domain, the operations of the algorithm steps in the gV,V(Q) algorithm are all performed by the quadratic extended domain modulo addition and modulo subtraction subcircuit 213 and the quadratic extended domain modulo multiplication subcircuit 214. For example, the operation 2Vy in Step 6 4 The operation 9Vx in Step 6 is performed by the quadratic extended-range modular multiplier circuit 214. 4 -4VxVy 2 It is performed by the secondary extended-range mode-addition-mode-subtraction subcircuit 213 .

[0108] It can be understood that, by performing operations according to the above algorithm steps, when executing the three operations of quadratic extended-domain modular addition, quadratic extended-domain modular subtraction, and quadratic extended-domain modular multiplication, any two of the three operations can be executed simultaneously, thereby speeding up the operation of the gV,V(Q) algorithm by nearly one-fold.

[0109] f q The decomposition of the power algorithm is shown in Table 3. The operation circuit 20 includes two identical operator circuit groups 21. The two identical operator circuit groups 21 both include a base field modular addition and subtraction subcircuit 211 and a base field modular multiplication subcircuit 212.

[0110] Table 3f q Power algorithm decomposition

[0111] f q The power algorithm is decomposed into six algorithm steps: Step 1, Step 2, Step 3, Step 4, Step 5, and Step 6. Each algorithm step includes two operations.

[0112] f q The input of the power algorithm includes g, sel, c, f q The result of the power algorithm includes w. Here, g and w are both elements on the twelve-power extended domain; sel is the input signal used to select the 1st, 2nd, 3rd, or 6th power of q; and c is a pre-stored parameter that can be a fixed value.

[0113] g includes g_0, g_1, g_2, g_3, g_4, g_5, g_6, g_7, g_8, g_9, g_10, and g_11, c includes c_0, c_1, c_2, c_3, c_4, c_5, c_6, c_7, c_8, c_9, c_10, and c_1. w = g·c, accordingly, w includes g_0·c_0, g_1·c_1, g_2·c_2, g_3·c_3, g_4·c_4, g_5·c_5, g_6·c_6, g_7·c_7, g_8·c_8, g_9·c_9, g_10·c_10, and g_11·c_11. Among them, g_0, g_1, g_2, g_3, g_4, g_5, g_6, g_7, g_8, g_9, g_10 and g_11 are all elements on the base domain.

[0114] Since g consists of 12 base field elements, f q The operations in the algorithm steps of the power algorithm are all performed by the base field modular addition and subtraction subcircuit 211 and the base field modular multiplication subcircuit 212. For example, the operation g_0·c_0 in Step 1 is performed by the base field modular multiplication subcircuit 212.

[0115] It can be understood that, when performing the operations of base field modular addition, base field modular subtraction and base field modular multiplication according to the above algorithm steps, any two of the three operations can be performed simultaneously, thereby converting f q The power algorithm operates twice as fast.

[0116] The decomposition of the quartic extended-range modular multiplication algorithm is shown in Table 4. The operation circuit 20 includes two identical operator circuit groups 21. The two identical operator circuit groups 21 each include a quadratic extended-range modular addition and subtraction subcircuit 213 and a quadratic extended-range modular multiplication subcircuit 214.

[0117] Table 4 Decomposition of the quartic extended-domain modular multiplication algorithm

[0118] The quartic extended-field modular multiplication algorithm is decomposed into five algorithm steps: Step 1, Step 2, Step 3, Step 4, and Step 5. Step 1, Step 2, Step 3, and Step 4 each include two operations, and Step 5 includes one operation.

[0119] The inputs to the quartic extended-field modular multiplication algorithm include a and b, and the result is c. a, b, and c are all elements of the quartic extended field, a consists of a0 and a1, b consists of b0 and b1, and c consists of c_0 and c_1. a0, a1, b0, and b1 are all elements of the quadratic extended field. c_0 = a0b0 + θa1b1. c_1 = (a1 + a0)(b1 + b0) - (a0b0 + a1b1).

[0120] Because both a and b consist of two elements in the quadratic extended-range, the algorithm steps in the quartic extended-range modular multiplication algorithm are performed by quadratic extended-range modular addition and subtraction subcircuit 213 and quadratic extended-range modular multiplication subcircuit 214. For example, the operation a0b0 in Step 1 is performed by quadratic extended-range modular multiplication subcircuit 214, and the operation a0+a1 in Step 2 is performed by quadratic extended-range modular addition and subtraction subcircuit 213.

[0121] It can be understood that, when performing operations according to the above algorithm steps, any two of the three operations of quadratic extended-domain modular addition, quadratic extended-domain modular subtraction, and quadratic extended-domain modular multiplication can be performed simultaneously, thereby doubling the operation speed of the quadratic extended-domain modular multiplication algorithm.

[0122] In this embodiment, the quartic extended-range modular multiplication algorithm serves as an intermediate algorithm for the other algorithms in SM9. That is, the other algorithms in SM9 perform operations based on the results of the quartic extended-range modular multiplication algorithm. Therefore, when the quartic extended-range modular multiplication algorithm is accelerated, the operation speed of the other algorithms will also increase accordingly.

[0123] The steps of each preset algorithm can be executed sequentially or according to the actual computational process, without limitation. For example, the gU,V(Q) algorithm can be executed sequentially in Step 1, Step 2, Step 3, Step 4, Step 5, Step 6, Step 7, Step 8, Step 9, Step 10, Step 11, and Step 12 to obtain g_1_2. Alternatively, Step 1, Step 2, Step 3, and Step 5 can be executed sequentially, followed by Step 11 and Step 12 to obtain g_1_2.

[0124] In the above-mentioned embodiment, since the quartic extended-field modular multiplication algorithm is the basis for many high-order operations, its computational speed is crucial to the overall performance of the SM9. Improving the computational speed of the quartic extended-field modular multiplication algorithm significantly increases the computational speed of the bilinear pairing operation and the twelve-fold extended-field modular exponentiation operation within the algorithm engine.

[0125] The secondary expansion domain point addition algorithm in the secondary expansion domain point addition operation, the secondary expansion domain point doubling algorithm in the secondary expansion domain point doubling operation, the base domain point addition algorithm in the base domain point addition operation, and the base domain point doubling algorithm in the base domain point doubling operation can also be decomposed and reconstructed to obtain the corresponding algorithm steps.

[0126] In some embodiments, the operation result is at least part of the step results of multiple algorithm steps.

[0127] In this embodiment, each algorithm step includes m step results, that is, each operation corresponds to one step result. The operation result is part of the step results of multiple algorithm steps, or the operation result is all the step results of multiple algorithm steps. For example, the operation result of the gU,V(Q) algorithm is 6 step results out of the 27 step results of the corresponding 13 algorithm steps, such as Rx is the step result of the first operation of Step 9, Ry is the step result of the operation of Step 13, Rz is the step result of the second operation of Step 5, g_1_2 is the step result of the first operation of Step 12, g_3_4 is the step result of the second operation of Step 9, and g_11_12 is the step result of the second operation of Step 11; the operation result of the gV,V(Q) algorithm is 6 step results out of the 29 step results of the corresponding 15 algorithm steps, such as Rx is the step result of the second operation of Step 6, Ry is the step result of the first operation of Step 12, Rz is the step result of the first operation of Step 10, g_1_2 is the step result of the first operation of Step 14, g_3_4 is the step result of the second operation of Step 12, and g_11_12 is the step result of the second operation of Step 15;q The result of the power algorithm is the result of all 12 steps in the corresponding 6 algorithm steps; the result of the quartic extended-field modular multiplication algorithm is the result of 2 steps in the 9 steps in the corresponding 5 algorithm steps, for example, c_0 is the result of the first operation in Step 4; c_1 is the result of the operation in Step 5.

[0128] In some embodiments, the preset algorithm includes a first algorithm and a second algorithm, the first algorithm is decomposed into a first number of algorithm steps, and the second algorithm is decomposed into a second number of algorithm steps, the first number and the second number are different.

[0129] In this embodiment, the preset algorithm includes a first algorithm with a first number of algorithm steps and a second algorithm with a second number of algorithm steps, wherein the first number and the second number are different. It is understandable that different preset algorithms have different decomposition methods. For example, the gU, V(Q) algorithm includes 13 algorithm steps, the gV, V(Q) algorithm includes 15 algorithm steps, and the f q The power algorithm includes 6 algorithm steps, and the quartic extended-field modular multiplication algorithm includes 5 algorithm steps.

[0130] Please refer to FIG5 , which is a schematic diagram of the framework of the security chip provided by the embodiment of the present application. The security chip 2 includes an algorithm engine 1 .

[0131] The specific structure of the algorithm engine 1 refers to the above embodiment. Since the security chip 2 adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described in detail here.

[0132] Please refer to Figure 6, which is a schematic diagram of the framework of an electronic device provided in an embodiment of the present application. The electronic device 3 includes a security chip 2.

[0133] The specific structure of the security chip 2 is referred to the above embodiment. Since the electronic device 3 adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described in detail here.

[0134] Please refer to Figure 7, which is a flow chart of the encryption method provided in an embodiment of the present application. The encryption method is applied to SM9 and specifically includes the following steps.

[0135] Step S102: performing calculations on the preset algorithm in SM9 to achieve encryption.

[0136] In this embodiment, the encryption method can be applied to scenarios such as electronic identity authentication, electronic signature, and encrypted communication, and the relevant information is encrypted by performing calculation operations on the relevant information according to the preset algorithm in SM9. The calculation operations are implemented by the algorithm engine 1.

[0137] The specific process of the algorithm engine 1 implementing the operation operation is referred to the above embodiment. Since the encryption method adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described in detail here.

[0138] Those skilled in the art will understand that in the above-mentioned method of the specific implementation method, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0139] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0140] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.

[0141] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device implementation methods described above are only schematic. For example, the division of modules or units is only a logical function division. There may be other division methods in actual implementation. For example, units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0142] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0143] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server or network device, etc.) or a processor to execute all or part of the steps of the various implementation methods of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

Claims

1. An algorithm engine, characterized in that: Applicable to SM9, including: An input circuit, used to obtain input of a preset algorithm in the SM9; an operation circuit, configured to operate the preset algorithm according to the input to obtain an operation result of the preset algorithm; An output circuit, configured to output the operation result; The preset algorithm is decomposed into a plurality of algorithm steps, and each of the plurality of algorithm steps includes m operations; The operation circuit includes n identical operation sub-circuit groups for performing the m operations in each algorithm step, wherein m and n are integers greater than 1, and m is greater than or equal to n.

2. The algorithm engine according to claim 1, characterized in that: When m is equal to n, the n operation sub-circuit groups simultaneously perform the m operations in each algorithm step.

3. The algorithm engine according to claim 1 or 2, characterized in that: Each of the n operator sub-circuit groups includes: a base-field modular addition and subtraction subcircuit and a base-field modular multiplier subcircuit, wherein the base-field modular addition and subtraction subcircuit is used to perform a base-field modular addition or a base-field modular subtraction operation, and the base-field modular multiplier circuit is used to perform a base-field modular multiplication operation; and / or A secondary extended-range modular addition and subtraction subcircuit and a secondary extended-range modular multiplier circuit, wherein the secondary extended-range modular addition and subtraction subcircuit is used to perform a secondary extended-range modular addition or a secondary extended-range modular subtraction operation, and the secondary extended-range modular multiplier circuit is used to perform a secondary extended-range modular multiplication operation.

4. The algorithm engine according to claim 1 or 2, characterized in that: The SM9 includes bilinear pairing operation, twelve-times extended-domain modular exponentiation operation, quadratic extended-domain point addition operation, quadratic extended-domain point doubling operation, base-domain point addition operation and base-domain point doubling operation; The preset algorithm includes an algorithm of at least one of the bilinear pairing operation, the twelve-order extended-field modular exponentiation operation, the quadratic extended-field point addition operation, the quadratic extended-field point doubling operation, the base-field point addition operation, and the base-field point doubling operation.

5. The algorithm engine according to claim 4, characterized in that: The operation result is at least part of the step results of the multiple algorithm steps.

6. The algorithm engine according to claim 4, characterized in that: The preset algorithm includes a first algorithm and a second algorithm, the first algorithm is decomposed into a first number of algorithm steps, the second algorithm is decomposed into a second number of algorithm steps, and the first number and the second number are different.

7. The algorithm engine according to claim 1, characterized in that: The performing operation on the preset algorithm according to the input to obtain an operation result of the preset algorithm includes: The input is converted from an affine coordinate system to a Jacobi weighted mapping coordinate system, so as to operate the preset algorithm according to the input to obtain an operation result of the preset algorithm.

8. A security chip, characterized in that: Comprising an algorithm engine as described in any one of claims 1-7.

9. An electronic device, characterized in that: Comprising the security chip as claimed in claim 8.

10. An encryption method, characterized in that: Applicable to SM9, including: Performing an operation on the preset algorithm in the SM9 to achieve encryption, wherein the operation is implemented by the algorithm engine according to any one of claims 1 to 7.

Images