Preparation method for heterojunction solar cell, and heterojunction solar cell

Abstract

The present application relates to the field of solar cell preparation, and discloses a preparation method for a heterojunction solar cell, and a heterojunction solar cell. The preparation method for a heterojunction solar cell comprises: providing a silicon substrate, and performing texturing treatment on a light receiving surface and a backlight surface of the silicon substrate; forming a mask layer on the light receiving surface; removing the mask wrapping plating on the backlight surface; performing fine treatment on the backlight surface, so that the backlight surface is formed into a surface having a microstructure; removing the mask layer; respectively forming a first intrinsic passivation layer and a second intrinsic passivation layer on the light receiving surface and the backlight surface; and respectively forming a first conductive type doped layer and a second conductive type doped layer on the first intrinsic passivation layer and the second intrinsic passivation layer, wherein the second conductive type doped layer comprises a plurality of second sub-doped layers which are stacked, and the refractive indexes of the second sub-doped layers are different. The present application can improve the uniformity and flatness of the back surface and reduce the reflectivity of the back surface, thereby improving the double-sided rate and improving the back surface efficiency of the cell.

Description

Preparation method of heterojunction solar cell and heterojunction solar cell Technical Field

[0001] The present application belongs to the technical field of solar cell preparation, and specifically relates to a preparation method of a heterojunction solar cell and a heterojunction solar cell. Background Art

[0002] As a new type of high-efficiency solar cell, heterojunction solar cells have become a new hot topic in the photovoltaic field in recent years. They have the advantages of simple structure, simple process, high conversion efficiency, high open-circuit voltage, and low temperature coefficient. The existing single-sided texturing method of heterojunction solar cells usually adopts a double-sided conventional texturing silicon wafer, then deposits a protective layer on the front side, and then uses an alkaline solution to corrode and polish the pyramid surface on the back side of the silicon wafer without the protective layer to form a flat surface. The protective layer on the front side is then removed to obtain a single-sided texturing silicon wafer with a pyramid textured surface on the front side and a polished flat surface on the back side. However, when the protective layer is deposited on the front side of the silicon wafer, the wrap-around plating phenomenon will inevitably occur. The wrap-around protective layer will cover the textured surface on the back side, causing it to not be processed during backlight polishing, and ultimately resulting in the presence of textured surface on the back side, which in turn makes the morphology of the back side of the silicon wafer uneven. The uneven morphology of the back side of the silicon wafer can lead to insufficient or excessive local passivation, which seriously affects the open-circuit voltage and series resistance of the heterojunction cell. It can also affect the film quality and uniformity of the subsequent intrinsic passivation layer and doping layer, that is, it affects the stability of the effect of the intrinsic passivation layer and doping layer.

[0003] In addition, although the stability of the effects of the intrinsic passivation layer and the doping layer can be ensured by improving the uniformity of the back surface morphology of the silicon wafer, the reflectivity of the back surface will also be increased, the optical utilization rate will be low, the short-circuit current will be low, and the double-sidedness will be reduced, such as the double-sidedness is only 70% to 80%.

[0004] Therefore, there is an urgent need to find effective technical solutions to solve or alleviate one or more of the above problems. Summary of the Invention

[0005] In view of the above-mentioned problems, the present invention aims to at least partially solve one of the technical problems in the related art. To this end, the present invention provides a method for preparing a heterojunction solar cell and a heterojunction solar cell, which are primarily used to alleviate the problems of poor backside structural uniformity or low bifaciality of the cell. The method can improve the uniformity and flatness of the backside, reduce the backside reflectivity, and increase the bifaciality of the cell.

[0006] In order to solve the above technical problems, this application is implemented as follows:

[0007] According to one aspect of the present application, an embodiment of the present application provides a method for preparing a heterojunction solar cell, the method comprising:

[0008] Providing a silicon substrate and performing texturing on the light-receiving surface and the backlight surface of the silicon substrate;

[0009] forming a mask layer on the textured surface of the light-receiving surface of the silicon substrate;

[0010] removing the mask wrap on the backlight surface of the silicon substrate by using a de-wrap solution;

[0011] Performing fine processing on the backlight surface of the silicon substrate so that the backlight surface of the silicon substrate is formed into a surface with a microstructure;

[0012] removing the mask layer;

[0013] forming a first intrinsic passivation layer and a second intrinsic passivation layer on the light-receiving surface and the backlight surface of the silicon substrate respectively;

[0014] A first conductive type doped layer and a second conductive type doped layer are formed on the first intrinsic passivation layer and the second intrinsic passivation layer, respectively, wherein the second conductive type doped layer includes a plurality of second sub-doped layers stacked together, and the refractive index of each second sub-doped layer is different.

[0015] In addition, the method for preparing a heterojunction solar cell according to the present application may also have the following additional technical features:

[0016] In some embodiments, the mask layer satisfies at least one of the following characteristics:

[0017] The method of forming the mask layer includes one or more of plate-type PECVD, tubular PECVD or PVD;

[0018] The mask layer includes at least one of silicon oxide, silicon nitride or silicon oxynitride;

[0019] The refractive index of the mask layer is 1.6 to 1.8;

[0020] The thickness of the mask layer is 20nm to 200nm.

[0021] In some embodiments, the de-wrap solution comprises a mixed solution consisting of alkali, hydrogen peroxide, and water;

[0022] Optionally, in the mixed solution, the mass percentage of the alkali is 1% to 10%, the mass percentage of the hydrogen peroxide is 5% to 30%, and the mass percentage of the water is 60% to 94%;

[0023] Optionally, the base includes at least one of sodium hydroxide or potassium hydroxide;

[0024] Optionally, the mass concentration of the hydrogen peroxide is 10wt% to 50wt%.

[0025] In some embodiments, the temperature of removing the mask on the backlight surface of the silicon substrate during the plating process is 40° C. to 80° C., and the time is 150 seconds to 300 seconds.

[0026] In some embodiments, the fine processing of the backlight surface of the silicon substrate specifically includes:

[0027] Treating the backlight surface of the silicon substrate with an alkaline solution at a temperature of 40° C. to 80° C. for 100 seconds to 600 seconds;

[0028] Optionally, the alkaline solution includes at least one of a potassium hydroxide solution or a sodium hydroxide solution;

[0029] Optionally, the mass percentage concentration of the alkaline solution is 1% to 60%.

[0030] In some embodiments, removing the mask layer specifically includes:

[0031] Using an acidic solution at a temperature of 25°C to 45°C, the mask layer is removed;

[0032] Optionally, the acidic solution includes at least one of hydrofluoric acid or hydrochloric acid;

[0033] Optionally, the mass percentage concentration of the acidic solution is 5% to 10%.

[0034] In some embodiments, the second conductive type doped layer satisfies at least one of the following characteristics:

[0035] The number of layers of the second sub-doped layer is three or more;

[0036] The refractive index of each of the second sub-doped layers gradually decreases along a direction from approaching the second intrinsic passivation layer to away from the second intrinsic passivation layer;

[0037] The total refractive index of the second conductive type doped layer is in the range of 2.8 to 3.8;

[0038] The refractive index of the second sub-doped layer close to the second intrinsic passivation layer is 3.5-3.8, and the refractive index of the second sub-doped layer far from the second intrinsic passivation layer is 2.8-3.1;

[0039] The total thickness of the second conductive type doped layer is 5 nm to 50 nm;

[0040] The thickness of the second sub-doping layer is 0.5 nm to 5 nm.

[0041] In some embodiments, the preparation method satisfies at least one of the following characteristics:

[0042] The first intrinsic passivation layer and the second intrinsic passivation layer include a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer, respectively;

[0043] The silicon substrate is an N-type silicon substrate, the first conductive type doped layer is an amorphous silicon or microcrystalline silicon layer doped with a Group VA element, and the second conductive type doped layer is an amorphous silicon or microcrystalline silicon layer doped with a Group IIIA element;

[0044] Alternatively, the second conductive type doped layer is an oxygen-doped microcrystalline silicon layer doped with a Group IIIA element.

[0045] In some embodiments, after forming the first conductivity type doped layer and the second conductivity type doped layer, the method further includes:

[0046] forming a first transparent conductive layer on the first conductive type doped layer, and forming a second transparent conductive layer on the second conductive type doped layer;

[0047] A first electrode is formed on the first transparent conductive layer, and a second electrode is formed on the second transparent conductive layer.

[0048] According to another aspect of the present application, an embodiment of the present application provides a heterojunction solar cell, wherein the heterojunction solar cell is manufactured using the aforementioned method for manufacturing a heterojunction solar cell, and the heterojunction solar cell comprises:

[0049] A silicon substrate, comprising a light-receiving surface and a backlight surface that are oppositely disposed;

[0050] The light receiving surface has a suede structure, and a first intrinsic passivation layer, a first conductive type doping layer, a first transparent conductive layer and a first electrode are sequentially arranged on the suede structure;

[0051] The backlight surface has a microstructured surface, and a second intrinsic passivation layer, a second conductive type doped layer, a second transparent conductive layer and a second electrode are sequentially arranged on the surface of the microstructure; wherein the second conductive type doped layer includes a plurality of second sub-doped layers stacked together, and the refractive index of each layer of the second sub-doped layer is different.

[0052] The implementation of the technical solution of the present invention has at least the following beneficial effects:

[0053] (1) After forming a mask layer on the light-receiving surface of the silicon substrate, the present invention uses a de-coating solution to remove the mask coating on the backlight surface, thereby achieving the removal of the backside coating layer without affecting the protective effect of the mask layer on the light-receiving surface, improving the uniformity and flatness of the backlight surface morphology, ensuring the stability of the subsequent deposition of heterojunction passivation layers, doping layers and other structures on the backlight surface, improving the film quality and uniformity of the second intrinsic passivation layer and the second conductive type doping layer, and also improving the crystallization rate of the second conductive type doping layer.

[0054] (2) The second conductive type doping layer of the present invention includes a second sub-doping layer stacked in multiple layers, and the refractive index of each second sub-doping layer is different. By setting up multiple second sub-doping layers with different refractive indices, while ensuring conductivity, the optical band gap can be further widened, effectively reducing the reflection of light at the interface, thereby reducing the reflectivity of the backlight surface, solving the problem of low anti-reflection effect of the backlight surface structure, and increasing the short-circuit current, thereby effectively improving the bifaciality of the battery and further improving the backlight surface efficiency.

[0055] (3) The present invention performs fine processing on the backlight surface of the silicon substrate, so that the backlight surface of the silicon substrate is formed into a surface with a microstructure, which can increase the passivation effect. Compared with the ordinary velvet surface, the surface with a microstructure has a better anti-epitaxial passivation effect, which can make the battery cell show a Voc gain effect of at least 1mV, thereby increasing the battery performance, reducing the coating process cavity, and saving equipment costs.

[0056] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] FIG1 is a schematic flow chart of a method for preparing a heterojunction solar cell according to some exemplary embodiments of the present application;

[0058] FIG2 is a schematic diagram of a single-side texturing process according to some exemplary embodiments of the present application;

[0059] FIG3 is a schematic flow chart of a method for preparing a heterojunction solar cell according to some other exemplary embodiments of the present application;

[0060] FIG4 is a topographical image of the back surface of the unmasked wrap-around layer and the unmasked wrap-around layer after refinement treatment according to Example 1 of the present invention (in FIG4 , the upper portion shows the unmasked wrap-around layer, and the lower portion shows the unmasked wrap-around layer);

[0061] FIG5 is a schematic diagram of scanning the backlight surface after removing the mask layer according to Example 1 of the present invention;

[0062] FIG6 is a schematic diagram of scanning a portion of the backlight surface where the back mask layer is not removed in Comparative Example 1 of the present invention;

[0063] FIG7 is a schematic diagram comparing the crystallization rates of the crystallites P of Example 1 of the present invention and Comparative Example 1 (in FIG7 , the polished surface crystallites P refer to the crystallization rate of the crystallites P of Example 1, and the partially textured surface crystallites P refer to the crystallization rate of the crystallites P of Comparative Example 1);

[0064] FIG8 is a schematic diagram comparing the conversion efficiency, open circuit voltage, short circuit current and fill factor of Example 1 of the present invention and Comparative Example 1;

[0065] FIG9 is a schematic structural diagram of a heterojunction solar cell provided by some exemplary embodiments of the present application;

[0066] FIG10 is a schematic structural diagram of a heterojunction solar cell provided in some other exemplary embodiments of the present application.

[0067] Description of reference numerals:

[0068] 10-silicon substrate;

[0069] 21 - first intrinsic passivation layer; 31 - first conductive type doped layer; 41 - first transparent conductive layer; 51 - first electrode;

[0070] 22 - second intrinsic passivation layer; 32 - second conductive type doping layer; 320 - second sub-doping layer; 321 - second sub-doping layer A; 322 - second sub-doping layer B; 323 - second sub-doping layer C; 324 - second sub-doping layer D; 42 - second transparent conductive layer; 52 - second electrode. DETAILED DESCRIPTION

[0071] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0072] In the related art, the single-sided texturing method of heterojunction solar cells usually adopts a double-sided conventional texturing silicon wafer, and uses plate-type or tube-type CVD, PVD and other equipment to deposit a layer of silicon oxide, silicon nitride or silicon oxynitride on the front side of the silicon wafer as a protective layer, and then uses an alkaline solution to corrode and polish the pyramid on the unprotected surface of the back side of the silicon wafer to form a flat surface, and then uses an acid solution to remove the silicon oxide or silicon nitride protective layer on the front side to obtain a single-sided texturing silicon wafer with a pyramid velvet surface on the front side and a polished flat surface on the back side. However, on the one hand, when using plate-type or tube-type CVD, PVD and other equipment to deposit a silicon oxide, silicon nitride or silicon oxynitride protective layer on the front side, the phenomenon of wrap-around plating is inevitable. The wrap-around protective layer of silicon nitride or the like will cover the velvet surface on the back side, causing it to not be processed during the polishing of the back side, and ultimately causing the velvet surface to partially exist on the back side. For bifacial microcrystalline heterojunction cells, the passivation effect of the intrinsic amorphous silicon layer is highly sensitive to substrate topography. Passivation conditions on the pyramid textured surface differ significantly from those on the polished surface. Non-uniformity in the backside topography of the silicon wafer can lead to localized under- or over-passivation, severely impacting the open-circuit voltage and series resistance of the heterojunction cell. More importantly, it has been found that heterojunction cell doping layers, such as the microcrystalline P layer, crystallize relatively easily on the polished surface. This microcrystalline P layer exhibits a higher overall crystallinity, better conductivity, and more uniform grain size. High-quality microcrystalline P layers deposited on a uniform surface significantly improve hole transport and collection in heterojunction cells. Therefore, a uniform and smooth silicon wafer surface topography on the backside of bifacial microcrystalline heterojunction cells is crucial for improving cell efficiency. Furthermore, even a small amount of wrap-around plating can cover the backside textured surface and affect polishing, significantly impacting process stability and yield in large-scale production of single-sided textured cells. Therefore, effectively removing wrap-around plating on the backside and improving backside uniformity and flatness are crucial.

[0073] On the other hand, while improving the uniformity and flatness of the backside topography of the silicon wafer, it also leads to higher backside reflectivity, resulting in lower backside current, a bifaciality of only 70% to 80%, and low backside cell efficiency. Therefore, it is necessary to resolve the conflicting issue of improving backside uniformity and flatness while reducing backside reflectivity, thereby effectively improving the bifaciality and backside efficiency of the cell.

[0074] In view of this, the technical solution of the embodiment of the present application provides a method for preparing a heterojunction solar cell and a heterojunction solar cell. The technical solution of the embodiment of the present application adds a step of cleaning and removing the back mask wrapping layer after depositing the mask protective layer on the front of the heterojunction single-sided texturing solar cell. By using a specific de-wrapping solution, such as an alkali + hydrogen peroxide solution of a certain concentration and ratio, after a certain period of treatment, it is possible to remove the back wrapping layer without affecting the protective effect of the front mask layer, thereby improving the uniformity and flatness of the back plane during the subsequent back processing; ensuring the stability of the effect of the subsequent back deposition of heterojunction passivation layer, doping layer and other structures. At the same time, by combining multiple layers of sub-doped layers with different refractive indices together, the advantages of the doped thin film layer can be maximized, while ensuring passivation, it can also improve effective absorption and effectively reduce the reflection of light at the interface, thereby effectively improving the cell bifaciality and back cell efficiency. That is, while improving the uniformity and flatness of the back morphology of the silicon wafer, the present application can also reduce the reflectivity of the back, increase the short-circuit current, and effectively improve the cell bifaciality and back cell efficiency. The specific technical solution is described below.

[0075] As shown in FIG. 1 to FIG. 10 , in some embodiments, a method for preparing a heterojunction solar cell is provided, the method comprising:

[0076] Providing a silicon substrate 10, the silicon substrate 10 includes two oppositely disposed surfaces along the thickness direction, namely, a light-receiving surface and a backlight surface, and performing texturing treatment on the light-receiving surface and the backlight surface of the silicon substrate;

[0077] forming a mask layer on the textured surface of the light-receiving surface of the silicon substrate;

[0078] Using a de-wrap solution, removing the mask wrap on the backlight surface of the silicon substrate;

[0079] Performing fine processing on the backlight surface of the silicon substrate so that the backlight surface of the silicon substrate is formed into a surface with a microstructure;

[0080] removing the mask layer;

[0081] Forming a first intrinsic passivation layer 21 and a second intrinsic passivation layer 22 on the light-receiving surface and the backlight surface of the silicon substrate respectively;

[0082] A first conductive type doping layer 31 and a second conductive type doping layer 32 are formed on the first intrinsic passivation layer 21 and the second intrinsic passivation layer 22, respectively. The second conductive type doping layer 32 includes a plurality of second sub-doping layers 320 stacked together, and the refractive index of each second sub-doping layer 320 is different.

[0083] The above-mentioned silicon substrate includes two opposite surfaces along the thickness direction, namely the front and back surfaces; the light-receiving surface (front surface) of the silicon substrate is the surface facing the sun, that is, the surface facing sunlight, and the backlight surface (back surface) of the silicon substrate is the surface facing away from the sun.

[0084] It should be understood that the preparation method of this embodiment is not limited to the specific type of silicon substrate (e.g., silicon wafer). For example, it can be a single crystal silicon substrate, a polycrystalline silicon substrate, or a quasi-single crystal silicon substrate. The silicon substrate can be P-type doped or N-type doped. In other words, the silicon substrate can be an N-type silicon wafer or a P-type silicon wafer. Optionally, in this embodiment, an N-type single crystal silicon wafer is selected as the silicon substrate.

[0085] After multiple experimental verifications, the inventors of the present application found that by removing the mask wrap plating on the backlight side of the silicon substrate through a de-wrap plating solution, compared with the case where the mask wrap plating on the backlight side is not removed, after the cell structure film layer is deposited on the single-sided textured cell with the velvet surface remaining on the back, due to the different passivation requirements of the velvet surface and the plane (or the plane with a microstructure), the pyramid velvet surface is more difficult to passivate than the plane under the same conditions, resulting in its minority carrier lifetime being only 1125 us; after removing the wrap plating on the back side, the backlight side is a completely plane or a plane with a microstructure, the uniformity and flatness of the backlight side are better, and the minority carrier lifetime of the cell is about 2516 us, which shows that the passivation effect of the single-sided textured heterojunction cell is significantly improved after removing the back wrap plating layer.

[0086] The inventors of this application also discovered that by removing the mask plating on the backlight side of the silicon substrate through the de-plating solution, the front structure of the double-sided microcrystalline single-sided textured heterojunction cell is basically the same as that of a conventional double-sided textured microcrystalline heterojunction cell. However, because the backlight side is a completely flat surface or a flat surface with a microstructure, the grown second conductivity type doped layer, such as the microcrystalline P layer, has higher crystallinity, better conductivity, and more uniform grain size. For cells that do not undergo the backlight side mask plating, the microcrystalline P crystallization rate in the area where the texture remains due to plating is 36%, while the crystallization rate in the conventional flat area is close to that under the fully polished backside condition, both of which are around 55%. Furthermore, thanks to the improvement in the morphological uniformity and flatness of the backlight surface, the improvement in the crystallization rate and grain size of the microcrystalline P layer, the conversion efficiency of the double-sided microcrystalline single-sided texturing heterojunction battery is about 25.88%; while the battery without removing the backlight mask plating, that is, the battery with plating on the backlight side, has a conversion efficiency of only 25.70% due to the difference in the back passivation conditions and the uneven crystallization rate of the microcrystalline P layer.

[0087] On the other hand, in some cases, after the mask plating on the backlight side of the silicon substrate is removed by de-plating solution, the reflectivity of the backlight side is about 30% to 40%; while for the solar cell that has not removed the mask plating on the backlight side, that is, the backlight side still has obvious velvet remaining, the reflectivity of the backlight side is about 20% to 30%.

[0088] In addition, although the bifaciality of existing double-sided textured heterojunction cells is high, the efficiency is low due to insufficient passivation performance. Therefore, the present invention configures the backlight surface as a plane or surface with a microstructure (a back micro-texture structure). The refined microstructure of the prepared backlight surface has a better anti-epitaxial passivation effect than ordinary texture, and exhibits a Voc gain effect of 1mV in the cell. However, the reflectivity of this backlight surface structure is relatively high. In addition, the second conductive type doped layer of the existing backlight surface, such as the microcrystalline P layer, mostly adopts a single-layer film structure with a high refractive index, usually between 3.5 and 3.8. The optical utilization is low and the reflectivity is high, resulting in a low backlight current and a bifaciality of only 70% to 80%. In order to improve this phenomenon, the inventors of this application set up multiple layers of second sub-doped layers with different refractive indices, such as combining stacked microcrystalline P structures with different refractive indices. This can maximize the advantages of the doped microcrystalline P thin film layer, while ensuring passivation and improving effective absorption, and can reduce the backlight reflectivity, thereby effectively improving the battery bifaciality and back battery efficiency.

[0089] As shown in FIG3 or FIG2 , in some specific embodiments, the method for preparing a heterojunction solar cell specifically includes the following steps:

[0090] S100. Provide a silicon substrate 10, which includes two side surfaces opposite to each other along the thickness direction, namely a light-receiving surface and a backlight surface. Perform a texturing treatment on the light-receiving surface and the backlight surface of the silicon substrate to form texturing structures on the light-receiving surface and the backlight surface, such as forming a first texturing structure and a second texturing structure, respectively.

[0091] Optionally, the silicon substrate 10 is an N-type single crystal silicon wafer.

[0092] Optionally, the first velvet structure and the second velvet structure both have pyramid structures.

[0093] By texturing the single-crystal silicon wafer on both sides, the light-receiving surface can be given a uniform textured light-trapping structure. For example, this light-trapping structure can be a pyramid-shaped textured structure formed by alkaline etching. In other embodiments, the front side of the single-crystal silicon wafer exhibits an anti-reflective textured surface, and the anti-reflective textured surface is pyramid-shaped. Of course, in other embodiments, this textured structure can also take other structural forms, and this embodiment is not limited thereto.

[0094] It should be noted that the specific operation mode and process conditions of the above-mentioned texturing treatment can be selected and regulated by those skilled in the art according to actual conditions. For example, a texturing cleaning machine is used, and an alkali texturing method is used to place the silicon substrate in an alkaline texturing solution for texturing treatment. Optionally, the alkaline texturing solution includes a KOH solution or a NaOH solution, and the mass percentage concentration of the alkaline texturing solution needs to be controlled below 10%, preferably 1% to 5%, for example, it can be 1%, 2%, 3%, 4%, 5%, etc.; the texturing time is 3min to 30min, for example, it can be 3min, 5min, 6min, 8min, 10min, 15min, 30min, etc.; the reaction temperature is 50 to 85°C, for example, it can be 50°C, 60°C, 70°C, 80°C, 85°C, etc. Optionally, the texturing treatment also uses a texturing additive, and the mass percentage concentration of the texturing additive is 0.5% to 5%. Among them, the texturing additive can regulate the etching effect of the alkaline solution on the texturing surface.

[0095] S200 , forming a mask layer on the textured surface of the light-receiving surface of the silicon substrate 10 ; that is, performing mask protection on the textured surface structure of the light-receiving surface, and providing a mask protection layer on the textured surface structure.

[0096] In this embodiment, a double-sided textured silicon substrate (e.g., a single-crystal silicon wafer) is masked on a single side, i.e., the front side is masked, resulting in a double-sided textured single-crystal silicon wafer protected by a single-side mask. The primary function of this masking layer is to protect the first textured surface from corrosion during subsequent refinement or wet chemical processing.

[0097] Optionally, the mask layer is formed by one or more of plate-type PECVD, tube-type PECVD, or PVD.

[0098] Optionally, the material of the mask layer includes silicon oxide (SiO x ), silicon nitride (SiN x ) or silicon oxynitride (SiN x O x ) at least one; for example, the mask layer may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a stacked structure of two or more of the above film layers.

[0099] In this embodiment, there are many ways to deposit a mask protective layer on the front of a heterojunction single-sided texturing solar cell, including but not limited to plate-type PECVD, tube-type PECVD, PVD, etc. The deposited mask layer includes silicon oxide, silicon nitride, silicon oxynitride, etc. It is understandable that the degree of mask wrapping is different under different processes and different film layers. By adding a step of cleaning and removing the mask wrapping layer, not only can the passivation effect of the back side of the single-sided texturing heterojunction cell be improved, but also the stability and compatibility of the process in large-scale mass production can be improved.

[0100] For example, in one specific embodiment, silicon nitride is deposited on the first textured structure on the light-receiving surface of the silicon substrate using PECVD (plasma-enhanced chemical vapor deposition) technology to form a mask layer. The mask layer formation process is preferably a deposition technology such as PECVD. Operating conditions such as deposition temperature and time can be adjusted based on actual process conditions.

[0101] Optionally, the refractive index of the mask layer is 1.6 to 1.8; for example, the refractive index of the mask layer can be 1.6, 1.65, 1.7, 1.75, 1.8, etc. If the refractive index of the mask layer is too large, such as greater than 1.8, it will make it difficult to completely remove the mask protective layer. If the refractive index of the mask layer is too small, such as less than 1.6, the mask protective layer will be easily removed in subsequent steps.

[0102] Optionally, the thickness of the mask layer is 20 nm to 200 nm. Optionally, the thickness of the mask layer is 20 nm to 100 nm. Optionally, the thickness of the mask layer is 30 nm to 80 nm. For example, the thickness of the mask layer can be 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, etc. If the thickness of the mask layer is too small, its protective ability is poor. If the thickness of the mask layer is too large, such as exceeding 200 nm, the cost is significantly increased.

[0103] S300, using a de-coating solution to remove the mask wrap on the backlight side of the silicon substrate; that is, cleaning the silicon wafer on which the mask layer is deposited on one side in step S200 to remove the mask wrap layer on the backlight side.

[0104] The method for improving the back passivation of a battery of the present invention comprises the following steps: after depositing a mask protective layer on the light-receiving side (front) of the battery, a specific de-plating solution, such as an alkali + hydrogen peroxide solution of a certain concentration and ratio, is used to clean the silicon wafer to remove the mask protective layer plating on the unmasked surface; thereby, the surface uniformity and flatness of the back side of the silicon wafer after the wet chemical treatment process (or polishing process) on the backlight side can be improved, thereby ensuring the film quality and uniformity of subsequent intrinsic passivation layers and doping layers, such as the intrinsic amorphous silicon layer and the P-type microcrystalline silicon coating.

[0105] Optionally, the de-wrapping solution includes a mixed solution consisting of alkali, hydrogen peroxide and water.

[0106] Optionally, in the mixed solution, the mass percentage of the base is 1% to 10%, the mass percentage of the hydrogen peroxide is 5% to 30%, and the mass percentage of the water is 60% to 94%. That is, based on the total mass of the mixed solution, the mass percentage of the base in the mixed solution is 1% to 10%, for example, 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, etc.; the mass percentage of the hydrogen peroxide in the mixed solution is 5% to 30%, for example, 5%, 8%, 10%, 12%, 15%, 20%, 22%, 25%, 28%, 30%, etc.; and the mass percentage of the water (pure water) is 60% to 94%, for example, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 94%, etc.

[0107] Therefore, by using the mixed solution composed of alkali, hydrogen peroxide and water in the above specific proportion as the de-wrap solution, the mask wrap layer on the backlight surface can be effectively removed, and the cleaning and removal effect is better.

[0108] Optionally, the base includes, but is not limited to, at least one of sodium hydroxide (NaOH) or potassium hydroxide (KOH).

[0109] Optionally, the mass concentration of the hydrogen peroxide is 10 wt% to 50 wt%; for example, the mass concentration of the hydrogen peroxide can be 10 wt%, 20 wt%, 30 wt%, 40 wt%, 50 wt%, etc.

[0110] Optionally, the temperature for removing the mask on the backlight surface of the silicon substrate during the plating process is 40° C. to 80° C., and the time is 150 seconds to 300 seconds.

[0111] When cleaning and removing the mask plating on the backlight surface, the removal is carried out at a temperature of 40℃~80℃, for example, 40℃, 50℃, 60℃, 70℃, 80℃, etc., and the cleaning time is 150s~300s, for example, 150s, 160s, 180s, 200s, 240s, 260s, 280s, 300s, etc.

[0112] S400: Performing a refinement treatment on the backlight surface of the silicon substrate 10, so that the backlight surface of the silicon substrate 10 forms a surface having a microstructure. For example, wet chemical treatment is performed on the second velvet structure of the backlight surface to flatten at least a portion of the pyramidal structures of the second velvet structure, thereby removing at least a portion of the pyramidal structures of the second velvet structure, flattening and refining the structure to obtain a refined microstructure, thereby forming the backlight surface into a flat surface with a refined microstructure.

[0113] The embodiment of the present invention can effectively increase the passivation effect by forming a refined microstructure on the backlight surface. It has a better anti-epitaxial passivation effect than the existing backlight surface structure, and exhibits a Voc gain effect of 1mV on the battery cell. However, a large number of experiments have found that when the back side is a polished surface, the solder strip is prone to debonding during the subsequent component packaging process. Therefore, the refined microstructure of the backlight surface can have sufficient adhesion to the subsequent printed grid lines, which can alleviate the debonding problem caused by direct polishing of the back side; its structure is flatter, which has an improvement effect on the battery opening voltage, and helps to improve battery efficiency. In addition, the refined microstructure of the backlight surface can reduce the surface area of ​​the back side, greatly shorten the coating time, and can make the various functional layers of the backlight surface, such as the back microcrystalline doping layer and the back TCO layer, thinned to a certain extent, effectively improving the economic benefits of production.

[0114] Optionally, the refined microstructure includes a plurality of block structures, wherein at least some of the block structures have partially overlapping surfaces. The embodiment of the present invention does not limit the number or range of overlapping block structures.

[0115] By refining the velvet surface of the backlight side, the resulting surface features a fine, small-block structure—a microstructured surface composed of multiple small blocks, some of which overlap, creating a flatter structure. This reduces the surface area of ​​the backside and makes passivation easier. Compared to existing pyramid-shaped or polished backside structures, this refined, small-block microstructure offers superior anti-epitaxial passivation and sufficient adhesion, helping to improve battery performance.

[0116] Optionally, the size of the block structure is 0.1 μm to 20 μm. That is, the size of each independent unit in the plurality of blocks is 0.1 μm to 20 μm. This size refers to the average length or average width of the square cross section of the block.

[0117] Optionally, during the refinement treatment, the backlight surface of the silicon substrate is treated with an alkaline solution at a temperature of 40°C to 80°C for 100 to 600 seconds. The treatment temperature is 40°C to 80°C, further 45°C to 78°C, for example, 40°C, 45°C, 50°C, 55°C, 60°C, 65°C, 70°C, 75°C, 78°C, 80°C, etc. The treatment time is 100 to 600 seconds, further 150 to 500 seconds, for example, 100 seconds, 120 seconds, 150 seconds, 180 seconds, 200 seconds, 240 seconds, 300 seconds, 360 seconds, 400 seconds, 500 seconds, etc.

[0118] Optionally, the alkaline solution includes at least one of a potassium hydroxide solution or a sodium hydroxide solution.

[0119] Optionally, the mass percentage concentration of the alkaline solution is 1% to 60%. For example, the mass percentage concentration of the alkaline solution can be 1%, 2%, 4%, 5%, 6%, 8%, 10%, 12%, 15%, 20%, 30%, 40%, 50%, 60%, etc.

[0120] Therefore, the double-sided textured single-crystalline silicon wafer protected by a single-sided mask is placed in an alkaline solution with a mass concentration of 1% to 60% at 40℃ to 80℃ for chemical treatment on the back of the texture, forming a single-crystalline silicon wafer with a textured surface protected by a mask on one side and a chemically treated microstructure on the other side. The back side after treatment is characterized by a fine small square structure.

[0121] S500 , removing the mask layer; that is, removing the mask layer on the first textured structure, thereby obtaining a single-sided textured silicon wafer with a pyramid textured surface on the light-receiving side and a surface with a refined microstructure on the backlight side.

[0122] After the refinement process, the mask layer on the first textured structure of the light-receiving surface is removed to reveal the first textured structure.

[0123] Optionally, the mask layer is removed using an acidic solution at a temperature of 25°C to 45°C, for example, 25°C, 30°C, 35°C, 40°C, etc. For example, a single-sided mask-protected single-crystalline silicon wafer is placed in an acidic solution at 25°C to 30°C to remove the protective mask layer, thereby forming a single-crystalline silicon wafer with a backlight-side microstructure.

[0124] Optionally, the acidic solution includes at least one of hydrofluoric acid (HF) or hydrochloric acid (HCl); for example, the solution for removing the mask layer can be an HF solution with an appropriate amount of HCl added. Furthermore, the mass percentage concentration of the acidic solution is 5% to 10%, and further can be 6% to 8%, for example, 5%, 6%, 6.5%, 7%, 8%, 9%, and 10%. This can produce a single-sided textured silicon wafer with a pyramid textured surface on the front and a refined microstructured surface on the back, without any wrap-around plating on the back.

[0125] S600: Prepare a double-sided intrinsic passivation layer. Form a first intrinsic passivation layer 21 and a second intrinsic passivation layer 22 on the light-receiving surface and the backlight surface of the silicon substrate 10, respectively. That is, form the first intrinsic passivation layer 21 on the first textured structure on the light-receiving surface, and form the second intrinsic passivation layer 22 on the microstructured surface on the backlight surface.

[0126] The first intrinsic passivation layer 21 and the second intrinsic passivation layer 22 can be prepared by deposition methods such as plasma assisted chemical vapor deposition (PECVD) or catalytic chemical vapor deposition (CAT-CVD). The specific operation method and operating conditions can be selected and set by those skilled in the art according to actual conditions.

[0127] Optionally, the first intrinsic passivation layer 21 and the second intrinsic passivation layer 22 include a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer, respectively. For example, the first intrinsic passivation layer 21 may be a first intrinsic amorphous silicon layer, and the second intrinsic passivation layer 22 may be a second intrinsic amorphous silicon layer.

[0128] S700: Prepare a doped layer. Form a first conductivity type doped layer 31 and a second conductivity type doped layer 32 on the first intrinsic passivation layer 21 and the second intrinsic passivation layer 22, respectively. That is, the first conductivity type doped layer 31 is formed on the first intrinsic passivation layer 21, and the second conductivity type doped layer 32 is formed on the second intrinsic passivation layer 22. The second conductivity type doped layer 32 includes a plurality of stacked second sub-doped layers 320, each of which has a different refractive index.

[0129] Optionally, chemical vapor deposition is used to prepare the first conductive type doped layer 31 and the second conductive type doped layer 32. In this embodiment, the silicon substrate 10 is an N-type silicon substrate, the first conductive type doped layer 31 is an N-type doped layer, and the second conductive type doped layer 32 is a P-type doped layer. For example, the first conductive type doped layer 31 is an amorphous silicon or microcrystalline silicon layer doped with a Group VA element, and the second conductive type doped layer 32 is an amorphous silicon or microcrystalline silicon layer doped with a Group IIIA element. The Group VA element includes one or more of nitrogen, phosphorus, arsenic, and antimony. Preferably, in this embodiment, the Group VA element is phosphorus. The Group IIIA element includes one or more of indium, boron, aluminum, and gallium. Preferably, in this embodiment, the Group IIIA element is boron.

[0130] Optionally, the first conductive type doped layer 31 , ie, the N-type doped layer, is an amorphous silicon or microcrystalline silicon layer doped with phosphorus, preferably a microcrystalline silicon layer, also called a microcrystalline N layer.

[0131] Optionally, the second conductive type doped layer 32 , ie, the P-type doped layer, is an amorphous silicon or microcrystalline silicon layer doped with boron, preferably a microcrystalline silicon layer.

[0132] Preferably, in some embodiments, the second conductive type doped layer 32 is a microcrystalline silicon layer doped with boron, also referred to as a microcrystalline P layer.

[0133] Alternatively, in some other embodiments, the second conductive type doped layer 32 is an oxygen-doped microcrystalline silicon layer doped with Group IIIA elements, such as an oxygen-doped microcrystalline silicon layer doped with boron, also called an oxygen-doped microcrystalline P layer.

[0134] Given the existing single-sided texturing process for mass-producing heterojunction cells, to ensure good passivation, the back-side microcrystalline P layer requires a single, oxygen-free film with a refractive index of 3.5 to 3.8. This results in a high reflectivity, which in turn reduces the short-circuit current, lowers the bifaciality, and lowers the back-side cell efficiency. Furthermore, the existing single-layer microcrystalline P layer structure results in a very narrow window for adjusting the refractive index, making it difficult to match the optimal range, which seriously affects the light transmittance of the heterojunction cell.

[0135] To improve the above phenomenon, the embodiment of the present invention provides a multi-layer second sub-doping layer 320. Therefore, compared with the single-layer microcrystalline P structure that can only provide a good passivation effect but poor optical utilization, the thickness and refractive index of each dielectric film of the stacked microcrystalline P structure are matched and designed, which can increase the optical utilization while ensuring passivation. The short-circuit current Isc of the battery cell is increased by 200 to 400 mA, thereby increasing the battery efficiency on the back of the battery cell by 0.3% to 0.8% and the bifaciality by 2% to 6%.

[0136] Furthermore, the multi-layer second sub-doped layer 320 , such as the stacked microcrystal P, has a wider adjustable refractive index window and is less sensitive to deposition temperature, power, and gas flow, thereby reducing the impact of device fluctuations on battery efficiency.

[0137] The second conductivity type doped layer 32 in embodiments of the present invention can be a microcrystalline P layer (undoped with oxygen) or an oxygen-doped microcrystalline P layer. For example, in some embodiments, the second conductivity type doped layer 32 is an oxygen-doped microcrystalline P layer. The laminated microcrystalline P layer is doped with N2O. Because nitrogen in the laminated microcrystalline P layer has a minimal effect on crystallinity, it does not degrade passivation performance. Furthermore, the refractive index of each layer in the laminated microcrystalline P layer is adjusted by adjusting the flow rate of the doped nitrous oxide (N2O). N2O dissociates at low CVD power output, making it easy to match the refractive index of each layer to an optimal range, while also reducing production costs.

[0138] Optionally, the second sub-doped layer 320 has three or more layers; that is, the second sub-doped layer 320 has at least three layers. As an example, the second sub-doped layer 320 may have three to ten layers, further three to eight layers, further three to six layers, for example, the second sub-doped layer 320 may have three, four, five, six, or more layers.

[0139] Optionally, the refractive index of each second sub-doped layer 320 gradually decreases from the second intrinsic passivation layer 22 to the second intrinsic passivation layer 22. That is, the refractive index of each second sub-doped layer 320 gradually decreases from the second intrinsic passivation layer 22 to the second transparent conductive layer 42. In comparison, the refractive index of the second sub-doped layer 320 close to the second intrinsic passivation layer 22 is the largest, while the refractive index of the second sub-doped layer 320 close to the second transparent conductive layer 42 is the smallest. The refractive index of the second sub-doped layer 320 located in the middle is between the maximum and minimum values.

[0140] Optionally, the total refractive index of the second conductive type doped layer 32 is in the range of 2.8 to 3.8.

[0141] The present invention adopts a microcrystalline P structure with N≥3 layers of different refractive indices and thicknesses, wherein the refractive index of the second sub-doped layer close to the second intrinsic passivation layer is greater than the refractive index of the intermediate layer, the refractive index of the second sub-doped layer in the intermediate layer is greater than the refractive index of the second sub-doped layer close to the second transparent conductive layer, and the total refractive index range of the second conductive type doped layer is 2.8 to 3.8. In this way, while ensuring conductivity, the optical band gap is further widened, the reflection of light at the interface is effectively reduced, the short-circuit current is increased, and thus the battery bifaciality and the bifacial equivalent battery efficiency are improved.

[0142] Optionally, the refractive index of the second sub-doped layer 320 proximate to the second intrinsic passivation layer 22 is 3.5-3.8, and the refractive index of the second sub-doped layer 320 distal to the second intrinsic passivation layer 22 is 2.8-3.1. That is, the refractive index of the second sub-doped layer 320 proximate to the second transparent conductive layer 42 is 2.8-3.1. As an example, the number of second sub-doped layers 320 is four. Along the direction from the second intrinsic passivation layer 22 to the second transparent conductive layer 42, the second sub-doped layers 320 are, in order, a second sub-doped layer A321, a second sub-doped layer B322, a second sub-doped layer C323, and a second sub-doped layer D324. The refractive index of the second sub-doped layer A321 is 3.5-3.8, the refractive index of the second sub-doped layer B322 is 3.3-3.5, the refractive index of the second sub-doped layer C323 is 3.1-3.3, and the refractive index of the second sub-doped layer D324 is 2.8-3.1. Therefore, this gradual change of the refractive index from 2.8 to 3.1 to 3.1 to 3.3 to 3.3 to 3.5 to 3.5 to 3.8 can further reduce the reflectivity and increase the light transmittance compared to a single-layer microcrystalline P layer, which helps to improve the efficiency of the battery.

[0143] Optionally, the total thickness of the second conductive type doping layer 32 is 5 nm to 50 nm; for example, the total thickness of the second conductive type doping layer 32 can be 5 nm, 6 nm, 8 nm, 10 nm, 15 nm, 20 nm, 30 nm, 40 nm, 50 nm, etc.

[0144] Optionally, the thickness of the second sub-doping layer 320 is 0.5 nm to 5 nm. The thicknesses of different second sub-doping layers 320 can be the same or different. For example, by making different first sub-doping layers 320 have different thicknesses, it is helpful to adjust different second sub-doping layers to have different refractive indices.

[0145] Therefore, through the microcrystalline P anti-reflection structure in this embodiment, that is, through the setting of multiple layers of the second sub-doped layer 320 with different refractive indices, the back reflectivity can be effectively reduced, solving the problem of low anti-reflection effect of the back micro-velvet structure, effectively improving the bifaciality of the back micro-velvet structure heterojunction battery, and further improving the back efficiency, which is suitable for industrial applications.

[0146] S800 , preparing a transparent conductive layer (TCO layer): forming a first transparent conductive layer 41 on the first conductive type doped layer 31 , and forming a second transparent conductive layer 42 on the second conductive type doped layer 32 .

[0147] A transparent conductive layer (TCO) refers to a film layer of a transparent conductive oxide. TCO is a general term for a series of semiconductor materials that are both light-transmitting and conductive, mainly including ITO (indium tin oxide), IWO (tungsten-doped indium oxide), AZO (aluminum-doped zinc oxide), etc. This embodiment does not limit the specific material of the transparent conductive layer.

[0148] The equipment and method for preparing the transparent conductive layer may include, but are not limited to, a magnetron sputtering device (PVD) or other applicable various deposition equipment.

[0149] Optionally, the thickness of the second transparent conductive layer 42 is 50 nm to 200 nm. For example, the thickness of the second transparent conductive layer 42 can be 50 nm, 60 nm, 80 nm, 100 nm, 120 nm, 150 nm, 200 nm, etc. In the embodiment of the present application, by forming a refined microstructure on the back surface, the thickness of the microcrystalline P layer and the second transparent conductive layer can be reduced compared to the thickness of conventional doping layers and conductive layers, thereby helping to reduce the weight of the battery.

[0150] S900: Prepare metal electrodes: Form a first electrode 51 on the first transparent conductive layer 41, and form a second electrode 52 on the second transparent conductive layer 42. Both the first electrode 51 and the second electrode 52 are metal electrodes.

[0151] Alternatively, electrodes can be prepared using screen printing. For example, a silicon wafer is screen-printed with a low-temperature silver paste, and then the screen-printed single-crystal silicon wafer is placed in a curing furnace for curing at 190°C, enabling power generation on both sides.

[0152] In this embodiment, after removing the mask layer, the backlight side microstructured single crystal silicon wafer can be subjected to enhanced plasma chemical vapor deposition, physical vapor deposition, and screen printing to form a heterojunction solar cell with an intrinsic passivation layer.

[0153] It should be pointed out here that in the preparation method of the heterojunction solar cell, the specific processes of preparing the transparent conductive layer and preparing the metal electrode can refer to the existing technology and adopt conventional production process flow or operation mode. This embodiment does not limit this and will not be described in detail here.

[0154] Based on the same inventive concept, the present invention also provides a heterojunction solar cell, which can be manufactured using the aforementioned method for manufacturing a heterojunction solar cell. As shown in FIG9 or FIG10 , the heterojunction solar cell includes:

[0155] A silicon substrate 10, comprising a first surface and a second surface opposite to each other in a thickness direction, wherein the first surface is a light-receiving surface and the second surface is a backlight surface;

[0156] The light receiving surface has a suede structure, and a first intrinsic passivation layer 21 is located on the suede structure;

[0157] a first conductive type doped layer 31 located on the first intrinsic passivation layer 21;

[0158] a first transparent conductive layer 41 located on the first conductive type doped layer 31;

[0159] a first electrode 51 located on the first transparent conductive layer 41;

[0160] The backlight surface has a microstructured surface, and a second intrinsic passivation layer 22 is located on the refined microstructure of the backlight surface;

[0161] A second conductive type doped layer 32 located on the second intrinsic passivation layer 22; wherein the second conductive type doped layer 32 includes a plurality of stacked second sub-doped layers 320, each of which has a different refractive index;

[0162] a second transparent conductive layer 42 located on the second conductive type doped layer 32;

[0163] The second electrode 52 is located on the second transparent conductive layer 42 .

[0164] The first conductive type doped layer 31 may be an N-type doped layer, and the second conductive type doped layer 32 may be a P-type doped layer.

[0165] It should be understood that the heterojunction solar cell of this embodiment and the aforementioned method for preparing a heterojunction solar cell are based on the same inventive concept, and thus have at least all the features and advantages of the method for preparing a heterojunction solar cell, which will not be described in detail here.

[0166] In order to verify the effect of the method for preparing a heterojunction solar cell provided by the embodiment of the present invention, the present invention also carried out some specific examples and comparative experiments. Example 1

[0167] A method for preparing a heterojunction solar cell, comprising:

[0168] S100. Providing a silicon substrate. The silicon substrate is an N-type single crystal silicon wafer. The silicon substrate includes two opposing surfaces along the thickness direction, namely, a light-receiving surface and a backlight surface. The light-receiving surface and the backlight surface of the silicon substrate are subjected to a texturing treatment. The texturing treatment is performed using an alkaline texturing method using a texturing cleaning machine, and the silicon substrate is placed in an alkaline texturing solution for texturing treatment.

[0169] S200 , forming a mask layer on the textured surface of the light-receiving surface of the silicon substrate; specifically, depositing silicon nitride on the textured surface of the light-receiving surface of the silicon substrate by using PECVD technology to form the mask layer.

[0170] The deposited silicon nitride mask layer has a refractive index of 1.75 and a thickness of about 50 nm.

[0171] S300: Remove the mask wrap on the backlight surface of the silicon substrate using a de-wrap solution. The de-wrap solution comprises a mixed solution of alkali, hydrogen peroxide, and water. The mixed solution comprises 5% by weight of NaOH, 30% by weight of hydrogen peroxide, and 65% by weight of water. The cleaning temperature for removing the mask wrap is 60°C, and the cleaning time is 180 seconds.

[0172] S400: Performing a refinement treatment on the backlight surface of the silicon substrate to form a microstructured surface. During the refinement treatment, the backlight surface of the silicon substrate is treated with an alkaline solution at a temperature of 55° C. for 200 seconds. The alkaline solution is a NaKOH solution having a mass percent concentration of 50%.

[0173] S500: Remove the mask layer, thereby obtaining a single-sided textured silicon wafer having a pyramid textured surface on the light-receiving side and a surface with a refined microstructure on the backlight side. The mask layer is removed using an acidic solution at a temperature of 30° C. The acidic solution is HF solution with an appropriate amount of HCl added.

[0174] The reflectivity of the light-receiving side and the backlight side of the silicon wafer prepared in step S500 is tested, and then the subsequent steps S600 to S900 are carried out to test the passivation effect and the conversion efficiency of the heterojunction cell finally supported.

[0175] S600: forming a first intrinsic passivation layer on the textured structure of the light-receiving side, and forming a second intrinsic passivation layer on the surface with the microstructure of the backlight side, wherein the first intrinsic passivation layer is a first intrinsic amorphous silicon layer, and the second intrinsic passivation layer is a second intrinsic amorphous silicon layer.

[0176] S700: Form a first conductive type doped layer on the first intrinsic passivation layer, and form a second conductive type doped layer on the second intrinsic passivation layer, wherein the first conductive type doped layer is a microcrystalline N layer, and the second conductive type doped layer is a microcrystalline P layer or an oxygen-doped microcrystalline P layer.

[0177] S800 , forming a first transparent conductive layer on the first conductive type doped layer, and forming a second transparent conductive layer on the second conductive type doped layer.

[0178] S900 , forming a first electrode on the first transparent conductive layer, and forming a second electrode on the second transparent conductive layer. Comparative Example 1

[0179] The preparation method of the heterojunction solar cell of Comparative Example 1 is substantially the same as that of Example 1, except that step S300 is omitted in Comparative Example 1, that is, the de-coating step of the backlight surface is not performed in Comparative Example 1.

[0180] FIG4 shows the morphology of the backlight surface after the mask layer is removed in Example 1 of the present invention. As can be seen from FIG4 , there is no wrap-around plating on the backlight surface of the silicon wafer prepared through step S500 in Example 1 of the present invention, thereby improving the uniformity and flatness of the backlight surface.

[0181] Table 1 shows the test comparison of the heterojunction battery of Example 1 of the present invention with single-sided texturing and removal of the wrap-around plating and Comparative Example 1 with single-sided texturing but without removal of the wrap-around plating.

[0182] Table 1

[0183]

[0184] In Table 1, the reflectivity test was performed on the light-receiving surface and the backlight surface of the silicon wafer prepared in step S500 of Example 1 of the present invention using the NXT reflectivity tester. The results showed that the reflectivity of the light-receiving surface of the silicon wafer was 11.01%, and the reflectivity of the backlight surface of the silicon wafer was 35.52%. The reflectivity of the backlight surface of the silicon wafer of Comparative Example 1, which was not subjected to the removal of the back surface coating, was 24.18%. At the same time, as can be seen from Figure 5, the backlight surface of the silicon wafer obtained in step S500 of Example 1 of the present invention is a surface with a microstructure, that is, the backlight surface has a flat square, and it can be determined that the backlight surface does not have a velvet surface caused by the coating. As can be seen from Figure 6, Comparative Example 1 did not remove the back surface coating, resulting in the back edge of its silicon wafer still having an unpolished pyramid velvet surface due to the protection of the coating mask layer.

[0185] In Table 1, the passivation effect of the single-sided textured silicon wafer in the battery prepared in Example 1 was tested using a Sinto WCT-120 minority carrier lifetime tester. After step S500, the preparations of steps S600 and S700 were performed, such as depositing an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer on the single-sided textured silicon wafer by plate-type PECVD to form a passivation structure. As shown in Table 1, because the pyramid velvet surface is more difficult to passivate than the polished plane or the surface with a microstructure under the same conditions, the minority carrier lifetime of the single-sided textured silicon wafer in Comparative Example 1, which did not undergo step S300 to remove the back-side plating layer, was measured to be 1125 us under the same passivation structure, while the minority carrier lifetime of the single-sided textured silicon wafer in Example 1, which was completely polished on the back, that is, with no residual velvet structure on the back, was 2516 us. This shows that after completely removing the pyramid velvet residue caused by the back-side plating, the passivation efficiency of the single-sided textured silicon wafer has been greatly improved.

[0186] As shown in Table 1 and Figure 7 , in Comparative Example 1, where no masking was performed on the backlight surface, the crystallization rate of the microcrystalline P layer deposited on the local suede surface was only 36%. In contrast, in Example 1, the crystallization rate of the microcrystalline P layer deposited on the polished surface, i.e., the surface with the microstructure, reached 55%, thereby improving the crystallization rate of the microcrystalline P layer. It should be understood that the "microcrystalline P layer on the polished surface" in Figure 7 refers to the microcrystalline P layer deposited on the backlight surface of the microstructured surface.

[0187] Further, referring to Table 1 and FIG8 , the conversion efficiency of the double-sided microcrystalline heterojunction battery in Example 1 in which the back-side coating was removed was 25.88%, which was significantly better than the 25.70% of the group of the non-removed mask coating layer in Comparative Example 1. In addition, as shown in FIG8 , the short-circuit current of the heterojunction battery in Example 1 was lower than that in Comparative Example 1, and the open-circuit voltage and fill factor of the heterojunction battery in Example 1 were also higher than those in Comparative Example 1. This shows that Example 1 of the present invention removes the coating of the mask protective layer on the backlight side, improves the uniformity and flatness of the backlight side in the subsequent process, improves the passivation effect of the subsequently deposited intrinsic passivation layer and the crystallization rate of the double-sided microcrystalline doping layer, and thus obtains a higher conversion efficiency of the heterojunction battery. Example 2

[0188] The method for preparing the heterojunction solar cell of Example 2 is substantially the same as that of Example 1, with the main difference being step S700.

[0189] In step S700 of embodiment 2, the second conductive type doped layer is a microcrystalline P layer, and the second conductive type doped layer includes a plurality of stacked second sub-doped layers, each second sub-doped layer having a different refractive index.

[0190] In this embodiment, the number of second sub-doping layers is four. Along the direction from the second intrinsic passivation layer to the second transparent conductive layer, the second sub-doping layers are the second sub-doping layer A, the second sub-doping layer B, the second sub-doping layer C, and the second sub-doping layer D. The refractive index of the second sub-doping layer A is 3.7, the refractive index of the second sub-doping layer B is 3.5, the refractive index of the second sub-doping layer C is 3.1, the refractive index of the second sub-doping layer D is 2.8, the refractive index of the total doping layer is 3.3, and the total thickness of the second conductive type doping layer is 25nm. While ensuring conductivity, the above arrangement can further widen the optical band gap, effectively reduce the reflection of light at the interface, and thus reduce the reflectivity of the backlight surface, solve the problem of low anti-reflection effect of the backlight surface structure, and increase the short-circuit current, thereby effectively improving the bifaciality of the battery and further improving the backlight surface efficiency. Comparative Example 2

[0191] The preparation method of the heterojunction solar cell of Comparative Example 2 is basically the same as that of Example 2. Both are cells with a single-sided texturing back microstructure treatment. The difference is that in step S700 of Comparative Example 2, the second conductive type doped microcrystalline P layer is a single layer, that is, the microcrystalline P layer in Comparative Example 2 has a fixed refractive index and a thickness of 25nm.

[0192] The performance tests were carried out on the batteries of Example 2 and Comparative Example 2. The test results are shown in Table 2. As can be seen from Table 2, Example 2 of the present invention, by setting a plurality of second sub-doped layers with different refractive indices, can reduce the reflectivity of the backlight surface, solve the problem of low anti-reflection effect of the backlight surface structure, and increase the short-circuit current, thereby effectively improving the bifaciality of the battery and further improving the backlight surface efficiency. At the same time, there is no loss in the efficiency of the front side of the battery of Example 2. The multi-refractive index doped sublayer on the back side greatly improves the total power generation efficiency of the single-sided velvet back microstructure battery.

[0193] Table 2

[0194]

[0195] Parts not described in detail in the specification of the present invention are well known to those skilled in the art.

[0196] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0197] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for preparing a heterojunction solar cell, characterized in that: The method comprises: Providing a silicon substrate and performing texturing on the light-receiving surface and the backlight surface of the silicon substrate; forming a mask layer on the textured surface of the light-receiving surface of the silicon substrate; removing the mask wrap on the backlight surface of the silicon substrate by using a de-wrap solution; Performing fine processing on the backlight surface of the silicon substrate so that the backlight surface of the silicon substrate is formed into a surface with a microstructure; removing the mask layer; forming a first intrinsic passivation layer and a second intrinsic passivation layer on the light-receiving surface and the backlight surface of the silicon substrate respectively; A first conductive type doped layer and a second conductive type doped layer are formed on the first intrinsic passivation layer and the second intrinsic passivation layer, respectively, wherein the second conductive type doped layer includes a plurality of second sub-doped layers stacked together, and the refractive index of each second sub-doped layer is different.

2. The method for preparing a heterojunction solar cell according to claim 1, wherein: The mask layer satisfies at least one of the following characteristics: The method of forming the mask layer includes one or more of plate-type PECVD, tubular PECVD or PVD; The mask layer includes at least one of silicon oxide, silicon nitride or silicon oxynitride; The refractive index of the mask layer is 1.6 to 1.8; The thickness of the mask layer is 20nm to 200nm.

3. The method for preparing a heterojunction solar cell according to claim 1, wherein: The de-wrap solution comprises a mixed solution consisting of alkali, hydrogen peroxide and water.

4. The method for preparing a heterojunction solar cell according to claim 3, wherein: In the mixed solution, the mass percentage of the alkali is 1% to 10%, the mass percentage of the hydrogen peroxide is 5% to 30%, and the mass percentage of the water is 60% to 94%.

5. The method for preparing a heterojunction solar cell according to claim 3, wherein: The base comprises at least one of sodium hydroxide or potassium hydroxide; and / or, The mass concentration of the hydrogen peroxide is 10wt% to 50wt%.

6. The method for preparing a heterojunction solar cell according to claim 1, wherein: The temperature of the mask plating process for removing the backlight surface of the silicon substrate is 40° C. to 80° C., and the time is 150s to 300s.

7. The method for preparing a heterojunction solar cell according to claim 1, wherein: The fine processing of the backlight surface of the silicon substrate specifically includes: The backlight surface of the silicon substrate is treated with an alkaline solution at a temperature of 40° C. to 80° C. for 100 seconds to 600 seconds.

8. The method for preparing a heterojunction solar cell according to claim 7, wherein: The alkaline solution includes at least one of a potassium hydroxide solution or a sodium hydroxide solution; and / or, The mass percentage concentration of the alkaline solution is 1% to 60%.

9. The method for preparing a heterojunction solar cell according to claim 1, wherein: The removing of the mask layer specifically includes: The mask layer is removed using an acidic solution at a temperature of 25°C to 45°C.

10. The method for preparing a heterojunction solar cell according to claim 9, wherein: The acidic solution includes at least one of hydrofluoric acid or hydrochloric acid; and / or, The mass percentage concentration of the acidic solution is 5% to 10%.

11. The method for preparing a heterojunction solar cell according to any one of claims 1 to 10, characterized in that: The second conductive type doped layer satisfies at least one of the following characteristics: The number of layers of the second sub-doped layer is three or more; The refractive index of each of the second sub-doped layers gradually decreases along a direction from approaching the second intrinsic passivation layer to away from the second intrinsic passivation layer; The total refractive index of the second conductive type doped layer is in the range of 2.8 to 3.8; The refractive index of the second sub-doped layer close to the second intrinsic passivation layer is 3.5-3.8, and the refractive index of the second sub-doped layer far from the second intrinsic passivation layer is 2.8-3.1; The total thickness of the second conductive type doped layer is 5 nm to 50 nm; The thickness of the second sub-doping layer is 0.5 nm to 5 nm.

12. The method for preparing a heterojunction solar cell according to any one of claims 1 to 10, characterized in that: The first intrinsic passivation layer and the second intrinsic passivation layer include a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer, respectively.

13. The method for preparing a heterojunction solar cell according to any one of claims 1 to 10, characterized in that: The silicon substrate is an N-type silicon substrate, the first conductive type doped layer is an amorphous silicon or microcrystalline silicon layer doped with a Group VA element, and the second conductive type doped layer is an amorphous silicon or microcrystalline silicon layer doped with a Group IIIA element; Alternatively, the second conductive type doped layer is an oxygen-doped microcrystalline silicon layer doped with a Group IIIA element.

14. The method for preparing a heterojunction solar cell according to any one of claims 1 to 10, characterized in that: After forming the first conductive type doped layer and the second conductive type doped layer, the method further includes: forming a first transparent conductive layer on the first conductive type doped layer, and forming a second transparent conductive layer on the second conductive type doped layer; A first electrode is formed on the first transparent conductive layer, and a second electrode is formed on the second transparent conductive layer.

15. A heterojunction solar cell, characterized in that: The heterojunction solar cell comprises: A silicon substrate, comprising a light-receiving surface and a backlight surface that are oppositely disposed; The light receiving surface has a suede structure, and a first intrinsic passivation layer, a first conductive type doping layer, a first transparent conductive layer and a first electrode are sequentially arranged on the suede structure; The backlight surface has a microstructured surface, and a second intrinsic passivation layer, a second conductive type doped layer, a second transparent conductive layer and a second electrode are sequentially arranged on the surface of the microstructure; wherein the second conductive type doped layer includes a plurality of second sub-doped layers stacked together, and the refractive index of each layer of the second sub-doped layer is different.

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