Image sensor and electronic device

Abstract

Embodiments of the present application relate to the technical field of photoelectric conversion, and provide an image sensor and an electronic device, used for mitigating the influence of focusing pixels on peripheral pixels. First pixel structures in the image sensor are provided in a substrate; each first pixel structure comprises a first photoelectric conversion portion, a second photoelectric conversion portion, and a third N-type doped layer; the first photoelectric conversion portion comprises a first N-type doped layer and a first P-type doped layer that are used for forming a PN junction; the second photoelectric conversion portion comprises a second N-type doped layer and a second P-type doped layer that are used for forming a PN junction; the third N-type doped layer is arranged in the first P-type doped layer, and the third N-type doped layer is coupled with the first N-type doped layer and a first voltage end. When light is incident to each first pixel structure, the first photoelectric conversion portion receives a part of the light and an electrical signal obtained by performing photoelectric conversion is cleared in real time and cannot be outputted, and the second photoelectric conversion portion receives the other part of the light and an electrical signal obtained by performing photoelectric conversion is outputted.

Description

Image sensor and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on April 1, 2024, with application number 202410390835.6 and invention name “An image sensor and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of photoelectric conversion technology, and in particular to an image sensor and an electronic device. Background Art

[0003] As electronic devices become increasingly versatile, image sensors are increasingly used in them. Image sensors receive light signals, excite electrons, and collect them, allowing them to generate corresponding electrical signals based on the light signals, achieving conversion from light to electrical signals. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) have been widely used due to their high integration, low power consumption, and low production cost.

[0004] To improve image sensor performance, phase detection autofocus (PDAF) technology can be used to determine the correct lens position and prevent the image from being out of focus, which can cause the optical image sensor to malfunction. However, the half-shield technology currently used in image sensors can affect surrounding pixels during operation, thereby reducing the quality of the resulting image. Summary of the Invention

[0005] The present application provides an image sensor and an electronic device for alleviating the impact of a focus pixel on surrounding pixels.

[0006] To achieve the above objectives, this application adopts the following technical solutions:

[0007] In one aspect of the present application, an image sensor is provided, which may include a first voltage terminal, a substrate, and a plurality of first pixel structures. The first pixel structure is disposed within the substrate. In addition, the first pixel structure includes a first photoelectric conversion unit, a second photoelectric conversion unit, and a third N-type doped layer. The first photoelectric conversion unit includes a first N-type doped layer and a first P-type doped layer arranged in a stacked manner. The second photoelectric conversion unit includes a second N-type doped layer and a second P-type doped layer arranged in a stacked manner. The third N-type doped layer is disposed within the first P-type doped layer and is coupled to the first N-type doped layer, and the third N-type doped layer is coupled to the first voltage terminal.

[0008] In summary, the image sensor provided by the embodiments of the present application may include multiple first pixel structures located on a substrate. To enable the first pixel structure to implement the PDAF function, the first pixel structure may include a first photoelectric converter and a second photoelectric converter. When light strikes the first pixel structure, the first photoelectric converter receives a portion of the light, and the resulting electrical signal from the photoelectric conversion is cleared in real time and cannot be output. The second photoelectric converter receives the remaining portion of the light, and the resulting electrical signal from the photoelectric conversion is output. In this case, on the one hand, only a portion of the first pixel structure, for example, the second photoelectric converter of the first pixel structure, can output phase data. The remaining portion of the first pixel structure, namely the first photoelectric converter of the first pixel structure, cannot output an electrical signal and is shielded. As a result, the phase data output by the first pixel structure varies depending on the position of the first photoelectric converter. Phase differences exist between the different phase data, and the PDAF technology described above can be implemented based on this phase difference. On the other hand, in related art, to enable PDAF functionality in image sensor pixels, a shielding layer is provided within the pixel to block a portion of the light incident on the pixel. Since the shielding layer not only blocks the light but also reflects the incident light, the reflected light is incident on the surrounding pixels, thereby affecting the accuracy of the electrical signals output by the surrounding pixels. Therefore, the surrounding pixels also need to be corrected. In comparison, in the image sensor provided by the embodiment of the present application, the electrical signals converted by part of the photoelectric conversion unit in the first pixel structure with PDAF function are cleared in real time, making it impossible for it to output signals. Therefore, there is no need to set the above-mentioned shielding layer to avoid affecting the surrounding pixels.

[0009] In an optional embodiment, the image sensor further includes a plurality of first microlenses disposed on the substrate. Each first microlens covers a first pixel structure. The first microlenses can converge incident light onto the first pixel structure to improve photoelectric conversion efficiency.

[0010] In an optional embodiment, the image sensor further includes a back-end process structure, which is arranged on a substrate, and the back-end process structure includes an insulating layer and a first metal wire. The first metal wire is arranged in the insulating layer, and the two ends of the first metal wire are coupled to the third N-type doped layer and the first voltage terminal, respectively. In this way, the third N-type doped layer can be coupled to the first voltage terminal through the first metal wire. For example, a front-end process can be used to first form a first photoelectric conversion unit, a second photoelectric conversion unit, and a third N-type doped layer in the substrate. Then, a back-end process is used to form a back-end process structure on the substrate, wherein a portion of the metal pattern layer in the back-end process structure can be used as the above-mentioned first metal wire.

[0011] In one optional embodiment, the back-end process structure and the first microlens are disposed on opposite sides of the substrate. In this case, the image sensor is a back-illuminated image sensor. Alternatively, the back-end process structure is disposed between the first microlens and the substrate. In this case, the image sensor is a front-shielded image sensor.

[0012] In an optional embodiment, the image sensor further includes an output trace, which is disposed on the substrate. In addition, the first pixel structure further includes a source follower transistor and a selection transistor. The gate of the source follower transistor is coupled to the second photoelectric conversion unit, and the first electrode of the source follower transistor is coupled to the first voltage terminal. The first electrode of the selection transistor is coupled to the second electrode of the source follower transistor, and the second electrode of the selection transistor is coupled to the output trace. In this case, the first photoelectric conversion unit and the second photoelectric conversion unit receive incident light and perform photoelectric conversion. In the first photoelectric conversion unit, the first N-type doped layer is coupled to the first voltage terminal through the third N-type doped layer. When the first voltage terminal outputs a high voltage, the electrons stored in the first photoelectric conversion unit are cleared in real time. When the selection transistor is turned on, the electrical signal stored in the second photoelectric conversion unit can turn on the selection transistor, so that the electrical signal from the first voltage terminal can be transmitted to the output trace through the source follower transistor and the selection transistor, so that the first pixel structure can output the electrical signal converted from a portion of the incident light. Furthermore, in the first electrode of the source follower transistor and the first photoelectric conversion unit, the first N-type doped layer is coupled to the first voltage terminal, thereby enabling the voltage terminals of different devices to be shared, thereby simplifying the circuit structure.

[0013] In an optional embodiment, the image sensor further includes a reset transistor, wherein the first electrode of the reset transistor is coupled to the first voltage terminal, and the second electrode of the reset transistor is coupled to the second photoelectric conversion unit. In this way, before the source follower transistor is turned on, the reset transistor can be turned on first to reset the second photoelectric conversion unit via the reset voltage terminal, thereby improving the accuracy of the photoelectric conversion of the image sensor. In addition, the first electrode of the reset transistor Trst and the first photoelectric conversion unit, the first N-type doped layer are both coupled to the above-mentioned first voltage terminal, which can realize the sharing of voltage terminals of different devices and achieve the purpose of simplifying the circuit structure.

[0014] In an optional embodiment, the third N-type doped layer extends to the first voltage terminal and is coupled to the first voltage terminal. For example, the first voltage terminal can be a pad structure formed by a doping process. Based on this, a front-end process can be used to first form the first photoelectric conversion unit, the second photoelectric conversion unit and the above-mentioned pad structure in the substrate. Then, a third N-type doped layer is formed by a doping process, and the doping area of ​​the third N-type doped layer is controlled so that the third N-type doped layer can extend to the pad structure and couple with the pad structure, thereby achieving the purpose of coupling the third N-type doped layer to the first voltage terminal.

[0015] In one optional embodiment, the image sensor further includes a transfer control voltage terminal. Furthermore, the first pixel structure further includes a floating extension region and a first transfer transistor. The first transfer transistor is coupled at its two electrodes to the first photoelectric conversion unit and the floating diffusion region, respectively. The gate of the first transfer transistor is coupled to the transfer control voltage terminal. Based on this, the circuit structure for controlling the photoelectric conversion unit is a 4T structure, for example, including a source follower transistor, a gate transistor, a reset transistor, and the first transfer transistor.

[0016] In an optional embodiment, the voltage of the first voltage terminal is greater than the voltage of the transmission control voltage terminal. For example, when the first voltage terminal is a high voltage, such as the power supply voltage VDD, the transmission control voltage terminal can be a low voltage.

[0017] In an optional embodiment, the transmission control voltage terminal is grounded. For example, the gate of the first transmission transistor is coupled to the ground voltage.

[0018] In an optional embodiment, the first pixel structure further includes a third P-type doped layer disposed within the substrate. A vertical projection of the gate of the first transfer transistor on the substrate overlaps with a region where the third P-type doped layer is located. In this manner, the third P-type doped layer can be disposed between the first N-type doped layer serving as the first photoelectric conversion unit and the floating diffusion region, thereby isolating the first N-type doped layer from the floating diffusion region and preventing electrons from the first N-type doped layer from flowing into the floating diffusion region, thereby preventing the first photoelectric conversion unit from outputting any electrical signals.

[0019] In an optional embodiment, the doping concentration of the third N-type doped layer is greater than the doping concentration of the first N-type doped layer. In this way, the conductivity of the third N-type doped layer can be greater than the conductivity of the first N-type doped layer, thereby making it easier for the third N-type doped layer to couple with the first voltage terminal.

[0020] In an optional embodiment, the first pixel structure includes two first photoelectric conversion units and two second photoelectric conversion units. The two first photoelectric conversion units and the two second photoelectric conversion units form a 2×2 matrix. The two first photoelectric conversion units are located on the same side of the 2×2 matrix. In this case, the image sensor 20 can be a 2×2 on-chip lens (OCL) structure.

[0021] In one optional embodiment, the image sensor further includes multiple second pixel structures disposed within the substrate. The second pixel structures include at least two third photoelectric conversion units, each of which includes a stacked fourth N-type doped layer and a fourth P-type doped layer. In this manner, all third photoelectric conversion units within the region where the second pixel structures are located can perform photoelectric conversion on incident light to achieve image capture.

[0022] In an optional embodiment, the number of the plurality of first pixel structures accounts for 1% to 12% of the sum of the plurality of first pixel structures and the plurality of second pixel structures. When the above proportion is less than 1%, the number of first pixel structures 21 in the image sensor 20 is relatively small, which is not conducive to ensuring the accuracy of PDAF. Furthermore, when the above proportion is greater than 12%, the number of first pixel structures 21 in the image sensor 20 is relatively large, resulting in a relatively small number of second pixel structures 22, thereby reducing the accuracy of image acquisition.

[0023] In an optional embodiment, the image sensor further includes a plurality of second microlenses disposed on the substrate, with the second microlenses and the first microlenses located on the same side of the substrate, and each second microlens covering each second pixel structure. The technical effects of the second microlenses are the same as those of the first microlenses and are not further described here.

[0024] In one optional embodiment, the plurality of first pixel structures include a left pixel structure and a right pixel structure. In the left pixel structure, the first photoelectric converter is located on the left side. In the right pixel structure, the first photoelectric converter is located on the right side. Based on this, the right side portion of the left pixel structure, i.e., the second photoelectric converter in the left pixel structure, can output R phase data. The left side portion of the right pixel structure, i.e., the second photoelectric converter in the right pixel structure, can output the aforementioned L phase data.

[0025] Another aspect of the present application provides an electronic device comprising a circuit board and any one of the above image sensors, wherein the image sensor is coupled to the circuit board. The above electronic device has the same technical effects as the image sensor provided in the above embodiment, and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0027] FIG2 is a schematic structural diagram of the camera module in FIG1 ;

[0028] FIG3 is a schematic diagram of the exploded structure of the camera module in FIG2 ;

[0029] FIG4A is a schematic diagram of a pixel arrangement of the image sensor in FIG3 ;

[0030] FIG4B is a schematic diagram of a pixel structure of the image sensor in FIG3 ;

[0031] FIG5( a ) and FIG5 ( b ) are schematic diagrams of autofocus and phase difference data, respectively;

[0032] FIG6( a ) and FIG6 ( b ) are schematic diagrams of another type of autofocus and another type of phase difference data, respectively;

[0033] FIG7( a ) and FIG7 ( b ) are schematic diagrams of another autofocus and another phase difference data, respectively;

[0034] FIG8 is a cross-sectional view taken along the dotted line O3-O4 in FIG4B;

[0035] FIG9 is a cross-sectional view taken along the dotted line O5-O6 in FIG4B;

[0036] FIG10 is a schematic diagram of a pixel structure of an image sensor provided by related art;

[0037] FIG11 is a cross-sectional view taken along the dotted line O7-O8 in FIG4B;

[0038] FIG12 is a schematic diagram of an exploded structure of an image sensor provided in an embodiment of the present application;

[0039] FIG13 is a schematic diagram of another exploded structure of an image sensor provided in an embodiment of the present application;

[0040] FIG14 is another cross-sectional view taken along the dotted line O3-O4 in FIG4B;

[0041] FIG15 is another cross-sectional view taken along the dotted line O3-O4 in FIG4B;

[0042] FIG16 is a top view taken along the direction A in FIG14 ;

[0043] FIG17 is another top view taken along the direction A in FIG14;

[0044] FIG18 is a schematic diagram of a control circuit of a pixel structure provided in an embodiment of the present application;

[0045] FIG19 is a schematic diagram of a control circuit of another pixel structure provided in an embodiment of the present application;

[0046] FIG20 is a schematic diagram of a control circuit of another pixel structure provided in an embodiment of the present application;

[0047] FIG21 is a schematic diagram of a control circuit of another pixel structure provided in an embodiment of the present application;

[0048] FIG22 is another cross-sectional view taken along the dotted line O3-O4 in FIG4B;

[0049] FIG23 is a top view taken along the direction B in FIG22;

[0050] FIG24 is another top view taken along the direction B in FIG22;

[0051] FIG. 25 is another cross-sectional view obtained by cutting along the dotted line O3 - O4 in FIG. 4B .

[0052] Figure numerals: 01-electronic device; 02-display screen; 03-back cover; 04-middle frame; 05-processor; 06-opening; 07-lens cover; 08-camera hole; 10-camera module; 11-variable aperture; 12-lens assembly; 13-motor; 100-aperture hole; 14-filter; 15-circuit board; 20-image sensor; 200-pixel structure; 21-first pixel structure; 211-left pixel structure; 212-right pixel structure; 22-second pixel structure; 2101-first photoelectric conversion unit; 311-first N-type doped layer; 312-second N-type doped layer 321; 210 2-second photoelectric conversion unit; 321-second N-type doping layer; 322-second P-type doping layer; 2111-third N-type doping layer; 28-pixel isolation structure; 09-shielding layer; 2103-third photoelectric conversion unit; 331-fourth N-type doping layer; 332-fourth P-type doping layer; 23-first microlens; 27-second microlens; 24-color filter; 25-substrate; 26-back-end process structure; 261-insulating layer; 262-metal pattern layer; 2621-first metal wire; 2201-floating diffusion area; 2622-second metal wire; 2202-third P-type doping layer. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0054] In the following, the terms "first," "second," etc., are used for descriptive convenience only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0055] In addition, unless otherwise clearly specified and limited, the term "coupling" should be understood in a broad sense. For example, "coupling" can be a direct electrical connection, such as physical contact and electrical conduction between two components. It can also be understood as the electrical connection between different components in the circuit structure through physical lines such as printed circuit board (PCB) copper foil or wires that can transmit electrical signals to transmit electrical signals; or, "coupling" can be an indirect electrical connection between two components through an intermediate medium; or, "coupling" can be an electrical connection between two components in an air / non-contact manner, for example, two components are electrically connected by capacitive coupling to transmit electrical signals.

[0056] In the embodiments of the present application, the descriptions "vertical" and "parallel" respectively indicate approximately vertical and approximately parallel within a certain error range, and the error range may be a range in which the deviation angle relative to absolute vertical and absolute parallel is less than or equal to 5°, 8° or 10°, respectively, and no specific limitation is made here.

[0057] In the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the components schematically placed in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0058] In the drawings of the embodiments of the present application, components are represented by guide lines with arrows; parts are represented by guide lines only; and hollow structures such as openings and holes are represented by guide lines with wavy lines at the ends.

[0059] An embodiment of the present application provides an electronic device having a display function. The electronic device can be applied to various communication systems or communication protocols, such as Bluetooth (BT) communication technology, global positioning system (GPS) communication technology, global system of mobile communication (GSM) communication technology, wireless fidelity (WiFi) communication technology, wideband code division multiple access wireless (WCDMA) communication technology, long term evolution (LTE), 5G communication technology, and other future communication technologies.

[0060] The electronic device in the embodiment of the present application can be a mobile phone with an image acquisition function, a tablet computer (pad), a laptop computer, a smart home, a camera, a video camera, a smart wearable device (for example, a smart watch, a smart bracelet, smart glasses, a smart helmet), a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, etc. The electronic device can also be a handheld device with a wireless communication function, a computing device or other processing device connected to a wireless modem, an in-vehicle device, an electronic device in a 5G network, or an electronic device in a public land mobile communication network (PLMN) to be evolved in the future, etc., and the embodiment of the present application is not limited to this. For the convenience of illustration, the following examples are all taken as an example of an electronic device being a mobile phone.

[0061] In some embodiments, as shown in FIG1 , the electronic device 01 provided in the embodiment of the present application may include a display screen 02, a rear case 03 located on the back of the display screen 02 (arranged opposite to the display surface of the display screen 02), and a middle frame 04 located between the display screen 02 and the rear case 03. The middle frame 04 can support the display screen 02. The display screen 02 can be a liquid crystal display (LCD), or an organic light emitting diode (OLED) display screen, or a micro or mini light-emitting diode (light-emitting diode) display screen, or a quantum dot light emitting diode (QLED) display screen, etc. The present application does not limit the type of the above display screens.

[0062] The electronic device 01 may further include a processor 05 coupled to the display screen 02. The processor 05 may be disposed on a side of the middle frame 04 away from the display screen 02. The rear housing 03 is buckled onto the middle frame 04, thereby forming an installation space between the rear housing 03 and the middle frame 04 for accommodating the processor 05, a battery, and other components.

[0063] For example, the processor 05 may include one or more processing units, for example, the processor may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0064] In some embodiments, in order to enable the above-mentioned electronic device 01 to realize image acquisition, that is, shooting function, the electronic device 01 provided in the above-mentioned embodiment of the present application may also include a camera module 10, and the camera module 10 may be a front camera module or a rear camera module. For example, the front camera module or the rear camera module may include multiple camera modules 10 as shown in Figure 1. Taking the rear camera module as an example, an opening 06 for exposing part of the camera module 10 is provided on the rear shell 03. In addition, the electronic device 01 also includes a lens cover 07, which is buckled on the camera module 10 to protect the camera module 10. The lens cover 07 has a camera hole 08 for exposing the lens of the camera module 10.

[0065] The camera module 10 may be one or more of a standard camera module, a telephoto camera module, a wide-angle camera module, an ultra-telephoto camera module, and an ultra-wide-angle camera module. This application does not limit the number of camera modules 10 . FIG1 illustrates an example in which a rear-facing camera module includes three camera modules 10 .

[0066] The structure of the camera module 10 is described below by way of example. In some embodiments of the present application, as shown in FIG2 , the camera module 10 may include a variable aperture 11, a lens assembly 12, and a motor 13. For ease of description, an XYZ coordinate system is established in the figure, where the Z direction may be the direction of the optical axis O1-O2 of the lens assembly 12, i.e., the thickness direction of the camera module 10 and its components. The XY plane formed by the X and Y directions may be perpendicular to the direction of the optical axis O1-O2 of the lens assembly 12.

[0067] Based on this, the lens assembly 12 may include one or more optical lenses, so that the lens assembly 12 having the optical lenses may utilize the refraction principle of the optical lenses to converge the light of the object being photographed onto the focal plane of the camera module 10 for imaging. The variable aperture 11 is arranged on the light incident side of the lens assembly 12. The variable aperture 11 has an aperture hole 100 with adjustable aperture. By changing the aperture size of the aperture hole 100, the amount of external light entering the camera module 10 can be adjusted. In addition, the motor 13 can drive the lens assembly 12 to move in the Z direction to achieve auto focus (AF). Or, for example, the motor 13 can also drive the lens assembly 12 to move in the XY plane or rotate around the optical axis OO of the lens assembly 12 to achieve optical image stabilization.

[0068] On this basis, in order to enable the camera module 10 to perform photoelectric conversion on light incident therein to generate image information, as further shown in FIG3 , the camera module 10 may further include a filter 14, an image sensor 20, and a circuit board 15. The image sensor 20 is disposed on the circuit board 15 and coupled to the circuit board 15, thereby enabling the image sensor 20 to be coupled to the processor 05 (as shown in FIG1 ) disposed on the circuit board 15. For example, the circuit board 15 may be a PCB or a flexible printed circuit (FPC), which is not limited in this application.

[0069] The filter 14 is disposed on the light-entering side of the image sensor 20. For example, the filter 14 may be an infrared filter that filters out infrared light from the ambient light while transmitting visible light. Alternatively, for example, the filter 14 may be a dual-bandpass filter that selectively transmits wavelengths within two regions of the ambient light, such as visible light and infrared light, visible light and ultraviolet light, or ultraviolet light and infrared light.

[0070] Furthermore, the image sensor 20 is positioned at the focal plane of the camera module 10 so as to receive the optical image of the subject focused by the lens assembly 12. For example, the image sensor 20 may be a CIS or a charge coupled device (CCD) image sensor. For ease of explanation, the following examples utilize a CIS as the image sensor.

[0071] In some embodiments of the present application, as shown in FIG4A , the image sensor 20 may include multiple pixel structures 200 arranged in a matrix. Each pixel structure 200 may convert received light into an electrical signal proportional to the received light. The processor 05 (shown in FIG1 ) receives the electrical signals output by each pixel structure 200 and outputs a corresponding image based on the electrical signals, thereby achieving image acquisition.

[0072] In order to enable the image sensor 20 to output a color image, the pixel structure 200 may filter the received light before performing photoelectric conversion. The colors of the light filtered by the adjacent plurality of pixel structures 200 may include at least three primary colors, such as red (R), green (G), and blue (B). Each pixel structure 200 may serve as a pixel of the image sensor 20. The present application does not limit the arrangement of the plurality of pixel structures 200 in the image sensor 20, that is, the pixel arrangement. For example, the Bayer array arrangement shown in FIG. 4A may be used.

[0073] 4A is an example of a pixel structure 200 with a rectangular outline, which does not limit the outline of the pixel structure 200. In other embodiments of the present application, the outline of the pixel structure 200 may also be circular, elliptical, etc.

[0074] On this basis, in order to enable the image sensor 20 to have the PDAF function, a pixel structure with the PDAF function needs to be set in the image sensor 20, so that the processor 05 can output a control signal to the motor 13 in Figure 3 according to the information provided by the above-mentioned pixel structure with the focusing function, so that the motor 13 can drive the lens assembly 12 to move along the Z direction to achieve the purpose of automatic focusing.

[0075] In some embodiments of the present application, as further shown in FIG4B , the plurality of pixel structures 200 in the image sensor 20 may include a plurality of first pixel structures 21 and a plurality of second pixel structures 22. Wherein, the second pixel structures 22 may convert all or substantially all of the received light signals into light signals, and output the converted light signals to the processor 05 (as shown in FIG1 ), provided that the photoelectric conversion efficiency requirements are met. Thus, the processor 05 may obtain data of the light signals incident on the second pixel structures 22.

[0076] In addition, the first pixel structure 21 is a pixel structure with a PDAF function. Among them, a portion of the first pixel structure 21 (for example, the white painted portion) can output an electrical signal to the processor 05 (as shown in Figure 1) after photoelectric conversion. This portion is the portion with signal output. Moreover, another portion of the first pixel structure 21 (for example, the black painted portion) does not output the converted electrical signal to the processor 05 after photoelectric conversion. This portion is the portion without signal output. Therefore, the processor 05 can only obtain data from a portion of the light signal incident on the first pixel structure 21.

[0077] Based on this, in order for the processor 05 to obtain human-like left and right eye visual difference information, i.e., phase detection (PD) data, based on different first pixel structures 21, as shown in FIG4B , the plurality of first pixel structures 21 may include a left pixel structure 211 and a right pixel structure 212.

[0078] For example, in the left pixel structure 211, the portion without an electrical signal output (e.g., the black portion) is located on the left side (i.e., the left half), thereby enabling the processor 05 (as shown in FIG1 ) to obtain data of the light signal incident on the right side of the left pixel structure 211, i.e., right (R) phase data. In addition, in the right pixel structure 212, the portion without an electrical signal output (e.g., the black portion) is located on the right side (i.e., the right half), thereby enabling the processor 05 to obtain data of the light signal incident on the left side of the right pixel structure 212, i.e., left (L) phase data.

[0079] Based on this, in some embodiments of the present application, as shown in (a) of FIG. 5 , when the light reflected by the photographed object (represented by the black circle) passes through the left pixel structure 211 and forms an image c1 on the focal plane, the image c2 formed by the light reflected by the photographed object passes through the right pixel structure 212 and forms an image c1 on the focal plane. Image c1 is located on the right, and image c2 is located on the left. Therefore, as shown in (b) of FIG. 5 , the peak position b1 of the R phase data from the left pixel structure 211 obtained by the processor 05 (as shown in FIG. 1 ) does not overlap with the peak position b2 of the L phase data from the right pixel structure 212, and there is a phase difference. Peak position b1 is located on the right, and peak position b2 is located on the left.

[0080] In this case, the processor 05 (as shown in FIG. 1 ) can drive the lens assembly 12 to move downward in the Z direction, so that the distance between the lens assembly 12 and the focal plane decreases from the distance h1 shown in FIG. 5 (a) to the distance h0 shown in FIG. 6 (a). At this time, the image c1 formed on the focal plane by the light reflected by the object being photographed (represented by the black circle) after passing through the left pixel structure 211 coincides with the image c2 formed on the focal plane after the light reflected by the object being photographed passes through the right pixel structure 212. Therefore, as shown in FIG. 6 (b), the peak position b1 of the R phase data from the left pixel structure 211 obtained by the processor 05 (as shown in FIG. 1 ) coincides with the peak position b2 of the L phase data from the right pixel structure 212, achieving autofocus.

[0081] Alternatively, in other embodiments of the present application, as shown in (a) of FIG7 , when the light reflected by the photographed object (represented by the black circle) passes through the left pixel structure 211 and forms an image c1 on the focal plane, the image c2 formed by the light reflected by the photographed object passes through the right pixel structure 212 and forms an image c1 on the focal plane. Image c1 is located on the left, and image c2 is located on the right. Therefore, as shown in (b) of FIG7 , the peak position b1 of the R phase data from the left pixel structure 211 obtained by the processor 05 (as shown in FIG1 ) does not overlap with the peak position b2 of the L phase data from the right pixel structure 212, and there is a phase difference. Peak position b1 is located on the right, and peak position b2 is located on the right.

[0082] In this case, the processor 05 (as shown in FIG. 1 ) can drive the lens assembly 12 to move upward in the Z direction, so that the distance between the lens assembly 12 and the focal plane increases from the distance h2 shown in FIG. 7 (a) to the distance h0 shown in FIG. 6 (a). At this time, the image c1 formed on the focal plane by the light reflected from the object being photographed (represented by the black circle) after passing through the left pixel structure 211 coincides with the image c2 formed on the focal plane after the light reflected from the object being photographed passes through the right pixel structure 212. Therefore, as shown in FIG. 6 (b), the peak position b1 of the R phase data from the left pixel structure 211 obtained by the processor 05 (as shown in FIG. 1 ) coincides with the peak position b2 of the L phase data from the right pixel structure 212, achieving autofocus.

[0083] In summary, the image sensor 20 provided in the embodiment of the present application has a first pixel structure 21 capable of implementing the PDAF function. The first pixel structure 21 includes a left pixel structure 211 capable of obtaining R phase data, and a right pixel structure 212 capable of obtaining L phase data. The processor 05 (as shown in FIG1 ) obtains the phase difference data between the R phase data and the L phase data, and determines the focus position of the lens assembly 12 based on the phase difference data, thereby driving the lens assembly 12 to move in the Z direction and distance to achieve the purpose of autofocus.

[0084] Furthermore, as can be seen from the above, in order for the left pixel structure 211 to provide R phase data and the right pixel structure 212 to provide L phase data, the left half of the left pixel structure 211 and the right half of the right pixel structure 212 do not output any signal. The following describes the structure of an image sensor 20 having either the left pixel structure 211 or the right pixel structure 212.

[0085] In some embodiments of the present application, as shown in FIG8 (a cross-sectional view taken along the dashed line O3-O4 in FIG4B ), the image sensor 20 further includes a substrate 25, and the plurality of first pixel structures 21 are disposed within the substrate 25. For example, the substrate 25 may be a semiconductor substrate, such as a silicon (Si) substrate. For example, the substrate 25 may be a P-type doped silicon substrate, i.e., a P-type silicon substrate.

[0086] Based on this, the first pixel structure 21 may include a first photoelectric conversion unit 2101, a second photoelectric conversion unit 2102, and a third N-type doped layer 2111. The first photoelectric conversion unit 2101 may include a first N-type doped layer 311 and a first P-type doped layer 312 stacked together. The first N-type doped layer 311 and the first P-type doped layer 312 may form a PN junction of the first photoelectric conversion unit 2101. The second photoelectric conversion unit 2102 may include a second N-type doped layer 321 and a second P-type doped layer 322 stacked together. The second N-type doped layer 321 and the second P-type doped layer 322 may form a PN junction of the second photoelectric conversion unit 2102.

[0087] For example, the PN junction can be formed by performing N-type or P-type doping on the substrate 25 in the front end of line (FEOL). For example, the first N-type doping layer 311 and the second N-type doping layer 321 can be formed by performing N-type doping on the substrate 25, such as doping with a tetravalent element. In the formed first N-type doping layer 311 and the second N-type doping layer 321, free electrons are majority carriers and holes are minority carriers. In this way, the first N-type doping layer 311 and the second N-type doping layer 321 are mainly conductive by free electrons. The greater the concentration of the doped element during the N-type doping process, the higher the concentration of majority carriers (free electrons), and the stronger the conductivity of the first N-type doping layer 311 and the second N-type doping layer 321.

[0088] In addition, the first P-type doping layer 312 and the second P-type doping layer 322 can be formed by performing P-type doping in the substrate 25, for example, by doping with divalent elements. In the formed first P-type doping layer 312 and the second P-type doping layer 322, free holes are majority carriers and free electrons are minority carriers. In this way, the first P-type doping layer 312 and the second P-type doping layer 322 are mainly conductive by holes. The greater the concentration of the doped element during the P-type doping process, the higher the concentration of majority carriers (holes), and the stronger the conductive properties of the first P-type doping layer 312 and the second P-type doping layer 322.

[0089] For example, the first photoelectric conversion unit 2101 and the second photoelectric conversion unit 2102 may be photodiodes (PDs). Based on this, the first N-type doped layer 311 may be the first end a1 of the first photoelectric conversion unit 2101, and the first P-type doped layer 312 may be the second end a2 of the first photoelectric conversion unit 2101. Similarly, the second N-type doped layer 321 may be the first end a1 of the second photoelectric conversion unit 2102, and the second P-type doped layer 322 may be the second end a2 of the second photoelectric conversion unit 2102. The photoelectric conversion unit in the embodiments of the present application may be a light-emitting diode or a light-emitting transistor, which is not limited in this application.

[0090] In some embodiments of the present application, the first photoelectric conversion unit 2101 and the second photoelectric conversion unit 2102 may occupy half of the area where the first pixel structure 21 is located. To separate the first photoelectric conversion unit 2101 and the second photoelectric conversion unit 2102, the image sensor 20 may further include a pixel isolation structure 28 disposed within the substrate 25. For example, P-type doping may be performed within the substrate 25 to form a P-well, which may serve as the pixel isolation structure 28.

[0091] On this basis, as shown in FIG8 , the third N-type doped layer 2111 can be disposed within the first P-type doped layer 312, and the third N-type doped layer 2111 is coupled to the first N-type doped layer 311. Furthermore, in some embodiments of the present application, the image sensor 20 can further include a first voltage terminal V1. The third N-type doped layer 2111 can be coupled to the first voltage terminal V1. Since the third N-type doped layer 2111 is coupled to both the first N-type doped layer 311 and the first voltage terminal V1, the first N-type doped layer 311 in the first photoelectric conversion unit 2101 can be coupled to the first voltage terminal V1 via the third N-type doped layer 2111.

[0092] 8 is merely a schematic diagram of the coupling between the third N-type doped layer 2111 and the first voltage terminal V1, and does not limit the coupling method between the third N-type doped layer 2111 and the first voltage terminal V1. The coupling method between the third N-type doped layer 2111 and the first voltage terminal V1 will be illustrated below.

[0093] Based on this, when the voltage of the first voltage terminal V1 is a high voltage, the first voltage terminal V1 can cause the electrons stored in the first N-type doped layer 311 of the first photoelectric conversion unit 2101 to be extracted from the first photoelectric conversion unit 2101 through the third N-type doped layer 2111, so as to clear the electrons in the first photoelectric conversion unit 2101 in real time, so that the first photoelectric conversion unit 2101 cannot output an electrical signal. For example, the voltage of the first voltage terminal V1 can be the power supply voltage VDD, or a voltage near the power supply voltage VDD, or greater than 0V or the ground voltage VSS. This application does not limit the voltage size of the first voltage terminal V1, as long as it can ensure that the electrons in the first photoelectric conversion unit 2101 are cleared in real time.

[0094] For example, the doping concentration of the third N-type doping layer 2111 can be greater than the doping concentration of the first N-type doping layer 311. In this way, the conductivity of the third N-type doping layer 2111 can be greater than the conductivity of the first N-type doping layer 311, thereby making it easier for the third N-type doping layer 2111 to couple with the first voltage terminal V1.

[0095] In summary, as shown in FIG4B , the image sensor 20 provided in the embodiment of the present application may include a plurality of first pixel structures 21 located on a substrate 25 (as shown in FIG8 ). To enable the first pixel structure 21 to implement the PDAF function, the first pixel structure 21 may include a first photoelectric conversion unit 2101 and a second photoelectric conversion unit 2102. As shown in FIG8 , when light is incident on the first pixel structure 21, the first photoelectric conversion unit 2101 receives a portion of the light, and the electrical signal after photoelectric conversion is cleared in real time and cannot be output. The second photoelectric conversion unit 2102 receives another portion of the light, performs photoelectric conversion, and outputs an electrical signal.

[0096] Among them, the first photoelectric conversion unit 2101 shown in Figure 8 is located on the left side of the first pixel structure 21, so the first pixel structure 21 is the left pixel structure 211 shown in Figure 4B. The right side portion of the left pixel structure 211, that is, the second photoelectric conversion unit 2102 in the left pixel structure 211 can output the above-mentioned R phase data. Similarly, as shown in Figure 9 (a cross-sectional view obtained by cutting along the dotted line O5-O6 in Figure 4B), the first photoelectric conversion unit 2101 is located on the right side of the first pixel structure 21, so the first pixel structure 21 is the right pixel structure 212 shown in Figure 4B. The left side portion of the right pixel structure 212, that is, the second photoelectric conversion unit 2102 in the right pixel structure 212 can output the above-mentioned L phase data.

[0097] In this case, on the one hand, only a portion of the first pixel structure 21, for example, the second photoelectric conversion unit 2102 of the first pixel structure 21, can output phase data. Another portion of the first pixel structure 21, namely the first photoelectric conversion unit 2101 of the first pixel structure 21, cannot output an electrical signal and is shielded. As a result, when the position of the first photoelectric conversion unit 2101 is different, the phase data output by the first pixel structure 21 is different. For example, when the first pixel structure 21 is the left pixel structure 211 described above, the second photoelectric conversion unit 2102 in the left pixel structure 211 can output the R phase data described above. When the first pixel structure 21 is the right pixel structure 212 described above, the second photoelectric conversion unit 2102 in the right pixel structure 212 can output the L phase data described above. The processor 05 (as shown in FIG. 1 ) obtains the phase difference data between the R phase data and the L phase data, and determines the focus position of the lens assembly 12 based on the phase difference data, thereby driving the lens assembly 12 to move in the Z direction and distance to achieve the purpose of autofocus.

[0098] On the other hand, in the related art, in order to make the pixels of the image sensor have the PDAF function, as shown in Figure 10, a shielding layer (half shield) 09 is set in the pixel, and the shielding layer 09 can block a part of the light incident on the pixel. For example, the shielding layer 09 can be made of metal material. Since the shielding layer 09 reflects the incident light while blocking the light, the reflected light is incident on the surrounding pixels, thereby affecting the accuracy of the electrical signals output by the surrounding pixels. Therefore, it is also necessary to correct the surrounding pixels. In comparison, in the image sensor 20 provided in the embodiment of the present application, the electrical signal converted by part of the photoelectric conversion part in the first pixel structure 21 with the PDAF function is cleared in real time, so that it cannot output a signal. Therefore, there is no need to set the above-mentioned shielding layer to avoid affecting the surrounding pixels.

[0099] As can be seen from the above, in order to enable the image sensor 20 to realize the image acquisition function, as shown in Figure 4B, the image sensor 20 can further include multiple second pixel structures 22 as shown in Figure 4B. As can be seen from the above, when the photoelectric conversion efficiency requirements are met, the second pixel structure 22 can convert all or nearly all of the received light signals into light signals.

[0100] Based on this, as shown in Figure 11 (a cross-sectional view obtained by cutting along the dotted line O7-O8 in Figure 4B), the second pixel structure 22 is arranged in the substrate 25. The second pixel structure 22 may include at least two third photoelectric conversion parts 2103. The third photoelectric conversion part 2103 may include a fourth N-type doping layer 331 and a fourth P-type doping layer 332 that are stacked. Similarly, the fourth N-type doping layer 331 and the fourth P-type doping layer 332 may form a PN junction of the third photoelectric conversion part 2103. For example, the second pixel structure 22 may include two third photoelectric conversion parts 2103, and each third photoelectric conversion part 2103 may occupy half of the area where the second pixel structure 22 is located. In this way, all third photoelectric conversion parts 2103 within the area where the second pixel structure 22 is located can perform photoelectric conversion on the incident light to achieve image acquisition.

[0101] In some embodiments of the present application, in the image sensor 20 shown in Figure 12, the number of the plurality of first pixel structures 21 in the sum of the number of the plurality of first pixel structures 21 and the plurality of second pixel structures 22 may account for 1% to 12%. When the above-mentioned proportion is less than 1%, the number of the first pixel structures 21 in the image sensor 20 is small, which is not conducive to ensuring the accuracy of PDAF. In addition, when the above-mentioned proportion is greater than 12%, the number of the first pixel structures 21 in the image sensor 20 is large, resulting in a small number of the second pixel structures 22, which reduces the accuracy of image acquisition. For example, the above-mentioned proportion may be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 10%, 11% or 12%.

[0102] On this basis, as shown in FIG12 , the image sensor 20 may include a plurality of first microlenses 23, each of which may cover a first pixel structure 21. The first microlenses 23 may converge incident light onto the first pixel structure 21 to improve photoelectric conversion efficiency. Furthermore, the image sensor 20 may also include a plurality of second microlenses 27, each of which may cover a second pixel structure 22. The technical effects of the second microlenses 27 are similar and will not be further described here.

[0103] For example, as shown in Figure 12, a first pixel structure 21 may include a first photoelectric conversion unit 2101 and a second photoelectric conversion unit 2102, and the first photoelectric conversion unit 2101 and the second photoelectric conversion unit 2102 may occupy half of the area where the first pixel structure 21 is located. The first photoelectric conversion unit 2101 and the second photoelectric conversion unit 2102 may share a first microlens 23. In addition, a second pixel structure 22 may include two third photoelectric conversion units 2103, and each third photoelectric conversion unit 2103 may occupy half of the area where the second pixel structure 22 is located. The two third photoelectric conversion units 2103 may share a second microlens 27. In this case, the image sensor 20 may be a 2×1 on-chip lens (OCL) structure, referred to as a 2×1 OCL structure, or a dual PD structure.

[0104] As another example, as shown in FIG13 , the first pixel structure 21 may include two first photoelectric conversion units 2101 and two second photoelectric conversion units 2102, and the two first photoelectric conversion units 2101 and the two second photoelectric conversion units 2102 may share one first microlens 23. The two first photoelectric conversion units 2101 and the two second photoelectric conversion units 2102 may form a 2×2 matrix. The two first photoelectric conversion units 2101 may be located on the same side of the 2×2 matrix, i.e., the area where the first pixel structure 21 is located, so that the two first photoelectric conversion units 2101 may occupy half of the area where the first pixel structure 21 is located. The two second photoelectric conversion units 2102 may be located on the other side of the 2×2 matrix, i.e., the area where the first pixel structure 21 is located, so that the two second photoelectric conversion units 2102 may occupy the other half of the area where the first pixel structure 21 is located.

[0105] 13 , a second pixel structure 22 may include four third photoelectric conversion units 2103, each of which may occupy ¼ of the area where the second pixel structure 22 is located. The four third photoelectric conversion units 2103 may share one second microlens 27. In this case, the image sensor 20 may have a 2×2 OCL structure.

[0106] On this basis, in some embodiments of the present application, when the image sensor 20 may be an active pixel sensor (APS), as shown in FIG14 , the image sensor 20 may further include a back-end process structure 26 disposed on a substrate 25. The back-end process structure 26 may have a circuit structure for controlling the photoelectric conversion unit. For example, the back-end process structure 26 may include an insulating layer 261 and a multi-layer metal pattern layer 262 disposed in the insulating layer 261. The metal pattern layer 262 includes metal traces and electronic components for constituting the circuit structure. The metal pattern layer 262 may be prepared in a back-end of line (BEOL) process.

[0107] For example, the image sensor 20 may be a backside illumination (BSI) image sensor. In this case, as shown in FIG14 (another cross-sectional view taken along dashed line O3-O4 in FIG4B ), the back-end process structure 26 and the first microlens 23 may be disposed on opposite sides of the substrate 25. Consequently, light from the first microlens 23 can be directly incident on the first photoelectric conversion unit 2101 and the second photoelectric conversion unit 2102 within the substrate 25 without passing through the back-end process structure 26, thereby minimizing light loss.

[0108] 14 , in order to filter the light from the first microlens 23 to obtain one of the three primary colors, the image sensor 20 may further include a color filter (CF) 24. The color filter 24 may be disposed on the surface of the first microlens 23 facing the substrate 25.

[0109] Alternatively, as another example, the image sensor 20 may be a front-side illumination (FSI) image sensor. In this case, as shown in FIG15 (another cross-sectional view taken along dashed line O3-O4 in FIG4B ), the back-end process structure 26 may be disposed between the first microlens 23 and the substrate 25. Thus, light from the first microlens 23 may first pass through the back-end process structure 26 before being incident on the first photoelectric conversion unit 2101 and the second photoelectric conversion unit 2102 within the substrate 25.

[0110] As can be seen from the above, as shown in Figure 8, in the first photoelectric conversion unit 2101, the first N-type doped layer 311 can be coupled to the first voltage terminal V1 via the third N-type doped layer 2111. When the voltage at the first voltage terminal V1 is high, the first voltage terminal V1 can cause electrons stored in the first N-type doped layer 311 of the first photoelectric conversion unit 2101 to be extracted from the first photoelectric conversion unit 2101 via the third N-type doped layer 2111, thereby clearing the electrons in the first photoelectric conversion unit 2101 in real time and preventing the first photoelectric conversion unit 2101 from outputting an electrical signal. The following describes an example of how the third N-type doped layer 2111 is coupled to the first voltage terminal V1.

[0111] In some embodiments of the present application, as shown in FIG14 , the back-end process structure 26 may include an insulating layer 261 and a multi-layer metal pattern layer 262 disposed within the insulating layer 261. The first metal pattern layer 262 may include a first metal line 2621 as shown in FIG16 (a top view taken along the direction A in FIG14 ). The first metal line 2621 may be disposed within the insulating layer 261 (as shown in FIG14 ). The first metal line 2621 may have two ends coupled to the third N-type doped layer 2111 and the first voltage terminal V1, respectively.

[0112] Based on this, as shown in FIG16 , when first metal wire 2621 is used to couple third N-type doped layer 2111 to first voltage terminal V1, a FEOL process can be used to first form first photoelectric conversion unit 2101, second photoelectric conversion unit 2102, and third N-type doped layer 2111 within substrate 25 as shown in FIG14 . A BEOL process is then used to form back-end-of-line (BEOL) structure 26 on substrate 25. A portion of first metal pattern layer 262 in back-end-of-line (BEOL) structure 26 can serve as the first metal wire 2621.

[0113] For example, as shown in FIG16 , the first voltage terminal V1 may be a pad structure 29 formed by ion doping in the substrate 25. For example, N-type doping is performed in the substrate 25 to form the pad structure 29. Alternatively, for another example, the first voltage terminal V1 may be a pin in the image sensor 20 for coupling to the circuit board 15 shown in FIG3 . This application does not limit the configuration of the first voltage terminal V1. For convenience of description, the following description is based on an example in which the first voltage terminal V1 is the pad structure 29 shown in FIG16 .

[0114] Alternatively, as another example, as shown in FIG17 (a top view taken along the direction A in FIG14 ), the third N-type doped layer 2111 can extend to the first voltage terminal V1, and the third N-type doped layer 2111 can be coupled to the first voltage terminal V1. Based on this, when the first voltage terminal V1 is a pad structure 29 formed by a doping process, a FEOL process can be used to first form the first photoelectric conversion unit 2101, the second photoelectric conversion unit 2102, and the pad structure 29 within the substrate 25 as shown in FIG14 . Then, the third N-type doped layer 2111 is formed by a doping process, and the doping area of ​​the third N-type doped layer 2111 is controlled so that the third N-type doped layer 2111 can extend to the pad structure 29 and couple to the pad structure 29, thereby achieving the purpose of coupling the third N-type doped layer 2111 to the first voltage terminal V1.

[0115] In addition, when the image sensor 20 is coupled to the circuit board 15 shown in FIG3 , the circuit board 15 can independently provide a high voltage to the first voltage terminal V1 of the image sensor 20. Alternatively, when the image sensor 20 can be an APS, the first voltage terminal V1 can also be coupled to the circuit structure in the back-end process structure 26 to achieve voltage terminal sharing. The following describes the manner in which the third N-type doped layer 2111 is coupled to the first voltage terminal V1 in any of FIG16 or FIG17 , taking the image sensor 20 as a 2×1 OCL structure, that is, the first pixel structure 21 of the image sensor 20 includes a first photoelectric conversion unit 2101 and a second photoelectric conversion unit 2102 as an example, to illustrate the manner in which the first voltage terminal V1 is coupled to the above-mentioned circuit structure.

[0116] In some embodiments of the present application, the back-end process structure 26 shown in FIG14 may further include an output trace RL shown in FIG18 , which is disposed on the substrate 25 as part of the first metal pattern layer 262. The first pixel structure 21 may further include a source follower transistor Tsf, a gate transistor Tsel, and a reset transistor Trst as shown in FIG18 .

[0117] Continuing with FIG18 , the gate (gate, g) of the source-follower transistor Tsf can be coupled to the first P-type doped layer 312 and the second P-type doped layer 322 (as shown in FIG14 ). That is, the gate g of the source-follower transistor Tsf is coupled to the second photoelectric conversion unit 2102, and the first electrode d1 of the source-follower transistor Tsf can be coupled to the first voltage terminal V1. The first electrode d1 of the gate transistor Tsel is coupled to the second electrode d2 of the source-follower transistor Tsf, and the second electrode d2 of the gate transistor Tsel can be coupled to the output trace SL.

[0118] In this case, the first photoelectric conversion unit 2101 and the second photoelectric conversion unit 2102 receive the incident light and perform photoelectric conversion. In the first photoelectric conversion unit 2101, the first N-type doped layer 311 as the first end a1 is coupled to the first voltage end V1 through the third N-type doped layer 2111 (as shown in FIG14 ). When the first voltage end V1 outputs a high voltage, such as the power supply voltage VDD, it can be seen from the above that the electrons stored in the first photoelectric conversion unit 2101 are cleared in real time. When the selection transistor Tsel is turned on, the electrical signal stored in the second photoelectric conversion unit 2102 can turn on the selection transistor Tsel, so that the electrical signal from the first voltage end V1 can be transmitted to the output trace SL through the source follower transistor Tsf and the selection transistor Tsel. The output trace SL can be coupled to the processor 05 on the circuit board (as shown in FIG1 ) so that the first pixel structure 21 can output the electrical signal converted from a portion of the incident light to the above-mentioned processor 05.

[0119] Furthermore, the first electrode d1 of the source follower transistor Tsf and the first N-type doped layer 311 as the first terminal a1 in the first photoelectric conversion unit 2101 are both coupled to the first voltage terminal V1, thereby enabling the sharing of voltage terminals of different devices and simplifying the circuit structure.

[0120] Furthermore, the first electrode d1 of the reset transistor Trst can be coupled to the reset voltage terminal Vrst, and the second electrode d2 of the reset transistor Trst can be coupled to the first P-type doped layer 312 and the second P-type doped layer 322 (as shown in FIG14 ). That is, the second electrode d2 of the reset transistor Trst is coupled to the second photoelectric conversion unit 2102. In this way, before the source follower transistor Tsf is turned on, the reset transistor Trst can be turned on first to reset the second photoelectric conversion unit 2102 via the reset voltage terminal Vrst, thereby improving the photoelectric conversion accuracy of the image sensor 20.

[0121] In the embodiment of the present application, the first electrode d1 of the transistor may be the source electrode (source, s) of the transistor, and the second electrode d2 may be the drain electrode (drain, d) of the transistor. Alternatively, the first electrode d1 of the transistor may be the drain electrode d of the transistor, and the second electrode d2 may be the source electrode s of the transistor, which is not limited in the present application.

[0122] The above description is based on an example in which the first N-type doped layer 311 as the first terminal a1 and the first electrode d1 of the gate transistor Tsel in the first photoelectric conversion unit 2101 are coupled to the first voltage terminal V1. In this case, the first voltage terminal V1 may be the power supply voltage VDD.

[0123] Alternatively, in other embodiments of the present application, as shown in FIG19 , the first electrode d1 of the selection transistor Tsel can receive the power supply voltage VDD. In the first photoelectric conversion unit 2101, the first N-type doped layer 311 serving as the first terminal a1 and the first electrode d1 of the reset transistor Trst can be coupled to the first voltage terminal V1. Similarly, the first electrode d1 of the reset transistor Trst and the first N-type doped layer 311 serving as the first terminal a1 in the first photoelectric conversion unit 2101 are both coupled to the first voltage terminal V1, thereby enabling the sharing of voltage terminals across different devices and simplifying the circuit structure.

[0124] Alternatively, in other embodiments of the present application, as shown in Figure 20, in the first photoelectric conversion unit 2101, the first N-type doped layer 311 serving as the first terminal a1, the first electrode d1 of the selection transistor Tsel, and the first electrode d1 of the reset transistor Trst can all be coupled to the first voltage terminal V1.

[0125] The above description uses as an example a circuit structure for controlling the photoelectric conversion portion including three transistors, such as a source follower transistor Tsf, a gate transistor Tsel, and a reset transistor Trst, i.e., a 3T structure. In other embodiments of the present application, as shown in FIG21 , the image sensor may further include a transmission control voltage terminal VX. In addition, the first pixel structure 21 may further include a floating diffusion (FD) 2201 and a first transfer transistor TX1 and a second transfer transistor TX2.

[0126] FIG21 illustrates an example in which the first electrode d1 of the reset transistor Trst is coupled to the reset voltage terminal Vrst, and the first electrode d1 of the source follower transistor Tsf receives the power supply voltage VDD. In other embodiments of the present application, the first electrode d1 of the reset transistor Trst or the first electrode d1 of the source follower transistor Tsf can be electrically coupled to the first voltage terminal V1.

[0127] The first transfer transistor TX1 has two electrodes (first electrode d1 and second electrode d2) coupled to the first photoelectric conversion unit 2101 and the floating diffusion 2201, respectively. The gate g of the first transfer transistor TX1 is coupled to the transfer control voltage terminal VX. Similarly, the second transfer transistor TX2 has two electrodes coupled to the second photoelectric conversion unit 2102 and the floating diffusion 2201, respectively.

[0128] In this case, when the second transfer transistor TX2 is turned on, the electrical signal stored in the second photoelectric conversion unit 2102 can be transmitted to the floating diffusion area 2201. Similarly, when the selection transistor Tsel is turned on, the power supply voltage VDD can be transmitted to the output line SL through the source follower transistor Tsf and the selection transistor Tsel.

[0129] Furthermore, because the first N-type doped layer 311, serving as the first terminal a1, in the first photoelectric conversion unit 2101 is coupled to the first voltage terminal V1 (e.g., the power supply voltage VDD), it can be seen from the above description that the electrons in the first N-type doped layer 311 of the first photoelectric conversion unit 2101 are emptied in real time, preventing the first photoelectric conversion unit 2101 from transmitting an electrical signal to the floating diffusion area 2201. Therefore, to further ensure that the first photoelectric conversion unit 2101 does not transmit an electrical signal to the floating diffusion area 2201, in some embodiments of the present application, the voltage of the first voltage terminal V1 may be greater than the voltage of the transmission control voltage terminal VX.

[0130] For example, when the first voltage terminal V1 is a high voltage, such as the power supply voltage VDD, the transmission control voltage terminal VX can be a low voltage. For example, as shown in Figure 22 (another cross-sectional view obtained by cutting along the dotted line O3-O4 in Figure 4B), the gate TXG of the first transmission transistor is coupled to the ground voltage VSS. In this case, the transmission control voltage terminal VX can be grounded. This application does not limit the voltage of the transmission control voltage terminal VX, as long as it can ensure that the first transmission transistor TX1 is in the off state. The structure of the second photoelectric conversion unit is not shown in Figure 22.

[0131] Based on this, for example, to couple the gate TXG of the first transfer transistor to the ground voltage VSS, the first metal pattern layer 262 in the back-end process structure 26 (as shown in FIG14 ) may include a second metal line 2622 as shown in FIG23 (a top view taken along the direction B in FIG22 ). The two ends of the second metal line 2622 may be coupled to the gate TXG and the ground voltage VSS (not shown in FIG23 ), respectively. Similarly, the second metal line 2622 and the first metal line 2621 may be completed in the above-mentioned BEOL process.

[0132] Alternatively, as another example, as shown in FIG24 (another top view taken along the direction B in FIG22 ), in the FEOL process, the third N-type doped layer 2111 is extended to the first voltage terminal V1 and coupled to the first voltage terminal V1. In the BEOL process, a second metal line 2622 is prepared for coupling the gate TXG of the first transfer transistor to the ground voltage VSS.

[0133] As can be seen from the above, FIG18 is an example of a circuit structure for controlling the photoelectric conversion unit having a 3T structure. FIG21 is an example of a circuit structure for controlling the photoelectric conversion unit having a 4T structure, for example, including a source follower transistor Tsf, a gate transistor Tsel, a reset transistor Trst, and a transfer transistor (TX1 or TX2). This does not limit the above circuit structure, and the configuration of other circuit structures can be obtained similarly, which will not be repeated here.

[0134] In other embodiments of the present application, to further ensure that the first photoelectric conversion unit 2101 does not transmit electrical signals to the floating diffusion area 2201, as shown in FIG25 (another cross-sectional view obtained by cutting along the dotted line O3-O4 in FIG4B ), the first pixel structure 21 may further include a third P-type doped layer 2202, which is disposed within the substrate 25. The vertical projection of the gate TXG of the first transfer transistor TX1 on the substrate 25 may overlap with the region where the third P-type doped layer 2202 is located.

[0135] In this way, the third P-type doped layer 2202 can be disposed between the first N-type doped layer 311, which serves as the first photoelectric conversion unit 2101, and the floating diffusion region 2201. This can isolate the first N-type doped layer 311 from the floating diffusion region 2201, preventing electrons in the first N-type doped layer 311 from flowing into the floating diffusion region 2201, thereby preventing the first photoelectric conversion unit 2101 from outputting any electrical signals. In this case, the gate TXG of the first transfer transistor TX1 can be coupled to the low voltage, such as the ground voltage VSS, or connected to a gate voltage for turning on the first transfer transistor TX1.

[0136] The above is only a specific embodiment of the present application, but the scope of protection of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An image sensor, characterized in that: include: a first voltage terminal; substrate; A plurality of first pixel structures are disposed in the substrate; The first pixel structure includes: The first photoelectric conversion portion includes a first N-type doping layer and a first P-type doping layer stacked together; The second photoelectric conversion portion includes a second N-type doping layer and a second P-type doping layer stacked together; The third N-type doping layer is disposed in the first P-type doping layer and coupled to the first N-type doping layer. The third N-type doping layer is coupled to the first voltage terminal.

2. The image sensor according to claim 1, wherein The image sensor further includes: A plurality of first micro lenses are disposed on the substrate; one first micro lens covers one first pixel structure.

3. The image sensor according to claim 2, wherein: The image sensor further includes a back-end process structure, which is disposed on the substrate and includes: Insulation layer; A first metal wire is disposed in the insulating layer, and two ends of the first metal wire are respectively coupled to the third N-type doped layer and the first voltage end.

4. The image sensor according to claim 3, wherein: The back-end process structure and the first microlens are respectively arranged on opposite sides of the substrate; or, The back-end process structure is arranged between the first microlens and the substrate.

5. The image sensor according to claim 1 or 2, characterized in that The image sensor further includes: An output wiring is provided on the substrate; The first pixel structure further includes: a source-follower transistor, wherein a gate of the source-follower transistor is coupled to the second photoelectric conversion unit, and a first electrode of the source-follower transistor is coupled to the first voltage terminal; A gate transistor, wherein a first electrode of the gate transistor is coupled to a second electrode of the source follower transistor, and a second electrode of the gate transistor is coupled to the output wiring.

6. The image sensor according to claim 1 or 2, characterized in that The image sensor further includes: A reset transistor, wherein a first electrode of the reset transistor is coupled to the first voltage terminal, and a second electrode of the reset transistor is coupled to the second photoelectric conversion unit.

7. The image sensor according to claim 5 or 6, characterized in that The third N-type doped layer extends to the first voltage terminal and is coupled to the first voltage terminal.

8. The image sensor according to any one of claims 1 to 7, wherein: The image sensor further includes a transmission control voltage terminal; The first pixel structure further includes: floating diffusion area; A first transfer transistor, wherein two electrodes of the first transfer transistor are respectively coupled to the first photoelectric conversion portion and the floating diffusion area; and a gate of the first transfer transistor is coupled to the transfer control voltage terminal.

9. The image sensor according to claim 8, wherein: The voltage of the first voltage terminal is greater than the voltage of the transmission control voltage terminal.

10. The image sensor according to claim 8 or 9, characterized in that The transmission control voltage terminal is grounded.

11. The image sensor according to any one of claims 8 to 10, characterized in that: The first pixel structure further includes: A third P-type doped layer is disposed in the substrate; a vertical projection of the gate of the first transfer transistor on the substrate overlaps with a region where the third P-type doped layer is located.

12. The image sensor according to any one of claims 1 to 11, characterized in that: The doping concentration of the third N-type doping layer is greater than the doping concentration of the first N-type doping layer.

13. The image sensor according to any one of claims 1 to 12, wherein: The first pixel structure includes two first photoelectric conversion parts and two second photoelectric conversion parts; the two first photoelectric conversion parts and the two second photoelectric conversion parts form a 2×2 matrix; The two first photoelectric conversion parts are located on the same side of the 2×2 matrix.

14. The image sensor according to any one of claims 1 to 13, wherein: The image sensor further includes: A plurality of second pixel structures are arranged in the substrate; the second pixel structures include at least two third photoelectric conversion parts; the third photoelectric conversion parts include a fourth N-type doping layer and a fourth P-type doping layer that are stacked.

15. The image sensor according to claim 13, wherein: The number of the plurality of first pixel structures accounts for 1% to 12% of the total number of the plurality of first pixel structures and the plurality of second pixel structures.

16. The image sensor according to any one of claims 1 to 15, characterized in that: The plurality of first pixel structures include: a left pixel structure, wherein the first photoelectric conversion portion is located on the left side; A right pixel structure, in which the first photoelectric conversion portion is located on the right side.

17. An electronic device, characterized in that: include: circuit boards; The image sensor according to any one of claims 1 to 16, wherein the image sensor is coupled to the circuit board.

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