Methods of patterning for high aspect ratio catalyst assisted chemical etching

Abstract

Catalyst assisted chemical etching of semiconductor substrate can achieve extreme aspect ratio (better than 1000:1), reproducibility and controlled etching quality for submicron feature size in the direction perpendicular to the substrate. The current patterning methods of the catalyst layer suffer of carbon contamination that affects the etching quality and limits the high-resolution pattern transfer in the semiconductor substrate for high aspect ratio etching. The present method allows to use semiconductor standard manufacturing processes to realize carbon-free pattern of catalyst layer by a physical separation with an interlayer material between the catalyst and the polymeric resist used in common lithographic methods. The present method allows to realize controlled predefined nanostructures with high resolution, high fidelity and high throughput yield during the catalyst assisted chemical etching of silicon for X-ray optics nanofabrication.

Description

[0001] Methods of patterning for high aspect ratio catalyst assisted chemical etching

[0002] The present invention is related to a method of patterning a catalyst for reducing the catalyst contamination in high aspect ratio catalyst assisted chemical etching.

[0003] Catalyst assisted chemical etching allows to pattern extremely high aspect ratio - in the range of 1000:1 or even higher aspect ratio - in silicon substrates, with recess forming in the direction perpendicular (vertical) to the substrate. The mechanism is different from conventional wet etching or dry etching process, where the substrate material is removed in the mask-free regions. In catalyst assisted chemical etching the substrate material is removed underneath a catalyst covered region with a consequent sinking down of the catalyst region inside the semiconductor substrate material. The catalyst for silicon etching is usually Ag, Au, Pt, Pd. It has been recently demonstrated also with Cu, TiN, Ru, Rh, Graphene Oxide. The etchant contains HF in liquid or gas form and an oxidant in liquid or gas form.

[0004] Catalyst assisted chemical etching with CMOS compatible catalyst has been recently demonstrated therefore, the present invention might have a relevant impact for 3D semiconductor devices, if properly addressed. The fabrication of silicon electron multipler sensors by catalyst assisted chemical etching in gas phase has been recently demonstrated. Submicron feature size is critical and the device fabrication cannot be addressed with more conventional etching technologies, such as dry-etch. Nanofabrication of X-ray optics at high aspect ratio template (submicron feature size and aspect ratio in the range > 200:1) such as gratings and zone plates with submicron features with silicon as for X-ray interferometers applications is improved with the present invention. The present invention would allow to extend the energy range of dual phase interferometers for material science and medical applications. Other interesting applications are nanostructured bio-interfaces, silicon based photonics, metasurfaces, high aspect ratio nanostructures for metalenses in silicon, silicon based thermoelectrical devices, nanostructures for batteries or other energy applications, sensor devices which requires high aspect ratio nanostructured components, MEMS.

[0005] Extreme high aspect ratio (10’000:1) has been reported using MacEtch in gas phase but only using self-assembled catalyst nanoscale patterns (10 nm feature size), which are random and cannot be defined a priori. Nanoscale patterns needs high resolution lithography such as electron beam lithography, interference lithography or nanoimprint lithography, using a layer of carbon-based resist material that can be patterned at the nanoscale. Then, the pattern is transferred to the catalyst layer.

[0006] Prior art shows that a very thin layer of amorphous carbon formed during electron beam lithography underneath of a catalyst layer is sufficient for localized blocking of the metal assisted etching of silicon. The carbon residuals are responsible for uncontrolled etching, unreproducible etching rate and uncontrolled change of the etching direction, limiting so far the aspect ratio of patterned nanostructures, especially in gas-phase MacEtch, where the process is extremely diffusion limited. The smaller is the feature size, the higher is the probability of introducing a local defect, which pins the catalyst and can initiate a rotation movement, introducing a dramatic distortion and compromising the pattern transfer fidelity.

[0007] According to the present invention, the new method comprises the step of creating a carbon-free physical separation between the catalyst layer and the patterned layer, which shows improved throughput yield, higher level of control of the catalyst movement and increased etching rate.

[0008] The pattern transfer at nanoscale from the layer where the lithographic method has been executed to the catalyst layer can produce several defects, which compromise the quality of the etching in the direction perpendicular to the substrate, introducing huge deformations during the etching. Catalyst assisted chemical etching of silicon has been achieved by patterning catalyst nanoparticles and catalyst thin films using colloidal crystal templating, photo- and electron beam lithography, microcontact imprinting, and focused ion beam deposition. However, the etching direction of the catalyst pattern is difficult to control and a significant deformation of the catalyst pattern can occur during the etching process. Extreme aspect ratio (10’000:1) has been demonstrated in self-assembled nanostructures of platinum on silicon substrates without the use of pattern transfer method from lithographic step involving polymeric resist materials. It has been demonstrated that a very thin layer of amorphous carbon formed using electron beam deposition underneath of a catalyst layer is sufficient for localized blocking of gold assisted etching of silicon. This has not been recognized so far as a limiting factor for the quality of catalyst assisted chemical etching at nanoscale for high aspect ratio structures since most of the experiments have been conducted in liquid phase and for limited aspect ratio, the pinning effect of a carbon residual in the catalyst layer is less evident and less critical for low aspect ratio etching. Instead, this effect is particularly relevant for catalyst assisted chemical etching with high resolution nanoscale patterns and for high aspect ratio etching. The methods used so far for pattern transfer into the catalyst layer, such as lift-off and ion beam etching, have a very low throughput yield and cause low quality structures produced by catalyst assisted chemical etching. With conventional lithographic methods, usually a plasma cleaning step is performed before the catalyst deposition, wherein the plasma contains oxygen to provide a reactive specie for residuals of resist material.

[0009] However, these methods are not efficient to provide a carbon-free surface suitable for a clean interfacial contact of the catalyst with the substrate, especially with dense patterns and pattern features at nanoscale. The observation is not trivial since the catalyst assisted chemical etching is much more sensitive to surface chemistry than other etching processes, such as for example alkaline- based wet-etching and plasmabased dry-etching processes. Common cleaning treatments used for example for pattern transfer in plasma-based dry-etching processes are not sufficient. The effect of partial cleaning of the surface is not obvious since the catalyst assisted chemical etching is not a standard process. A carbon contaminated surface underneath the catalyst can produce a degradation of the etching profile or a local decrease of the etching rate but the phenomena has not been systematically investigated so the effects can be erroneously attributed to other concurrent mechanisms, such a local decrease of the reactant species or partially reactive catalyst due to chemical instability or low reliability of pattern transfer method such as lift-off for feature size in the range of 1- 100 nm. More aggressive chemicals damage the resist pattern limiting the choice of available treatments to restore the surface quality of the semiconductor substrate before the catalyst is deposited. Moreover, the resist material can be deteriorated and being a source of carbon contamination even during the catalyst deposition, especially for thermal evaporation of high melting temperature catalyst materials, such as Au, Pt, Ru, Pd etc. In liftoff, the catalyst is deposited on a patterned resist and then lifted off. This might cause the catalyst being redeposited elsewhere on the substrate. While it produces precise patterning in certain regions, it suffers from high detectivity and low yield overall. Additionally, lift-off typically requires an undercut layer below the resist which limits the resolution of the nanopattern.

[0010] In order to overcome these deficiencies, the present invention discloses a method according to claim 1. In particular, said method comprises a method step of creating a physical separation between the catalyst layer and the patterned polymer layer in order to eliminate completely the carbon contamination underneath of the catalyst layer in contact with the semiconductor substrate. The manufacturing sequence to realize such physical separation comprises common process steps in semiconductor manufacturing where the 3D structuring is obtained layer by layer by a top down approach and processing one layer per time.

[0011] The concept of the physical separation layer in the present invention differs in the function with respect to the undercut layer, used to promote lift-off, or to favor the catalyst brake, which helps only in the initial phase of the catalyst assisted reaction. The function of the separation layer is not intended to modify the catalytic activity of the catalyst layer or to reduce the porosity in the etched structures, which can be a secondary effect if the separation layer is not completely removed before the process of catalyst assisted chemical etching. In some embodiments of the present invention the separation layer is removed before the process of catalyst assisted chemical etching. The function of the separation layer is not intended to tune the etching depth in different regions but the opposite, the separation layer improves the uniformity of the etching depth in the whole patterned area.

[0012] Other preferred embodiments of the present invention are disclosed in the dependent claims 2 to 14.

[0013] Applications

[0014] Semiconductor nanofabrication (the method can be CMOS compatible); nanofabrication of high aspect ratio (>200:1) X-ray optics such as gratings and zone plates with submicron features with silicon as template, nanostructured bio-interfaces, silicon based photonics, metasurfaces, high aspect ratio nanostructures for metalenses in silicon, silicon based thermoelectrical devices, nanostructures for batteries or other energy applications, sensor devices which requires high aspect ratio nanostructured components, MEMS.

[0015] Preferred embodiments of the present invention are hereinafter described in more detail with reference to the attached drawings which depict the following:

[0016] Figure 1 depicts cross sectional view of creating a pattern for catalyst assisted chemical etching according to one embodiment of the present invention: providing a semiconductor substrate (A); providing a separation layer on top of the semiconductor substrate (B); providing a patterning layer (C); providing a pattern to the patterning layer (D); transferring the pattern to the separation layer (E); providing a catalyst layer and a patterned catalyst layer (F); exposing the semiconductor substrate and the patterned catalyst layer thereon to a process of catalyst assisted chemical etching (G).

[0017] Figure 2 depicts cross sectional view of creating a pattern for catalyst assisted chemical etching according to one embodiment of the present invention: providing a semiconductor substrate (A); providing a separation layer on top of the semiconductor substrate (B); providing a patterning layer (C); providing a pattern to the patterning layer (D); transferring the pattern to the separation layer (E); removing the patterning layer (F); providing a catalyst layer and a patterned catalyst layer (G); exposing the semiconductor substrate and the patterned catalyst layer thereon to a process of catalyst assisted chemical etching (H).

[0018] Figure 3 depicts cross sectional view of creating a pattern for catalyst assisted chemical etching according to one embodiment of the present invention: providing a semiconductor substrate (A); providing a sacrificial layer on top of the semiconductor substrate (B); providing a separation layer (C); providing a patterning layer (D); providing a pattern to the patterning layer (E); transferring the pattern to the separation layer (F); transferring the pattern to the sacrificial layer (G); providing a catalyst layer and a patterned catalyst layer (H); exposing the semiconductor substrate and the patterned catalyst layer thereon to a process of catalyst assisted chemical etching (I).

[0019] Figure 4 depicts cross sectional view of creating a pattern for catalyst assisted chemical etching according to one embodiment of the present invention: providing a semiconductor substrate (A); providing a sacrificial layer on top of the semiconductor substrate (B); providing a separation layer (C); providing a patterning layer (D); providing a pattern to the patterning layer (E); transferring the pattern to the separation layer (F); transferring the pattern to the sacrificial layer (G); removing the patterning layer (H); providing a catalyst layer and a patterned catalyst layer (I); exposing the semiconductor substrate and the patterned catalyst layer thereon to a process of catalyst assisted chemical etching (J).

[0020] Figure 5 depicts cross sectional view of creating a pattern for catalyst assisted chemical etching according to one embodiment of the present invention: providing a semiconductor substrate (A); providing a sacrificial layer on top of the semiconductor substrate (B); providing a separation layer (C); providing a patterning layer (D); providing a pattern to the patterning layer (E); transferring the pattern to the separation layer (F); transferring the pattern to the sacrificial layer (G); removing the patterning layer (H); providing a catalyst layer (I), removing the separation layer and the catalyst layer in contact with the separation layer providing a patterned catalyst layer (J); exposing the semiconductor substrate and the patterned catalyst layer thereon to a process of catalyst assisted chemical etching (K).

[0021] Figure 6 depicts cross sectional view of creating a pattern for catalyst assisted chemical etching according to one embodiment of the present invention: providing a semiconductor substrate (A); providing a catalyst layer on top of the semiconductor substrate (B); providing a separation layer (C); providing a patterning layer (D); providing a pattern to the patterning layer (E); transferring the pattern to the separation layer (F); transferring the pattern to the catalyst layer (G); removing the patterning layer (H); removing the separation layer, (I); exposing the semiconductor substrate and the patterned catalyst layer thereon to a process of catalyst assisted chemical etching (J).

[0022] Figure 7 depicts cross sectional view of creating a pattern for catalyst assisted chemical etching according to one embodiment of the present invention: providing a semiconductor substrate (A); providing a first separation layer on top of the semiconductor substrate (B); providing a patterning layer on top of the first separation layer (C); providing a pattern to the patterning layer (D); providing a second separation layer (E); transferring the pattern to the second separation layer by mean of lift-off (F); transferring the pattern to the first separation layer (G); transferring the pattern to the catalyst layer (H); eventually removing the second separation layer and the catalyst layer thereon (I); exposing the semiconductor substrate and the patterned catalyst layer thereon to a process of catalyst assisted chemical etching (J).

[0023] Figure 8 depicts cross sectional view of a variation of previous examples comprising the sequence of providing a patterned separation layer (A); removing the patterning layer (B); etching the semiconductor substrate (C); providing the catalyst layer (D); exposing the semiconductor substrate and the patterned catalyst layer thereon to a process of catalyst assisted chemical etching (E). Figure 9 depicts cross sectional view of a variation of previous examples comprising the sequence of providing a first patterned catalyst layer (A); exposing the semiconductor substrate and the patterned catalyst layer thereon to a process of catalyst assisted chemical etching (B); providing a second catalyst layer (C); eventually removing the separation layer and the second catalyst layer in contact with the separation layer (D); exposing the semiconductor substrate and the second patterned catalyst layer thereon to a process of catalyst assisted chemical etching (E).

[0024] Figure 10. Tilted cross section scanning electron microscopy of silicon etched with high aspect ratio according to one embodiment of the present invention.

[0025] Figure 11 . Tilted cross section scanning electron microscopy of silicon etched with high aspect ratio according to one embodiment of the present invention, high magnification image of the top part of the etched structure showed in Figure 6.

[0026] Figure 12. Tilted cross section scanning electron microscopy of silicon etched with high aspect ratio according to one embodiment of the present invention.

[0027] Figure 13. Tilted cross section scanning electron microscopy of silicon etched with high aspect ratio according to a previous experiment, showing the problem with carbon contamination. As the area containing a catalyst that was patterned while in contact with a carbon containing patterning layer etches distinctly from the surrounding area were no patterning happened.

[0028] Figure 14. Tilted cross section scanning electron microscopy of silicon etched with high aspect ratio according to one embodiment of the present invention. Here the separation layer contained a multilayer of materials, including a functional ferromagnetic one.

[0029] Figure 15. Tilted cross section scanning electron microscopy of silicon etched with high aspect ratio according to one embodiment of the present invention, high magnification image of the top part of the etched structure (in Figure 14) showing the stack of materials in the separation layer, including a functional ferromagnetic layer.

[0030] Detailed description

[0031] Catalyst assisted chemical etching allows to pattern extremely high aspect ratio - in the range of 1000:1 - in silicon substrates, with recess forming in the direction perpendicular (vertical) to the substrate. The mechanism is different from conventional wet etching or dry etching process, where the substrate material is removed in the mask-free regions. In catalyst assisted chemical etching the substrate material is removed underneath a catalyst covered region with a consequent sinking down of the catalyst region inside the semiconductor substrate material. The catalyst for silicon etching is usually Ag, Au, Pt, Pd. It has been recently demonstrated also with Cu, TiN, Ru, Graphene Oxide. The etchant contains HF in liquid or gas form and an oxidant in liquid or gas form. Extreme high aspect ratio (10’000:1) has been reported using MacEtch in gas phase but only using self-assembled catalyst nanoscale patterns (10 nm feature size), which are random and cannot be defined a priori. Nanoscale patterns needs high resolution lithography such as electron beam lithography, interference lithography or nanoimprint lithography, using a layer of carbon-based resist material that can be patterned at the nanoscale. Then, the pattern is transferred to the catalyst layer. Prior art shows that a very thin layer of amorphous carbon formed during electron beam lithography underneath of a catalyst layer is sufficient for localized blocking of the metal assisted etching of silicon. The carbon residuals are responsible for uncontrolled etching, unreproducible etching rate and uncontrolled change of the etching direction, limiting so far the aspect ratio of patterned nanostructures, especially in gas-phase MacEtch, where the process is extremely diffusion limited. The smaller is the feature size, the higher is the probability of introducing a local defect, which pins the catalyst and can initiate a rotation movement, introducing a dramatic distortion and compromising the pattern transfer fidelity. The new method consists in creating a carbon-free physical separation between the catalyst layer and the patterned layer, which shows improved throughput yield, higher level of control of the catalyst movement and increased etching rate.

[0032] The pattern transfer at nanoscale from the layer where the lithographic method has been executed to the catalyst layer can produce several defects which compromise the quality of the etching in the direction perpendicular of the substrate, introducing huge deformations during the etching. Catalyst assisted chemical etching of silicon has been achieved by patterning catalyst nanoparticles and catalyst thin films using colloidal crystal templating, photo- and electron beam lithography, microcontact imprinting, and focused ion beam deposition. However, the etching direction of the catalyst patterns is difficult to control and significant deformation of the catalyst patterns can occur during the etching process. Extreme aspect ratio (10’000:1) has been demonstrated in self-assembled nanostructures of platinum on silicon substrates without the use of pattern transfer method from lithographic step involving polymeric resist materials. It has been demonstrated that a very thin layer of amorphous carbon formed using electron beam deposition underneath of a catalyst layer is sufficient for localized blocking of gold assisted etching of silicon. This has not been recognized so far as a limiting factor for the quality of catalyst assisted chemical etching at nanoscale for high aspect ratio structures since most of the experiments have been conducted in liquid phase and for limited aspect ratio, the pinning effect of a carbon residual in the catalyst layer is less evident and less critical for low aspect ratio etching. Instead, this effect is particularly relevant for catalyst assisted chemical etching with high resolution nanoscale patterns and for high aspect ratio etching.

[0033] The methods used so far for pattern transfer into the catalyst layer, such as lift-off and ion beam etching, have a very low throughput yield and cause low quality structures produced by catalyst assisted chemical etching. With conventional lithographic methods, usually a plasma cleaning step is performed before the catalyst deposition, wherein the plasma contains oxygen to provide a reactive species for residuals of resist material.

[0034] However, these methods are not efficient to provide a carbon-free surface suitable for a clean interfacial contact of the catalyst with the substrate, especially whit dense patterns and pattern features at nanoscale. The observation is not trivial since the catalyst assisted chemical etching is much more sensitive to surface chemistry than other etching processes, such as for example alkaline- based wet-etching and plasmabased dry-etching processes. Common cleaning treatments used for example for pattern transfer in plasma-based dry-etching processes are not sufficient. The effect of partial cleaning of the surface is not obvious since the catalyst assisted chemical etching is not a standard process. A carbon contaminated surface underneath the catalyst can produce a degradation of the etching profile or a local decrease of the etching rate but the phenomena has not been systematically investigated so the effects can be erroneously attributed to other concurrent mechanisms, such a local decrease of the reactant species or partially reactive catalyst due to chemical instability or low reliability of pattern transfer method such as lift-off for feature size in the range of 1- 100 nm. More aggressive chemicals damage the resist pattern limiting the choice of available treatments to restore the surface quality of the semiconductor substrate before the catalyst is deposited. Moreover, the resist material can be deteriorated and being a source of carbon contamination even during the catalyst deposition, especially for high melting temperature catalyst materials, such as Au, Pt, Ru, Pd etc.

[0035] The present invention lies in the creating of a physical separation between the catalyst layer and the patterned polymer layer in order to eliminate completely the carbon contamination underneath of the catalyst layer in contact with the semiconductor substrate. The manufacturing sequence to realize such physical separation consists of common process steps in semiconductor manufacturing where the 3D structuring is obtained layer by layer by a top down approach and processing one layer per time. In one embodiment, Pt has been used as a catalyst material for metal assisted chemical etching in HF vapor environment. The new method allows improved throughput yield, higher level of control of the catalyst movement during the etching, increased etching rate, improved aspect ratio in comparison to Pt lift-off method. The structures in the patterned polymer layer preferentially have vertical or negative slope, the positive slope of the patterning layer can be more critical unless the patterning layer is constituted of more than one layer including a so called lift-off layer at the interface with the separation layer.

[0036] The separation layer is a layer that is not active in the process of lithography so that it cannot be the source of uncontrolled residuals blocking or reducing the quality and the etching rate of the process of catalyst assisted chemical etching. The separation layer has thickness larger than the catalyst layer thickness. The material of the separation layer is any material that has no reactivity in the process of catalyst assisted chemical etching. The material of the separation layer is any material that has a slower reactivity in the process of catalyst assisted chemical etching than the main catalyst material. The separation layer is constituted by any stack of materials, wherein the lowest layer is one of the two preceding cases, and the others serve for functionality. This functionality includes, but is not limited to: magnetism (see Figures 14 and 15).

[0037] Other patterning strategies such as catalyst lift-off have extremely low throughput yield, resulting in catalyst re-deposition and consequent etching in regions where etching was not programmed. The main limitation of other patterning methods disclosed in prior art is due to the contamination of the catalyst during the pattern transfer that cannot be eliminated completely afterwards. The proposed method is solving the problem at the origin, eliminating the contact of the catalyst layer with the layer that is acting as a source of carbon contamination.

[0038] The patterning sequence requires a plurality of different layers, the exact sequence of deposition steps and removal steps and the exact number of the different layers depend on the patterning method as a skilled person in the field immediately recognizes. Here, we provide some examples of representative procedures helping to describe the concept of a physical separation of the catalyst layer from the patterning layers. The described sequences are provided as examples of the actual realization of the present invention. The present invention is described by the following examples but is not limited to. In one embodiment of the present invention (Figure 1), the following procedure is provided. The semiconductor substrate is first coated with a separation layer, then a patterning layer is provided on top of the separation layer. The separation layer can be provided but is not limited to by a coating method comprising physical evaporation, sputtering, electrodeposition, spin coating, dip coating, spray coating, thermal growth, plasma deposition, chemical vapor deposition, atomic layer deposition etc. The patterning layer could be but is not restricted to a polymeric resist material and is provided by but not limited to spin coating, or dip coating, or spray coating. The patterning layer is patterned by using but not restricted to a lithographic method such as but not limited to interference lithography, or electron beam lithography, or nanoimprint lithography, or direct laser writing lithography, or mask lithography, or ion beam lithography. The pattern transfer to the separation layer is provided by but not limited to plasma etching, or ion beam etching, or wet etching. The surface is cleaned by mean of a plasma treatment containing oxygen, or a wet process. The catalyst layer is deposited on top of the patterned surface of the substrate so that in a plurality of features the catalyst layer is directly in contact with the substrate and in another plurality of features the catalyst layer is on top of the patterned patterning layer, this represents the patterned catalyst. The catalyst layer can be provided but is not limited to by a coating method comprising physical evaporation, sputtering, electrodeposition, spin coating, dip coating, spray coating, thermal growth, plasma deposition, chemical vapor deposition, atomic layer deposition etc. The catalyst assisted chemical etching can be performed by immersing the substrate and the patterned catalyst in a liquid etching solution containing at least HF, comprising water and an oxidant, such as but not limited to 02 or H2O2. The catalyst assisted chemical etching can be performed by exposing the substrate and the patterned catalyst to a gas-phase etching solution containing at least HF, comprising water and an oxidant, such as but not limited to 02 or H2O2, wherein the gas-phase could be provided by a stream of vapor HF and the oxidant from a gas containing at least 02, such but not limited to air. The catalyst assisted chemical etching occurs by sinking the catalyst features in direct contact with the substrate into the substrate with a preferential etching occurring in the direction perpendicular to the surface of the semiconductor substrate.

[0039] In another embodiment of the present invention (Figure 2), the procedure comprises the removal of the patterning layer (Fig.2F) after the pattern transfer to the separation layer (Fig.2E) and before the deposition of the catalyst layer (Fig.2G). The thickness of the catalyst layer is smaller than the thickness of the separation layer. The process of catalyst assisted chemical etching is performed (Fig.2H). In one example, according to the procedure described in Figure 2, a <100 N-type silicon wafer with resistivity in the range of 1-30 Ohm cm has been used as semiconductor substrate. A separation layer has been deposited by physical evaporation on top of the silicon wafer. The separation layer thickness is more than 10 nm. A patterning layer has been deposited by spin coating a polymeric resist material suitable for electron beam lithography. A pattern has been created in the patterning layer by mean of a standard electron beam lithography method. The pattern has been transferred to the separation layer by mean of plasma etching. The catalyst layer is deposited by physical evaporation on top of the patterned substrate. The catalyst material is platinum, the catalyst layer thickness is more than 5 nm and less than 30 nm. The catalyst assisted chemical etching has been realized by exposing the substrate and the patterned catalyst to a vapor stream of water diluted HF solution and air. The substrate and the patterned catalyst are maintained at a temperature higher than 30 degrees Celsius during the catalyst assisted chemical etching. The silicon is etched for more than 10 micrometers in direction perpendicular to the wafer surface (Figure 10), as well as more than 20 micrometers perpendicular to the wafer surface (Figure 12), the patterned catalyst sank into the silicon substrate with minimal deformation in comparison to contaminated catalyst (Figure 13). The achieved aspect ratio is in the range of 100:1 (Figure 10) and 200:1 (Figure 12). Figure 11 shows the detail of the top structure with the presence of the separation layer below the catalyst layer.

[0040] In another embodiment of the present invention (Figure 3), the procedure comprises the presence on an additional sacrificial layer below the separation layer. This layer could be but not limited to an adhesion layer, or anti refractive coating, or an additional semiconductor layer. The thickness of the sacrificial layer can be smaller or larger than the catalyst layer thickness. The pattern transfer (Fig.3G) to the sacrificial layer is provided by but not limited to plasma etching, or ion beam etching, or wet etching. The pattern transfer (Fig.3G) to the sacrificial layer is provided before the catalyst layer deposition (Fig.3H). Then catalyst assisted chemical etching is performed (Fig .31).

[0041] In another embodiment of the present invention (Figure 4), the procedure comprises the removal of the patterning layer on top of the separation layer (Fig.4H) before the catalyst layer deposition (Fig.41). In another embodiment of the present invention (Figure 5), the procedure comprises the removal of the separation layer and the catalyst layer in contact with the separation layer (Fig.5 J) before process of catalyst assisted chemical etching (Fig.5K).

[0042] In another embodiment of the present invention (Figure 6), the procedure comprises that: first the catalyst layer is deposited on top of the semiconductor substrate (Fig ,6B) , second the separation layer is provided (Fig.6C), third the patterning layer is provided (Fif.6D). The pattern is provided to the patterning layer (Fig. 6E), the pattern is first transferred to the separation layer (Fig.6F) and then to the catalyst layer (Fig.6G). The pattern transfer to the catalyst layer is provided by but not limited to plasma etching, or ion beam etching, or wet etching. Finally, the patterning layer (Fig.6H) and the separation layer (Fig.61) are removed and the catalyst assisted chemical etching is performed (Fig.6J).

[0043] In another embodiment of the present invention (Figure 7), the procedure comprises: providing a semiconductor substrate (Fig.7A); providing a first separation layer on top of the semiconductor substrate (Fig.7B); providing a patterning layer on top of the first separation layer (Fig.7C); providing a pattern to the patterning layer (Fig.7D); providing a second separation layer (Fig.7E); transferring the pattern to the second separation layer by mean of lift-off (Fig.7F); transferring the pattern to the first separation layer (Fig.7G); transferring the pattern to the catalyst layer (Fig.7H); eventually removing the second separation layer and the catalyst layer thereon (Fig.71); exposing the semiconductor substrate and the patterned catalyst layer thereon to a process of catalyst assisted chemical etching (Fig.7J).

[0044] In another embodiment of the present invention (Figure 8), a variation of the previous examples comprises the etching of the semiconductor substrate (Fig.8C) after the patterning of the separation layer (Fig.8A). The catalyst is layer the deposited (Fig.8D) and the process of catalyst assisted etching is performed (Fig.8D).

[0045] In another embodiment of the present invention (Figure 9), a variation of the previous examples comprises a first step of catalyst assisted chemical etching (Fig.9A), a step of removal of the first catalyst layer (Fig.9B) and a deposition of a second catalyst (Fig.9C), eventually the second catalyst being different from the first catalyst. A second step of catalyst assisted chemical etching is performed (Fig. 9F) with or without the eventual removal of the separation layer and the catalyst layer in contact with the separation layer (Fig.9E).

Claims

Patent claims1. A method of patterning a catalyst for reducing the catalyst contamination in high aspect ratio catalyst assisted chemical etching, the method comprises the steps of:(a) providing a semiconductor substrate,(b) providing a plurality of layers of other materials than the said semiconductor substrate at one surface of the said semiconductor substrate, wherein at least a patterning layer is one of the said layers of other materials, wherein at least a separation layer is one of the said layers of other materials, wherein at least a catalyst layer is one of the said layers of other materials, wherein the material of the said separation layer is other than the material of the said patterning layer or the said catalyst layer, wherein the order of providing the different layers varies depending on the lithographic method,(c)providing a pattern to the said patterning layer, wherein the said patterning layer comprises a material suitable for a lithographic process,(d) transferring the pattern from the patterning layer to the separation layer and providing a patterned separation layer,(e) transferring the pattern from the said separation layer to the said catalyst layer and providing a patterned catalyst layer on the said semiconductor substrate,(f) exposing the said semiconductor substrate and the said patterned catalyst layer thereon to a catalyst assisted chemical etching.

2. The method according to claim 1 , wherein the semiconductor substrate is initially coated with a sacrificial layer and the pattern is transferred in the said sacrificial layer after providing the patterned separation layer and before providing the catalyst layer.

3. The method according to claim 1 , wherein transferring the pattern from the separation layer to the catalyst layer consists of a plasma etching process.

4. The method according to claim 1 , wherein transferring the pattern from the patterning layer to the separation layer comprises a plasma etching process.

5. The method according to claim 1 , wherein transferring the pattern from the patterning layer to the separation layer comprises a lift-off process.

6. The method according to claim 1 , wherein the separation layer consists of a material inert to the catalyst assisted chemical etching process.

7. The method according to claim 1 , wherein the separation layer contains a material selected from the group consisting of: AI2O3, SiO2, Si, AIF3, Al, AlSiCu, TaSiN, TiN, Ti3AI, Ti, Ti oxides, Cr, Cr oxides.

8. The method according to claim 1 , wherein the separation layer comprises a material with slower reactivity in the catalyst assisted chemical etching with respect to the said catalyst material.

9. The method according to claim 1 , wherein the separation layer has a thickness larger than the thickness of the said catalyst layer.

10. The method according to claim 1 , wherein the separation layer comprises a stack of different materials, wherein a material in the stack has magnetic properties.

11. The method according to claim 1 , wherein the semiconductor substrate contains a semiconductor selected from the group consisting of: Si, Ge, or an alloy containing elements from groups III and V in the periodic table.

12. The method according to claim 1 , wherein the metal contains a metal selected from the group of: Au, Ag, Pt, Pd, Cu, Ni, W, Rh, Tr, lrO2, Ru, RuO2, Ru oxides, TiN, TaN, graphene, graphene oxide.

13. The method according to claim 1 , wherein the catalyst assisted chemical etching comprises HF in vapor phase as evaporated from a liquid solution containing water diluted HF or a gas containing HF.

14. The method according to claim 1 , wherein the catalyst assisted chemical etching comprises a solution of water diluted HF in liquid phase.

15. The method according to any of the preceding claims, wherein the patterned catalyst layer comprises structures with submicron feature size.

16. The method according to any of the preceding claims, wherein the patterned catalyst layer comprises arrays of structures with submicron feature size.

17. The method according to any of the preceding claims, wherein the patterned catalyst layer comprises an X-ray diffractive grating pattern with periodicfeatures, and wherein the etched semiconductor structure comprises an X-ray diffractive grating with periodic features.

18. The method according to any of the preceding claims, wherein the patterned catalyst layer comprises an X-ray diffractive optics pattern with periodic features with multiple periods, and wherein the etched semiconductor structure comprises an X-ray diffractive optics with periodic features with multiple periods.

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