Digital phase-locked loop circuit and a method thereof

Abstract

The present disclosure relates to a digital phase-locked loop (PLL) circuit (100). The digital PLL circuit includes a phase frequency detector (102) configured to compare a phase difference between an input reference signal and a feedback signal from a current controlled oscillator, and generate a plurality of signals. An error to digital convertor (104) electrically 5 connected to the phase frequency detector (102) and configured to convert the plurality of signals into a plurality of digital signals. A digital controller (106) electrically connected to the error to digital convertor (104), and configured to process and convert the plurality of digital signals into a plurality of current signals. A current controlled oscillator (108) electrically connected to the digital controller (106), and configured to receive the plurality of 0 current signals from the digital controller (106) and control a phase of the feedback signal to synchronize with a phase of the input reference signal.

Description

DIGITAL PHASE-LOCKED LOOP CIRCUIT AND AMETHOD THEREOFTECHNICAL FIELD

[0001] The present disclosure relates generally to a phase-locked loop. In particular, the present disclosure relates to a digital phase-locked loop (PLL) circuit and a method for controlling a phase of a feedback signal of a current controlled oscillator.BACKGROUND

[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.

[0003] Phase-locked loops (PLLs) are essential components in modem electronics, finding widespread use in telecommunications, computing, and various other electronic applications. As a semiconductor industry advances, microprocessors are operating at increasingly higher frequencies. The PLLs are crucial in these microprocessors, serving as both system synchronizers and frequency integrators. The PLLs ensure timing consistency between an external reference clock and an internal clock, facilitating the use of high- frequency internal clocks.

[0004] Additionally, the PLLs play a vital role in communication systems, where they are used for system synchronization, clock and data recovery, and frequency integration. They are indispensable in numerous applications for system design, highlighting their importance in modem electronics. Although the PLLs are widely utilized, conventional PLLs are analog PLLs and digital PLLs containing phase frequency detector(s), analog loop filter(s), and voltage / current-controlled oscillator(s).

[0005] However, the conventional digital PLLs encounter several challenges, including a frequency drift and a high-frequency systematic jitter. The frequency drift may refer to the PLL's tendency to deviate from the desired frequency over time, which can lead to synchronization issues and affect an overall performance of the system. The high-frequency systematic jitter may refer to unwanted variations in output signal's timing, which can degrade signal quality and reliability. These challenges may be particularly problematic in high-speed communication systems and other applications where precise timing and frequency control are crucial.

[0006] Therefore, there is, a need for improving a performance and a reliability of PLLs in modem electronic systems by overcoming the deficiencies of the prior art(s).OBJECTS OF THE PRESENT DISCLOSURE

[0007] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are listed herein below.

[0008] An object of the present disclosure is to provide a digital phase-locked loop (PLL) circuit that includes an error to duty cycle modulated digital convertor to convert a plurality of signals into a plurality of digital signals.

[0009] Another object of the present disclosure is to provide a digital PLL circuit that includes a digital controller to process and convert a plurality of duty cycle modulated digital signals into a plurality of current signals.

[0010] Another object of the present disclosure is to provide a digital PLL circuit that includes a current controlled oscillator to control a phase of a feedback signal to synchronize with a phase of the input reference signal in a more efficient manner.

[0011] Another object of the present disclosure is to provide a current controlled oscillator to reduce a frequency drift, a phase noise, and a high frequency systematic jitter of a digital PLL circuit, and improve a performance and a reliability of the digital PLL circuit.

[0012] The other objects and advantages of the present invention will be apparent from the following description when read in conjunction with the accompanying drawings, which are incorporated for illustration of the preferred embodiments of the present invention and are not intended to limit the scope thereof.SUMMARY

[0013] Aspects of the present disclosure relate generally a phase-locked loop. In particular, the present disclosure relates to a digital phase-locked loop (PLL) circuit.

[0014] In an aspect, the present disclosure relates to a digital phase-locked loop (PLL) circuit. The digital PLL circuit includes a phase frequency detector configured to compare a phase difference between an input reference signal and a feedback signal from a current controlled oscillator, and generate a plurality of signals based on the comparison. The digital PLL circuit includes an error to digital convertor electrically connected to the phase frequency detector and configured to convert the plurality of signals into a plurality of duty cycle modulated digital signals. The digital PLL circuit includes a digital controller electrically connected to the error to digital convertor, and configured to process and convertthe plurality of digital signals into a plurality of current signals. The digital PLL circuit includes a current controlled oscillator electrically connected to the digital controller, and configured to receive the plurality of current signals from the digital controller and control a phase of the feedback signal to synchronize with a phase of the input reference signal.

[0015] In an embodiment, the plurality of signals may include at least one of one or more UP signals and one or more down (DN) signals.

[0016] In an embodiment, the digital controller may be configured to convert the plurality of digital signals into the plurality of current signals by being configured to convert the plurality of digital signals into one or more duty cycles of the plurality of digital signals, and convert the one or more duty cycles of the plurality of digital signals into the plurality of current signals.

[0017] In an embodiment, the current controlled oscillator may be configured to control the phase of the feedback signal based on a course correction and a fine correction performed by the digital controller.

[0018] In an embodiment, during the course correction, the digital controller may be configured to determine a direction and a magnitude of a frequency error between the input reference signal and the feedback signal, and generate a plurality of control signals based on the frequency error to perform maximum adjustments to a frequency of the feedback signal to match a frequency of the input reference signal.

[0019] In an embodiment, during the fine correction, the digital controller may be configured to continuously monitor the phase difference between the input signal and the feedback signal, and generate a plurality of control signals based on the phase difference to perform minimum adjustments to the frequency of the feedback signal to match the frequency of the input reference signal.

[0020] In an embodiment, the current controlled oscillator may be configured to receive the plurality of current signals from the digital controller through a low-pass filter.

[0021] In an embodiment, the low-pass filter may be configured to filter out noise and high-frequency disturbances in the plurality of current signals and generate a control voltage to control the phase of the feedback signal.

[0022] In an aspect, the present disclosure relates to a method for controlling a phase of a feedback signal of a current controlled oscillator. The method includes comparing, by a digital PLL circuit, a phase difference between an input reference signal and a feedback signal from a current controlled oscillator, and generating a plurality of signals based on the comparison. The method includes converting, by the digital PLL circuit, the plurality ofsignals into a plurality of digital signals. The method includes processing and converting, by the digital PLL circuit, the plurality of digital signals into a plurality of current signals. The method includes controlling, by the digital PLL circuit, a phase of the feedback signal to synchronize with a phase of the input reference signal using the plurality of current signals.

[0023] In an embodiment, converting, by the digital controller, the plurality of digital signals into the plurality of current signals may include converting, by the digital PLL circuit, the plurality of digital signals into one or more duty cycles of the plurality of digital signals, and converting, by the digital PLL circuit, the one or more duty cycles of the plurality of digital signals into the plurality of current signals.

[0024] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated herein, and constitute a part of the present disclosure, illustrate exemplary embodiments of the disclosed methods and systems in which like reference numerals refer to the same parts throughout the different drawings. Components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Some drawings may indicate the components using block diagrams and may not represent an internal circuitry of each component. It will be appreciated by those skilled in the art that the present disclosure of such drawings includes the present disclosure of electrical components, electronic components, or circuitry commonly used to implement such components.

[0026] The diagrams are for illustration only, which thus is not a limitation of the present disclosure, and wherein:

[0027] FIG. 1 illustrates an example block diagram of a digital phase-locked loop (PLL) circuit, in accordance with an embodiment of the present disclosure.

[0028] FIGs. 2 A and 2B illustrate exemplary views depicting an error to digital convertor and duty cycle modulation of the digital PLL circuit, in accordance with an embodiment of the present disclosure.

[0029] FIG. 3 illustrates an exemplary view of a duty cycle modulated digital signal to current conversion, in accordance with an embodiment of the present disclosure.

[0030] FIG. 4 illustrates an example flow chart for implementing a method for controlling a phase of a feedback signal of a current controlled oscillator, in accordance with an embodiment of the present disclosure.

[0031] FIG. 5 illustrates an example flow chart for implementing a method for controlling a phase of a feedback signal of a current controlled oscillator, in accordance with an embodiment of the present disclosure.DETAILED DESCRIPTION

[0032] In the following description, for the purposes of explanation, various specific details are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent, however, that embodiments of the present disclosure may be practiced without these specific details. Several features described hereafter can each be used independently of one another or with any combination of other features. An individual feature may not address all of the problems discussed above or might address only some of the problems discussed above. Some of the problems discussed above might not be fully addressed by any of the features described herein.

[0033] The ensuing description provides exemplary embodiments only, and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the exemplary embodiments will provide those skilled in the art with an enabling description for implementing an exemplary embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the scope of the disclosure as set forth.

[0034] Specific details are given in the following description to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in a block diagram form in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments.

[0035] Also, it is noted that individual embodiments may be described as a process which is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completedbut could have additional steps not included in a figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination can correspond to a return of the function to the calling function or the main function.

[0036] The word “exemplary” and / or “demonstrative” is used herein to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as “exemplary” and / or “demonstrative” is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to preclude equivalent exemplary structures and techniques known to those of ordinary skill in the art. Furthermore, to the extent that the terms “includes,” “has,” “contains,” and other similar words are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising” as an open transition word without precluding any additional or other elements.

[0037] Reference throughout this specification to “one embodiment” or “an embodiment” or “an instance” or “one instance” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and / or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0039] The present disclosure a phase-locked loop. In particular, the present disclosure relates to a digital phase-locked loop (PLL) circuit. The digital PLL circuit disclosed in the present disclosure overcomes the drawbacks, shortcomings, and limitations associated with aconventional PLL by including a digital controller configured to process and convert a plurality of digital signals into a plurality of current signals, and a current controlled oscillator configured to control a phase of a feedback signal to synchronize with a phase of an input reference signal. The present disclosure can be described in enabling detail in the following examples, which may represent more than one embodiment of the present disclosure.

[0040] The description of terms and features related to the present disclosure shall be clear from the embodiments that are illustrated and described; however, the present disclosure is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents of the embodiments are possible within the scope of the present disclosure. Additionally, the present disclosure can include other embodiments that are within the scope of the claims but are not described in detail with respect to the following description.

[0041] In an aspect, the present disclosure relates to a digital PLL circuit. The digital PLL circuit may include a phase frequency detector configured to compare a phase difference between an input reference signal and a feedback signal from a current controlled oscillator, and generate a plurality of signals based on the comparison. The digital PLL circuit may include an error to digital convertor electrically connected to the phase frequency detector and configured to convert the plurality of signals into a plurality of digital signals. The digital PLL circuit may include a digital controller electrically connected to the error to digital convertor, and configured to process and convert the plurality of digital signals into a plurality of current signals. The digital PLL circuit may include a current controlled oscillator electrically connected to the digital controller, and configured to receive the plurality of current signals from the digital controller and control a phase of the feedback signal to synchronize with a phase of the input reference signal.

[0042] In an aspect, the present disclosure relates to a method for controlling a phase of a feedback signal of a current controlled oscillator. The method may include comparing a phase difference between an input reference signal and a feedback signal from the current controlled oscillator, and generating a plurality of signals based on the comparison. The method may include converting the plurality of signals into a plurality of digital signals. The method may include processing and converting the plurality of digital signals into a plurality of current signals. The method may include controlling a phase of the feedback signal to synchronize with a phase of the input reference signal using the plurality of current signals.

[0043] Various embodiments of the present disclosure will be explained in detail with reference to FIGs. 1-5.

[0044] With reference to FIGs. 1 to 3, a digital PLL circuit (100) is a type of electronic circuit that uses digital logic components to perform several functions in a system. The digital PLL circuit (100) may be commonly used in the systems, for example, but not limited to, communication systems, clock generation systems, and frequency synthesis systems. The digital PLL circuit (100) may generate an output signal whose phase may be locked to a phase of an input reference signal.

[0045] In the digital PLL circuit (100), analog components such as, for example, voltage-controlled oscillators (VCOs) and phase detectors, may be replaced with digital counterparts. Therefore, the digital PLL circuit (100) may have improved noise immunity, easier integration with digital systems, and an ability to implement advanced features such as programmable loop fdters and digital modulation in an efficient manner. Further, the digital PLL circuit (100) may operate on digital signals and logic, offering flexibility and programmability compared to conventional analog PLLs.

[0046] In an embodiment, the digital PLL circuit (100) may include a phase frequency detector (102) configured to compare a phase difference between the input reference signal and a feedback signal obtained from a current controlled oscillator (108). The feedback signal may be an output signal of the current controlled oscillator (108). The current controlled oscillator (108) may generate the feedback signal whose frequency and phase can be adjusted based on a control voltage it receives. The phase difference may indicate necessary adjustment for the feedback signal from the current controlled oscillator (108) to align with the phase of the input reference signal.

[0047] In an embodiment, the phase frequency detector (102) may be configured to generate a plurality of signals based on the phase difference comparison between the input reference signal and the feedback signal. The plurality of signals may include, but not limited to, one or more UP signals and one or more down (DN) signals. The one or more UP signals may indicate that the frequency of the current controlled oscillator (108) has to be increased to reduce the phase difference between the input reference signals and the feedback signals. The one or more down (DN) signals may indicate that the frequency of the current controlled oscillator (108) has to be decreased. These signals may be used by the digital PLL circuit (100) to lock onto the input reference signal's phase and maintain synchronization. In an embodiment, in addition to the one or more UP signals and the one or more down (DN) signals, the phase frequency detector (102) may generate other signals depending on a designand requirements of the digital PLL circuit (100). These signals may be used for fine-tuning an operation of the digital PLL circuit (100), and ensuring stable phase locking in the digital PLL circuit (100).

[0048] In an embodiment, the digital PLL circuit (100) may include an error to digital convertor (104). The error to digital convertor (104) may be electrically connected to the phase frequency detector (102). The error to digital convertor (104) may be configured to receive the plurality of signals generated by the phase frequency detector (102). The error to digital convertor (104) may be configured to convert the plurality of signals into a plurality of digital signals, as illustrated in FIGs. 2A and 2B. For example, the plurality of signals generated by the phase frequency detector (102), i.e., the one or more UP signals and the one or more down (DN) signals may be analog signals that represent the phase difference between the input reference signal and the feedback signal from the current controlled oscillator (108). The error to digital convertor (104) may be configured to convert the analog signals into digital signals, which can be processed by a digital logic within the digital PLL circuit (100).

[0049] In an embodiment, the digital PLL circuit (100) may include a digital controller (106). The digital controller (106) may be electrically connected to the error to digital convertor (104). The digital controller (106) may be configured to process the plurality of digital signals, and convert the plurality of digital signals into a plurality of current signals, as illustrated in FIG. 3. In an embodiment, the digital controller (106) may convert the plurality of digital signals into the plurality of current signals by converting the plurality of digital signals into one or more duty cycles of the plurality of digital signals. Further, the digital controller (106) may convert the one or more duty cycles of the plurality of digital signals into the plurality of current signals.

[0050] In an embodiment, the digital controller (106) may be configured to perform a course correction and a fine correction of the control voltage applied to the current controlled oscillator (108). The course correction may involve making larger adjustments to the control voltage to bring a frequency of the current controlled oscillator (108) closer to a desired frequency. During the course correction, the digital controller (106) may be configured to determine a direction and a magnitude of a frequency error between the input reference signal and the feedback signal. The digital controller (106) may be configured to generate a plurality of control signals based on the frequency error to perform maximum adjustments to a frequency of the feedback signal in order to match a frequency of the input reference signal.

[0051] In an embodiment, once the frequency of the current controlled oscillator (108) reaches closer to the desired frequency, the digital controller (106) may perform the fine correction to adjust the control voltage more subtly to precisely match the frequency of the current controlled oscillator (108) to the desired frequency. In an embodiment, during the fine correction, the digital controller (106) may be configured to continuously monitor the phase difference between the input reference signal and the feedback signal. The digital controller (106) may be configured to generate a plurality of control signals based on the phase difference to perform minimum adjustments to the frequency of the feedback signal in order to match the frequency of the input reference signal. This process may help the digital PLL circuit (100) to achieve and maintain synchronization between the input reference signal and the feedback signal.

[0052] In an embodiment, the digital PLL circuit (100) may include a current controlled oscillator (108). The current controlled oscillator (108) may be electrically connected to the digital controller (106). The current controlled oscillator (108) may be configured to receive the plurality of current signals from the digital controller (106) and control a phase of the feedback signal to synchronize with a phase of the input reference signal.

[0053] In an embodiment, the current controlled oscillator (108) may be configured to receive the plurality of current signals from the digital controller (106) through a low-pass filter (110). The low -pass filter (110) may be configured to filter out noise and high- frequency disturbances in the plurality of current signals and generate the control voltage to control the phase of the feedback signal. In an embodiment, the current controlled oscillator (108) may be configured to control the phase of the feedback signal based on the course correction and the fine correction performed by the digital controller (106). Therefore, the current controlled oscillator (108) may reduce a frequency drift and a high-frequency systematic jitter generated in the digital PLL circuit (100).

[0054] In an embodiment, the digital PLL circuit (100) may include one or more counters. The counters may be used to divide the frequency of the input reference signal. This may be often done to generate a lower-frequency signal that may be compared with a reference frequency in the phase frequency detector (102). In an embodiment, the one or more counters may be configured to multiply the frequency of the input reference signal for generating higher-frequency clock signals or for performing frequency synthesis. In an embodiment, the one or more counters may be used in the phase frequency detector (102) to compare the phase of the input reference signal with the phase of the feedback signal from the current controlled oscillator (108). The one or more counters may be configured to counta number of clock cycles between edges of the input reference signal and the feedback signal, providing a measure of the phase difference between the input reference signal and the feedback signal. In an embodiment, the one or more counters may be used in a frequency acquisition process of the digital PLL circuit (100), where the digital PLL circuit (100) locks onto the frequency of the input reference signal. The one or more counters may be used to track the frequency error, adjust the current controlled oscillator (108) accordingly, and compare the frequencies of the input reference signal and the feedback signal to achieve a phase -locked operation.

[0055] FIG. 4 illustrates an example flow chart (400) for implementing a method for controlling a phase of a feedback signal of a current controlled oscillator, in accordance with an embodiment of the present disclosure.

[0056] With reference to FIG. 4, at 402, the method may include determining a frequency of a digital PLL circuit (100) based on a multiplication factor applied to a frequency of the input reference signal and the frequency of the input reference signal, which may be expressed as follows: fpLL = N *fref . (1)Where, f i.i. is an output frequency of the current controlled oscillator that the digital PLL circuit (100) generates or locks onto.N is a value of one or more counters in a feedback path of the digital PLL circuit (100). N determines a multiplication factor applied to the frequency of the input reference signal. fref is the frequency of the input reference signal applied to the digital PLL circuit (100) that the current controlled oscillator tries to match.

[0057] In the digital PLL circuit (100), the frequency of the current controlled oscillator may be adjusted to be a multiple of the reference frequency, which may be achieved by changing the multiplication factor. This may allow the digital PLL circuit (100) to synchronize the phase and the frequency of a feedback signal (obtained from the current controlled oscillator) with the phase and the frequency of the input reference signal.

[0058] At 404, the frequency of the digital PLL circuit (100) may be determined by setting a course correction value, a duty cycle of a fine correction, and a current of a current controlled oscillator to minimum. The course correction value may be a parameter that represents an amount of frequency adjustment needed to bring the digital PLL circuit (100) into alignment with the input reference signal. By setting the course correction value tominimum, the digital PLL circuit (100) may make a coarse adjustment to its output frequency, moving it closer to a desired frequency.

[0059] The duty cycle of the fine correction may be a proportion of time that the fine correction is active compared to a total cycle time. By setting the duty cycle to its minimum, the fine correction may make subtle adjustments to the output frequency, allowing the digital PLL circuit (100) to fine-tune its frequency alignment. Further, by setting the current of the current controlled oscillator to its minimum, the current controlled oscillator may produce a lowest possible frequency, which can be used as a reference point for frequency adjustment of the digital PLL circuit (100).

[0060] At 406, the method may include determining if the phase of the input reference signal is less than the phase of the feedback signal obtained from the current controlled oscillator.

[0061] At 408, if the phase of the input reference signal is less than the phase of the feedback signal obtained from the current controlled oscillator, the method may include providing a signal (e.g., UP = 1) indicating that the frequency of the current controlled oscillator is lagging behind the reference frequency, where the signal (e.g., UP = 1) may be detected by a phase frequency detector (102), as illustrated in FIG. 1. Further, the method may include increasing the frequency of the current controlled oscillator to reduce a phase difference between the feedback signal and the input reference signal. In another embodiment, the method may include providing a signal (e.g., DN = 0) indicating that the frequency of the current controlled oscillator is leading the frequency of the input reference signal, and decreasing the frequency of the current controlled oscillator to reduce the phase difference the feedback signal and the input reference signal.

[0062] Based on the indication of the signal, the method may include determining if the duty cycle of the fine correction is maximum. If the duty cycle of the fine correction is maximum, the method may include decreasing the duty cycle of the fine correction to minimum, and increasing the course correction value and the current of the current controlled oscillator, thereby controlling the phase and the frequency of the current controlled oscillator.

[0063] At 410, if the phase of the input reference signal is greater than the phase of the feedback signal, the method may include providing a signal (e.g., UP = 0) indicating that the frequency of the current controlled oscillator is leading the frequency of the input reference frequency. Further, the method may include decreasing the frequency of the current controlled oscillator to reduce the phase difference between the feedback signal and the input reference signal based on the signal. In another embodiment, the method may includeproviding a signal (e.g., DN = 1) indicating that the frequency of the current controlled oscillator is lagging behind the frequency of the input reference signal, and increasing the frequency of the current controlled oscillator to reduce the phase difference between the feedback signal and the input reference signal.

[0064] At 412, based on the indication of the signal at 410, the method may include determining if the duty cycle of the fine correction is minimum.

[0065] At 414, if the duty cycle of the fine correction is minimum, the method may include increasing the duty cycle of the fine correction to maximum, and decreasing the course correction value and the current of the current controlled oscillator.

[0066] At 416, if the duty cycle of the fine correction is maximum, the method may include decreasing the duty cycle of the fine correction to minimum and decreasing the current of the current controlled oscillator to control the phase and the frequency of the current controlled oscillator.

[0067] FIG. 5 illustrates an example flow chart (500) for implementing a method for controlling a phase of a feedback signal of a current controlled oscillator, in accordance with an embodiment of the present disclosure.

[0068] With reference to FIG. 5, at 502, the method may include comparing a phase difference between an input reference signal and a feedback signal obtained from a current controlled oscillator, by a digital PLL circuit (100).

[0069] At 504, the method may include generating a plurality of signals based on the phase difference comparison between the input reference signal and the feedback signal. The plurality of signals may be UP signals and down (DN) signals.

[0070] At 506, the method may include converting the plurality of signals into a plurality of duty cycle modulated digital signals.

[0071] At 508, the method may include processing the plurality of digital signals and converting the plurality of digital signals into a plurality of current signals with duty cycle modulation for fine control of a phase of the feedback signal. The plurality of digital signals may be initially converted into one or more duty cycles of the plurality of digital signals, and then the one or more duty cycles of the plurality of digital signals may be converted into the plurality of current signals.

[0072] At 510, the method may include controlling the phase of the feedback signal to synchronize with a phase of the input reference signal using the plurality of current signals.

[0073] It will be apparent to those skilled in the art that the structure of the disclosure may be provided using some or all of the mentioned features and components withoutdeparting from the scope of the present disclosure. While various embodiments of the present disclosure have been illustrated and described herein, it will be clear that the disclosure is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the disclosure, as described in the claims.ADVANTAGES OF THE PRESENT INVENTION

[0074] The present disclosure provides a digital phase-locked loop (PLL) circuit that includes an error to digital convertor to efficiently convert a plurality of signals into a plurality of digital signals.

[0075] The present disclosure provides a digital controller to process and convert a plurality of digital signals into a plurality of current signals.

[0076] The present disclosure provides a current controlled oscillator to control a phase of a feedback signal to synchronize with a phase of the input reference signal in a more efficient manner.

[0077] The present disclosure provides a current controlled oscillator to reduce a frequency drift, a phase noise, and a high frequency systematic jitter of a digital PLL circuit.

[0078] The present disclosure provides a digital controller and a current controlled oscillator to improve a performance and a reliability of a digital PLL circuit.

Claims

I Claim:

1. A digital phase-locked loop (PLL) circuit (100), comprising: a phase frequency detector (102) configured to compare a phase difference between an input reference signal and a feedback signal from a current controlled oscillator (108), and generate a plurality of signals based on the comparison; an error to digital convertor (104) electrically connected to the phase frequency detector (102) and configured to convert the plurality of signals into a plurality of digital signals; and a digital controller (106) electrically connected to the error to digital convertor (104), and configured to process and convert the plurality of digital signals into a plurality of current signals; wherein the current controlled oscillator (108) is electrically connected to the digital controller (106), and configured to receive the plurality of current signals from the digital controller (106) and control a phase of the feedback signal to synchronize with a phase of the input reference signal.

2. The digital phase-locked loop (PLL) circuit (100) as claimed in claim 1, wherein the plurality of signals comprises at least one of: one or more UP signals and one or more down (DN) signals.

3. The digital phase-locked loop (PLL) circuit (100) as claimed in claim 1, wherein the digital controller (106) is configured to convert the plurality of digital signals into the plurality of current signals by being configured to convert the plurality of digital signals into one or more duty cycles of the plurality of digital signals, and convert the one or more duty cycles of the plurality of digital signals into the plurality of current signals.

4. The digital phase-locked loop (PLL) circuit (100) as claimed in claim 1, wherein the current controlled oscillator (108) is configured to control the phase of the feedback signal based on a course correction and a fine correction performed by the digital controller (106).

5. The digital phase-locked loop (PLL) circuit (100) as claimed in claim 4, wherein during the course correction, the digital controller (106) is configured to determine a direction and a magnitude of a frequency error between the input reference signal and the feedback signal, and generate a plurality of control signals based on the frequency error to performmaximum adjustments to a frequency of the feedback signal to match a frequency of the input reference signal.

6. The digital phase-locked loop (PLL) circuit (100) as claimed in claim 4, wherein during the fine correction, the digital controller (106) is configured to continuously monitor the phase difference between the input reference signal and the feedback signal, and generate a plurality of control signals based on the phase difference to perform minimum adjustments to a frequency of the feedback signal to match a frequency of the input reference signal.

7. The digital phase-locked loop (PLL) circuit (100) as claimed in claim 1, wherein the current controlled oscillator (108) is configured to receive the plurality of current signals from the digital controller (106) through a low-pass filter (110).

8. The digital phase-locked loop (PLL) circuit (100) as claimed in claim 7, the low-pass filter (110) is configured to filter out noise and high-frequency disturbances in the plurality of current signals and generate a control voltage to control the phase of the feedback signal.

9. A method for controlling a phase of a feedback signal of a current controlled oscillator, the method comprising: comparing, by a digital phase-locked loop (PLL) circuit (100), a phase difference between an input reference signal and a feedback signal from a current controlled oscillator, and generating a plurality of signals based on the comparison; converting, by the digital PLL circuit (100), the plurality of signals into a plurality of digital signals; processing and converting, by the digital PLL circuit (100), the plurality of digital signals into a plurality of current signals; and controlling, by the digital PLL circuit (100), a phase of the feedback signal to synchronize with a phase of the input reference signal using the plurality of current signals.

10. The method as claimed in claim 9, wherein converting, by the digital PLL circuit (100), the plurality of digital signals into the plurality of current signals comprises: converting, by the digital PLL circuit (100), the plurality of digital signals into one or more duty cycles of the plurality of digital signals; and converting, by the digital PLL circuit (100), the one or more duty cycles of the plurality of digital signals into the plurality of current signals.

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