Power semiconductor module and power conversion apparatus

Abstract

This power semiconductor module may comprise: a common drain pad; a first power semiconductor device disposed on a first region of the common drain pad; a second power semiconductor device disposed on a second region of the common drain pad; a molding layer disposed on a peripheral region of the common drain pad and surrounding the side part of each of the first power semiconductor device and the second power semiconductor device; a common gate pad disposed on the first power semiconductor device and the second power semiconductor device; and source pads arranged on the first power semiconductor device and the second power semiconductor device. The source pads may surround at least two outer parts of the common gate pad.

Description

Power semiconductor modules and power conversion devices

[0001] The present disclosure relates to a power semiconductor module and a power conversion device.

[0002] Unlike system semiconductors or memory that process and store information or signals, power semiconductor devices are core components that convert, store, distribute, and control the power entering electronic devices, and are widely used in most electronic products.

[0003] In line with the recent global trend toward strengthening environmental protection, electric and hydrogen-powered eco-friendly vehicles are gaining widespread attention as alternatives to conventional fossil fuel-powered vehicles. These eco-friendly vehicles utilize numerous power semiconductor components. These eco-friendly vehicles include hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), electric vehicles (EVs), and fuel cell electric vehicles (PCEVs).

[0004] Although Si power semiconductor devices have been widely used in the past, there is a strong demand for the development of new power semiconductor devices due to their low power, low dielectric breakdown characteristics, and low thermal conductivity.

[0005] Accordingly, active research is being conducted on power semiconductor devices based on semiconductor compounds such as SiC, GaN, and Ga2O3, which have energy bandgaps approximately three times greater than conventional Si power semiconductor devices. Power semiconductor devices based on these semiconductor compounds exhibit high power, high dielectric breakdown characteristics, and high thermal conductivity.

[0006] Meanwhile, as illustrated in FIGS. 1A and 1B, the inverter includes power semiconductor elements (30, 40) based on semiconductor compounds. A plurality of power semiconductor elements (30, 40) are mounted between a first substrate (10) and a second substrate (20) using a flip-chip bonding method. Each power semiconductor element (30, 40) has a gate electrode (30a, 40a) and a source electrode (30b, 40b) positioned on the same surface. In this case, the gate electrode (30a) and the source electrode (30b) of each of some of the power semiconductor elements (30) are electrically connected upwardly to the first substrate (20), and the gate electrode (40a) and the source electrode (40b) of each of other power semiconductor elements (40) are electrically connected downwardly to the second substrate (10).

[0007] The inverter has a terminal (or lead frame) (50) disposed between a first substrate (10) and a second substrate (20). Since the thickness of the terminal (50) is greater than the thickness of the power semiconductor element (30, 40), the upper or lower portion of the power semiconductor element (30, 40) is spaced apart from the first substrate (10) or the second substrate (20). To compensate for this spacing, a spacer (70, 80) is disposed on the upper or lower portion of the power semiconductor element (30, 40).

[0008] Meanwhile, as power semiconductor devices (30, 40) are increasingly required to have higher performance, die sizes are being reduced. In addition, the size of gate electrodes (30a, 40a) is being reduced to maximize the active area of ​​power semiconductor devices (30, 40).

[0009] Accordingly, when bonding the power semiconductor element (30, 40) to the first substrate (10) or the second substrate (20), the bonding process risk is high. For example, defects such as gate open or gate-source short may occur due to misalignment such as die shift. Since the size of the gate electrode (30a, 40a) is reduced, detachment of the power semiconductor element (30, 40) may occur due to insufficient bonding strength, thereby lowering reliability.

[0010] When power semiconductor elements (30, 40) and spacers (70, 80) are bonded and tested at high voltages (>1,200 V) without insulation, sparks may fly due to insulation problems, making it impossible to perform a full test. If an inverter is implemented using numerous power semiconductor elements (30, 40) that have not been fully tested, the inverter must be discarded if one of these power semiconductor elements (30, 40) is defective. Therefore, there is an urgent need to develop a technology that enables a full test.

[0011] There is a problem that an electrical short occurs between the source electrode (30b, 40b) and the drain electrode of the power semiconductor elements (30, 40) in the process of mounting and EMC-filling power semiconductor elements (30, 40) to which spacers (70, 80) are joined between the first substrate (10) and the second substrate (20).

[0012] It is difficult to secure yield because it is vulnerable to surface foreign matter or EMC filling defects. The weak bonding caused by the small size of the gate electrode (30a, 40a) is difficult to select through electrical evaluation, and it is difficult to completely select it even through bonding surface inspection, so the possibility of defective products is very high. When reliability is evaluated during the development stage, delamination of the gate electrode (30a, 40a) occurs, and if continuous thermal stress is applied, the possibility of field defects is also very high.

[0013] The present invention aims to solve the above-mentioned and other problems.

[0014] Another object of the present invention is to provide a power semiconductor module and a power conversion device capable of increasing yield.

[0015] Another object of the present invention is to provide a power semiconductor module and a power conversion device capable of preventing bonding failure.

[0016] Another object of the present invention is to provide a power semiconductor module and a power conversion device capable of ensuring reliability.

[0017] Another object of the present invention is to provide a power semiconductor module and a power conversion device capable of preventing electrical short circuits.

[0018] Another object of the present invention is to provide a power semiconductor module and a power conversion device capable of high voltage testing during a manufacturing process.

[0019] The technical problems of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0020] According to one aspect of the embodiment to achieve the above or other objects, a power semiconductor module includes: a common drain pad; a first power semiconductor element on a first region of the common drain pad; a second power semiconductor element on a second region of the common drain pad; a common gate pad on the first power semiconductor element and the second power semiconductor element; and a source pad on the first power semiconductor element and the second power semiconductor element; wherein the common drain pad is electrically connected to a first drain electrode of the first power semiconductor element and a second drain electrode of the second power semiconductor element, the common gate pad is electrically connected to a first gate electrode of the first power semiconductor element and a second gate electrode of the second power semiconductor element, the source pad is electrically connected to a first source electrode of the first power semiconductor element and a second source electrode of the second power semiconductor element, and the source pad surrounds at least two outer sides of the common gate pad.

[0021] The above source pad may include a common source pad vertically overlapping the first power semiconductor element and the second power semiconductor element.

[0022] The above common source pad has an opening, and the above common gate pad can be positioned in the opening.

[0023] The above common gate pad may include a first short side and a second short side in one direction and a first long side and a second long side in a direction perpendicular to the one direction.

[0024] The above common source pad can be arranged on the first end side, the second end side and the first end side of the above common gate pad.

[0025] The above common source pad may be placed on the second side of the above common gate pad.

[0026] The first end side of the common gate pad may be positioned between the first gate electrode and the first source electrode, and the second end side of the common gate pad may be positioned between the second gate electrode and the second source electrode.

[0027] The source pad may include a first source pad and a second source pad that vertically overlap the first source electrode of the first power semiconductor element and the second source electrode of the second power semiconductor element, respectively.

[0028] The first power semiconductor element and the second power semiconductor element may further include a pad for a Kelvin source spaced apart from the source pad.

[0029] The size of the common gate pad may be larger than the gate pad size of the first power semiconductor device or the gate pad size of the second power semiconductor device.

[0030] According to another aspect of the embodiment, a power semiconductor module includes: a common drain pad; a first power semiconductor element on a first region of the common drain pad; a second power semiconductor element on a second region of the common drain pad; a common gate pad on the first power semiconductor element and the second power semiconductor element; and a source pad on the first power semiconductor element and the second power semiconductor element; wherein the common drain pad is electrically connected to a first drain electrode of the first power semiconductor element and a second drain electrode of the second power semiconductor element, the common gate pad is electrically connected to a first gate electrode of the first power semiconductor element and a second gate electrode of the second power semiconductor element, the source pad is electrically connected to a first source electrode of the first power semiconductor element and a second source electrode of the second power semiconductor element, and the common gate pad can vertically overlap at least one of the first source electrode and the second source electrode.

[0031] The common gate pad may be arranged across the first source electrode and the first gate electrode and the second gate electrode and the second source electrode along the one direction on the first region of the common drain pad.

[0032] The above source pad may include a common source pad vertically overlapping the first power semiconductor element and the second power semiconductor element.

[0033] The common source pad may be arranged across the first source electrode and the second source electrode along the one direction on the second region of the common drain pad.

[0034] The area of ​​the common source pad may be larger than the area of ​​the source pad of the first power semiconductor device or the area of ​​the source pad of the second power semiconductor device.

[0035] The area of ​​the common drain pad may be greater than the sum of the area of ​​the common gate pad and the area of ​​the common source pad.

[0036] The source pad may include a first source pad and a second source pad that vertically overlap the first source electrode of the first power semiconductor element and the second source electrode of the second power semiconductor element, respectively.

[0037] The first power semiconductor element and the second power semiconductor element may further include a pad for a Kelvin source spaced apart from the source pad.

[0038] According to another aspect of the embodiment, a power conversion device includes: a first substrate; a second substrate; and a plurality of power semiconductor modules between the first substrate and the second substrate, wherein each of the plurality of power semiconductor modules includes: a common drain pad; a first power semiconductor element on a first region of the common drain pad; a second power semiconductor element on a second region of the common drain pad; a common gate pad on the first power semiconductor element and the second power semiconductor element; and a common source pad on the first power semiconductor element and the second power semiconductor element, wherein the common source pad surrounds at least two side portions of the common gate pad, and in some of the plurality of power semiconductor modules, the common drain pad is electrically connected to the first substrate, and the common gate pad and the common source pad are each electrically connected to the second substrate, and in the remaining modules of the plurality of power semiconductor modules, the common drain pad is electrically connected to the second substrate, and the common gate pad and the common source pad are each electrically connected to the first substrate.

[0039] It may further include a plurality of terminals connected to each of the first substrate and the second substrate.

[0040] The effects of the power semiconductor module and power conversion device according to the present disclosure are described as follows.

[0041] According to at least one of the present disclosures, by packaging a plurality of power semiconductor devices, a common gate pad connecting gate electrodes of the plurality of power semiconductor devices can be expanded as much as possible, thereby preventing bonding or detachment defects and increasing yield. In addition, since the common gate pad and the common source pad can be expanded, the separation distance between the respective power semiconductor devices can be increased, and a molding layer can be filled between the respective power semiconductor devices. Accordingly, not only are the thermal characteristics of the respective power semiconductor devices hardly affected by each other, but also the heat dissipation characteristics of the heat generated from each power semiconductor device can be improved.

[0042] According to at least one of the present disclosures, by packaging a plurality of power semiconductor devices, the power semiconductor devices having a very thin thickness are not exposed to the outside, thereby preventing electrical shorts caused by foreign substances or dust, etc., and thus increasing the yield.

[0043] According to at least one of the present disclosures, when packaging a plurality of power semiconductor devices, the plurality of power semiconductor devices are surrounded by a molding layer, so that defects can be detected through a high-voltage test of 1,200 V or more before being mounted in a power conversion device. Accordingly, there is an advantage in that power semiconductor modules that have defects through a full test can be discarded in advance, thereby fundamentally blocking potential risks such as damage due to failure in the withstand voltage or rating of each power semiconductor device, thereby improving product reliability.

[0044] According to at least one of the present disclosures, the common drain pad is expanded to a size that covers all of the plurality of power semiconductor devices and has excellent thermal characteristics, so that excellent electrode characteristics as well as excellent heat dissipation characteristics can be obtained.

[0045] According to at least one of the present disclosures, there is an advantage in that the degree of freedom in manufacturing a power semiconductor module can be maximized by more easily obtaining a power semiconductor module including a desired number of power semiconductor devices by packaging a plurality of power semiconductor devices.

[0046] According to at least one of the present disclosures, each power semiconductor module can be manufactured to have the same thickness as the largest thickness among the thicknesses of the terminals. Therefore, when each power semiconductor module and the terminals are mounted between a first substrate and a second substrate, each power semiconductor module is in surface contact with the first substrate and the second substrate, thereby eliminating the need for a separate member such as a spacer, thereby preventing poor bonding between each power semiconductor module and the spacer and facilitating the assembly process of the power conversion device.

[0047] FIG. 1a is a drawing showing a plurality of power semiconductor elements mounted on a first substrate, and FIG. 1b is a drawing showing a second substrate bonded to the first substrate shown in FIG. 1a.

[0048] Figure 2 is a circuit diagram illustrating an inverter according to the present disclosure.

[0049] Fig. 3 is a cross-sectional view illustrating a power conversion device according to the present disclosure.

[0050] FIG. 4 is a cross-sectional view illustrating a power semiconductor module according to the first aspect of the present disclosure.

[0051] FIG. 5 is a cross-sectional view illustrating the first power semiconductor element illustrated in FIG. 4.

[0052] FIG. 6 is a cross-sectional view of a plurality of power semiconductor devices packaged in the first aspect of the present disclosure.

[0053] FIG. 7a is a cross-sectional view showing a power semiconductor module having two power semiconductor elements by cutting the wafer illustrated in FIG. 6.

[0054] FIG. 7b is a cross-sectional view showing a power semiconductor module having one power semiconductor element by cutting the wafer shown in FIG. 6.

[0055] Figure 8 is a drawing showing a plurality of power semiconductor modules mounted on a first substrate.

[0056] FIG. 9 is a first exemplary diagram illustrating the layout of a common gate pad and a common source pad according to the present disclosure.

[0057] FIG. 10 is a second exemplary diagram illustrating the layout of a common gate pad and a common source pad according to the present disclosure.

[0058] FIG. 11 is a third exemplary diagram illustrating the layout of a common gate pad and a common source pad according to the present disclosure.

[0059] FIG. 12 is a fourth exemplary diagram illustrating the layout of a power semiconductor module according to the present disclosure.

[0060] Figures 13a to 13d are examples of various modifications of the common gate pad illustrated in Figure 12.

[0061] FIG. 14 is a fifth exemplary diagram illustrating the layout of a power semiconductor module of the present disclosure.

[0062] FIG. 15 is a sixth example of the layout of a power semiconductor module according to the present disclosure. FIG. 12 is a sixth example of the layout of a power semiconductor module according to the present disclosure.

[0063] Figures 16a to 16h are manufacturing process diagrams of a power semiconductor module according to the present disclosure.

[0064] Fig. 17 is a cross-sectional view illustrating a power semiconductor module according to the present disclosure.

[0065] Fig. 18 is a cross-sectional view showing a plurality of power semiconductor devices packaged in the present disclosure.

[0066] FIG. 19a is a cross-sectional view showing a power semiconductor module having two power semiconductor elements by cutting the wafer shown in FIG. 18.

[0067] FIG. 19b is a cross-sectional view showing a power semiconductor module having one power semiconductor element by cutting the wafer shown in FIG. 18.

[0068] FIG. 20 is a seventh exemplary diagram illustrating the layout of a common gate pad and a common source pad according to the present disclosure.

[0069] FIG. 21 is an eighth example diagram illustrating a layout of a common gate pad and a common source pad according to the present disclosure.

[0070] FIG. 22 is a ninth exemplary diagram illustrating the layout of a common gate pad and a common source pad according to the present disclosure.

[0071] FIG. 23 is a tenth exemplary diagram illustrating a layout of a common gate pad and a common source pad according to the present disclosure.

[0072] FIG. 24 is an eleventh exemplary diagram illustrating a layout of a common gate pad and a common source pad according to the present disclosure.

[0073] FIGS. 25a to 25h illustrate a manufacturing process of a power semiconductor module according to the present disclosure.

[0074] The sizes, shapes, and dimensions of components depicted in the drawings may differ from the actual components. Furthermore, even if the same components are depicted with different sizes, shapes, and dimensions across drawings, this is merely an example within the drawings, and the same components may have the same sizes, shapes, and dimensions across drawings.

[0075] Hereinafter, the present disclosure disclosed in this specification will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, the same or similar components will be given the same reference numbers, and redundant descriptions thereof will be omitted. The suffixes 'module' and 'part' for components used in the following description are given or used interchangeably in consideration of the ease of writing the specification, and do not have distinct meanings or roles in themselves. In addition, the attached drawings are intended to make it easy to understand the present disclosure disclosed in this specification, and the technical ideas disclosed in this specification are not limited by the attached drawings. In addition, when an element such as a layer, region, or substrate is referred to as existing 'on' another element, this includes that it may be directly on the other element, or that other intermediate elements may exist therebetween.

[0076] Figure 2 is a circuit diagram illustrating an inverter according to the present disclosure.

[0077] Referring to FIG. 2, the inverter (1000) according to the present disclosure can be applied to applications such as three-phase motors or compressors. The inverter (1000) can output three-phase power. The inverter (1000) can be a power conversion device or can be included in a power conversion device. The inverter (1000) can include a switching circuit. The power conversion device can also be referred to as a power semiconductor device.

[0078] An inverter (1000) according to the present disclosure can convert DC power into AC power and supply the converted AC power to a load (1200) to drive the load (1200). A converter may be connected to the input side of the inverter (1000) according to the present disclosure to convert AC power into DC power. In this case, the DC power converted by the converter can be converted into AC power by the inverter (1000) and then used to drive the load (1200). The load (1200) may be a motor or an electric motor, but is not limited thereto.

[0079] The inverter (1000) according to the present disclosure may include a three-phase inverter, but is not limited thereto. In this case, a phase difference of 120 degrees may be present between the first phase, the second phase, and the third phase. The inverter (1000) according to the present disclosure may include a plurality of legs (100A, 100B, 100C). For example, the first leg (100A), the second leg (100B), and the third leg (100C) may be connected in parallel to a load (1200), i.e., a motor, through a first node (N1), a second node (N2), and a third node (N3), respectively. The first leg (100A) may include a first arm (100a) and a second arm (100b) that are connected in series to each other, the second leg (100B) may include a third arm (100c) and a fourth arm (100d) that are connected in series to each other, and the third leg (100C) may include a fifth arm (100e) and a sixth arm (100f) that are connected in series to each other. Here, the first arm (100a), the third arm (100c), and the fifth arm (100e) may be referred to as upper arms, and the second arm (100b), the fourth arm (100d), and the sixth arm (100f) may be referred to as lower arms. Each of the first arm (100a) to the sixth arm (100f) may be referred to as a switching module, a submodule, or the like.

[0080] The first arm (100a) to the sixth arm (100f) may each include switching elements (Q1 to Q6) and diodes (100a-2 to 100f-2). The switching elements (Q1 to Q6) and the diodes (100a-2 to 100f-2) may be formed simultaneously using the same semiconductor process. The switching elements (Q1 to Q6) may include power semiconductor elements.

[0081] In order for DC power to be converted into AC power by the inverter (1000) according to the present disclosure, the switching elements (Q1 to Q6) of each of the first arm (100a) to the sixth arm (100f) can be controlled to be turned on / off.

[0082] For example, when the first switching element (Q1) of the first arm (100a) of the first leg (100A) is in the ON state, the fourth switching element (Q4) of the fourth arm (100d) of the second leg (100B) and / or the sixth switching element (Q6) of the sixth arm (100f) of the third leg (100C) may be in the ON state. Accordingly, DC power may be supplied to the first phase inductor of the motor.

[0083] For example, when the third switching element (Q3) of the third arm (100c) of the second leg (100B) is turned on, the sixth switching element (Q6) of the sixth arm (100f) of the third leg (100C) and / or the second switching element (Q2) of the second arm (100b) of the first leg (100A) may be turned on. Accordingly, DC power may be supplied to the second phase inductor of the motor. The second phase may be 120 degrees behind the first phase.

[0084] For example, when the fifth switching element (Q5) of the fifth arm (100e) of the third leg (100C) is turned on, the second switching element (Q2) of the second arm (100b) of the first leg (100A) and / or the fourth switching element (Q4) of the fourth arm (100d) of the second leg (100B) may be turned on. Accordingly, DC power may be supplied to the third phase inductor of the motor. The third phase may be 120 degrees behind the second phase.

[0085] Accordingly, AC power can be generated by the DC power supplied to each of the first phase inductor, the second phase inductor, and the third inductor.

[0086] Meanwhile, although not shown, in order to increase the internal pressure characteristics, the switching elements of each of the first arm (100a) to the sixth arm (100f), i.e., the power semiconductor elements (Q1 to Q6), may be provided in multiple numbers, each connected in series with each other.

[0087] Although not shown, in order to increase the current characteristics, the switching elements of each of the first arm (100a) to the sixth arm (100f), i.e., the power semiconductor elements (Q1 to Q6), may be provided in multiple numbers connected in parallel with each other.

[0088] Meanwhile, the switching elements (Q1 to Q6) and diodes (100a-2 to 100f-2) constituting the first arm (100a) to the sixth arm (100f) can be packaged to form a power semiconductor module.

[0089] As an example, the first leg (100A), the second leg (100B), and the third leg (100C) can each be configured as power semiconductor modules. That is, the first arm (100a) and the second arm (100b) of the first leg (100A) can be packaged to configure a first power semiconductor module. The third arm (100c) and the fourth arm (100d) of the second leg (100B) can be packaged to configure a second power semiconductor module. The fifth arm (100e) and the sixth arm (100f) of the third leg (100C) can be packaged to configure a third power semiconductor module.

[0090] As another example, the first leg (100A), the second leg (100B), and the third leg (100C) can be configured as a single power semiconductor module. That is, the first arm (100a) and the second arm (100b) of the first leg (100A), the third arm (100c) and the fourth arm (100d) of the second leg (100B), and the fifth arm (100e) and the sixth arm (100f) of the third leg (100C) can be packaged to configure a single power semiconductor module.

[0091] The unexplained symbol VDC represents the input voltage, which may be, for example, a DC voltage. The unexplained symbol CDC acts as a capacitor, which can charge the input voltage (VDC).

[0092] Meanwhile, power semiconductor devices are typically called dies when manufactured on a wafer, and can be called chips after being separated by cutting the wafer. Hereinafter, dies and chips will be collectively referred to as power semiconductor devices.

[0093] Fig. 3 is a cross-sectional view illustrating a power conversion device according to the present disclosure. Fig. 4 is a cross-sectional view illustrating a power semiconductor module according to the first aspect of the present disclosure.

[0094] Although the first power semiconductor module (230) among the plurality of power semiconductor modules (230, 240, 260, 270 of FIG. 8) is illustrated in FIG. 4, the structure of each of the second power semiconductor module (240), the third power semiconductor module (260), and the fourth power semiconductor module (270) may be identical to the structure of the first power semiconductor module (230) illustrated in FIG. 4. Therefore, the structure of each of the second power semiconductor module (240), the third power semiconductor module (260), and the fourth power semiconductor module (270) can be easily understood from the structure of the first power semiconductor module (230) illustrated in FIG. 4.

[0095] Referring to FIG. 3, a power conversion device (200) according to the present disclosure may include a first substrate (210), a second substrate (220), a first power semiconductor module (230), a second power semiconductor module (240), terminals (250), etc.

[0096] The first substrate (210) and the second substrate (220) may each include an insulating layer (211, 221), a first metal layer (213, 223), a second metal layer (215, 225), etc. The insulating layers (211, 221) may be made of an inorganic material, a ceramic material, an alumina material, a plastic material, a glass material, etc.

[0097] The first metal layer (213, 223) may include a plurality of circuit patterns (not shown). The plurality of circuit patterns may be electrically connected to the first power semiconductor module (230) and the second power semiconductor module (240). Therefore, the first metal layer (213, 223) may be formed of a metal material having excellent electrical conductivity. For example, the first metal layer (213, 223) may have a single-layer structure or a multi-layer structure made of copper (Cu), gold (Au), aluminum (Al), platinum (Pt), or the like.

[0098] The first metal layer (213, 223) can be formed of a material having excellent electrical conductivity as well as heat dissipation performance.

[0099] The circuit pattern may be referred to as a heat dissipation pattern. In this case, the first metal layer (213, 223) may include a plurality of heat dissipation patterns. The plurality of heat dissipation patterns may be electrically connected to the first power semiconductor module (230) and the second power semiconductor module (240).

[0100] The second metal layer (215, 225) can quickly discharge heat generated from the first power semiconductor module (230) and the second power semiconductor module (240) to the outside. Therefore, the second metal layer (215, 225) can be formed of a material having excellent heat dissipation properties. For example, the second metal layer (215, 225) can be aluminum (Al) or an aluminum alloy, but is not limited thereto. The second metal layer (215, 225) can be called a heat dissipation layer or a heat dissipation plate.

[0101] The first power semiconductor module (230) and the second power semiconductor module (240) can be mounted between the first substrate (210) and the second substrate (220).

[0102] In the present disclosure, the first power semiconductor module (230) and the second power semiconductor module (240) may each include at least two power semiconductor elements. The two or more power semiconductor elements may be connected in parallel with each other.

[0103] Although a first power semiconductor module (230) and a second power semiconductor module (240) are illustrated in FIG. 1, four power semiconductor modules (230, 240, 260, 270 in FIG. 8) or more power semiconductor modules may be provided. In this case, the first power semiconductor module (230) and the third power semiconductor module (260) may be connected in parallel with each other, and the second power semiconductor module (240) and the fourth power semiconductor module (270) may be connected in parallel with each other. The first power semiconductor module (230) may be connected in series with the second power semiconductor module (240) or the fourth power semiconductor module (270). The second power semiconductor module (240) may be connected in series with the second power semiconductor module (240) or the fourth power semiconductor module (270).

[0104] In Fig. 8, the first leg (100A) illustrated in Fig. 1, for example, may be configured by power semiconductor modules (230, 240, 260, 270). In this case, the first arm (100a) of the first leg (100A) may be configured by the first power semiconductor module (230) and the third power semiconductor module (260) of Fig. 8, and the second arm (100b) of the first leg (100A) may be configured by the second power semiconductor module (240) and the fourth power semiconductor module (270). The first switching element (Q1) of the first arm (100a) may be configured by a plurality of power semiconductor elements of each of the first power semiconductor module (230) and the third power semiconductor module (260). The second switching element (Q2) of the second arm (100b) may be configured by a plurality of power semiconductor elements of each of the second power semiconductor module (240) and the fourth power semiconductor module (270). The second leg (100B) and the third leg (100C) illustrated in FIG. 1 may also be configured by power semiconductor modules (230, 240, 260, 270) in FIG. 8.

[0105] Meanwhile, terminals (250) (or lead frames) may serve to connect an external circuit (or driver) and the first power semiconductor module (230) and the second power semiconductor module (240).

[0106] For example, at least five terminals may be provided, but this is not limited thereto. For example, the first terminal and the second terminal may be electrically connected to the first power semiconductor module (230) through corresponding circuit patterns of the first substrate (210). For example, the third terminal may be commonly connected to the first power semiconductor module (230) and the second power semiconductor module (240) through corresponding circuit patterns of the first substrate (210) or the second substrate (220). Alternatively, a third terminal formed integrally with two sub-terminals may be provided. In this case, the two sub-terminals may be electrically connected to the first power semiconductor module (230) and the second power semiconductor module (240), respectively.

[0107] For example, the fourth terminal and the fifth terminal may be electrically connected to the second power semiconductor module (240) through corresponding circuit patterns of the second substrate (220). In this case, the first terminal and the fourth terminal may provide a switching signal, a gate signal, a control signal, etc. that control the on / off of the first power semiconductor module (230) and the second power semiconductor module (240), respectively.

[0108] The thickness of each of the first power semiconductor module (230) and the second power semiconductor module (240) may be equal to the largest thickness among the thicknesses of each of the terminals (250). The thickness of each of the terminals (250) may be determined in consideration of the power, voltage, current, etc. supplied to the first power semiconductor module (230) or the second power semiconductor module (240). Accordingly, the first power semiconductor module (230) and the second power semiconductor module (240) may be in direct surface contact with the first substrate (210) and the second substrate (220), respectively. In this case, a separate member such as a spacer for filling the gap between the first power semiconductor module (230) (or the second power semiconductor module (240)) and the first substrate (210) or between the first power semiconductor module (230) (or the second power semiconductor module (240)) and the second substrate (220) is not required, so that poor bonding between the first power semiconductor module (230) (or the second power semiconductor module (240)) and the spacer can be prevented, and the assembly process of the power conversion device can be facilitated.

[0109] Referring to FIG. 3, the first power semiconductor module (230) and the second power semiconductor module (240) may include a common drain pad (231, 241), a common gate pad (237, 247), a common source pad (239, 249), etc.

[0110] As illustrated in FIG. 4, the first power semiconductor module (230) may include a first power semiconductor element (232-1), a second power semiconductor element (232-2), a molding layer (233), etc. Although not illustrated, the second power semiconductor module (240) may also include a first power semiconductor element, a second power semiconductor element, a molding layer, etc. In the second power semiconductor module (240), the first power semiconductor element, the second power semiconductor element, and the molding layer, which are not illustrated, may have the same structure, shape, and / or function as the first power semiconductor element (232-1), the second power semiconductor element (232-2), and the molding layer (233) of the first power semiconductor module (230), respectively.

[0111] The common drain pad (231) may serve to support the first power semiconductor element (232-1), the second power semiconductor element (232-2), the molding layer (233), the common gate pad (237), and the common source pad (239). The common drain pad (231) may serve as a common electrode that commonly connects the first drain electrode (320) of the first power semiconductor element (232-1) and the second drain electrode (360) of the second power semiconductor element (232-2). The common drain pad (231) may serve as an electrode pad that electrically connects each of the first power semiconductor element (232-1) and the second power semiconductor element (232-2) to the first substrate (210) or the second substrate (220). Therefore, the common drain pad (231) may be formed of a metal material having excellent electrical conductivity. For example, the common drain pad (231) may include copper (Cu). For example, the common drain pad (231) may have a three-layer structure of copper (Cu)-molybdenum (Mo)-copper (Cu). The common drain pad (231) may be called a conductive layer, a metal layer, a support layer, a conductive support layer, a support member, a heat dissipation member, etc.

[0112] The common drain pad (231) may include a first region (231-1), a second region (231-2), and a remaining region (231-3). The first region (231-1) and the second region (231-2) may be positioned spaced apart from each other, and the remaining region (231-3) may be an area excluding the first region (231-1) and the second region (231-2), i.e., a peripheral region.

[0113] A first power semiconductor element (232-1) and a second power semiconductor element (232-2) may be disposed on a common drain pad (231). The first power semiconductor element (232-1) may be disposed on a first region (231-1) of the common drain pad (231), and the second power semiconductor element (232-2) may be disposed on a second region (231-2) of the common drain pad (231). The first region (231-1) may have a size corresponding to the size of the first power semiconductor element (232-1), and the second region (231-2) may have a size corresponding to the size of the second power semiconductor element (232-2). Since the first region (231-1) and the second region (231-2) are positioned spaced apart from each other, the first power semiconductor element (232-1) and the second power semiconductor element (232-2) can also be positioned spaced apart from each other.

[0114] Although the drawing shows a first power semiconductor element (232-1) and a second power semiconductor element (232-2), more power semiconductor elements may be provided.

[0115] FIG. 5 is a cross-sectional view illustrating the first power semiconductor element illustrated in FIG. 4.

[0116] Although the first power semiconductor element (232-1) among the power semiconductor elements (232-1, 232-2 of FIG. 4) is illustrated in FIG. 5, the structure of the second power semiconductor element (232-2) may be identical to the structure of the first power semiconductor element (232-1). Accordingly, the structure of the second power semiconductor element (232-2) can be easily understood from the structure of the first power semiconductor element (232-1) illustrated in FIG. 5.

[0117] Referring to FIGS. 4 and 5, the first power semiconductor element (232-1) may include a first semiconductor layer (310), a first drain electrode (320), a first gate electrode (330), a first source electrode (340), etc. The second power semiconductor element (232-2) may include a second semiconductor layer (350), a second drain electrode (360), a second gate electrode (370), and a second source electrode (380).

[0118] The first semiconductor layer (310) and the second semiconductor layer (350) can be formed using a semiconductor process on a substrate made of a semiconductor compound such as SiC, GaN, or Ga2O3.

[0119] The first drain electrode (320) may be disposed on the lower side of the first semiconductor layer (310), and the first gate electrode (330) and the first source electrode (340) may be disposed on the upper side of the first semiconductor layer (310). Since the first gate electrode (330) and the first source electrode (340) are disposed on the same side of the first semiconductor layer (310), the first gate electrode (330) and the first source electrode (340) may be positioned to be spaced apart from each other so that a short circuit does not occur between them. Since the first gate electrode (330) and the first source electrode (340) are disposed on the same side of the first semiconductor layer (310), the first power semiconductor element (232-1) may have a flip-chip structure.

[0120] The second drain electrode (360) may be disposed on the lower side of the second semiconductor layer (350), and the second gate electrode (370) and the second source electrode (380) may be disposed on the upper side of the second semiconductor layer (350). Since the second gate electrode (370) and the second source electrode (380) are disposed on the same side of the second semiconductor layer (350), the second gate electrode (370) and the second source electrode (380) may be positioned to be spaced apart from each other so that a short circuit does not occur between them. Since the second gate electrode (370) and the second source electrode (380) are disposed on the same side of the second semiconductor layer (350), the second power semiconductor element (232-2) may have a flip-chip structure.

[0121] A common gate pad (237) may be disposed on the first power semiconductor element (232-1) and the second power semiconductor element (232-2). The common gate pad (237) may be commonly connected to the first gate electrode (330) of the first power semiconductor element (232-1) and the second gate electrode (370) of the second power semiconductor element (232-2). The common gate pad (237) may vertically overlap with the first gate electrode (330) of the first power semiconductor element (232-1) and be electrically connected to the first gate electrode (330). The common gate pad (237) may vertically overlap with the second gate electrode (370) of the second power semiconductor element (232-2) and be electrically connected to the second gate electrode (370). The common gate pad (237) can extend from the first gate electrode (330) of the first power semiconductor element (232-1) toward the second gate electrode (370) of the second power semiconductor element (232-2).

[0122] Meanwhile, in the conventional power conversion device (or inverter), a plurality of power semiconductor elements (30, 40 in FIGS. 1a and 1b) are directly bonded to the first substrate (10) or the second substrate (20). To improve performance, the size (or area) of the power semiconductor elements has been gradually reduced. To maximize the active area in the reduced power semiconductor elements (30, 40), the size of the gate electrodes (30a, 40a) has been reduced. Therefore, bonding defects occur during the bonding process between the power semiconductor elements (30, 40) and the first substrate (10) or the second substrate (20), and the bonding strength of the gate electrodes (30a, 40a) is weak, resulting in a defect in which the power semiconductor elements (30, 40) are detached.

[0123] However, in the present disclosure, the size (or area) of the common gate pad (237) may be larger than the size (or area) of the first power semiconductor element (232-1) or the size (or area) of the second power semiconductor element (232-2). Therefore, even if a common gate pad (237) larger than the size of the first power semiconductor element (232-1) or the size of the second power semiconductor element (232-2) is bonded to the first substrate (210) or the second substrate (220) to implement the power conversion device (200), not only will bonding failure not occur, but the bonding strength will be greatly increased, so that defects such as detachment can be prevented. In this way, bonding failure or detachment failure can be prevented, so that the yield can be increased.

[0124] Meanwhile, a common source pad (239) may be disposed on the first power semiconductor element (232-1) and the second power semiconductor element (232-2). The common source pad (239) may be commonly connected to the first source electrode (340) of the first power semiconductor element (232-1) and the second source electrode (380) of the second power semiconductor element (232-2).

[0125] The common source pad (239) may be vertically overlapped with the first source electrode (340) of the first power semiconductor element (232-1) and electrically connected to the first source electrode (340). The common source pad (239) may be vertically overlapped with the second source electrode (380) of the second power semiconductor element (232-2) and electrically connected to the second source electrode (380). The common source pad (239) may extend from the first source electrode (340) of the first power semiconductor element (232-1) toward the second source electrode (380) of the second power semiconductor element (232-2).

[0126] The size of the common source pad (239) may be at least half of the sum of the sizes of the first power semiconductor element (232-1) and the second power semiconductor element (232-2). The outer side of the common source pad (239) may be disposed on one outer side of the first power semiconductor element (232-1) and / or the second power semiconductor element (232-2). For example, the common source pad (239) may be positioned closer to one outer side of the common drain pad (231) than to one outer side of the first source electrode (340) of the first power semiconductor element (232-1). For example, the common source pad (239) may be positioned closer to another outer side of the common drain pad (231) than to one outer side of the second source electrode (380) of the second power semiconductor element (232-2).

[0127] The common source pad (239) may be arranged on the same layer as the common gate pad (237). The common source pad (239) may be formed simultaneously with the common gate pad (237) using the same material as the common gate pad (237) and the same process. For example, the common gate pad (237) and the common source pad (239) may be formed of a metal having excellent electrical conductivity, such as copper (Cu), but are not limited thereto.

[0128] The common source pad (239) may be spaced apart from the common gate pad (237) to prevent short circuiting with the common gate pad (237). The common source pad (239) may surround the common gate pad (237).

[0129] The size (or area) of the common drain pad (231) may be larger than the sum of the size (or area) of the common gate pad (237) and the size (or area) of the common source pad (239).

[0130] In the present disclosure, the size of the common gate pad (237) is much larger than the size (or area) of the first gate electrode (330) of the first power semiconductor device (232-1) or the size (or area) of the second gate electrode (370) of the second power semiconductor device (232-2), and therefore, the common gate pad (237) may be referred to as a scalable gate pad (hereinafter referred to as SGP). In the present disclosure, the size of the common source pad (239) is much larger than the size of the first source electrode (340) of the first power semiconductor device (232-1) or the size of the second source electrode (380) of the second power semiconductor device (232-2), and therefore, the common source pad (239) may be referred to as a scalable source pad (hereinafter referred to as SSP).

[0131] Meanwhile, the molding layer (233) may be disposed on the peripheral region (231-3) of the common drain pad (231). The molding layer (233) may surround the side of the first power semiconductor element (232-1) and the side of the second power semiconductor element (232-2). The first power semiconductor element (232-1) and the second power semiconductor element (232-2) may not be exposed to the outside due to the molding layer (233). The molding layer (233) may be formed of a resin material having excellent insulating performance. For example, the molding layer (233) may be formed of an EMC (Epoxy Molding Compound) molding material, but is not limited thereto. The EMC molding material may be a sealing material that protects the first power semiconductor element (232-1) and the second power semiconductor element (232-2) from heat, moisture, impact, insulation breakdown, etc.

[0132] Meanwhile, a power semiconductor device used to implement a conventional power conversion device was subjected to a high-voltage test of 1,200 V or more on the power semiconductor device without a molding layer (233) disposed around it. Accordingly, sparks were emitted during a high-voltage test of 1,200 V or more on the power semiconductor device, making it impossible to perform the high-voltage test. Therefore, when a power conversion device (200) is implemented using power semiconductor devices that have not been subjected to a high-voltage test, there is always a potential risk of damage due to poor internal pressure or rating of the power semiconductor device, which lowers product reliability.

[0133] However, in the present disclosure, a power semiconductor module (230 in FIG. 4) can be manufactured in which a first power semiconductor element (232-1) and a second power semiconductor element (232-2) are surrounded by a molding layer (233). In the power semiconductor module (230 in FIG. 4) manufactured in this manner, even if a high voltage test of 1,200 V or more is performed on each of the first power semiconductor element (232-1) and the second power semiconductor element (232-2), a complete test is possible without sparks. Therefore, a power conversion device (200 in FIG. 3) according to the present disclosure can be implemented using a plurality of power semiconductor modules (230) that have undergone a complete test. Accordingly, since the first power semiconductor element (232-1) and the second power semiconductor element (232-2) included in each of the plurality of power conversion modules (230, 240) of the power conversion device (200 of FIG. 3) according to the present disclosure have undergone complete testing, potential risks such as damage due to internal pressure or rating failure of the power semiconductor element (232-1, 232-2) can be fundamentally blocked, thereby improving product reliability.

[0134] In addition, when manufacturing a power conversion device (200 in FIG. 3) according to the present disclosure using a plurality of power semiconductor modules (230 in FIG. 4) in which a first power semiconductor element (232-1) and a second power semiconductor element (232-2) are surrounded by a molding layer (233), the first power semiconductor element (232-1) and the second power semiconductor element (232-2) are not exposed to the outside, so an electrical short due to foreign matter or dust is prevented, and the yield can be increased.

[0135] Meanwhile, the spacing between multiple power semiconductor elements (30, 40 in FIGS. 1A and 1B) included in a conventional power conversion device (or inverter) is very narrow, so that adjacent power semiconductor elements (30, 40) are greatly affected by each other's thermal characteristics, and the heat dissipation characteristics of the heat generated from each power semiconductor element (30, 40) are not good.

[0136] However, in the present disclosure, the separation distance (d1) between the first power semiconductor element (232-1) and the second power semiconductor element (232-2) may be greater than the separation distance (d2) between the common gate pad (237) and the common source pad (239). The separation distance (d1) between the first power semiconductor element (232-1) and the second power semiconductor element (232-2) may be 1 / 3 or more of the width (w1) of the first power semiconductor element (232-1) or the width (w2) of the second power semiconductor element (232-2). For example, when the size (or area) of each of the first power semiconductor element (232-1) and the second power semiconductor element (232-2) is at least 5 mm or less × 5 mm or less, the separation distance (d1) between the first power semiconductor element (232-1) and the second power semiconductor element (232-2) may be 4 mm or more.

[0137] In this way, the separation distance (d1) between the first power semiconductor element (232-1) and the second power semiconductor element (232-2) is increased, and the molding layer (233) is filled between the first power semiconductor element (232-1) and the second power semiconductor element (232-2), so that not only are the thermal characteristics of the first power semiconductor element (232-1) and the second power semiconductor element (232-2) hardly affected by each other, but also the heat dissipation characteristics of the heat generated in the first power semiconductor element (232-1) and the second power semiconductor element (232-2) can be improved. The separation distance (d1, d2) can be more easily understood from FIGS. 9 to 11.

[0138] Meanwhile, referring again to FIG. 4, the first power semiconductor module (230) may include a first gate contact (234-1), a first source contact (234-2), a second gate contact (235-1), a second source contact (235-2), an insulating layer (236), etc.

[0139] The first gate contact (234-1) and the first source contact (234-2) may be respectively disposed on the first gate electrode (330) and the first source electrode (340) of the first power semiconductor element (232-1). Although the drawing illustrates that the size of the first gate contact (234-1) is the same as the size of the first gate electrode (330) and that the size of the first source contact (234-2) is the same as the size of the first source electrode (340), they may be different from each other.

[0140] The second gate contact (235-1) and the second source contact (235-2) may be respectively disposed on the second gate electrode (370) and the second source electrode (380) of the second power semiconductor element (232-2). Although the drawing illustrates that the size of the second gate contact (235-1) is the same as the size of the second gate electrode (370) and that the size of the second source contact (235-2) is the same as the size of the second source electrode (380), they may be different from each other.

[0141] An insulating layer (236) is placed between the common gate pad (237) and the common source pad (239), so as to insulate the common gate pad (237) and the common source pad (239).

[0142] As illustrated in FIG. 4, the outer surface of the common drain pad (231) and the outer surface of the molding layer (233) can be vertically aligned. As illustrated in FIG. 6, a package (FIG. 6) packaged using a plurality of power semiconductor elements (232-1 to 232-4) is cut, thereby manufacturing a power semiconductor module (230 in FIG. 7A) including at least two or more power semiconductor elements (232-1, 232-2), or manufacturing a power semiconductor module (400 in FIG. 7B) including a single power semiconductor element (232-4). In this way, since a power semiconductor module that can be expanded to various numbers is manufactured, in the present disclosure, the first power semiconductor module (230) and the second power semiconductor module (240) may each be referred to as an SSM (Scalable Sub-Module).

[0143] Fig. 6 is a cross-sectional view showing a plurality of power semiconductor devices packaged in the present disclosure.

[0144] As illustrated in FIG. 6, a plurality of power semiconductor devices (232-1 to 232-4) may be packaged on a common drain pad (231'). For example, a common drain pad (231') may be formed on a wafer (not illustrated), and a plurality of power semiconductor devices (232-1 to 232-4), a molding layer (233), a common gate pad (237), a common source pad (239), etc. may be formed on the common drain pad (231'). In FIG. 6, the side surface of the molding layer (233) is illustrated to be aligned with the side surface of the common drain pad (231'), but this is not limited thereto, and the side surface of the common drain pad (231') may be exposed to the outer side on both sides more than the side surface of the molding layer (233).

[0145] A process opposite to the above-described process may also be performed. For example, a plurality of power semiconductor elements (232-1 to 232-4) may be attached on pre-prepared common gate pads (237) and common source pads (239), and a common drain pad (231') may be attached on the plurality of power semiconductor elements (232-1 to 232-4). In addition, a molding layer (233) may be formed around each of the plurality of power semiconductor elements (232-1 to 232-4).

[0146] Thereafter, a cutting process is performed according to a preset sawing lane (2000), so that power semiconductor modules (230, 400) illustrated in FIGS. 7A and 7B can be manufactured. The wafer can be removed by performing a process such as grinding. By removing the wafer, the common drain pad (231) is exposed to the outside, and the exposed common drain pad (231) can be directly electrically connected to a circuit pattern of a first substrate (210) or a second substrate (220) using a bonding agent such as silver paste, as illustrated in FIG. 3.

[0147] Accordingly, after a plurality of power semiconductor elements (232-1 to 232-4) are packaged on a common drain pad (231'), they are cut according to a sawing lane (2000) set in consideration of the number of power semiconductor elements (232-1 to 232-4) desired by the customer, thereby facilitating the manufacture of power semiconductor modules (230, 400) according to the number of power semiconductor elements (232-1 to 232-4), and thus the degree of freedom in the manufacture of power semiconductor modules (230, 400) can be maximized.

[0148] Figure 8 illustrates a plurality of power semiconductor modules mounted on a first substrate.

[0149] As illustrated in FIG. 8, in order to implement a power conversion device (200) according to the present disclosure, a plurality of power semiconductor modules (230, 240, 260, 270) may be mounted on a first substrate (210) using a bonding process. For example, a plurality of power semiconductor modules (230, 240, 260, 270) may be bonded on the first substrate (210) using a bonding agent such as silver paste.

[0150] For example, the common drain pad of each of the first power semiconductor module (230) and the third power semiconductor module (260) may be bonded to the first circuit pattern of the first substrate (210). For example, the common gate pad of each of the second power semiconductor module (240) and the fourth power semiconductor module (270) may be bonded to the second circuit pattern of the first substrate (210), and the common source pad of each of the second power semiconductor module (240) and the fourth power semiconductor module (270) may be bonded to the third circuit pattern of the first substrate (210).

[0151] After the second substrate (not shown) is positioned on the first substrate (210), it can be bonded to a plurality of power semiconductor modules (230, 240, 260, 270). In this case, the common gate pad of each of the first power semiconductor module (230) and the third power semiconductor module (260) can be bonded to the fourth circuit pattern of the second substrate, and the common source pad of each of the first power semiconductor module (230) and the third power semiconductor module (260) can be bonded to the fifth circuit pattern of the second substrate. The common drain pad of each of the second power semiconductor module (240) and the fourth power semiconductor module (270) can be bonded to the sixth circuit pattern of the second substrate. The third circuit pattern and the sixth circuit pattern can be commonly connected to an output terminal.

[0152] Thereafter, by performing an EMC molding process, a molding layer (not shown) is formed between at least the first substrate (210) and the second substrate, thereby manufacturing the power conversion device (200). To distinguish it from the molding layer (233) of the power semiconductor module (230 of FIG. 4), the molding layer (233) of the power semiconductor module (230) may be referred to as the first molding layer, and the molding layer between the first substrate (210) and the second substrate may be referred to as the second molding layer.

[0153] FIG. 9 is a first exemplary diagram illustrating the layout of a common gate pad and a common source pad according to the present disclosure.

[0154] As shown in Fig. 9, a first power semiconductor element (232-1) and a second power semiconductor element (232-2) can be placed on a common drain pad (231).

[0155] The first power semiconductor element (232-1) may include a first gate electrode (330) and a first source electrode (340) disposed on the same surface, that is, on the upper surface of the first semiconductor layer (320 in FIG. 4). The second power semiconductor element (232-2) may include a second gate electrode (370) and a second source electrode (380) disposed on the same surface, that is, on the upper surface of the second semiconductor layer (350). In this case, the first source electrode (340), the first gate electrode (330), the second gate electrode (370), and the second source electrode (380) may be disposed in a row in the following order along one direction (X-axis direction): the first source electrode (340), the first gate electrode (330), the second gate electrode (370), and the second source electrode (380).

[0156] The distance between the first gate electrode (330) of the first power semiconductor element (232-1) and the second gate electrode (370) of the second power semiconductor element (232-2) may be smaller than the distance between the first source electrode (340) of the first power semiconductor element (232-1) and the second source electrode (380) of the second power semiconductor element (232-2).

[0157] A common gate pad (237) and a common source pad (239) may be placed on the first power semiconductor element (232-1) and the second power semiconductor element (232-2).

[0158] A common gate pad (237) is placed in the center area of ​​the common drain pad (231), and a common source pad (239) can surround the common gate pad (237).

[0159] The central region of the common drain pad (231) may be a region between the first region (231-1) (see FIG. 4) and the second region (231-2) (see FIG. 4) of the common drain pad (231). The outer side of the common gate pad (237) may have a first short side (237a) and a second short side (237b) in one direction. The outer side of the common gate pad (237) may have a first long side (237c) and a second long side (237d) in a direction perpendicular to one direction (X-axis direction), i.e., a vertical direction (Y-axis direction). The length of each of the first long side (237c) and the second long side (237d) may be greater than the length of each of the first short side (237a) and the second short side (237b). A rectangle can be formed by the first end side (237a), the second end side (237b), the first long side (237c), and the second long side (237d). In the drawing, the common gate pad (237) is depicted as having a rectangular shape, but it can also be transformed into other shapes.

[0160] The common gate pad (237) may be vertically overlapped with the first power semiconductor device (232-1). The common gate pad (237) may be vertically overlapped with the first gate electrode (330) of the first power semiconductor device (232-1). The common gate pad (237) may be vertically overlapped with the second power semiconductor device (232-2). The common gate pad (237) may be vertically overlapped with the second gate electrode (370) of the second power semiconductor device (232-2). The size of the common gate pad (237) may be larger than the sum of the sizes of the first gate electrode (330) of the first power semiconductor device (232-1) and the second gate electrode (370) of the second power semiconductor device (232-2).

[0161] The common gate pad (237) may be spaced apart from the common drain pad (231) exposed between the first power semiconductor element (232-1) and the second power semiconductor element (232-2) and may be positioned so as to overlap spatially between the upper and lower sides. The first end side (237a) of the common gate pad (237) may be positioned between the first gate electrode (330) and the first source electrode (340) of the first power semiconductor element (232-1). The second end side (237b) of the common gate pad (237) may be positioned between the second gate electrode (370) and the second source electrode (380) of the second power semiconductor element (232-2).

[0162] The common source pad (239) may be vertically overlapped with the first power semiconductor element (232-1). The common source pad (239) may be vertically overlapped with the first source electrode (340) of the first power semiconductor element (232-1). The common source pad (239) may be vertically overlapped with the second power semiconductor element (232-2). The common source pad (239) may be vertically overlapped with the second source electrode (380) of the second power semiconductor element (232-2).

[0163] The size of the common gate pad (237) may be larger than the sum of the sizes of the first source electrode (340) of the first power semiconductor element (232-1) and the second source electrode (380) of the second power semiconductor element (232-2). Therefore, even if a common gate pad (237) larger than the size of the first power semiconductor element (232-1) or the size of the second power semiconductor element (232-2) is bonded to the first substrate (210) or the second substrate (220) to implement the power conversion device (200), not only will bonding failure not occur, but the bonding strength will be greatly increased so that defects such as detachment can be prevented. In this way, bonding failure or detachment failure can be prevented, so that the yield can be increased.

[0164] Meanwhile, the common source pad (239) can surround at least two outer sides of the common gate pad (237).

[0165] As illustrated in FIG. 9, the common source pad (239) may have a closed loop structure surrounding the common gate pad (237). The common source pad (239) may have an opening (280), and the common gate pad (237) may be positioned in the opening (280). In this case, the inner side of the common source pad (239) may be positioned spaced apart from the outer side of the common gate pad (237).

[0166] The common source pad (239) may be disposed on the first short side (237a), the second short side (237b), the first long side (237c), and the second long side (237d) of the common gate pad (237). The common source pad (239) may be disposed spaced apart from the first short side (237a) of the common gate pad (237). The common source pad (239) may be disposed spaced apart from the second short side (237b) of the common gate pad (237). The common source pad (239) may be disposed spaced apart from the first long side (237c) of the common gate pad (237). The common source pad (239) may be disposed spaced apart from the second long side (237d) of the common gate pad (237).

[0167] As illustrated in FIG. 9, the size of the common drain pad (231) may be larger than the sum of the sizes of the common gate pad (237) and the common source pad (239). In this way, as the size of the common drain pad (231) is greatly expanded, heat generated from the first power semiconductor element (232-1) and the second power semiconductor element (232-2) can be quickly dissipated to the outside. Therefore, as described above, the common drain pad (231) can serve as a heat dissipation member.

[0168] FIG. 10 is a second exemplary diagram illustrating the layout of a common gate pad and a common source pad according to the present disclosure.

[0169] In Fig. 10, the position of the first gate electrode (330) of the first power semiconductor element (232-1), the position of the second gate electrode (370) of the second power semiconductor element (232-2), the position of the common gate pad (237), and the shape of the common source pad (239) are the same as in Fig. 9. Therefore, in the following, components having the same shape, structure, and / or function are given the same drawing reference numerals and detailed descriptions are omitted.

[0170] As illustrated in Fig. 10, the first gate electrode (330) of the first power semiconductor element (232-1) may be positioned in one corner region. The second gate electrode (370) of the second power semiconductor element (232-2) may be positioned in one corner region.

[0171] The common gate pad (237) may be spaced apart from one side of the common drain pad (231) at a position where they overlap spatially vertically. The common gate pad (237) may vertically overlap with the first gate electrode (330) of the first power semiconductor element (232-1) and may vertically overlap with the second gate electrode (370) of the second power semiconductor element (232-2).

[0172] As illustrated in FIG. 10, the common source pad (239) may have an open structure surrounding the common gate pad (237). That is, the common source pad (239) may be disposed on the first short side (237a), the second short side (237b), and the first long side (237c) of the common gate pad (237). Alternatively, the common source pad (239) may not be disposed on the second long side (237d) of the common gate pad (237), but this is not limited thereto.

[0173] FIG. 11 is a third exemplary diagram illustrating the layout of a common gate pad and a common source pad according to the present disclosure.

[0174] In Fig. 11, the pad (290) for the Kelvin source is the same as in Fig. 10. Therefore, in the following, components having the same shape, structure, and / or function are given the same drawing reference numerals and detailed descriptions are omitted. The pad (290) for the Kelvin source can also be applied to the arrangement structure of the common source pad (239) of the common gate pad (237) in Fig. 9.

[0175] Typically, a power conversion device (200) using power semiconductor modules including a first power semiconductor element (232-1) and a second power semiconductor element (232-2) used as a switch can be driven. For example, when the first power semiconductor element (232-1) and the second power semiconductor element (232-2) are turned on, the driving current may rapidly increase, and an electromotive force may be generated due to parasitic capacitance on the source electrode. This electromotive force may flow into the gate electrode, causing a voltage drop. Accordingly, the voltage between the gate and the source may decrease, and the turn-on speed, i.e., the switching speed, may be slowed down. Similarly, the turn-off speed may be reduced when turning off.

[0176] To solve this problem, in the present disclosure, a pad (290) for a Kelvin source may be arranged. The pad (290) for a Kelvin source may be a pad for contacting a Kelvin source (or driver) that supplies a voltage different from the gate voltage supplied to the common gate pad (237). Therefore, by having the Kelvin source supply a voltage different from the gate voltage to the pad (290) for the Kelvin source, the above-described problem can be solved.

[0177] In the case where a power conversion device (200) is implemented using existing power semiconductor devices, there was a problem in that it was difficult to allocate a portion of the source electrode to a pad (290) for a Kelvin source because the size of the power semiconductor device was so small.

[0178] However, in the present disclosure, as described above, the size of the common source pad (239) may be formed to be at least larger than the size of the first power semiconductor element (232-1) or the size of the second power semiconductor element (232-2). Accordingly, as illustrated in FIG. 11, a portion of the common source pad (239) may be allocated as a pad (290) for a Kelvin source. That is, as illustrated in FIG. 10, since the size of the common source pad (239) is sufficiently wide, a portion of the common source pad (239) disposed on the area between the first power semiconductor element (232-1) and the second power semiconductor element (232-2) may be disposed as a pad (290) for a Kelvin source. Although the Kelvin source pad (290) is illustrated in the drawing as having a rectangular shape, various shapes are possible. By supplying the voltage from the Kelvin source to the pad (290) for the Kelvin source, the generation of an electromotive voltage on the common source pad (239) is suppressed, thereby preventing a decrease in the switching speed.

[0179] Meanwhile, in FIGS. 9 to 11, the first source electrode (340) and the second source electrode (380) are each depicted as rectangular, but may have other shapes, for example, shapes surrounding the first gate electrode (330) and the second gate electrode (370), respectively.

[0180] FIG. 12 is a fourth example diagram (500A) showing the layout of a power semiconductor module according to the present disclosure.

[0181] The power semiconductor module (500A) of the present disclosure illustrated in FIG. 12 can adopt the technical features of the power semiconductor module based on FIGS. 9 to 11 described above, and the following description will focus on the technical features of the power semiconductor module (500A) of the present disclosure illustrated in FIG. 12.

[0182] The power semiconductor module (500A) of the present disclosure illustrated in FIG. 12 is an example in which four power semiconductor elements (511 to 514) are arranged on a common drain pad (231) to form one module, and a common gate pad (530) is arranged on the four power semiconductor elements (511 to 514).

[0183] For example, the first to fourth power semiconductor elements (511 to 514) may each include first to fourth source electrodes (541 to 544) and first to fourth gate electrodes (not shown), respectively.

[0184] In a power semiconductor module (500A), the first to fourth power semiconductor elements (511 to 514) may include first to fourth source pads (540a to 540d) arranged on the first to fourth source electrodes (541 to 544), respectively.

[0185] Additionally, the power semiconductor module (500A) may include a common gate pad (530) disposed on the first to fourth gate electrodes of the first to fourth power semiconductor elements (511 to 514).

[0186] The first to fourth source pads (540a, 540b, 540c, 540d) may surround the common gate pad (530). When the power semiconductor module (500A) is divided into a central region and a peripheral region, the common gate pad (530) may be arranged in the central region, and the first to fourth source pads (540a, 540b, 540c, 540d) may be arranged in the peripheral region. The common gate pad (530) may vertically overlap the first to fourth gate electrodes in the central region. The common gate pad (530) may be arranged not only on the first to fourth gate electrodes in the central region, but also on the region between the first to fourth gate electrodes, thereby maximizing its size.

[0187] The power semiconductor module (500A) illustrated in Fig. 12 can be manufactured through the following manufacturing process.

[0188] First, a first lead frame including first to fourth source pads (540a, 540b, 540c, 540d) and a common gate pad (530) may be provided. A conductive adhesive may be formed on the first lead frame using a paste printing process or a dotting process, and the first to fourth power semiconductor elements (511 to 514) may be attached to the lead frame using the adhesive. Accordingly, the first to fourth power semiconductor elements (511 to 514) may be electrically connected to the first to fourth source pads (540a, 540b, 540c, 540d) and the common gate pad (530).

[0189] Thereafter, a conductive adhesive may be formed on a second lead frame including a common drain pad (231) using a paste printing process. Thereafter, the second lead frame may be attached to the first to fourth power semiconductor elements (511 to 514) using a sintering process or a soldering process. Accordingly, the first to fourth power semiconductor elements (511 to 514) may be electrically connected to the common drain pad (231).

[0190] Meanwhile, the common gate pad (530) illustrated in FIG. 12 can be placed in various positions with various shapes, as illustrated in FIGS. 13a to 13d.

[0191] As illustrated in FIGS. 13a and 13c, the first common gate pad (530a) may be positioned between the first source pad (540a) and the fourth source pad (540d), and the second common gate pad (530b) may be positioned between the second source pad (540b) and the third source pad (540c).

[0192] As shown in FIGS. 13b and 13d, the common gate pad (530) can be arranged to extend from a first region between the first source pad (540a) and the fourth source pad (540d) to a second region between the second source pad (540b) and the third source pad (540c).

[0193] Meanwhile, unlike FIGS. 13b and 13d, in FIGS. 13b and 13d, a groove may be formed on one side of each of the first to fourth source pads (540a, 540b, 540c, 540d) facing the first common gate pad (530a) and the second common gate pad (530b), respectively.

[0194] FIG. 14 is a fifth exemplary diagram illustrating the layout of a power semiconductor module of the present disclosure.

[0195] The power semiconductor module (500B) illustrated in FIG. 14 may be identical to the power semiconductor module (500A) illustrated in FIG. 12 except for the connection portion (550).

[0196] The connecting portion (550) can electrically connect the common gate pad (530) to the first substrate (210 in FIG. 3) or the second substrate (220 in FIG. 3). The connecting portion (550) can extend from the upper surface of the common gate pad (530) between the first source pad (540a) and the fourth source pad (540d). Alternatively, the connecting portion (550) can extend from the upper surface of the common gate pad (530) between the first source pad (540a) and the second source pad (540b), between the second source pad (540b) and the third source pad (540c), or between the third source pad (540c) and the fifth source pad (540d).

[0197] Fig. 15 is a sixth exemplary diagram illustrating the layout of a power semiconductor module according to the present disclosure. The power semiconductor module (500C) of the present disclosure illustrated in Fig. 15 may adopt the technical features of the power semiconductor module based on Figs. 9 to 12 described above, and the following description will focus on the technical features of the power semiconductor module (500C) of the present disclosure illustrated in Fig. 15.

[0198] The power semiconductor module (500C) of the present disclosure illustrated in FIG. 15 is an example in which a common gate pad (530) and a common source pad (540) are arranged on four power semiconductor elements.

[0199] For example, the power semiconductor module (500C) of the present disclosure illustrated in FIG. 12 is an example in which four power semiconductor elements (511 to 514) are arranged on a common drain pad (231) to constitute one module, and a common gate pad (530) and a common source pad (540) are arranged on the four power semiconductor elements (511 to 514).

[0200] For example, the power semiconductor module (500C) may include a common source pad (540) disposed on the first to fourth source electrodes (541 to 544) of the first to fourth power semiconductor elements (511 to 514) and a common gate pad (530) disposed on the first to fourth gate electrodes of the first to fourth power semiconductor elements (511 to 514).

[0201] In the power semiconductor module (500A) illustrated in FIG. 12, the first to fourth source pads (540a, 540b, 540c, 540d) surround the common gate pad (530), whereas in the power semiconductor module (500C0) illustrated in FIG. 15, one source pad (540) can surround the common gate pad (530). In the power semiconductor module (500A) illustrated in FIG. 12, the first to fourth source pads (540a, 540b, 540c, 540d) are formed integrally, so that one source pad (540) can be formed in the power semiconductor module (500C) illustrated in FIG. 15.

[0202] A connection pad (not shown) may be arranged to electrically connect the common gate pad (530) to the outside. The source pad (540) may have a separation region that includes at least the arranged connection pad so as not to be electrically shorted with the arranged connection pad. The separation region may be an area where the source pad (540) is not formed.

[0203] Meanwhile, FIG. 15 illustrates that the common gate pad (530) is positioned on the inside and the common source pad (540) is positioned on the outside, but the present disclosure is not limited thereto.

[0204] For example, in the additional disclosure, a common gate pad (530) may be placed on the outside, and a common source pad (540) may be placed on the inside.

[0205] Specifically, in the power semiconductor module (500C) of the present disclosure, the first to fourth gate electrodes (not shown) of the first to fourth power semiconductor elements (511 to 514) may be positioned at outer corners, respectively, and the first to fourth source electrodes (541 to 544) may be positioned at the inner side.

[0206] Thereafter, a common gate pad (530) may be placed on the first to fourth gate electrodes respectively positioned at the outer corners, and a common source pad (540) may be placed on the first to fourth source electrodes (541 to 544) positioned on the inner side.

[0207] Hereinafter, the manufacturing process of a power semiconductor module according to the present disclosure will be described with reference to FIGS. 16a to 16h. Meanwhile, the manufacturing process of a power semiconductor module according to the present disclosure is not limited to the process sequence or the process contents illustrated in FIGS. 16a to 16h, and the process sequence may be changed, some processes may be omitted, or other processes may be added.

[0208] First, as illustrated in FIG. 16A, a plurality of power semiconductor elements, for example, a first power semiconductor element (232-1) and a second power semiconductor element (232-2), may be provided. The first power semiconductor element (232-1) may include a first drain electrode (320), a first semiconductor layer (310), a first gate electrode (330), and a first source electrode (340). The second power semiconductor element (232-2) may include a second drain electrode (360), a second semiconductor layer (350), a second gate electrode (370), and a second source electrode (380).

[0209] In the first power semiconductor element (232-1), a first insulating layer (345) is disposed around each of the first gate electrode (330) and the second source electrode (380), so that a short circuit between the first gate electrode (330) and the first source electrode (340) can be prevented, and the first semiconductor layer (310) can be protected from heat, moisture, impact, etc. In the second power semiconductor element (232-2), a second insulating layer (385) is disposed around each of the second gate electrode (370) and the second source electrode (380), so that a short circuit between the second gate electrode (370) and the second source electrode (380) can be prevented, and the second semiconductor layer (350) can be protected from heat, moisture, impact, etc. The first insulating layer (345) and / or the second insulating layer (385) may be formed of an inorganic insulating material, but is not limited thereto.

[0210] As illustrated in FIG. 16b, a sputtering and / or electroplating process may be performed using the first insulating layer (345) as a mask, so that a first gate contact (234-1) and a first source contact (234-2) may be formed on the first gate electrode (330) and the first source electrode (340) of the first power semiconductor element (232-1), respectively. A sputtering and / or electroplating process may be performed using the second insulating layer (385) as a mask, so that a second gate contact (235-1) and a second source contact (235-2) may be formed on the second gate electrode (370) and the second source electrode (380) of the second power semiconductor element (232-2), respectively. Here, the contact may be referred to as a stud, a pillar, etc.

[0211] Meanwhile, unlike as shown in FIG. 16b, the process of forming the first gate contact (234-1) and the first source contact (234-2) on the first power semiconductor element (232-1) and the process of forming the first gate contact (235-1) and the first source contact (235-2) on the second power semiconductor element (232-2) can be formed after the process of forming the molding layer (233) by the overmolding process as shown in FIG. 16e.

[0212] The processes illustrated in FIGS. 16A and 16B can be performed at the wafer level. That is, after a drain electrode (320, 360), a semiconductor layer (310, 350), an insulating layer (345, 385), a plurality of gate electrodes (330, 370), a plurality of source electrodes (340, 380), a plurality of gate contacts (234-1, 235-1), and a plurality of source contacts (234-2, 235-2) are formed on a wafer (not shown), a cutting process can be performed. Accordingly, a first power semiconductor element (232-1) and a second power semiconductor element (232-2) can be formed from the wafer. The wafer can be removed before or after performing the cutting process.

[0213] As illustrated in Fig. 16c, a common drain pad (231) may be provided. The common drain pad (231) may be formed of a metal material having excellent electrical conductivity. For example, the common drain pad (231) may have a three-layer structure of copper (Cu)-molybdenum (Mo)-copper (Cu).

[0214] As illustrated in FIG. 16d, a first power semiconductor element (232-1) and a second power semiconductor element (232-2) may be bonded onto a common drain pad (231). For example, a sintering process may be used to bond the first power semiconductor element (232-1) and the second power semiconductor element (232-2) onto the common drain pad (231). A bonding agent such as silver paste may be used for a given process, but is not limited thereto.

[0215] As illustrated in FIG. 16e, a molding layer (233) may be formed on the first power semiconductor element (232-1) and the second power semiconductor element (232-2) using an EMC molding process. Thereafter, as illustrated in FIG. 16f, the molding layer (233) on the first power semiconductor element (232-1) and the second power semiconductor element (232-2) may be removed using an EMC grinding process. Accordingly, the upper surface of the molding layer (233) and the upper surfaces of each of the first gate contact (234-1), the first source contact (234-2), the second gate contact (235-1), and the second source contact (235-2) may be positioned on the same horizontal line. Meanwhile, as previously described, unlike that illustrated in FIG. 16e, the process of forming the first gate contact (234-1) and the first source contact (234-2) on the first power semiconductor element (232-1) and the process of forming the first gate contact (235-1) and the first source contact (235-2) on the second power semiconductor element (232-2) may be performed after the process of forming the molding layer (233) by the overmolding process illustrated in FIG. 16e.

[0216] For example, by grinding the overmolded molding layer (233), the first gate electrode (330) and the first source electrode (340) of the first power semiconductor element (232-1) and the second gate electrode (370) and the second source electrode (380) of the second power semiconductor element (232-2) are exposed.

[0217] As shown in FIG. 16h, a process of forming a first gate contact (234-1) and a first source contact (234-2) on the first power semiconductor element (232-1), a process of forming a first gate contact (235-1) and a first source contact (235-2) on the second power semiconductor element (232-2), and a process of forming a common gate pad (237) and a common source pad (239) can be performed thereafter.

[0218] As illustrated in FIGS. 16g and 16h, an insulating layer (236), a common gate pad (237), and a common source pad (239) may be formed. For example, after the insulating layer (236) is formed first, a sputtering and / or electroplating process may be performed using the insulating layer (236) as a mask to form the common gate pad (237) and the common source pad (239). The insulating layer (236) may be formed on an area remaining except for an area where the common gate pad (237) and the common source pad (239) are to be formed. The common gate pad (237) and the common source pad (239) may be surrounded by the insulating layer (236). As described above, the sizes of each of the common gate pad (237) and the common source pad (239) may be expanded. The size of each of the common gate pad (237) and the common source pad (239) can be freely adjusted by the layout of the insulating layer (236).

[0219] Meanwhile, the insulating layer (236) protects the first power semiconductor element (232-1) and the second power semiconductor element (232-2) from heat, moisture, etc., and thus may be called a passivation layer. The insulating layer (236) may be formed of an inorganic insulating material, but is not limited thereto.

[0220] Fig. 17 is a cross-sectional view illustrating a power semiconductor module according to the present disclosure.

[0221] Although the first power semiconductor module (230) among the plurality of power semiconductor modules (230, 240, 260, 270 of FIG. 8) is illustrated in FIG. 17, the structure of each of the second power semiconductor module (240), the third power semiconductor module (260), and the fourth power semiconductor module (270) may be identical to the structure of the first power semiconductor module (230) illustrated in FIG. 17. Therefore, the structure of each of the second power semiconductor module (240), the third power semiconductor module (260), and the fourth power semiconductor module (270) can be easily understood from the structure of the first power semiconductor module (230) illustrated in FIG. 17.

[0222] A second aspect of the present disclosure (Fig. 17) is identical to the second aspect of the present disclosure (Fig. 17) except that the common gate pads (237, 247) are further enlarged. In the second aspect of the present disclosure (Fig. 17), the same reference numerals are assigned to components having the same shape, structure, and / or function as in the first aspect of the present disclosure (Fig. 4), and detailed descriptions are omitted. The description omitted in the second aspect of the present disclosure (Fig. 17) can be readily understood from the description of the second aspect of the present disclosure (Fig. 17).

[0223] As illustrated in FIG. 17, the first power semiconductor module (230) may include a first power semiconductor element (232-1), a second power semiconductor element (232-2), a molding layer (233), etc.

[0224] Referring to FIG. 5 and FIG. 17, the first power semiconductor element (232-1) may include a first semiconductor layer (310), a first drain electrode (320), a first gate electrode (330), a first source electrode (340), etc. The second power semiconductor element (232-2) may include a second semiconductor layer (350), a second drain electrode (360), a second gate electrode (370), and a second source electrode (380).

[0225] A common gate pad (237) may be commonly connected to a first gate electrode (330) of a first power semiconductor element (232-1) and a second gate electrode (370) of a second power semiconductor element (232-2). The common gate pad (237) may extend from the first gate electrode (330) of the first power semiconductor element (232-1) toward the second gate electrode (370) of the second power semiconductor element (232-2).

[0226] The common gate pad (237) is placed not only on the first power semiconductor element (232-1) but also on the second power semiconductor element (232-2), so that its size (or area) can be expanded to the maximum.

[0227] The common gate pad (237) may vertically overlap the first gate electrode (330) of the first power semiconductor element (232-1), the first source electrode (340) of the first power semiconductor element (232-1), the first gate electrode (370) of the second power semiconductor element (232-2), and the second source electrode (380) of the second power semiconductor element (232-2), respectively.

[0228] The common gate pad (237) may extend from the central region of the common drain pad (231) to the first source electrode (340) via the first gate electrode (330) of the first power semiconductor element (232-1) and may vertically overlap with the first source electrode (340). The common gate pad (237) may extend from the central region of the common drain pad (231) to the second source electrode (380) via the second gate electrode (370) of the second power semiconductor element (232-2) and may vertically overlap with the second source electrode (380). The central region of the common drain pad (231) may be a region between the first region (231-1) (see FIG. 17) and the second region (231-2) (see FIG. 17) of the common drain pad (231).

[0229] In this way, by maximizing the size (or area) of the common gate pad (237), bonding or detachment defects can be prevented, thereby improving the yield.

[0230] An insulating layer is disposed between the common gate pad (237) and the first source electrode (340) and between the common gate pad (237) and the second source electrode (380), so that an electrical short between them can be prevented.

[0231] Meanwhile, a common source pad (239) may be disposed on the first power semiconductor element (232-1) and the second power semiconductor element (232-2). The common source pad (239) may be commonly connected to the first source electrode (340) of the first power semiconductor element (232-1) and the second source electrode (380) of the second power semiconductor element (232-2).

[0232] The common source pad (239) may be vertically overlapped with the first source electrode (340) of the first power semiconductor element (232-1) and electrically connected to the first source electrode (340). The common source pad (239) may be vertically overlapped with the second source electrode (380) of the second power semiconductor element (232-2) and electrically connected to the second source electrode (380). The common source pad (239) may extend from the first source electrode (340) of the first power semiconductor element (232-1) toward the second source electrode (380) of the second power semiconductor element (232-2).

[0233] The size (or area) of the common source pad (239) may be larger than the size (or area) of the first power semiconductor element (232-1) or the size (or area) of the second power semiconductor element (232-2). The outer side of the common source pad (239) may be disposed on one outer side of the first power semiconductor element (232-1) and / or the second power semiconductor element (232-2). For example, the common source pad (239) may be positioned closer to one outer side of the common drain pad (231) than to one outer side of the first source electrode (340) of the first power semiconductor element (232-1). For example, the common source pad (239) may be positioned closer to another outer side of the common drain pad (231) than to one outer side of the second source electrode (380) of the second power semiconductor element (232-2).

[0234] The common source pad (239) may be spaced apart from the common gate pad (237) to prevent short circuiting with the common gate pad (237). The common source pad (239) may surround the common gate pad (237).

[0235] The size (or area) of the common drain pad (231) may be larger than the sum of the size (or area) of the common gate pad (237) and the size (or area) of the common source pad (239).

[0236] Fig. 18 is a cross-sectional view showing a plurality of power semiconductor devices packaged in the present disclosure.

[0237] The structure of the package illustrated in FIG. 18 is identical to the structure of the package illustrated in FIG. 6 except for the common gate pad (237) and the common source pad (239). Accordingly, in the structure of the package illustrated in FIG. 18, components having the same shape, structure, and / or function as those of the structure of the package illustrated in FIG. 6 are given the same drawing reference numerals, and a detailed description thereof is omitted. As illustrated in FIG. 18, a plurality of power semiconductor devices (32-1 to 232-4) may be packaged on a common drain pad (231'). For example, a common drain pad (231') may be formed on a wafer (not shown), and a plurality of power semiconductor devices (32-1 to 232-4), a molding layer (233), a common gate pad (237), a common source pad (239), etc. may be formed on the common drain pad (231').

[0238] Thereafter, a cutting process is performed according to a preset sawing lane (2000), so that power semiconductor modules (230, 400) illustrated in FIGS. 19a and 19b can be manufactured.

[0239] Accordingly, after a plurality of power semiconductor elements (32-1 to 232-4) are packaged on a common drain pad (231'), they are cut according to a sawing lane (2000) set in consideration of the number of power semiconductor elements (32-1 to 232-4) desired by the customer, thereby facilitating the manufacture of power semiconductor modules (230, 400) according to the number of power semiconductor elements (32-1 to 232-4), and thus the degree of freedom in the manufacture of power semiconductor modules (230, 400) can be maximized.

[0240] FIG. 20 is a seventh exemplary diagram illustrating the layout of a common gate pad and a common source pad according to the present disclosure.

[0241] The structure of the package illustrated in FIG. 20 is identical to the structure of the package illustrated in FIG. 9, except for the common gate pad (237) and the common source pad (239). Accordingly, components in the structure of the package illustrated in FIG. 20 that have the same shape, structure, and / or function as those in the structure of the package illustrated in FIG. 9 are given the same drawing reference numerals, and a detailed description thereof is omitted.

[0242] As illustrated in Fig. 20, a first power semiconductor element (232-1) and a second power semiconductor element (232-2) can be placed on a common drain pad (231).

[0243] The first source electrode (340), the first gate electrode (330), the second gate electrode (370), and the second source electrode (380) may be arranged in a row in the following order along one direction (X-axis direction): the first source electrode (340), the first gate electrode (330), the second gate electrode (370), and the second source electrode (380).

[0244] A common gate pad (237) and a common source pad (239) may be placed on the first power semiconductor element (232-1) and the second power semiconductor element (232-2).

[0245] A common gate pad (237) is placed in the center area of ​​the common drain pad (231), and a common source pad (239) can surround the common gate pad (237).

[0246] The common gate pad (237) may be vertically overlapped with the first power semiconductor element (232-1). The size of the common gate pad (237) may be larger than the sum of the size of the first gate electrode (330) of the first power semiconductor element (232-1) and the size of the second gate electrode (370) of the second power semiconductor element (232-2).

[0247] The common gate pad (237) may be spaced apart from each other on a position that spatially overlaps the common drain pad (231) exposed between the first power semiconductor element (232-1) and the second power semiconductor element (232-2). The first short side (237a) of the common gate pad (237) may be positioned on the first source electrode (340) of the first power semiconductor element (232-1). The second short side (237b) of the common gate pad (237) may be positioned on the second source electrode (380) of the second power semiconductor element (232-2).

[0248] The common source pad (239) may be vertically overlapped with the first power semiconductor element (232-1). The common source pad (239) may be vertically overlapped with the second power semiconductor element (232-2).

[0249] As illustrated in Fig. 20, the size of the common drain pad (231) may be larger than the sum of the sizes of the common gate pad (237) and the common source pad (239). In this way, as the size of the common drain pad (231) is greatly expanded, heat generated from the first power semiconductor element (232-1) and the second power semiconductor element (232-2) can be quickly dissipated to the outside. Therefore, as described above, the common drain pad (231) can serve as a heat dissipation member.

[0250] Fig. 21 is an eighth exemplary diagram illustrating a layout of a common gate pad and a common source pad according to the present disclosure. In Fig. 21, the position of the first gate electrode (330) of the first power semiconductor element (232-1), the position of the second gate electrode (370) of the second power semiconductor element (232-2), the position of the common gate pad (237), and the shape of the common source pad (239) are the same as in Fig. 20. Therefore, components having the same shape, structure, and / or function are given the same drawing reference numerals and detailed descriptions are omitted hereinafter.

[0251] As illustrated in Fig. 21, the first gate electrode (330) of the first power semiconductor element (232-1) may be positioned in one corner region. The second gate electrode (370) of the second power semiconductor element (232-2) may be positioned in one corner region.

[0252] The common gate pad (237) and the common source pad (239) can be arranged parallel to each other along one direction (X-axis direction).

[0253] The first short side (237a) of the common gate pad (237) may be positioned between the first source electrode (340) of the first power semiconductor element (232-1) and one side of the common drain pad (231). The first short side (237a) of the common gate pad (237) may be positioned closer to one side of the common drain pad (231) than to the outer side of the first source electrode (340) of the first power semiconductor element (232-1). The outer side of the first source electrode (340) may be a side that is further away from the center region of the common drain pad (231) than the inner side of the first source electrode (340).

[0254] The second short side (237b) of the common gate pad (237) may be positioned between the second source electrode (380) of the second power semiconductor element (232-2) and the other side of the common drain pad (231). The second short side (237b) of the common gate pad (237) may be positioned closer to the other side of the common drain pad (231) than to the outer side of the second source electrode (380) of the second power semiconductor element (232-2). One side and the other side of the common drain pad (231) may be positioned to face each other. The outer side of the second source electrode (380) may be a side that is further away from the center region of the common drain pad (231) than the inner side of the second source electrode (380).

[0255] The size of the common gate pad (237) may be equal to or smaller than the size of the common source pad (239). With this arrangement structure, the size of the common gate pad (237) is further expanded, thereby preventing bonding or detachment defects and achieving a higher yield.

[0256] For example, the common gate pad (237) may be arranged across the first source electrode (340) and the first gate electrode (330) of the first power semiconductor element (232-1) and the second gate electrode (370) and the second source electrode (380) of the second power semiconductor element (232-2) along one direction (X-axis direction) on one side region of the common drain pad (231). For example, the common source pad (239) may be arranged across the first source electrode (340) of the first power semiconductor element (232-1) and the second source electrode (380) of the second power semiconductor element (232-2) along one direction (X-axis direction) on the other side region of the common drain electrode (231). Although the common gate pad (237) in the drawing is depicted as vertically overlapping only a portion of the first gate electrode (330) of the first power semiconductor element (232-1) and only a portion of the second gate electrode (370) of the second power semiconductor element (232-2), it may also vertically overlap the entire area of ​​the first gate electrode (330) and the entire area of ​​the second gate electrode (370).

[0257] Although not shown, the common source pad (239) may surround at least two outer sides of the common gate pad (237). FIG. 22 is a ninth exemplary diagram illustrating the layout of a common gate pad and a common source pad according to the present disclosure.

[0258] In Fig. 22, the pad (290) for the Kelvin source is the same as in Fig. 21. Therefore, in the following, components having the same shape, structure, and / or function are given the same drawing reference numerals and detailed descriptions are omitted. The pad (290) for the Kelvin source can also be applied to the arrangement structure of the common source pad (239) of the common gate pad (237) in Fig. 20.

[0259] Typically, a power conversion device (200) using power semiconductor modules including a first power semiconductor element (232-1) and a second power semiconductor element (232-2) used as a switch can be driven. For example, when the first power semiconductor element (232-1) and the second power semiconductor element (232-2) are turned on, the driving current may rapidly increase, and an electromotive force may be generated due to parasitic capacitance on the source electrode. This electromotive force may flow into the gate electrode, causing a voltage drop. Accordingly, the voltage between the gate and the source may decrease, and the turn-on speed, i.e., the switching speed, may be slowed down. Similarly, the turn-off speed may be reduced when turning off.

[0260] To solve this problem, in the present disclosure, a pad (290) for a Kelvin source may be arranged. The pad (290) for a Kelvin source may be a pad for contacting a Kelvin source (or driver) that supplies a voltage different from the gate voltage supplied to the common gate pad (237). Therefore, by having the Kelvin source supply a voltage different from the gate voltage to the pad (290) for the Kelvin source, the above-described problem can be solved.

[0261] In the case where a power conversion device (200) is implemented using existing power semiconductor devices, there was a problem in that it was difficult to allocate a portion of the source electrode to a pad (290) for a Kelvin source because the size of the power semiconductor device was so small.

[0262] However, in the present disclosure, as described above, the size of the common source pad (239) may be formed to be at least larger than the size of the first power semiconductor element (232-1) or the size of the second power semiconductor element (232-2). Accordingly, as illustrated in FIG. 22, a portion of the common source pad (239) may be allocated as a pad (290) for a Kelvin source. The pad (290) for a Kelvin source may be formed integrally with the common source pad (239) and designated as an area to be connected to the Kelvin source.

[0263] As illustrated in FIG. 21, since the size of the common source pad (239) is sufficiently wide, a portion of the common source pad (239) positioned on the area between the first power semiconductor element (232-1) and the second power semiconductor element (232-2) can be designated as a pad (290) for the Kelvin source. That is, since the size of the common source pad (239) is sufficiently wide, a pad of sufficient size to be connected to the Kelvin source can be allocated to the pad (290) for the Kelvin source. Although the pad (290) for the Kelvin source is illustrated in the drawing as having a rectangular shape, various shapes are possible. By supplying the voltage from the Kelvin source to the pad (290) for the Kelvin source, the generation of an electromotive voltage on the common source pad (239) is suppressed, and a decrease in the switching speed can be prevented.

[0264] Meanwhile, in FIGS. 20 to 22, the first source electrode (340) and the second source electrode (380) are each depicted as rectangular, but may have other shapes, for example, shapes surrounding the first gate electrode (330) and the second gate electrode (370), respectively.

[0265] FIG. 23 is a tenth exemplary diagram illustrating a layout of a power semiconductor module according to the present disclosure. The power semiconductor module of the present disclosure illustrated in FIG. 23 may adopt the technical features of the power semiconductor modules based on FIGS. 20 to 22 described above, and the following description will focus on the technical features of the power semiconductor module of the present disclosure illustrated in FIG. 23. The power semiconductor module (600A) of the present disclosure illustrated in FIG. 23 is an example in which four power semiconductor elements (611 to 614) are arranged on a common drain pad (601) to constitute one module, and a common gate pad (630) is arranged on the four power semiconductor elements (611 to 614).

[0266] For example, the first to fourth power semiconductor elements (611 to 614) may each include first to fourth source electrodes (641 to 644) and first to fourth gate electrodes (631 to 634), respectively.

[0267] In a power semiconductor module (600A), the first to fourth power semiconductor elements (611 to 614) may include first to fourth source pads (640a, 640b, 640c, 640d) arranged on the first to fourth source electrodes (641 to 644), respectively.

[0268] Additionally, the power semiconductor module (600A) may include a common gate pad (630) disposed on the first to fourth gate electrodes (631 to 634) of the first to fourth power semiconductor elements (611 to 614).

[0269] FIG. 24 is an eleventh exemplary diagram illustrating the layout of a power semiconductor module according to the present disclosure. The power semiconductor module of the present disclosure illustrated in FIG. 24 may adopt the technical features of the power semiconductor modules based on FIGS. 20 to 23 described above, and the following description will focus on the technical features of the power semiconductor module of the present disclosure illustrated in FIG. 24.

[0270] The power semiconductor module (600B) of the present disclosure illustrated in FIG. 24 is an example in which a common gate pad (630) and a common source pad (640) are arranged on four power semiconductor elements.

[0271] For example, the power semiconductor module of the present disclosure illustrated in FIG. 23 is an example in which four power semiconductor elements (611 to 614) are arranged on a common drain pad (601) to constitute one module, and a common gate pad (630) and a common source pad (640) are arranged on the four power semiconductor elements (611 to 614).

[0272] For example, the power semiconductor module (600B) may include a common source pad (640) disposed on the first to fourth source electrodes (641 to 644) of the first to fourth power semiconductor elements (611 to 614) and a common gate pad (630) disposed on the first to fourth gate electrodes (631 to 634) of the first to fourth power semiconductor elements (611 to 614).

[0273] Meanwhile, although FIG. 24 illustrates that the common gate pad (630) is positioned on the inside and the common source pad (640) is positioned on the outside, the present disclosure is not limited thereto. For example, in the additional present disclosure, the common gate pad (630) may be positioned on the outside and the common source pad (640) may be positioned on the inside.

[0274] Specifically, in the power semiconductor module (600B) of the present disclosure, the first to fourth gate electrodes (631 to 634) of the first to fourth power semiconductor elements (611 to 614) may be positioned at outer corners, respectively, and the first to fourth source electrodes (641 to 644) may be positioned at the inner side.

[0275] Thereafter, a common gate pad (630) may be placed on the first to fourth gate electrodes (631 to 634) positioned at the outer corners, respectively, and a common source pad (640) may be placed on the first to fourth source electrodes (641 to 644) positioned on the inner side.

[0276] Hereinafter, the manufacturing process of a power semiconductor module according to the present disclosure will be described with reference to FIGS. 25a to 25h. Meanwhile, the manufacturing process of a power semiconductor module according to the present disclosure is not limited to the process sequence or the process contents illustrated in FIGS. 25a to 25h, and the process sequence may be changed, some processes may be omitted, or other processes may be added.

[0277] First, as illustrated in FIG. 25A, a plurality of power semiconductor elements, for example, a first power semiconductor element (232-1) and a second power semiconductor element (232-2), may be provided. The first power semiconductor element (232-1) may include a first drain electrode (320), a first semiconductor layer (310), a first gate electrode (330), and a first source electrode (340). The second power semiconductor element (232-2) may include a second drain electrode (360), a second semiconductor layer (350), a second gate electrode (370), and a second source electrode (380).

[0278] In the first power semiconductor element (232-1), a first insulating layer (345) is disposed around each of the first gate electrode (330) and the second source electrode (380), so that a short circuit between the first gate electrode (330) and the first source electrode (340) can be prevented, and the first semiconductor layer (310) can be protected from heat, moisture, impact, etc. In the second power semiconductor element (232-2), a second insulating layer (385) is disposed around each of the second gate electrode (370) and the second source electrode (380), so that a short circuit between the second gate electrode (370) and the second source electrode (380) can be prevented, and the second semiconductor layer (350) can be protected from heat, moisture, impact, etc. The first insulating layer (345) and / or the second insulating layer (385) may be formed of an inorganic insulating material, but is not limited thereto.

[0279] As illustrated in FIG. 25b, a sputtering and / or electroplating process may be performed using the first insulating layer (345) as a mask, so that a first gate contact (234-1) and a first source contact (234-2) may be formed on the first gate electrode (330) and the first source electrode (340) of the first power semiconductor element (232-1), respectively. A sputtering and / or electroplating process may be performed using the second insulating layer (385) as a mask, so that a second gate contact (235-1) and a third source contact may be formed on the second gate electrode (370) and the second source electrode (380) of the second power semiconductor element (232-2), respectively. Here, the contact may be referred to as a stud, a pillar, or the like.

[0280] Meanwhile, unlike as shown in FIG. 25b, the process of forming the first gate contact (234-1) and the first source contact (234-2) on the first power semiconductor element (232-1) and the process of forming the first gate contact (235-1) and the first source contact (235-2) on the second power semiconductor element (232-2) can be formed after the process of forming the molding layer (233) by the overmolding process as shown in FIG. 25e.

[0281] The processes illustrated in FIGS. 25A and 25B can be performed at the wafer level. That is, after a drain electrode (320, 360), a semiconductor layer (310, 350), an insulating layer (345, 385), a plurality of gate electrodes (330, 370), a plurality of source electrodes (340, 380), a plurality of gate contacts (234-1, 235-1), and a plurality of source contacts (234-2, 235-2) are formed on a wafer (not shown), a cutting process can be performed. Accordingly, a first power semiconductor element (232-1) and a second power semiconductor element (232-2) can be formed from the wafer. The wafer can be removed before or after performing the cutting process.

[0282] As illustrated in Fig. 25c, a common drain pad (231) may be provided. The common drain pad (231) may be formed of a metal material having excellent electrical conductivity. For example, the common drain pad (231) may have a three-layer structure of copper (Cu)-molybdenum (Mo)-copper (Cu).

[0283] As illustrated in FIG. 25d, a first power semiconductor element (232-1) and a second power semiconductor element (232-2) may be bonded to the common drain pad (231). For example, a sintering process may be used to bond the first power semiconductor element (232-1) and the second power semiconductor element (232-2) to the common drain pad (231). A bonding agent such as silver paste may be used for a given process, but is not limited thereto.

[0284] As illustrated in FIG. 25e, a molding layer (233) may be formed on the first power semiconductor element (232-1) and the second power semiconductor element (232-2) using an EMC molding process. Thereafter, as illustrated in FIG. 25f, the molding layer (233) on the first power semiconductor element (232-1) and the second power semiconductor element (232-2) may be removed using an EMC grinding process. Accordingly, the upper surface of the molding layer (233) and the upper surfaces of each of the first gate contact (234-1), the first source contact (234-2), the second gate contact (235-1), and the second source contact (235-2) may be positioned on the same horizontal line.

[0285] Meanwhile, as previously described, unlike that illustrated in FIG. 25e, the process of forming the first gate contact (234-1) and the first source contact (234-2) on the first power semiconductor element (232-1) and the process of forming the first gate contact (235-1) and the first source contact (235-2) on the second power semiconductor element (232-2) may be performed after the process of forming the molding layer (233) by the overmolding process illustrated in FIG. 25e.

[0286] For example, by grinding the overmolded molding layer (233), the first gate electrode (330) and the first source electrode (340) of the first power semiconductor element (232-1) and the second gate electrode (370) and the second source electrode (380) of the second power semiconductor element (232-2) are exposed.

[0287] As shown in FIG. 25h, a process of forming a first gate contact (234-1) and a first source contact (234-2) on the first power semiconductor element (232-1), a process of forming a first gate contact (235-1) and a first source contact (235-2) on the second power semiconductor element (232-2), and a process of forming a common gate pad (237) and a common source pad (239) can be performed thereafter.

[0288] As illustrated in FIGS. 25g and 25h, an insulating layer (236), a common gate pad (237), and a common source pad (239) may be formed. The insulating layer (236) may be formed such that the common gate pad (237) vertically overlaps the first gate electrode (330) and the first source electrode (340) of the first power semiconductor element (232-1) and the second gate electrode (370) and the second source electrode (380) of the second power semiconductor element (232-2), respectively.

[0289] Thereafter, a sputtering and / or electroplating process may be performed using the insulating layer (236) as a mask to form a common gate pad (237) and a common source pad (239). The insulating layer (236) may be formed on the remaining area except for the area where the common gate pad (237) and the common source pad (239) are to be formed. The common gate pad (237) and the common source pad (239) may be surrounded by the insulating layer (236). As described above, the size of each of the common gate pad (237) and the common source pad (239) may be expanded. The size of each of the common gate pad (237) and the common source pad (239) may be freely adjusted by the layout of the insulating layer (236).

[0290] Meanwhile, the insulating layer (236) protects the first power semiconductor element (232-1) and the second power semiconductor element (232-2) from heat, moisture, etc., and thus may be called a passivation layer. The insulating layer (236) may be formed of an inorganic insulating material, but is not limited thereto.

[0291] The above detailed description should not be construed as limiting in any respect and should be considered illustrative only. The scope of this disclosure should be determined by a reasonable interpretation of the appended claims, and all changes within the equivalent scope of this disclosure are intended to be embraced therein.

Claims

1. Common drain pad; A first power semiconductor element on a first region of the common drain pad; A second power semiconductor element on a second region of the common drain pad; a common gate pad on the first power semiconductor element and the second power semiconductor element; and a source pad on the first power semiconductor element and the second power semiconductor element; The common drain pad is electrically connected to the first drain electrode of the first power semiconductor element and the second drain electrode of the second power semiconductor element, The common gate pad is electrically connected to the first gate electrode of the first power semiconductor element and the second gate electrode of the second power semiconductor element, The source pad is electrically connected to the first source electrode of the first power semiconductor element and the second source electrode of the second power semiconductor element, A power semiconductor module, wherein the source pad surrounds at least two outer sides of the common gate pad.

2. In paragraph 1, A power semiconductor module, wherein the source pad includes a common source pad vertically overlapping the first power semiconductor element and the second power semiconductor element.

3. In the second paragraph, the common source pad has an opening, A power semiconductor module, wherein the common gate pad is positioned in the opening.

4. A power semiconductor module in the second paragraph, wherein the common gate pad includes a first short side and a second short side in one direction and a first long side and a second long side in a direction perpendicular to the one direction.

5. A power semiconductor module in the fourth paragraph, wherein the common source pad is disposed on the first end side, the second end side, and the first end side of the common gate pad.

6. A power semiconductor module in the fifth paragraph, wherein the common source pad is disposed on the second side of the common gate pad.

7. In the fourth paragraph, the first end side of the common gate pad is positioned between the first gate electrode and the first source electrode, A power semiconductor module, wherein the second end side of the common gate pad is positioned between the second gate electrode and the second source electrode.

8. A power semiconductor module according to claim 1, wherein the source pad includes a first source pad and a second source pad that vertically overlap the first source electrode of the first power semiconductor element and the second source electrode of the second power semiconductor element, respectively.

9. A power semiconductor module according to claim 1, further comprising a pad for a Kelvin source spaced apart from the source pad on the first power semiconductor element and the second power semiconductor element.

10. A power semiconductor module in the first paragraph, wherein the size of the common gate pad is larger than the gate pad size of the first power semiconductor element or the gate pad size of the second power semiconductor element.

11. Common drain pad; A first power semiconductor element on a first region of the common drain pad; A second power semiconductor element on a second region of the common drain pad; a common gate pad on the first power semiconductor element and the second power semiconductor element; and a source pad on the first power semiconductor element and the second power semiconductor element; The common drain pad is electrically connected to the first drain electrode of the first power semiconductor element and the second drain electrode of the second power semiconductor element, The common gate pad is electrically connected to the first gate electrode of the first power semiconductor element and the second gate electrode of the second power semiconductor element, The source pad is electrically connected to the first source electrode of the first power semiconductor element and the second source electrode of the second power semiconductor element, A power semiconductor module, wherein the common gate pad vertically overlaps at least one of the first source electrode and the second source electrode.

12. In the 11th paragraph, the common gate pad is arranged across the first source electrode and the first gate electrode and the second gate electrode and the second source electrode along the one direction on the first region of the common drain pad, a power semiconductor module.

13. A power semiconductor module according to claim 11, wherein the source pad includes a common source pad vertically overlapping the first power semiconductor element and the second power semiconductor element.

14. A power semiconductor module in claim 13, wherein the common source pad is arranged across the first source electrode and the second source electrode along the one direction on the second region of the common drain pad.

15. In paragraph 13, The area of ​​the common source pad is larger than the area of ​​the source pad of the first power semiconductor device or the area of ​​the source pad of the second power semiconductor device. Power semiconductor modules.

16. A power semiconductor module in accordance with claim 13, wherein the area of ​​the common drain pad is greater than the sum of the area of ​​the common gate pad and the area of ​​the common source pad.

17. A power semiconductor module according to claim 1, wherein the source pad includes a first source pad and a second source pad that vertically overlap the first source electrode of the first power semiconductor element and the second source electrode of the second power semiconductor element, respectively.

18. A power semiconductor module according to claim 11, further comprising a pad for a Kelvin source spaced apart from the source pad on the first power semiconductor element and the second power semiconductor element.

19. First substrate; Second substrate; and A plurality of power semiconductor modules are included between the first substrate and the second substrate; Each of the above plurality of power semiconductor modules is Common drain pad; A first power semiconductor element on a first region of the common drain pad; A second power semiconductor element on a second region of the common drain pad; a common gate pad on the first power semiconductor element and the second power semiconductor element; and a common source pad on the first power semiconductor element and the second power semiconductor element; The above common source pad surrounds at least two sides of the above common gate pad, In some of the plurality of power semiconductor modules, the common drain pad is electrically connected to the first substrate, and the common gate pad and the common source pad are each electrically connected to the second substrate. In the remaining modules among the plurality of power semiconductor modules, the common drain pad is electrically connected to the second substrate, and the common gate pad and the common source pad are each electrically connected to the first substrate. Power conversion device.

20. In paragraph 19, A power conversion device further comprising a plurality of terminals connected to each of the first substrate and the second substrate.

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