Semiconductor structures and memory devices and methods for manufacturing the same

Abstract

A semiconductor structure is provided. The semiconductor structure comprises a first substrate, a second substrate, and a debonding layer. The second substrate is disposed on the first substrate. The second substrate comprises semiconductor material and has a thickness in a range from about 5 nm to about 10 μm. The debonding layer is disposed between the first substrate and the second substrate. At least a portion of the debonding layer is detachable from the first substrate by applying light or heat to the debonding layer.

Description

SEMICONDUCTOR STRUCTURES AND MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAMEBACKGROUNDRelated Application

[0001] This application claims priority to U.S. Provisional Patent Application Ser. No. 63 / 572,355, filed on Mar. 31, 2024, entitled “Semiconductor Structures and Processes for Manufacturing Semiconductor Devices” and U.S. Provisional Patent Application Ser. No. 63 / 639,696, filed on Apr. 28, 2024, entitled “Semiconductor Structures and Processes for Manufacturing Semiconductor Devices,” which are incorporated herein by reference in its entirety.Field of the Invention

[0002] The present disclosure relates to semiconductor structures, memory devices, and methods for manufacturing the same. In particular, some embodiments of the present disclosure relate to semiconductor structures including a debonding layer, methods for manufacturing the semiconductor structures, and methods for manufacturing memory devices using the semiconductor structures.Description of Related Art

[0003] The semiconductor industry faces continuous demand for improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density has come from repeated reduction in minimum feature size, allowing more components to be integrated into a given chip area. However, there are physical limitations to the limitations on the lithography process. On the other hand, while the dimension of the semiconductor devices is reduced and the integration density is increased, the space between these devices is decreased. The inter-device space becomes critical to the performance of the devices, and when the space is too small, these devices may interfere with each other. Therefore, compromise has to be made to balance the feature size and the inter-derice space and the performance of each device may need to be optimized.

[0004] As the lateral dimensions of semiconductor devices become smaller in each technology generation, it faces a bottleneck to further increase the integration density. An approach is to integrate devices through vertically stacking and interconnecting. A method for realizing this approach is using wafer-wafer bonding processes to form vertical electrical interconnections between stacked wafers. Specifically, first metal contacts in a first wafer are aligned to respectivesecond metal contacts in a second wafer, and the subsequent wafer-wafer bonding is performed to bond the first wafer and the second wafer. However, when the feature size of the metal contact is small, misalignment problems may arise during the wafer-wafer bonding process, and the electrical interconnections between stacked wafers may be failed. There is still a need to improve the manufacturing process for a higher integration density and better performance of the devices.SUMMARY

[0005] According to the present disclosure, a semiconductor structure is provided. The semiconductor structure comprises a first substrate, a second substrate, and a debonding layer. The second substrate is disposed on the first substrate. The second substrate comprises semiconductor material and has a thickness in a range from about 5 nm to about 10 μm. The debonding layer is disposed between the first substrate and the second substrate. At least a portion of the debonding layer is detachable from the first substrate by applying light or heat to the debonding layer.

[0006] In some embodiments, the second substrate is unpattemed.

[0007] In some embodiments, the second substrate comprises single crystalline semiconductor material.

[0008] In some embodiments, the debonding layer comprises compound semiconductor or polymer, and the first substrate is light transmittable such that at least a portion of the debonding layer is detachable from the first substrate by exposing the debonding layer to light passing through the first substrate.

[0009] In some embodiments, the debonding layer comprises polymer or germanium dioxide, and at least a portion of the debonding layer is detachable from the first substrate by applying heat to the debonding layer.

[0010] In some embodiments, the second substrate has a thickness in a range from about 5 nm to about 200 nm.

[0011] In some embodiments, the semiconductor structure further comprises a first dielectric layer between the debonding layer and the first substrate.

[0012] In some embodiments, the semiconductor structure further comprises a second dielectric layer between the debonding layer and the second substrate.

[0013] In some embodiments, the semiconductor structure further comprises a device metal layer. The second substrate is disposed between the device metal layer and the debonding layer.

[0014] In some embodiments, the debonding layer comprises a buffer layer and a crystalline layer, and the buffer layer of the debonding layer is in contact with the first substrate.

[0015] In some embodiments, the second substrate comprises a first semiconductor layer and a second semiconductor layer between the first semiconductor layer and the debonding layer. The first semiconductor layer and the second semiconductor layer are different in at least one of conductivity-type of dopant, dopant concentration, and composition of material.

[0016] According to the present disclosure, a method for manufacturing a semiconductor structure is provided. The method comprises providing a first structure comprises a first substrate. The method comprises providing a second structure comprises a semiconductor substrate. The method comprises forming a debonding layer on the first structure. The method comprises attaching the second structure to the first structure, such that the debonding layer is disposed between the first substrate and the semiconductor substrate. The method comprises removing a portion of the second structure and leaving a second substrate comprises semiconductor material and has a thickness in a range from about 5 nm to about 10 μm. At least a portion of the debonding layer is detachable from the first substrate by applying light or heat to the debonding layer.

[0017] In some embodiments, the semiconductor substrate comprises an implanted ion layer, and removing the portion of the second structure comprises removing a portion of the semiconductor substrate from approximately the implanted ion layer.

[0018] In some embodiments, the second structure comprise a third substrate and an etch stop layer between the third substrate and the semiconductor substrate, and removing the portion of the second structure comprises removing the third substrate and the etch stop layer.

[0019] In some embodiments, removing the portion of the second structure comprises removing a portion of the semiconductor substrate.

[0020] In some embodiments, providing the first structure comprises forming a first dielectric layer on the first substrate.

[0021] In some embodiments, the method comprises attaching the second structure to the first structure by a second dielectric layer.

[0022] In some embodiments, the method further comprises forming a device metal layer on the second substrate after removing the portion of the second structure.

[0023] According to the present disclosure, a method for manufacturing a memory device is provided. The method comprises providing a base substrate, the base substrate comprises a wiring layer. The method comprises providing a semiconductor structure. The semiconductor structure comprises a first substrate, a second substrate on the first substrate, and a debonding layer between the first substrate and the second substrate. The second substrate comprises semiconductor material and has a thickness in a range from about 5 nm to about 10 μm. The method comprises bonding the semiconductor structure and the base substrate to form a bonded structure by bonding a first bonding metal layer over the wiring layer and a second bonding metal layer over the second substrate. The method comprises detaching at least a portion of the debonding layer from the first substrate by applying light or heat to the debonding layer. The method comprises patterning the second substrate to form a plurality of devices.

[0024] In some embodiments, the debonding layer comprises compound semiconductor or polymer, and the method comprises detaching the at least a portion of the debonding layer from the first substrate by exposing the debonding layer to light passing through the first substrate.

[0025] In some embodiments, the debonding layer comprises polymer or germanium dioxide, and the method comprises detaching the at least a portion of the debonding layer from the first substrate by applying heat to the debonding layer.

[0026] In some embodiments, the wiring layer is in contact with the first bonding metal layer.

[0027] In some embodiments, the method further comprises patterning the first bonding metal layer and the second bonding metal layer to form a plurality of metal bonding contacts.

[0028] In some embodiments, the semiconductor structure comprises a first dielectric layer between the debonding layer and the first substrate. The method further comprises removing the first dielectric layer after detaching the at least a portion of the debonding layer from the first substrate.

[0029] In some embodiments, the semiconductor structure comprises a second dielectric layer between the debonding layer and the second substrate. The method further comprises removing the second dielectric layer after detaching the at least a portion of the debonding layer from the first substrate.

[0030] In some embodiments, a plurality of memory units are disposed in the base substrate.The plurality of devices are formed electrically connected to the plurality of memory units.

[0031] In some embodiments, the method further comprises forming a plurality of memory units or electrodes electrically connected to the plurality of devices.

[0032] According to the present disclosure, a memory device is provided. The memory device comprises a base substrate, a first diode, a first metal bonding contact and a memory unit. The base substrate comprises a wiring layer. The first diode is disposed over the base substrate. The first metal bonding contact is disposed between the base substrate and the first diode. The first metal bonding contact comprises a first metal layer, a second metal layer, and a metal bonding interface between the first metal layer and the second metal layer. The memory unit is disposed in the base substrate or over the first diode. The first metal layer of the first metal bonding contact is in contact with the wiring layer of the base substrate. The second metal layer of the first metal bonding contact is in contact with the first diode.

[0033] In some embodiments, the first diode comprises single crystalline semiconductor material.

[0034] In some embodiments, the first metal layer and the second metal layer of the first metal bonding contact comprise the same material composition.

[0035] In some embodiments, the first metal bonding contact comprises aluminum (Al) or titanium nitride (TiN).

[0036] In some embodiments, the first diode is a vertical P-N diode or a vertical Schottky diode has a height in a range from about 5 nm to about 1 μm.

[0037] In some embodiments, a first cunent flows through the first diode when the memory unit is selected for a first writing operation.

[0038] In some embodiments, the memory device further comprises an electrode disposed vertically between the memory unit and the first diode, wherein a first end of the first diode is electrically connected to a first word line, and a second end opposite to the first end of the first diode is electrically connected to the electrode.

[0039] In some embodiments, the memory device further comprises a second diode and a second metal bonding contact. The second diode is disposed over the electrode, a second metal bonding contact is disposed between the electrode and the second diode. The second metal bonding contactcomprises a first metal layer, a second metal layer, and a metal bonding interface between the first metal layer and the second metal layer. A first end of the second diode is electrically connected to the electrode. A second end opposite to the first end of the second diode is electrically connected to a second word line. A second current flows through the second diode when the memory unit is selected for a second writing operation.

[0040] In some embodiments, the memory device further comprises a second diode and a second metal bonding contact. The second diode is disposed over the base substrate. The second metal bonding contact is disposed between the base substrate and the second diode. The second metal bonding contact comprises a first metal layer, a second metal layer, and a metal bonding interface between the first metal layer and the second metal layer. The first metal layer of the second metal bonding contact is in contact with the wiring layer of the base substrate. The second metal layer of the second metal bonding contact is in contact with the second diode. A second cunent flows through the second diode when the memory unit is selected for a second writing operation.

[0041] In some embodiments, the memory device further comprises an electrode. The electrode is disposed vertically between the memory unit and the second diode. A first end of the second diode is electrically connected to the electrode. A second end opposite to the first end of the second diode is electrically connected to a second word line.

[0042] In some embodiments, the memory unit is disposed in the base substrate. A first end of the first diode is electrically connected to the memory unit through the first metal bonding contact. A second end opposite to the first end of the first diode is electrically connected to a read line.BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIGS. 1A to 1G are schematic diagrams illustrating semiconductor structures according to embodiments of the present disclosure.

[0044] FIGS. 2A to 2B are schematic diagrams illustrating semiconductor structures according to embodiments of the present disclosure.

[0045] FIG. 3 is a schematic diagram illustrating a semiconductor structure according to one embodiment of the present disclosure.

[0046] FIGS. 4A to 4F are schematic diagrams illustrating intermediate stages in the manufacture of a semiconductor structure according to one embodiment of the present disclosure.

[0047] FIGS. 5A to 5B are schematic diagrams illustrating intermediate stages in the manufacture of a semiconductor structure according to one embodiment of the present disclosure.

[0048] FIGS. 6A to 6D are schematic diagrams illustrating intermediate stages in the manufacture of a semiconductor structure according to one embodiment of the present disclosure.

[0049] FIG. 7 is a schematic diagram illustrating an intermediate stage in the manufacture of a semiconductor structure according to one embodiment of the present disclosure.

[0050] FIGS. 8A to 8B are schematic diagrams illustrating intermediate stages in the manufacture of a semiconductor structure according to one embodiment of the present disclosure.

[0051] FIGS. 9A to 9G are schematic diagrams illustrating intermediate stages in the manufacture of a memory device according to one embodiment of the present disclosure.

[0052] FIGS. 10A to 10B are schematic diagrams illustrating intermediate stages in the manufacture of a memory device according to one embodiment of the present disclosure.

[0053] FIGS. 11 to 15B are schematic diagrams illustrating memory devices according to embodiments of the present disclosure.DETAILED DESCRIPTION OF EMBODIMENTS

[0054] The terminology used in the description presented below is intended to be interpreted in its broadest reasonable manner, even though it is used in conjunction with a detailed description of certain specific embodiments of the technology. Certain terms may even be emphasized below; however, any terminology intended to be interpreted in any restricted manner will be specifically defined as such in this Detailed Description section. Components and achievement of a semiconductor structure or a device, according to the present disclosure may be illustrated in the following drawings and embodiments. However, the size and shape shown on drawings for the semiconductor structure(s) or the device(s) do not limit the features of the present disclosure.

[0055] The phrase “on ’ used in this application can mean directly on or indirectly on with intervening elements or layers. The spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0056] FIGS. 1A to 1G are schematic diagrams illustrating semiconductor structures according to embodiments of the present disclosure. Referring to FIG. 1A, a semiconductor structure 100 is provided. The semiconductor structure 100 comprises a first substrate 110, a second substrate 120, and a debonding layer 130. The second substrate 120 is disposed on the first substrate 110. The debonding layer 130 is disposed between the first substrate 110 and the second substrate 120.

[0057] The second substrate 120 comprises semiconductor material, such as silicon, germanium, or silicon germanium, or gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium nitride (GaN). In some embodiments, the second substrate 120 comprises single crystalline semiconductor material. The second substrate 120 may be a thin substrate made of semiconductor material. The second substrate 120 may have a thickness 120T in a range from about 5 nm to about 10 μm. In some embodiments, the second substrate 120 has a thickness 120T in a range from about 5 nm to about 5 μm, or from about 5 nm to about 200 nm. The second substrate 120 may be doped, e.g., with p-type dopant, such as boron, aluminum, gallium, indium, the like, or combinations thereof, or with a n-type dopant, such as phosphorus, arsenic, antimony, bismuth, the like, or combinations thereof. A dopant activation process can be performed to the semiconductor structure 100. In some embodiments, the second substrate 120 may be unpattemed. Specifically, the second substrate 120 may be substantially made of intrinsic semiconductor material, or thesecond substrate 120 may be doped uniformly across an entire layer in each usable die area. In some embodiments, the second substrate 120 may include a uniformly doped layer, as described below in greater detail. As such, no electric device is formed on the second substrate 120. In some embodiments, no electric device is formed in the usable die area of the second substrate 120. However, embodiments of the present disclosure are not so limited. In some embodiments, the second substrate 120 may be in direct contact with the debonding layer 130 without material layer or wiring structure(s) therebetween. In some embodiments, a dielectric layer may be disposed between the second substrate 120 and the debonding layer 130, as described below in greater detail with respect to FIGS. 2A and 2B.

[0058] At least a portion of the debonding layer 130 is detachable from the first substrate 110 by applying light or heat to the debonding layer 130. In some embodiments, the debonding layer 130 comprises compound semiconductor, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AIN), aluminium gallium nitride (AlGaN), polymer, such as polyimide, the like, or combination thereof, and the first substrate 110 is light transmittable such that at least a portion of the debonding layer! 30 is detachable from the first substrate 110 by exposing the debonding layer 130 to light passing through the first substrate 110. For example, the first substrate 110 may comprise sapphire or silicon carbide (SiC). In some embodiments, the debonding layer 130 comprises single crystalline silicon carbide, single crystalline gallium nitride, single crystalline aluminum nitride (AIN), and / or single crystalline aluminium gallium nitride (AlGaN), and the first substrate 110 comprises single crystalline sapphire or silicon carbide. The debonding layer 130 may comprise composition of material the same or different from the first substrate 110. The debonding layer 130 may be epitaxially formed on the first substrate 110. The debonding layer 130 may have a thickness in a range from about 5 nm to about 1 μm. The debonding layer 130 may be in direct contact with the first substrate 110 without material layer therebetween. In some embodiments, the debonding layer 130 may comprise polycrystalline silicon carbide, polycrystalline gallium nitride, polycrystalline aluminum nitride (AIN), polycrystalline aluminium gallium nitride (AlGaN), and / or polymer, such as polyimide, the like, or combination thereof, and the first substrate 110 may comprise sapphire, silicon carbide, glass, or any other light transmittable material.

[0059] In some embodiments, a laser beam of applicable wavelength may pass through the first substrate 110 and apply to the debonding layer 130. For example, an excimer laser of a wavelength of 308 nm may be used. In some embodiments, an excimer laser of a wavelength of 248 nm beam may be used. However, embodiments of the present disclosure are not so limited. Laser or light of applicable wavelength and suitable energy density may be used. Applicable wavelength and / orenergy density may vary depending on the material of the debonding layer 130, the light transmittance of the first substrate 110 and / or the characteristics of the interface 130I between the first substrate 110 and the debonding layer 130. The first substrate 110 may be light transmittable with respect to the applicable wavelength to the extent that at least a portion of the debonding layer 130 is detachable from the first substrate 110 by light passing through the first substrate 110.

[0060] In some embodiments, stress at the interface 130I between the first substrate 110 and the debonding layer 130 may be increased by laser, such that the main portion of the debonding layer 130 can be detached from the first substrate 110 substantially from the interface 130I. In some embodiments, a small portion of the debonding layer 130 near the first substrate 110 may undergo phase transition and / or chemical change caused by the laser or applicable light, such that the main portion of the debonding layer 130 can be detached from the first substrate 110.

[0061] In some embodiments, the debonding layer 130 comprises polymer, such as polyimide and high temperature endurable glue; germanium dioxide; the like, or combination thereof, and at least a portion of the debonding layer 130 is detachable from the first substrate 110 by applying heat to the debonding layer 130. In some embodiments, the heat may cause phase transition and / or chemical change of the debonding layer 130, such that at least a portion of the debonding layerl30, for example, a portion of the debonding layer 130 attached to the second substrate 120 or a second dielectric layer as described below in greater detail, can be detached from the first substrate 110. In some embodiments, heat may be applied to the debonding layer 130 by heating the semiconductor structure 100 or heating the first substrate 110 by a hot plate. For example, the debonding layer 130 may be heated to a temperature from about 250 °C to 450 °C. Applicable temperature may vary depending on the material of the debonding layer 130. As such, the semiconductor structure 100 may endure high temperature process(es), while the second substrate 120 therein can be detached from the first substrate 110 by applying light or heat to the debonding layer 130, for example, after being through one or more high temperature process(es).

[0062] Referring to FIG. 1B, a semiconductor structure 100A is provided. The semiconductor structure 100A shown in FIG. 1B may be substantially similar to the semiconductor structure 100 shown in FIG. 1A, where like reference numerals indicate like elements. As shown in FIG. 1B, the semiconductor structure 100A further comprises a device metal layer 140a. The second substrate 120 is disposed between the device metal layer 140a and the debonding layer 130. In the embodiment shown in FIG. 1B, the device metal layer 140a may be a Schottky material layer, such that a Schottky contact junction may be formed at the interface 140IS between the device metal layer 140a and the second substrate 120. In some embodiments, the device metal layer 140a may comprise suitable metal, alloy, or conductive metal compound, e.g., platinum (Pt), palladium (Pd),iridium (Ir), ruthenium (Ru), copper (Cu), tungsten (W), or combinations thereof. However, embodiments of the present disclosure are not so limited. The device metal layer 140a may be an unpattemed material layer.

[0063] As shown in FIG. 1B, the second substrate 120 comprises a first semiconductor layer 122a and a second semiconductor layer 124a between the first semiconductor layer 122a and the debonding layer 130. The first semiconductor layer 122a and the second semiconductor layer 124a are different in dopant concentration. For example, both the first semiconductor layer 122a and the second semiconductor layer 124a may be doped with n-type dopant as discussed above, wherein the second semiconductor layer 124a may be of a higher dopant concentration than the first semiconductor layer 122a. Each of the first semiconductor layer 122a and the second semiconductor layer 124a may be uniformly doped as discussed above.

[0064] Referring to FIG. 1C, a semiconductor structure 100B is provided. The semiconductor structure 100B shown in FIG. 1C may be substantially similar to the semiconductor structure 100A shown in FIG. 1B, where like reference numerals indicate like elements. As shown in FIG. 1C, the semiconductor structure 100B further comprises a device metal layer 140b. The second substrate 120 is disposed between the device metal layer 140b and the debonding layer 130. In the embodiment shown in FIG. 1C, the device metal layer 140b may be an Ohmic material layer, such that an Ohmic contact junction may be formed at the interface 140IC between the device metal layer 140b and the second substrate 120. In some embodiments, the device metal layer 140b may comprise suitable metal, alloy, or conductive metal compound, e.g., molybdenum (Mo), silver (Ag), titanium nitride (TiN), or combinations thereof. However, embodiments of the present disclosure are not so limited. The device metal layer 140b may be an unpattemed material layer. In some embodiments, the device metal layer 140b may be omitted.

[0065] As shown in FIG. 1C, the second substrate 120 comprises a first semiconductor layer 122b and a second semiconductor layer 124b between the first semiconductor layer 122b and the debonding layer 130. The first semiconductor layer 122b and the second semiconductor layer 124b are different in dopant concentration. For example, the first semiconductor layer 122b and the second semiconductor layer 124b may be doped with n-type dopant as discussed above, wherein the first semiconductor layer 122b may be of a higher dopant concentration than the second semiconductor layer 124b. Each of the first semiconductor layer 122b and the second semiconductor layer 124b may be uniformly doped as discussed above. However, embodiments of the present disclosure are not so limited.

[0066] Referring to FIG. 1D, a semiconductor structure 100C is provided. The semiconductor structure 100C shown in FIG. 1D may be substantially similar to the semiconductor structure 100Bshown in FIG. 1C, where like reference numerals indicate like elements. As shown in FIG. 1D, the second substrate 120 comprises a first semiconductor layer 122 and a second semiconductor layer 124 between the first semiconductor layer 122 and the debonding layer 130. The first semiconductor layer 122 and the second semiconductor layer 124 are different in conductivitytype of dopant. The first semiconductor layer 122 may be doped with a first conductivity-type of dopant, e.g., n-type dopant as discussed above, and the second semiconductor layer 124 may be doped with a second conductivity-type of dopant, e.g., p-type dopant as discussed above. In some embodiments, the first semiconductor layer 122 may be doped with p-type dopant as discussed above, and the second semiconductor layer 124 may be doped with n-type dopant as discussed above.

[0067] As shown in FIG. 1D, the first semiconductor layer 122 may further comprise a doped layer 122d and a heavily-doped layer 122h between the doped layer 122d and the device metal layer 140b. The heavily-doped layer 122h of the first semiconductor layer 122 may be of a higher dopant concentration than the doped layer 122d of the first semiconductor layer 122. The second semiconductor layer 124 may further comprise a doped layer 124d and a heavily-doped layer 124h between the doped layer 124d and the debonding layer 130. The heavily-doped layer 124h of the second semiconductor layer 124 may be of a higher dopant concentration than the doped layer 124d of the second semiconductor layer 124. Each of the doped layer 122d and the heavily-doped layer 122h of the first semiconductor layer 122 and the doped layer 124d and the heavily-doped layer 124h of the second semiconductor layer 124 may be uniformly doped as discussed above. However, in some other embodiments, the heavily-doped layer 122h of the first semiconductor layer 122 and the heavily-doped layer 124h of the second semiconductor layer 124 may be omitted.

[0068] Referring to FIG. 1E, a semiconductor structure 100D is provided. The semiconductor structure 100D shown in FIG. 1E may be substantially similar to the semiconductor structure 100B shown in FIG. 1C, where like reference numerals indicate like elements. As shown in FIG. 1E, the second substrate 120 comprises a first semiconductor layer 122 and a second semiconductor layer 124 between the first semiconductor layer 122 and the debonding layer 130. The second substrate 120 further comprises a third semiconductor layer 126 between the second semiconductor layer 124 and the debonding layer 130. The first semiconductor layer 122 and the second semiconductor layer 124 are different in conductivity-type of dopant, and the second semiconductor layer 124 and the third semiconductor layer 126 and are different in conductivity-type of dopant. The first semiconductor layer 122 and the third semiconductor layer 126 may be doped with a first conductivity-type of dopant, e.g., n-type dopant as discussed above, and the second semiconductor layer 124 may be doped with a second conductivity-type of dopant, e.g., p-type dopant as discussedabove. In some embodiments, the first semiconductor layer 122 and the third semiconductor layer 126 may be doped with p-type dopant as discussed above, and the second semiconductor layer 124 may be doped with n-type dopant as discussed above. Each of the first semiconductor layer 122, the second semiconductor layer 124, and the third semiconductor layer 126 may be uniformly doped as discussed above.

[0069] Referring to FIG. 1F, a semiconductor structure 100E is provided. The semiconductor structure 100E shown in FIG. 1F may be substantially similar to the semiconductor structure 100B shown in FIG. 1C, where like reference numerals indicate like elements. As shown in FIG. 1F, the second substrate 120 comprises a first semiconductor layer 121a and a second semiconductor layer 123a between the first semiconductor layer 121a and the debonding layer 130. The first semiconductor layer 121a and the second semiconductor layer 123a are different in composition of material. In the embodiment shown in FIG. 1F, the second substrate 120 may further comprise a third semiconductor layer 121b and a fourth semiconductor layer 123b similar to the first semiconductor layer 121a and the second semiconductor layer 123a, respectively, between the second semiconductor layer 123a and the debonding layer 130. The second substrate 120 may further comprise a fifth semiconductor layer 121c and a sixth semiconductor layer 123c similar to the first semiconductor layer 121a and the second semiconductor layer 123 a, respectively, between the fourth semiconductor layer 123b and the debonding layer 130. The first semiconductor layer 121a, the third semiconductor layer 121b, and the fifth semiconductor layer 121c may each comprise a first semiconductor material, e.g., silicon. The second semiconductor layer 123a, the fourth semiconductor layer 123b, and the sixth semiconductor layer 123c may each comprise a second semiconductor material, e.g., silicon-germanium. In some embodiments, the first semiconductor layer 121a, the third semiconductor layer 121b, and the fifth semiconductor layer 121c may each comprise silicon-germanium, and the second semiconductor layer 123a, the fourth semiconductor layer 123b, and the sixth semiconductor layer 123c may each comprise silicon. In the embodiment shown in FIG. 1F, the second substrate 120 comprises six semiconductor layers. However, this is not limiting as other number of semiconductor layers may be implemented.

[0070] Referring to FIG. 1G, a semiconductor structure 100F is provided. The semiconductor structure 100F shown in FIG. 1G maybe substantially similar to the semiconductor structure 100 shown in FIG. 1 A, where like reference numerals indicate like elements. The debonding layer 130 may have a multilayer structure. As shown in FIG. 1G, the debonding layer 130 comprises a buffer layer 132 and a crystalline layer 134. Each of the buffer layer 132 and the crystalline layer 134 comprises compound semiconductor, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AIN), aluminium gallium nitride (AlGaN); polymer, such as polyimide; the like,or combination thereof. As shown in FIG. 1G, the buffer layer 132 of the debonding layer 130 is in contact with the first substrate 110, such that an interface 130I is formed between the buffer layer 132 and the first substrate 110. The buffer layer 132 may be epitaxially formed on the surface of the first substrate 110, and the crystalline layer 134 may be epitaxially formed on the surface of the buffer layer 132. More crystallographic defects may exist in the buffer layer 132 than the crystalline layer 134. In some other embodiments, the crystalline layer 134 may be omitted. In some embodiments, by applying a laser of applicable wavelength to the debonding layer 130, at least a portion of the debonding layer 130 is detachable from the first substrate 110 substantially from the interface 130I, by the laser passing through the first substrate 110. In some embodiments, a dielectric layer may be disposed between the second substrate 120 and the crystalline layer 134 of the debonding layer 130, as described below in greater detail with respect to FIGS. 2A and 2B.

[0071] FIGS. 2A to 2B are schematic diagrams illustrating semiconductor structures according to embodiments of the present disclosure. Referring to FIG. 2A, a semiconductor structure 100G is provided. The semiconductor structure 100G shown in FIG. 2A may be substantially similar to the semiconductor structure 100 shown in FIG. 1A, where like reference numerals indicate like elements. As shown in FIG. 2A, the semiconductor structure 100G further comprises a first dielectric layer 150 between the debonding layer 130 and the first substrate 110. The first dielectric layer 150 may comprise silicon dioxide, silicon nitride, the like, other applicable material, or combinations thereof. However, embodiments of the present disclosure are not so limited.

[0072] As shown in FIG. 2A, the semiconductor structure 100G further comprises a second dielectric layer 160 between the debonding layer 130 and the second substrate 120. The second dielectric layer 160 may comprise silicon oxide, silicon nitride, the like, other applicable material, or combinations thereof. However, embodiments of the present disclosure are not so limited. The second dielectric layer 160 may be in direct contact with the second substrate 120 at a first surface 160S1 of the second dielectric layer 160. The second dielectric layer 160 may be in direct contact with the debonding layer 130 at a second surface 160S2 opposite to the first surface 160S1 of the second dielectric layer 160. In some embodiments, the second dielectric layer 160 may have a thickness in a range from about 5 nm to about 1 μm, for example, from about 5 nm to about 100 nm. The second dielectric layer 160 may be an unpattemed dielectric material layer without wiring structure(s) therein. In other words, no wiring structure(s) exist between the second substrate 120 and the debonding layer 130. However, embodiments of the present disclosure are not so limited.

[0073] Referring to FIG. 2B, a semiconductor structure 100H is provided. The semiconductor structure 100H shown in FIG. 2B may be substantially similar to the semiconductor structure 100G shown in FIG. 2A, where like reference numerals indicate like elements. As shown in FIG. 2B,the second dielectric layer 160 comprises a first layer 162 and a second layer 164. The first layer 162 of the second dielectric layer 160 may be in direct contact with the debonding layer 130, and the second layer 164 of the second dielectric layer 160 may be in direct contact with the second substrate 120. The semiconductor structure 100H may include a bonding interface 160B between the first layer 162 and the second layer 164 of the second dielectric layer 160. Covalent bonds occur at the bonding interface 160B between the first layer 162 and the second layer 164 of the second dielectric layer 160. The first layer 162 and the second layer 164 of the second dielectric layer 160 may each comprise silicon dioxide, silicon nitride, the like, other applicable material, or combinations thereof. The first layer 162 and the second layer 164 of the second dielectric layer 160 may bond the second substrate 120 to the debonding layer 130. However, embodiments of the present disclosure are not so limited. In some other embodiments, the first layer 162 and the second layer 164 of the second dielectric layer 160 may omitted, and the second substrate 120 may be in direct contact with the debonding layer 130.

[0074] FIG. 3 is a schematic diagram illustrating a semiconductor structure according to one embodiment of the present disclosure. Referring to FIG. 3, a semiconductor structure 100I is provided. The semiconductor structure 100I shown in FIG. 3 may be substantially similar to the semiconductor structure 100 shown in FIG. 1A, the semiconductor structure 100A shown in FIG. IB, or the semiconductor structure 100B shown in FIG. 1C, where like reference numerals indicate like elements. As shown in FIG. 3, the semiconductor structure 100I further comprises a bonding metal layer 170. The second substrate 120 is disposed between the bonding metal layer 170 and the debonding layer 130. The semiconductor structure 100I may further comprise a device metal layer 140 similar to the device metal layer 140a shown in FIG. 1B or device metal layer 140b shown in FIG. 1C. The device metal layer 140 may be disposed between the second substrate 120 and the bonding metal layer 170, and the bonding metal layer 170 may be in direct contact with the device metal layer 140.

[0075] The bonding metal layer 170 may comprise suitable metal, conductive metal compound (e.g., metal silicide, metal nitride), or metal alloy, e.g., aluminum (Al), gold (Au), indium (In), palladium (Pd), germanium (Ge), copper (Cu), aluminum-silicon alloy (Al-Si), titanium nitride (TiN), nickel silicide, cobalt silicide, tungsten silicide, chromium silicide, platinum silicide, titanium silicide, molybdenum silicide, palladium silicide, lead-tin alloy (Pb-Sn), aluminum-tin alloy (Al-Sn), gold-tin alloy (Au-Sn), indium-palladium alloy (In-Pd), indium-tin alloy (In-Sn), silver-tin alloy (Ag-Sn), gold-indium alloy (Au-In), copper-tin alloy (Cu-Sn), or combinations thereof. The bonding metal layer 170 may be an unpattemed material layer. The bonding metal layer 170 may facilitate a subsequent metal bonding process that bond the semiconductor structure100I (and the second substrate 120 and the device metal layer 140 therein) to another wafer. As such, devices can be formed from the semiconductor structure 100I and electrically connected to devices in the another wafer, as described below in greater detail.

[0076] FIGS. 4A to 4F are schematic diagrams illustrating intermediate stages in the manufacture of a semiconductor structure according to one embodiment of the present disclosure. Referring to FIG. 4A, a first structure 10A is provided. The first structure 10A comprises a first substrate 110. A debonding layer 130 is formed on the first structure 10A. In the embodiment shown in FIG. 4A, a first dielectric layer 150 is formed by deposition on the first substrate 110. The debonding layer 130 is formed on the first dielectric layer 150 by deposition or applicable method. However, embodiments of the present disclosure are not so limited. In some other embodiments, the debonding layer 130 may comprise single crystalline silicon carbide or single crystalline gallium nitride and may be epitaxially formed on a surface of the first substrate 110 without a first dielectric layer or other material layer therebetween. As shown in FIG. 4A, a first layer 162 of a second dielectric layer 160 may be formed on the debonding layer 130. The first layer 162 of the second dielectric layer 160 may comprise silicon oxide, silicon nitride, the like, other applicable material, or combinations thereof. The first layer 162 of the second dielectric layer 160 may be formed by deposition such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Other details of the first substrate 110, the debonding layer 130, the first dielectric layer 150, and the first layer 162 of the second dielectric layer 160 may be substantially similar to that described above with respect to FIGS. 1A to 2B, and related description is omitted for brevity.

[0077] Referring to FIG. 4B, a second structure 20A is provided. The second structure 20A comprises a semiconductor substrate 200. The semiconductor substrate 200 may be a semiconductor wafer. The semiconductor substrate 200 may comprise semiconductor material, such as silicon, germanium, or silicon germanium, or gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium nitride (GaN). In some embodiments, the semiconductor substrate 200 comprises single crystalline semiconductor material. The semiconductor substrate 200 may be undoped or doped with desired dopant concentration. The semiconductor substrate 200 may be unpatterned. In other words, the semiconductor substrate 200 may be substantially made of intrinsic semiconductor, or the semiconductor substrate 200 may be doped uniformly across an entire layer in region(s) forming usable die area.

[0078] In the embodiment shown in FIG. 4B, the semiconductor substrate 200 comprises an implanted ion layer 220. The implanted ion layer 220 is implanted inside the semiconductor substrate 200 at a certain depth. In one embodiment, hydrogen ions are implanted into thesemiconductor substrate 200 using a dosage of 1x1016ions / cm2to 2x1017ions / cm2at an implantation energy of 50 KeV to 150 KeV. The implanted ion layer 220 may be formed at a depth of about 1 μm to about 2 μm from a first surface 200S1 of the semiconductor substrate 200. These values are merely examples and are not intended to be limiting. Proper implantation voltage can be selected to have the peak of the implanted ions occur at the desired depth.

[0079] Referring to FIG. 4C, a second layer 164 of the second dielectric layer 160 is formed on the semiconductor substrate 200. The second layer 164 of the second dielectric layer 160 and the first layer 162 of the second dielectric layer 160 discussed above with respect to FIG. 4A may be formed before attaching the second structure 20A to the first structure 10A. In some embodiments, the second layer 164 of the second dielectric layer 160 may comprise silicon oxide, silicon nitride, the like, other applicable material, or combinations thereof. The second layer 164 of the second dielectric layer 160 may be formed by thermal oxidation or deposition such as CVD, PVD, or ALD. In some embodiments, the formation of the implanted ion layer 220 may be conducted after the formation of the second layer 164 of the second dielectric layer 160.

[0080] Referring to FIG. 4D, the second structure 20A is flipped and attached to the first structure 10A, such that the debonding layer 130 is disposed between the first substrate 110 and the semiconductor substrate 200. The second structure 20A may be attached to the first structure 10A by the second dielectric layer 160. For example, the second structure 20A may be attached to the first structure 10A through bonding the first layer 162 and the second layer 164 of the second dielectric layer 160 by fusion bonding process(es). The fusion bonding process(es) forms covalent bonds (e.g., Si-O bond) at the bonding interfacel60B between the first layer 162 and the second layer 164 of the second dielectric layer 160. In some embodiments, surfaces of both the first layer 162 and the second layer 164 of the second dielectric layer 160 are cleaned by RCA wafer cleaning process or other suitable process before bonding.

[0081] Referring to FIG. 4E, a portion of the second structure 20A is removed and a second substrate 120 is left on the first substrate 110. Specifically, a portion 200’ of the semiconductor substrate 200 is removed from approximately the implanted ion layer 220. In some embodiments, the portion 200’ of the semiconductor substrate 200 may be removed by heating the semiconductor substrate 200 and the implanted ion layer 220 therein. In some embodiments, the portion 200’ of the semiconductor substrate 200 may be removed by other methods, as long as a breaking portion of the semiconductor substrate 200 has been sufficiently weakened by previous ion implantation and subsequent processing, such as applying mechanical pressure to the semiconductor substrate 200 or dipping and quenching the semiconductor substrate 200 in liquid nitrogen. The removed portion 200’ of the semiconductor substrate 200 can be recycled and can be used for manufacturinganother second substrate 20A. In some embodiments, the exposed surface of the second substrate 120 after removal may be rough and may be planarized by chemical mechanical polishing (CMP), etching, and / or applicable process(es).

[0082] In some other embodiments, a second structure similar to the second structure 20A shown in FIG. 4B may not include an implanted ion layer 220, and a portion of the semiconductor substrate 200 may be removed, e.g., by grinding and / or suitable etching process, such that a second substrate similar to that shown in FIG. 4E can be left on the first substrate.

[0083] In the embodiment shown in FIG. 4E, the second substrate 120 comprises semiconductor material. The second substrate 120 may have a thickness in a range from about 5 nm to about 10 μm. In some embodiments, the second substrate 120 may have a thickness in a range from about 5 nm to about 5 μm, or from about 5 nm to about 200 nm. The thickness of the second substrate 120 may be substantially based on and / or controlled by the implanted depth of the implanted ion layer 220 and subsequent processing. A second substrate 120 with desired thickness, which may be determined by the technology nodes of the manufacturing process applied or will be applied to the second substrate 120, may be provided. As discussed above, the first substrate 110 and the debonding layer 130 are formed by selective materials and formation methods such that at least a portion of the debonding layer is detachable from the first substrate 110 by applying light or heat to the debonding layer 130.

[0084] The second substrate 120 shown in FIG. 4E may be doped after removing the portion 200’ of the semiconductor substrate 200. Dopant activation may be performed. In some embodiments, additional semiconductor layer may be epitaxially formed on the second substrate 120. The second substrate 120 may be unpattemed as discussed above.

[0085] Referring to FIG. 4F, a device metal layer 140 is formed on the second substrate 120 by deposition or other applicable method. Heat treatment may be conducted if necessary. The device metal layer 140 is formed after removing the portion of the second structure 20A. The device metal layer 140 may be formed directly on the planarized surface of the second substrate 120. Other details of the device metal layer 140 may be substantially similar to that described above with respect to FIGS. 1A to 3. In some embodiments, the device metal layer 140 may be omitted.

[0086] Referring to FIG. 4F, a bonding metal layer 170 is formed on the second substrate 120 by deposition or other applicable method. Heat treatment may be conducted if necessary. The bonding metal layer 170 is formed after removing the portion of the second structure 20A. The bonding metal layer 170 may be formed directly on the top surface of the device metal layer 140. Other details of the bonding metal layer 170 may be substantially similar to that described abovewith respect to FIG. 3. In some embodiments, the bonding metal layer 170 may be omitted. In the embodiments where the semiconductor structure comprises a device metal layer and / or a bonding metal layer, high temperature process, such as dopant activation, may be conducted before formation of the device metal layer 140 and / or the bonding metal layer 170. As such, semiconductor structures similar to that discussed above with respect to FIGS. 1A to 3 may be formed.

[0087] FIGS. 5A to 5B are schematic diagrams illustrating intermediate stages in the manufacture of a semiconductor structure according to one embodiment of the present disclosure. Referring to FIG. 5A, a second structure 20B is provided . The second structure 20B shown in FIG. 5A may be substantially similar to the second structure 20A shown in FIG. 4B, where like reference numerals indicate like elements. Specifically, the second structure 20B comprises a semiconductor substrate 200B. The semiconductor substrate 200B comprises a first semiconductor layer 202 and a second semiconductor layer 204. The first semiconductor layer 202 may be doped with a first conductivity-type of dopant, e.g., n-type dopant as discussed above, and the second semiconductor layer 204 may be doped with a second conductivity-type of dopant, e.g., p-type dopant as discussed above. In some embodiments, the first semiconductor layer 202 may be doped with p-type dopant as discussed above, and the second semiconductor layer 204 may be doped with n-type dopant as discussed above. In the embodiment shown in FIG. 5A, the first semiconductor layer 202 may further comprise a doped layer 202d and a heavily-doped layer 202h. The heavily-doped layer 202h of the first semiconductor layer 202 may be of a higher dopant concentration than the doped layer 202d of the first semiconductor layer 202. The second semiconductor layer 204 may further comprise a doped layer 204d and a heavily-doped layer 204h. The heavily-doped layer 204h of the second semiconductor layer 204 may be of a higher dopant concentration than the doped layer 204d of the second semiconductor layer 204. The doped layer 202d and the heavily-doped layer 202h of the first semiconductor layer 202 and the doped layer 204d and the heavily-doped layer 204h of the second semiconductor layer 204 may be formed by ion implantation and / or epitaxial growth. However, embodiments of the present disclosure are not so limited. In some other embodiments, the heavily-doped layer 202h of the first semiconductor layer 202 and the heavily-doped layer 204h of the second semiconductor layer 204 may be omitted. In some other embodiments, the implanted ion layer 220 is formed before formation of the first semiconductor layer 202 and the second semiconductor layer 204.

[0088] Referring to FIG. 5B, a semiconductor structure 100J is formed. The semiconductor structure 100J may be substantially similar to the semiconductor structures discussed above with respect to FIGS. 1A to 3, where like reference numerals indicate like elements. Processes similarto that described above with respect to FIGS. 4C to 4F may be performed. Specifically, after removing a portion of the semiconductor substrate 200B, a second substrate 120 is left. As shown in FIG. 5B, the second substrate 120 comprises a first semiconductor layer 122 and a second semiconductor layer 124. The first semiconductor layer 122 may further comprise a doped layer 122d and a heavily-doped layer 122h. The second semiconductor layer 124 may further comprise a doped layer 124d and a heavily-doped layer 124h. The doped layer 122d and the heavily-doped layer 122h of the first semiconductor layer 122 may be formed from the doped layer 202d and the heavily-doped layer 202h of the first semiconductor layer 202, respectively. The doped layer 124d and the heavily-doped layer 124h of the second semiconductor layer 124 may be formed from the doped layer 204d and the heavily-doped layer 204h of the second semiconductor layer 204, respectively. Each of the doped layer 122d and the heavily-doped layer 122h of the first semiconductor layer 122 and the doped layer 124d and the heavily-doped layer 124h of the second semiconductor layer 124 may be unpattemed. The first semiconductor layer 122 may be exposed by chemical mechanical polishing (CMP), etching, and / or applicable processes) before formation of the device metal layer 140 and / or the bonding metal layer 170 (if any). Dopant activation may be performed to the semiconductor structure 100J. In the embodiments where the semiconductor structure 100J comprises a device metal layer 140 and / or a bonding metal layer 170, dopant activation may be conducted before formation of the device metal layer 140 and / or the bonding metal layer 170.

[0089] In some other embodiments, a second structure similar to the second structure 20B shown in FIG. 5A may not include an implanted ion layer 220, and a portion of the semiconductor substrate 200B may be removed, e.g., by grinding and / or suitable etching process, such that a second substrate 120 similar to that shown in FIG. 5B can be left on the first substrate 110. As such, semiconductor structures similar to that discussed above with respect to FIGS. 1 A to 3 may be formed.

[0090] FIGS. 6A to 6D are schematic diagrams illustrating intermediate stages in the manufacture of a semiconductor structure according to one embodiment of the present disclosure. Referring to FIG. 6A, a second structure 20C is provided. The second structure 20C shown in FIG. 6A may be substantially similar to the second structure 20B shown in FIG. 5A, where like reference numerals indicate like elements. As shown in FIG. 6A, the second structure 20C comprises a semiconductor substrate 210, a third substrate 230 and an etch stop layer 240 between the third substrate 230 and the semiconductor substrate 210. In some embodiments, the third substrate 230 may comprise single crystalline semiconductor material. The etch stop layer 240may comprise silicon germanium and may be formed by epitaxial growth or suitable deposition process.

[0091] The semiconductor substrate 210 comprises semiconductor material, such as silicon, germanium, or silicon germanium, or gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium nitride (GaN). In some embodiments, the semiconductor substrate 210 comprises single crystalline semiconductor material. The semiconductor substrate 210 may comprise a first semiconductor layer 212 and a second semiconductor layer 214. The first semiconductor layer 212 may be doped with a first conductivity-type of dopant, e.g. , n-type dopant as discussed above, and the second semiconductor layer 214 may be doped with a second conductivity-type of dopant, e.g., p-type dopant as discussed above. In some embodiments, the first semiconductor layer 212 may be doped with p-type dopant as discussed above, and the second semiconductor layer 214 may be doped with n-type dopant as discussed above. The first semiconductor layer 212 may further comprise a doped layer 212d and a heavily-doped layer 212h. The second semiconductor layer 214 may further comprise a doped layer 214d and a heavily- doped layer 214h. The heavily-doped layer 212h of the first semiconductor layer 212 may be of a higher dopant concentration than the doped layer 212d of the first semiconductor layer 212. The heavily-doped layer 214h of the second semiconductor layer 214 may be of a higher dopant concentration than the doped layer 214d of the second semiconductor layer 214. Each of the doped layer 212d and the heavily-doped layer 212h of the first semiconductor layer 212 and the doped layer 214d and the heavily-doped layer 214h of the second semiconductor layer 214 may be unpattemed. The semiconductor substrate 210, e.g., the doped layer 212d and the heavily-doped layer 212h of the first semiconductor layer 212 and the doped layer 214d and the heavily-doped layer 214h of the second semiconductor layer 214, may be formed by epitaxial growth, suitable deposition process, and / or ion implantation. The semiconductor substrate 210 formed thereby may be a thin semiconductor layer having a thickness in a range from about 5 nm to about 10 μm, from about 5 nm to about 5 μm, or from about 5 nm to about 200 nm. However, embodiments of the present disclosure are not so limited. In some other embodiments, the semiconductor substrate 210 may include more or less sublayers.

[0092] Referring to FIG. 6B, the second structure 20C is flipped and attached to the first structure 10A such that the debonding layer 130 is disposed between the first substrate 110 and the semiconductor substrate 210. The second structure 20C may be attached to the first structure 10A by the second dielectric layer 160. Bonding process(es) similar to that described above with respect to FIG. 4D may be performed.

[0093] Referring to FIG. 6C, the third substrate 230 is removed. The third substrate 230 may be removed by suitable process(es) such as grinding, chemical mechanical polishing (CMP), and / or etching process. In one embodiment, the third substrate 230 is removed by grinding and / or CMP process, and the remained portion of the third substrate 230 is removed by suitable etching process. In some embodiments, an implanted ion layer similar to the implanted ion layer 220 discussed above may be formed in a way that the majority of ions are disposed in the etch stop layer 240. The third substrate 230 may be removed by process(es) similar to that described above with respect to FIG. 4E. The etch stop layer 240 may be selected to have a lower etch rate than the third substrate 230 under suitable etch conditions. The etch stop layer 240 is exposed after removing the third substrate 230.

[0094] Referring to FIG. 6D, the etch stop layer 240 is removed. The etch stop layer 240 may be removed by suitable etching process to expose the semiconductor substrate 210. As such, a second substrate 120 is left on the first substrate 110. The etch stop layer 240 may be used to monitor the etch endpoint of the third substrate 230 and may provide a top surface of the second substrate 120 with greater planarity. The second substrate 120 may be substantially similar to that described above with respect to FIG. 5B, and the related description is omitted for brevity. As such, semiconductor structures similar to that discussed above with respect to FIGS. 1A to 3 may be formed. In some embodiments, process(es) discussed above with respect to FIGS. 4F and 5B may be performed.

[0095] FIG. 7 is a schematic diagram illustrating an intermediate stage in the manufacture of a semiconductor structure according to one embodiment of the present disclosure. Referring to FIG. 7, a second structure 20D is provided. The second structure 20D shown in FIG. 7 may be substantially similar to the second structure 20C shown in FIG. 6A, where like reference numerals indicate like elements. Specifically, the second structure 20D further comprises an oxide layer 250 between the third substrate 230 and the etch stop layer 240. The oxide layer 250 may comprise silicon oxide or other applicable material. In some embodiments, the second structure 20D may be formed from a “SEOI substrate” comprising a semiconductor layer, an etch stop layer, and an oxide layer sequentially stacked on a base substrate. Details of structures and manufacturing methods of the SEOI substrates are as described in US application Ser. No. 18 / 857,838, the contents of which are incorporated herein by reference. The doped layer 212d and the heavily- doped layer 212h of the first semiconductor layer 212 and the doped layer 214d and the heavily- doped layer 214h of the second semiconductor layer 214 may be formed by dopant implantation, epitaxial growth and / or suitable deposition process.

[0096] Semiconductor structures similar to that discussed above with respect to FIGS. 1A to 3 may be formed from the second structure 20D. Process(es) discussed above with respect to FIGS. 4A to 4F, FIGS. 5A to 5B, and FIGS. 6A to 6D may be performed. In the present embodiment, the oxide layer 250 may be removed by suitable etching process, and the etch stop layer 240 is exposed after removing the oxide layer 250. The etch stop layer 240 is then removed to expose the semiconductor substrate 210.

[0097] FIGS. 8 A to 8B are schematic diagrams illustrating intermediate stages in the manufacture of a semiconductor structure according to one embodiment of the present disclosure. Referring to FIG. 8 A, a first structure 10A is provided, and a debonding layer 130 is formed on the first structure 10A. Details of the first structure 10A and the debonding layer 130 may be substantially similar to that described above with respect to FIG. 4A, and related description is omitted for brevity. In the embodiment shown in FIGS. 8A to 8C, the formation of a dielectric layer may be omitted.

[0098] Referring to FIG. 8B, a semiconductor substrate 210 is formed. The semiconductor substrate 210 may be substantially similar to that described above with respect to FIG. 6A, where like reference numerals indicate like elements. In the present embodiment, the semiconductor substrate 210 may comprise poly crystalline semiconductor material. The heavily-doped layer 212h of the first semiconductor layer 212, the doped layer 212d of the first semiconductor layer 212, the doped layer 214d of the second semiconductor layer 214, and the heavily-doped layer 214h of the second semiconductor layer 214 may be sequentially formed by suitable deposition process and / or dopant implantation. In some other embodiments, the semiconductor substrate 210 may include more or less sublayers. As such, semiconductor structures similar to that discussed above with respect to FIGS. 1A to 3 may be formed.

[0099] FIGS. 9 A to 9G are schematic diagrams illustrating intermediate stages in the manufacture of a memory device according to one embodiment of the present disclosure. Referring to FIG. 9A, a base substrate 300 is provided. The base substrate 300 may comprise a wiring layer 310. The wring layer 310 may comprise conductive lines and / or contacts. In some embodiments, the wiring layer 310 comprises word lines, bit lines, or the like. In some embodiments, the wiring layer 310 may comprise a plurality of conductive sublayers. The wiring layer 310 may comprise Pt, Pd, Ir, Ru, Cu, W, some other suitable material(s), or a combination of the foregoing. The wiring layer 310 may be formed by any suitable process (e.g., photolithography and etching process, damascene process, dual damascene process, or the like). The wiring layer 310 may be formed in a dielectric layer 311 using a damascene or dual damascene process or any suitable method.

[0100] The base substrate 300 may be a “semifinished product” wafer. The base substrate 300 may comprise semiconductor material, such as, silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium nitride (GaN), or diamond. In some embodiments, the base substrate 300 may comprise single crystalline semiconductor material. In some embodiments, the base substrate 300 may comprise a plurality of electronic devices, such as capacitors, resistors, diodes, transistors, and / or the like. In some embodiments, the plurality of electronic devices include one or more variable resistors, wherein the variable resistors may each comprise a magnetic tunnel junction (MTJ) structure, a phase-change material, a variable resistance material, or the like, such that the variable resistors may function as memory units. In some embodiments, the plurality of electronic devices include control device(s), word line selection device(s), and / or bit line selection device(s).

[0101] The wiring layer 310 may be disposed over the plurality of electronic devices. The wiring layer 310 may be electrically connected to and may provide wiring or contact for the plurality of electronic devices in the base substrate 300. The base substrate 300 may further comprise one or more wiring layer(s) electrically connected to the plurality of electronic devices. The plurality of electronic devices may be disposed in a plurality of device layers. In some embodiments, the plurality of device layers may be incorporated into or function as a processor such as a central processing unit (CPU), graphics processing unit (GPU), application-specific integrated circuit (ASIC), or the like. In some embodiments, the base substrate 300 may further comprise an alignment mark. The conductive features of the wiring layer 310 and / or other wiring layers in the base substrate 300, the plurality of electronic devices, and / or electronic devices and / or conductive features subsequently formed, as described below in greater details, may be fabricated according to the alignment mark (not shown). In some embodiments, the alignment mark may include a plurality of marking layers. In some embodiments, the base substrate 300 may further comprise a handle wafer (not shown), which may be made of glass, polysilicon, or ceramic.

[0102] As shown in FIG. 9A, a first bonding metal layer 370 is formed on the base substrate 300 over the wiring layer 310. In some embodiments, the first bonding metal layer 370 may be formed on a top surface 300T of the base substrate 300 and in contact with the wiring layer 310. The first bonding metal layer 370 may comprise suitable metal, conductive metal compound (e.g., metal silicide, metal nitride), or metal alloy, e.g., aluminum (Al), gold (Au), indium (In), palladium (Pd), germanium (Ge), copper (Cu), aluminum-silicon alloy (Al-Si), titanium nitride (TiN), nickel silicide, cobalt silicide, tungsten silicide, chromium silicide, platinum silicide, titanium silicide, molybdenum silicide, palladium silicide, lead-tin alloy (Pb-Sn), aluminum-tin alloy (Al-Sn), goldtin alloy (Au-Sn), indium-palladium alloy (In-Pd), indium-tin alloy (In-Sn), silver-tin alloy (Ag-Sn), gold-indium alloy (Au-In), copper-tin alloy (Cu-Sn), or combinations thereof. The first bonding metal layer 370 may have a thickness in a range from about 5 nm and about 500 nm. These values are merely examples and are not intended to be limiting. The first bonding metal layer 370 may be formed by deposition, such as CVD, PVD, or ALD, sputtering, evaporation, or electroplating. In some embodiments, the first bonding metal layer 370 may have a multilayer structure. In some embodiments, a base substrate may already include a first bonding metal layer.

[0103] Referring to FIG. 9B, a semiconductor structure 100K is provided. The semiconductor structure 100K may be substantially similar to the semiconductor structures discussed above with respect to FIGS. 1A to 3, where tike reference numerals indicate like elements. Specifically, the semiconductor structure 100K comprises a first substrate 110, a second substrate 120 on the first substrate 110, and a debonding layer 130 between the first substrate 110 and the second substrate 120. The second substrate 120 comprises semiconductor material. In some embodiments, the second substrate 120 comprises single crystalline semiconductor material. The second substrate 120 may have a thickness in a range from about 5 nm to about 10 μm. In the embodiment shown in FIG. 9B, the second substrate 120 may comprise a doped layer 122d and a heavily-doped layer 122h of the first semiconductor layer 122 and a doped layer 124d and a heavily-doped layer 124h of a second semiconductor layer 124. Each of the doped layer 122d and the heavily-doped layer 122h of the first semiconductor layer 122 and the doped layer 124d and the heavily-doped layer 124h of the second semiconductor layer 124 may be unpattemed. In some embodiments, the heavily-doped layer 122h of the first semiconductor layer 122 and the heavily-doped layer 124h of the second semiconductor layer 124 may be omitted. Related details of the first substrate 110, the second substrate 120, and the debonding layer 130 described above may apply here if applicable.

[0104] As shown in FIG. 9B, the semiconductor structure 100K may further comprise a device metal layer 140. The device metal layer 140 may be in direct contact with the second substrate 120 and an ohmic contact junction may be formed at the interface between the device metal layer 140 and the second substrate 120. Related details of the device metal layer 140, the device metal layer 140a, and / or device metal layer 140b described above with respect to FIGS. 1A to 3 may apply here if applicable. As shown in FIG. 9B, the semiconductor structure 100K may further comprise a first dielectric layer 150 between the debonding layer 130 and the first substrate 110. The semiconductor structure 100K may further comprise a second dielectric layer 160 between the debonding layer 130 and the second substrate 120. Related details of the first dielectric layer 150 and the second dielectric layer 160 described above with respect to FIGS. 1A to 3 may apply hereif applicable. The semiconductor structure 100K may be formed by processes substantially similar to that discussed above with respect to FIGS. 4A to 8B.

[0105] A second bonding metal layer 170 is formed on the semiconductor structure 100K over the second substrate 120. In the embodiment shown in FIG. 9B, the second bonding metal layer 170 is formed on and in contact with the device metal layer 140. In the embodiment where the device metal layer can be omitted, the second bonding metal layer 170 may be formed on and in contact with the second substrate 120. The second bonding metal layer 170 is formed before bonding the semiconductor structure 100K and the base substrate 300. The second bonding metal layer 170 may have a thickness in a range from about 5 nm to about 500 nm. These values are merely examples and are not intended to be limiting. The second bonding metal layer 170 may comprise suitable metal, conductive metal compound (e.g., metal silicide, metal nitride), or metal alloy, as discussed above. The second bonding metal layer 170 may be formed by deposition, such as CVD, PVD, or ALD, sputtering, evaporation, or electroplating. In some embodiments, the second bonding metal layer 170 may have a multilayer structure. In some embodiments, a semiconductor structure may already include a second bonding metal layer. Related details of the bonding metal layer 170 described above may apply here if applicable. The second bonding metal layer 170 may comprise composition of material the same as or similar to that of the first bonding metal layer 370. The composition of material and structure of the first bonding metal layer 370 and the second bonding metal layer 170 may be adjusted to achieve a desired bonding strength and / or device properties.

[0106] As shown in FIG. 9B, the semiconductor structure 100K and the base substrate 300 are bonded to form a bonded structure 400. The semiconductor structure 100K and the base substrate300 may be bonded by bonding the first bonding metal layer 370 and the second bonding metal layer 170. The first bonding metal layer 370 and the second bonding metal layer 170 may be bonded by thermal compression bonding, eutectic bonding, or reactive bonding. In some embodiments, the bonding of the first bonding metal layer 370 and the second bonding metal layer 170 may be direct bonding. For example, the first bonding metal layer 370 and the second bonding metal layer 170 may be bonded by thermal compression bonding process, such as diffusion bonding. In some embodiments, the surfaces of both the first bonding metal layer 370 and the second bonding metal layer 170 are cleaned by conventional cleaning techniques such as dry etching and plasma surface treatment before bonding. In one embodiment, external pressure is applied on the stacked base substrate 300, first bonding metal layer 370, second bonding metal layer 170, and semiconductor structure 100K during a thermal process. In some embodiments, the atoms at the surfaces of the first bonding metal layer 370 and the second bonding metal layer 170may inter-diffuse, so that metal bonds may be formed at a metal bonding interface 4021 to form a bonded metal layer 402. In one embodiment, the thickness of the bonded metal layer 402 may be in a range between 5 nm and 1000 nm. These values are merely examples and are not intended to be limiting. In some embodiments, the first bonding metal layer 370 and / or the second bonding metal layer 170 may include a diffusion barrier layer (not shown), which may include titanium, tungsten, tantalum, and / or nitrides thereof. The diffusion barrier layer may be in contact with the second substrate 120 to prevent metal diffusion from the bonded metal layer to the second substrate 120.

[0107] As shown in FIG. 9B, the first bonding metal layer 370 is unpattemed. The second bonding metal layer 170 may also be unpattemed. The metal bonding interface 4021 between the first bonding metal layer 370 and the second bonding metal layer 170 may extend continuously without a metal-dielectric interface therebetween. The metal bonding interface 4021 may extend continuously from a first point P1 over a first metal portion 312 of the wiring layer 310 to a second point P2 over the second metal portion 314 of the wiring layer 310. In some embodiments, the metal bonding interface 4021 may extend continuously substantially throughout a usable die area. By process(es) described herein, the connection between the bonding metal layers can be assured even when the feature size is small, and misalignment problem of wafer-wafer bonding may be avoided. The bonding between the semiconductor structure 100K and the base substrate 300 may be formed with desirable bonding strength and may be “self-aligned”, as described below in greater details. Thermal mismatch occurred at a metal-dielectric interface, which would lower the bonding strength and reliability, may also be avoided. Moreover, the greater coefficient of thermal expansion (CTE) of the metal portions, such as the first metal portion 312 and the second metal portion 314 of the wiring layer 310, compared to the dielectric layer 311, may generate larger pressure on the first bonding metal layer 370 and the second bonding metal layer 170 during bonding process. As such, a greater bonding strength may be achieved for the portions overlapping those metal portions, which may be remained after subsequent patterning process(es).

[0108] Referring to FIG. 9C, at least a portion of the debonding layer 130 is detached from the first substrate 110 by applying light or heat to the debonding layer 130. After the detaching process, a remained portion of the debonding layer 130’ may be left on the second substrate 120.

[0109] In some embodiments, the debonding layer 130 may comprise compound semiconductor or polymer as discussed above. The at least a portion of the debonding layer 130 may be detached from the first substrate 110 by exposing the debonding layer 130 to light 50 passing through the first substrate 110. For example, a UV laser 50 of applicable wavelength, e.g., 248 mn or 308 nm, may pass through the first substrate 110 and apply to the debonding layer 130. In someembodiments, a laser 50 may scan through regions of the first substrate 110. As discussed above, in some embodiments, stress at the interface between the first substrate 110 and the debonding layer 130 may be increased by laser 50, such that the main portion of the debonding layer 130 can be detached from the first substrate 110. In some embodiments, a small portion of the debonding layer 130 near the first substrate 110 may undergo chemical change and / or phase transition caused by the laser or applicable light 50, such that the main portion of the debonding layer 130 can be detached from the first substrate 110. In the embodiment where the semiconductor structure 100K comprises a first dielectric layer 150 between the debonding layer 130 and the first substrate 110, a laser or light 50 may pass through the first substrate 110 and the first dielectric layer 150 and apply to the debonding layer 130. The laser or light 50 may increase stress at the interface between the first dielectric layer 150 and the debonding layer 130 or may cause phase transition and / or chemical change occurred at a portion of the debonding layer 130 near the first dielectric layer 150.

[0110] In some embodiments, the debonding layer 130 comprises polymer as discussed above or germanium dioxide. The at least a portion of the debonding layer 130 may be detached from the first substrate 110 by applying heat to the debonding layer 130. For example, the bonded structure 400 may be heated. In some embodiments, the heat may cause phase transition and / or chemical change of the debonding layer 130, such that at least a portion of the debonding layer 130 can be detached from the first substrate 110. Related details of the first substrate 110, the debonding layer 130, and the first dielectric layer 150 described above may apply here if applicable.

[0111] Referring to FIG. 9D, the remained portion of the debonding layer 130’ is removed. In the embodiment where the semiconductor structure 100K comprises a second dielectric layer 160 between the debonding layer 130 and the second substrate 120, the second dielectric layer 160 may be removed after detaching the at least a portion of the debonding layer 130 from the first substrate 110. Suitable etching process may be performed to remove the remained portion of the debonding layer 130’ and the second dielectric layer 160. By including the second dielectric layer 160, an exposed surface 120E of the second substrate 120 exposed after removing the second dielectric layer 160 may have a better flatness. A better flatness of the exposed surface 120E may decrease thickness variation of the second substrate 120, especially when the second substrate 120 is a thin semiconductor layer. As such, electronic devices formed therefrom, as described below with greater detail, may have less defects and more uniform electrical characteristics. Yield rate may be improved. With disposition of the second dielectric layer 160, complete removal of the remained portion of the debonding layer 130’ can be ensured. In the present embodiment, the second dielectric layer 160 may be removed before patterning the second substrate 120. However,embodiments of the present disclosure are not so limited. In some embodiments, a protection layer (not shown) may be formed on the second substrate 120 to avoid damage to the semiconductor layers and / or semiconductor stacks during subsequent process(es), e.g., CMP process for formation of the dielectric isolation 501 described below wdth respect to FIGS. 9F and 9G. The protection layer may comprise silicon nitride (SiN) and / or the like.

[0112] In the embodiment where the semiconductor structure 100K comprises a first dielectric layer 150 between the debonding layer 130 and the first substrate 110, the first dielectric layer 150 may be removed after detaching the at least a portion of the debonding layer 130 from the first substrate 110. The first dielectric layer 150 may be removed by suitable etching process. With disposition of the first dielectric layer 150, the first substrate 110 can be recycled and can be used for manufacturing of another semiconductor structure after removing the first dielectric layer 150.

[0113] Referring to FIG. 9E, the second substrate 120 is patterned. Suitable process(es), such as photolithography and etching process, may be performed. Layers of the second substrate 120 may be defined by the same mask. In some embodiments, the patterning of the second substrate 120 may be performed according to the alignment mark disposed in the base substrate 300 as discussed above. The device metal layer 140 is patterned. In some embodiments, the device metal layer 140 and / or the second bonding metal layer 170 may function as an etch stop layer in the etching process for patterning the second substrate 120. The patterning of the second substrate 120 and the formation of the vertical devices may be performed after bonding the first bonding metal layer 370 and the second bonding metal layer 170 as discussed above with respect to FIG. 9B.

[0114] As shown in FIG. 9E, the bonded metal layer 402, i.e., the bonded first bonding metal layer 370 and second bonding metal layer 170, is patterned. Suitable process(es), such as photolithography and etching process, may be performed. For example, dry etching process (e.g., reactive-ion etching and inductively coupled plasma) can be used. In the embodiments where the bonded metal layer 402 comprises aluminum (e.g., aluminum alloy), dry etching using a mixed gas of boron trichloride (BCl3), chlorine (Cl2), and ammonia (NH3) as an etching gas may be performed. In the embodiments where the bonded metal layer 402 comprises titanium nitride (TiN), dry etching using a mixed gas of carbon tetrafluoride (CF4), BCl3, and nitrogen (N2), or argon (Ar) and Cl2as an etching gas may be performed. The present disclosure is not limited thereto. In some embodiments, the dielectric layer 311 may function as an etch stop layer in the etching process for patterning the bonded metal layer 402. In some embodiments, the patterning of the first bonding metal layer 370 and the second bonding metal layer 170 may be performed according to the alignment mark disposed in the base substrate 300 as discussed above. As such, the devices formed by process(es) disclosed herein may be aligned to and electrically connected to the conductiveportion of the wiring layer 310. In other words, the devices may be “self-aligned”. The patterning of the first bonding metal layer 370 and the second bonding metal layer 170 may be performed after bonding the first bonding metal layer 370 and the second bonding metal layer 170 as discussed above with respect to FIG. 9B.

[0115] As shown in FIG. 9E, trenches 405 extending through the second substrate 120, the device metal layer 140, and the bonded metal layer 402 are formed after the patterning process(es). A plurality of island-shaped vertical stacks 404a, 404b, 404c may be defined by the trenches 405. A plurality of devices (e.g., diodes) or structure for subsequent formation of a plurality of devices may be formed.

[0116] Referring to FIGS . 9F and 9G, a plurality of vertical devices 510a, 510b, 510c, 510d, 510e are formed. FIG. 9G shows a cross-sectional view of the structure shown in FIG. 9F along line A- A’. In the present embodiment, the vertical devices 510a, 510b, 510c, 510d, 510e may be vertical P-N diodes. However, embodiments of the present disclosure are not so limited. In some other embodiments, vertical schottky diodes, vertical transistor, and / or the like may be formed by processes similar to that described with respect to FIGS. 9A to 9G and FIGS. 10A to 10B. The vertical device 510a may comprise a first doped region 512a and a second doped region 514a. Each of the first doped region 512a and the second doped region 514a may further include a heavily-doped region. The second doped region 514a is disposed over and in contact with the first doped region 512a. The first doped region 512a may be doped with a first conductivity-type of dopant as described above, and the second doped region 514a may be doped with a second conductivity-type of dopant as described above. The vertical device 510a may further comprise a first ohmic contact 516a in contact with the first doped region 512a and a second ohmic contact 518a in contact with the second doped region 514a.

[0117] The first doped region 512a and the second doped region 514a of the vertical devices 510a may be formed from the first semiconductor layer 122 and the second semiconductor layer 124, respectively, by patterning the second substrate 120 as discussed above. The first ohmic contact 516a of the vertical devices 510a may be formed from the device metal layer 140 by patterning the device metal layer 140 as discussed above. As shown in FIG. 9F and 9G, a dielectric isolation 501 is formed. The dielectric isolation 501 may fill the trenches 405 and surround the plurality of vertical stacks 404a, 404b, 404c. The dielectric isolation 501 may include one or more stacked dielectric layers. The dielectric isolation 501 may comprise dielectric material such as silicon oxide, silicon oxynitride, low dielectric constant (low-k) materials, a combination thereof, and / or other applicable material. The dielectric isolation 501 may be formed by deposition such as CVD, PVD, or ALD, spinning, or any suitable method. The second ohmic contact 518a of the verticaldevices 510a may be formed in the dielectric isolation 501 using a damascene or dual damascene process or any suitable method. The vertical devices 510b, 510c, 510d, 510e may be substantially similar to the vertical device 510a and may be formed in the same process as the vertical device 510a, where like reference numerals indicate like elements.

[0118] As shown in FIGS. 9F and 9G, a plurality of metal bonding contacts 520a, 520b, 520c, 520d, 520e may also be formed. The metal bonding contacts 520a, 520b, 520c, 520d, 520e may be formed from the first bonding metal layer 370 and the second bonding metal layer 170 by patterning the bonded first bonding metal layer 370 and second bonding metal layer 170 (the bonded metal layer 402) as discussed above. The metal bonding contacts 520a, 520b, 520c, 520d, 520e may provide electrical contact for the vertical devices 510a, 510b, 510c, 510d, 510e, respectively. For example, the vertical device 510a can be electrically connected to the first metal portion 312 of the wiring layer 310 and electronic device(s) in the base substrate 300 through the metal bonding contact 520a. The dielectric isolation 501 may surround each of the vertical devices 510a, 510b, 510c, 510d, 510e, such that the vertical devices 510a, 510b, 510c, 510d, 510e may be laterally isolated from each other by the dielectric isolation 501. The dielectric isolation 501 may surround each of the metal bonding contacts 520a, 520b, 520c, 520d, 520e, such that the metal bonding contacts 520a, 520b, 520c, 520d, 520e may be laterally isolated from each other by the dielectric isolation 501. In some embodiments, a conformal diffusion barrier layer (not shown) can be formed surrounding at least a portion of the vertical devices and the contact structures before the formation of the dielectric isolation 501. The conformal diffusion barrier layer may include titanium, tungsten, tantalum, and nitrides thereof.

[0119] One or more wiring layer(s) may be formed over the dielectric isolation 501. The one or more wiring layer(s) may be electrically connected to the vertical devices 510a, 510b, 510c, 510d, 510e. The one or more wiring layer(s) may function as bit lines, read lines, word lines, and / or the like for memory device(s). In some embodiments, a plurality of memory units (e.g., variable resistors as discussed above) may be formed over the dielectric isolation 501 and electrically connected to one or more respective vertical device. In some embodiments, a plurality of memory units are disposed in the base substrate 300, and the vertical devices 510a, 510b, 510c, 510d, 510e are formed electrically connected to the plurality of memory units, e.g., a respective memory unit. As such, a memory device can be manufactured. Various memory devices may be formed by the process herein. For example, memory devices shown in FIGS. 11 to 15B may be formed by process described with respect to FIGS. 9A to 9G and / or FIGS. 10A to 10B. However, embodiments of the present disclosure are not so limited. Processes) similar to that described with respect to FIGS.9A to 9G and / or FIGS. 10A to 10B may be performed on semiconductor structures shown in FIGS.1A to 3 to form various vertical devices for various memory devices if applicable.

[0120] As such, vertical devices comprising single crystalline semiconductor material(s) may be formed on the base substrate 300. Such devices may have better performance than those made of polycrystalline and / or amorphous semiconductor material. As such, memory devices with smaller cell size and better performance may be achieved. In some embodiments, high-temperature process(es), such as annealing, dopant activation, and / or the like, may be performed to the semiconductor structure 100K before bonding to the base substrate 300, therefore, impact of such process(es) on the electronic devices and metal lines in the base substrate 300 may be avoided. Also, by processes disclosed herein, the plurality of vertical devices may be formed “self-aligned”, such that the plurality of vertical devices and the wiring layer can be easily aligned. Desirable alignment of a vertical device (e.g., the first vertical device 510a), the respective metal bonding contact (e.g., the first metal bonding contacts 520a), and the respective metal portion (e.g., the first metal portion 312) may be achieved throughout a usable die area, such that the yield may be improved. In some embodiments, such desirable alignment may be achieved throughout the whole wafer (e.g., the whole base substrate 300), since, for example, the vertical devices and the metal contacts are formed according to the alignment mark in the base substrate 300. As such, the misalignment problem of wafer-wafer bonding may be avoided. Also, the bonding interface in the metal bonding contacts may have better bonding strength and electrical connection.

[0121] FIGS. 10A to 10B are schematic diagrams illustrating intermediate stages in the manufacture of a memory device according to one embodiment of the present disclosure. Referring to FIG. 10A, a semiconductor structure 100A as shown in FIG. 1B may be used, and process(es) similar to that described above with respect to FIGS. 9 A to 9D may be performed if applicable, where like reference numerals indicate like elements.

[0122] Referring to FIG. 10B, a plurality of vertical devices 510a’, 510b’, 510c’ are formed. In the present embodiment, the vertical devices 510a’, 510b’, 510c’ maybe vertical schottky diodes. However, embodiments of the present disclosure are not so limited . The vertical device 510a’ may comprise a doped region 512a and a schottky contact 515a. The doped region 512a is disposed over and in contact with the schottky contact 515a. The first doped region 512a may be doped with a first conductivity-type of dopant as described above. The vertical device 510a’ may further comprise an ohmic contact 518a. The ohmic contact 518a is disposed over and in contact with the doped region 512a. Process(es) similar to that described above with respect to FIGS. 9E to 9G may be performed if applicable, where like reference numerals indicate like elements. The vertical devices 510b’, 510c’ may be substantially similar to the vertical device 510a’ and may be formedin the same process as the vertical device 510a’, where like reference numerals indicate like elements.

[0123] FIG. 11 is a schematic diagram illustrating a memory device according to one embodiment of the present disclosure. Referring to FIG. 11, a memory device 600 A is provided. The memory device 600A may be a spin-orbit torque type (SOT) MRAM device. The memory device 600A may comprise a base substrate 300, a first diode 610a, a first metal bonding contact 620a, and a memory unit 630.

[0124] The base substrate 300 comprises a wiring layer 310. In the embodiment shown in FIG. 11, the wiring layer 310 comprises a contact 315 disposed on the memory unit 630. In some embodiments, electronic devices, such as peripheral circuits of the memory array may already be formed in the base substrate 300. Details of the base substrate 300 and the wiring layer 310 discussed above may apply here.

[0125] The first diode 610a may be a vertical P-N diode. The first diode 610a may comprise single crystalline semiconductor material. The first diode 610a may be substantially similar to the vertical device 510a discussed above. As shown in FIG. 11, the first diode 610a is disposed over the base substrate 300. In some embodiments, the first diode 610a may have a height H 1 in a range from about 5 nm to about 1 μm.

[0126] The first metal bonding contact 620a is disposed between the base substrate 300 and the first diode 610a. The first metal bonding contact 620a may be substantially similar to the metal bonding contact 520a discussed above. The first metal bonding contact 620a may comprise material similar to that discussed above with respect to the bonding metal layer 170. In some embodiment, the first metal bonding contact 620a comprises aluminum (Al) (including aluminum alloy) or titanium nitride (TiN). The first metal bonding contact 620a may comprise a first metal layer 622a, a second metal layer 624a, and a metal bonding interface 623a between the first metal layer 622a and the second metal layer 624a of the first metal bonding contact 620a. As shown in FIG. 11, the first metal layer 622a of the first metal bonding contact 620a is in contact with the wiring layer 310 of the base substrate 300. The second metal layer 624a of the first metal bonding contact 620a is in contact with the first diode 610a. The first metal layer 622a and the second metal layer 624a of the first metal bonding contact 620a comprise the same material composition. The first diode 610a and the first metal bonding contact 620a may be formed by method(s) substantially similar to that described above with respect to FIGS. 9 A to 9G. In some embodiments, the first diode may be a vertical schottky diode and may be formed by method(s) substantially similar to that described above with respect to FIGS. 10A to 10B. A sidewall 625a of the first metal bonding contact 620a may be substantially continuous, since there may be substantially no observablemisalignment between the first metal layer 622a and the second metal layer 624a of the first metal bonding contact 620a. The first diode 610a and the first metal bonding contact 620a may be laterally surrounded by a dielectric isolation 601 similar to the dielectric isolation 501 as discussed above.

[0127] In the present embodiment, the memory unit 630 is disposed in the base substrate 300.The memory unit 630 may comprise variable resistors as discussed above. For example, the memory unit 630 may comprise a magnetic tunnel junction (MTJ) structure. The MTJ structure may comprise a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer between the free magnetic layer and the fixed magnetic layer. The first diode 610a is formed electrically connected to the memory unit 630. A first end 612a (e.g., a cathode end) of the first diode 610a may be electrically connected to the memory unit 630 through the first metal bonding contact 620a. The memory device 600A may further comprise an electrode 632. The electrode 632 may comprise materials with high spin Hall effect, for example, β-Tantalum (β-Ta), β-Tungsten (β-W), Ta, W, Pt, Cu doped with elements such as Ir, Bi, any other suitable material(s) which may exhibit high spin-orbit coupling, or a combination of the foregoing. In the present embodiment, the memory unit 630 is disposed over the electrode 632, such that currents flowing through the electrode 632 may produce spin injection to the memory unit 630 and may change the resistance thereof. The memory device 600A may further comprise a electronic device 634, such as a transistor. The electronic device 634 may control directions of currents flowing through the electrode 632, such that writing operations of the memory unit 630 can be performed. The memory device 600A may further comprise a word line 642 and a bit line 644 disposed in the base substrate 300. A read line 646 may be formed over and electrically connected to the first diode 610a. A second end 614a (e.g., an anode end) opposite to the first end 612a of the first diode 610a may be electrically connected to the read line 646. Despite that only one memory cell is illustrated in FIG. 11, a plurality of memory cells or an array of memory cells can be fabricated at the same time.

[0128] FIG. 12 is a schematic diagram illustrating a memory device according to one embodiment of the present disclosure. Referring to FIG. 12, a memory device 600B is provided. The memory device 600B may be a spin-orbit torque type (SOT) MRAM device. The memory device 600B may comprise a base substrate 300, a first diode 610a, a first metal bonding contact 620a, and a memory unit 630. In the present embodiment, the wiring layer 310 may comprise a first word line 642. Bit line 644 may be disposed in the base substrate 300. The first diode 610a and the first metal bonding contact 620a may be formed by method(s) substantially similar to that described above with respect to FIGS. 9A to 9G and FIGS. 10A to 10B. Details of the basesubstrate 300, the first diode 610a, and the first metal bonding contact 620a discussed above may apply here.

[0129] In the present embodiment, the memory unit 630 is disposed over the first diode 610a. The memory device 600B may further comprise an electrode 632. The electrode 632 may be disposed vertically between the memory unit 630 and the first diode 610a. As shown in FIG. 12, a first end 612a (e.g., a cathode end) of the first diode 610a is electrically connected to a first word line 642, and a second end 614a (e.g., an anode end) opposite to the first end 612a of the first diode 610a is electrically connected to the electrode 632. Details of the memory unit 630 and the electrode 632 discussed above may apply here.

[0130] The memory device 600B may furflier comprise a second diode 610b and a second metal bonding contact 620b. The second diode 610b may be substantially similar to the first diode 610a. The second diode 610b may be vertical P-N diode or vertical schottky diode. The second diode 610b may comprise single crystalline semiconductor material. The second diode 610b may be disposed over the electrode 632. The second metal bonding contact 620b may be disposed between the electrode 632 and the second diode 610b. The second metal bonding contact 620b comprises a first metal layer 622b, a second metal layer 624b, and a metal bonding interface 623b between the first metal layer 622b and the second metal layer 624b of the second metal bonding contact 620b. As shown in FIG. 12, a first end 612b (e.g., a cathode end) of the second diode 610b is electrically connected to the electrode 632, and a second end 614b (e.g., an anode end) opposite to the first end 612b of the second diode 610b is electrically connected to a second word line 643. The second diode 610b and the second metal bonding contact 620b may be formed by method(s) substantially similar to that described above with respect to FIGS. 9A to 9G and FIGS. 10A to 10B.

[0131] In one embodiment, a first current II may flow through the electrode 632 and the first diode 610a when the memory unit 630 is selected for a first writing operation. A second current 12 may flow through the second diode 610b and the electrode 632 when the memory unit 630 is selected for a second writing operation. Vias 641a, 641b and via 301 may be formed or disposed in the base substrate 300 for the first current II and the second current 12.

[0132] The memory device 600B may further comprise a third diode 610c and a third metal bonding contact 620c. The third diode 610c and the third metal bonding contact 620c may be substantially similar to the first diode 610a and the first metal bonding contact 620a discussed above with respect to FIG. 11, where like reference numerals indicate like elements. The third diode 610c may be vertical P-N diode or vertical schottky diode. The third diode 610c may comprise single crystalline semiconductor material. The third diode 610c is formed electricallyconnected to the memory unit 630. A first end 612c (e.g., a cathode end) of the third diode 610c may be electrically connected to the memory unit 630 through the third metal bonding contact 620c. A second end 614c (e.g., an anode end) opposite to the first end 612c of the third diode 610c may be electrically connected to a read line 646. The third diode 610c and the third metal bonding contact 620c may be formed by the same process(es) as the second diode 610b and the second metal bonding contact 620b. Details of the first diode 610a, the first metal bonding contact 620a, the second diode 610b, and the second metal bonding contact 620b discussed above may apply here.

[0133] In some embodiments, the first diode 610a and the first metal bonding contact 620a may be firstly formed on the first word line 642 (the wiring layer 310) by method(s) substantially similar to that described above with respect to FIGS. 9A to 9G and FIGS. 10A to 10B. Then, the electrode 632, the memory unit 630, and a contact 631 for the memory unit 630 may be formed by suitable method(s). The second diode 610b and the second metal bonding contact 620b and the third diode 610c and the third metal bonding contact 620c may then be formed on the via 641b and the contact 631 (as the “wiring layer” for the related processes), respectively, by method(s) substantially similar to that described above with respect to FIGS. 9A to 9G and FIGS. 10A to 10B. Despite that only one memory cell is illustrated in FIG. 12, a plurality of memory cells or an array of memory cells can be fabricated at the same time.

[0134] FIG. 13 is a schematic diagram illustrating a memory device according to one embodiment of the present disclosure. Referring to FIG. 13, a memory device 600C is provided. The memory device 600C may be a spin-orbit torque type (SOT) MRAM device. The memory device 600C may be substantially similar to the memory device 600B shown in FIG. 12, where like reference numerals indicate like elements. In the embodiment shown in FIG. 13, the memory device 600 further comprises a second diode 610b and a second metal bonding contact 620b. The second diode 610b may be substantially similar to the second diode 610b discussed above. The second diode 610b may be vertical P-N diode or vertical schottky diode. The second diode 610b may comprise single crystalline semiconductor material. In the present embodiment, the second diode 610b is disposed over the base substrate 300. The second metal bonding contact 620b is disposed between the base substrate 300 and the second diode 610b. The second metal bonding contact 620b comprises a first metal layer 622b, a second metal layer 624b, and a metal bonding interface 623b between the first metal layer 622b and the second metal layer 624b of the second metal bonding contact 620b. As shown in FIG. 13, the first metal layer 622 b of the second metal bonding contact 620b may be in contact with the wiring layer 310 of the base substrate 300. Specifically, in the present embodiment, the wiring layer 310 includes a connection portion 645,and the first metal layer 622b of the second metal bonding contact 620b may be in contact with the connection portion 645. The connection portion 645 may comprise Pt, Pd, Ir, Ru, Cu, W, some other suitable material(s), or a combination of the foregoing. The second metal layer 624b of the second metal bonding contact 620b may be in contact with the second diode 610b. The second diode 610b and the second metal bonding contact 620b may be formed by the same processes) as the first diode 610a and the first metal bonding contact 620a.

[0135] The memory device 600C further comprises an electrode 632. The electrode 632 is disposed vertically between the memory unit 630 and the second diode 610b. A first end 612b (e.g., a cathode end) of the second diode 610b may be electrically connected to the electrode 632. In the present embodiment, the first end 612b of the second diode 610b may be electrically connected to the electrode 632 through the connection portion 645 and a via 641b. A second end 614b (e.g., an anode end) opposite to the first end 612b of the second diode 610b is electrically connected to a second word line. As such, a second current 12 may flow through the second diode 610b and the electrode 632, when the memory unit 630 is selected for a second writing operation.

[0136] In the embodiment shown in FIG. 13, the first diode 610a and the first metal bonding contact 620a and the second diode 610b and the second metal bonding contact 620b may firstly be formed on the first word line 642 and the connection portion 645 (the wiring layer 310), respectively, by method(s) substantially similar to that described above with respect to FIGS. 9 A to 9G and FIGS. 10A to 10B. Then, the electrode 632, the memory unit 630, and a contact 631 for the memory unit 630 may be formed by suitable method(s). The third diode 610c and the third metal bonding contact 620c may then be formed on the contact 631. In some embodiments, the third diode 610c and the third metal bonding contact 620c may be formed by method(s) substantially similar to that described above with respect to FIGS. 9 A to 9G and FIGS. 10A to 10B. In some embodiments, the third diode 610c may comprise polysilicon and may be formed through suitable deposition method(s). Despite that only one memory cell is illustrated in FIG. 13, a plurality of memory cells or an array of memory cells can be fabricated at the same time.

[0137] FIG. 14 is a schematic diagram illustrating a memory device according to one embodiment of the present disclosure. Referring to FIG. 14, a memory device 600D is provided. The memory device 600D may be a spin-orbit torque type (SOT) MRAM device. The memory device 600D may be substantially similar to the memory device 600C shown in FIG. 13, where like reference numerals indicate like elements. In the embodiment shown in FIG. 14, the first end 612b (e.g., a cathode end) of the second diode 610b is over the second end 614b (e.g., an anodeend) of the second diode 610b. Despite that only one memory cell is illustrated in FIG. 14, a plurality of memory cells or an array of memory cells can be fabricated at the same time.

[0138] FIG. 15A is a schematic diagram illustrating a memory device according to one embodiment of the present disclosure. FIG. 15B is an electronic schematic diagram illustrating a memory array of the memory device shown in FIG. 15 A. Referring to FIG. 15 A, a memory device 600E is provided. The memory device 600E may be a spin-transfer torque type (STT) MRAM device or a resistive random-access memory (RRAM) device. The memory device 600E may have a structure substantially similar to the memory device 600B shown in FIG. 12, where like reference numerals indicate like elements.

[0139] In the embodiment shown in FIGS. 15A to 15B, the first diode 610a and the first metal bonding contact 620a may be formed on the first word line 642 of the wiring layer 310 by method(s) substantially similar to that described above with respect to FIGS. 9A to 9G and FIGS. 10A to 10B. The first diode 610a may be substantially similar to the first diode 610a discussed above. The first diode 610a may be vertical P-N diode or vertical schottky diode. The first diode 610a may comprise single crystalline semiconductor material. As shown in FIG. 15A, a first end 612a (e.g., a cathode end) of the first diode 610a is electrically connected to the first word line 642, and a second end 614a (e.g., an anode end) opposite to the first end 612a of the first diode 610a is electrically connected to a connection portion 645’. The connection portion 645’ may comprise Pt, Pd, Ir, Ru, Cu, W, some other suitable material(s), or a combination of the foregoing. Details of the first diode 610a and the first metal bonding contact 620a discussed above may apply here.

[0140] In the embodiment shown in FIGS. 15A to 15B, the second diode 610b and the second metal bonding contact 620b may be formed on via 641b (as the “wiring layer” for the related processes) by method(s) substantially similar to that described above with respect to FIGS. 9 A to 9G and FIGS. 10A to 10B. The second diode 610b may be substantially similar to the first diode 610a discussed above. The second diode 610b may be vertical P-N diode or vertical schottky diode. The second diode 610b may comprise single crystalline semiconductor material. As shown in FIG. 15A, a first end 612b (e.g., a cathode end) of the second diode 610b is electrically connected to the connection portion 645’, and a second end 614b (e.g., an anode end) opposite to the first end 612b of the second diode 610b is electrically connected to a second word line 643. Details of the second diode 610b and the second metal bonding contact 620b discussed above may apply here.

[0141] The memory device 600E may further comprise a via 641c electrically connecting the memory unit 630 to the bit line / read line 644. In one embodiment, a first current I1 may flow through the memory unit 630, the connection portion 645’, and the first diode 610a when thememory unit 630 is selected for a first writing operation. A second current 12 may flow through the second diode 610b, the connection portion 645’, and the memory unit 630 when the memory unit 630 is selected for a second writing operation.

[0142] In some embodiments, the first diode 610a and the first metal bonding contact 620a may be firstly formed on the first word line 642 (the wiring layer 310) by method(s) substantially similar to that described above with respect to FIGS. 9A to 9G and FIGS. 10A to 10B. Then, the connection portion 645 ’ , the memory unit 630, and a contact 631 for the memory unit 630 may be formed by suitable method(s). The memory unit 630 is formed electrically connected to the first diode 610a through the connection portion 645’. The second diode 610 b and the second metal bonding contact 620b may then be formed on the via 641b (as the “wiring layer” for the related processes) by method(s) substantially similar to that described above with respect to FIGS. 9 A to 9G and FIGS . 10A to 10B . Despite that only one memory cell is illustrated in FIG. 15A, a plurality of memory cells or an array of memory cells can be fabricated at the same time.

[0143] Referring to FIG. 15B, a plurality of memory cells may be arranged in rows and columns, wherein each cell is electrically connected to a first word line, such as a first word line 642-1, a first word line 642-2, or a first word line 642-3, a second word line, such as a second word line 643-1, a second word line 643-2, or a second word line 643-3, and a bit line / read line, such as a bit line / read line 644-1 or a bit line / read line 644-2. For example, a first device cell C1 may be electrically connected to and controlled by the first word line 642-1, the second word line 643-1, and the bit line / read line 644-1. The first device cell C1 may have a structure substantially similar to that shown in FIG. 15A. The number of the memory cells is not limited thereto.

[0144] The foregoing description of embodiments is provided to enable any person skilled in the art to make and use the subject matter. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the novel principles and subject matter disclosed herein may be applied to other embodiments without the use of the innovative faculty. Various aspects of the embodiments may be used in different combinations and various different subcombinations of aspects of the embodiments may be used together in a single structure or method without departing from the invention. The claimed subject matter set forth in the claims is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. It is contemplated that additional embodiments are within the spirit and true scope of the disclosed subject matter. Thus, it is intended that the present invention covers modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A semiconductor structure, comprising: a first substrate; a second substrate on the first substrate, the second substrate comprising semiconductor material and having a thickness in a range from about 5 nm to about 10 μm; and a debonding layer between the first substrate and the second substrate; wherein at least a portion of the debonding layer is detachable from the first substrate by applying light or heat to the debonding layer.

2. The semiconductor structure of claim 1, wherein the second substrate is unpattemed.

3. The semiconductor structure of claim 1, wherein the second substrate comprises single crystalline semiconductor material.

4. The semiconductor structure of claim 1, wherein the debonding layer comprises compound semiconductor or polymer, and the first substrate is light transmittable such that at least a portion of the debonding layer is detachable from the first substrate by exposing the debonding layer to light passing through the first substrate.

5. The semiconductor structure of claim 1, wherein the debonding layer comprises polymer or germanium dioxide, and at least a portion of the debonding layer is detachable from the first substrate by applying heat to the debonding layer..

6. The semiconductor structure of claim 1, wherein the second substrate has a thickness in a range from about 5 nm to about 200 nm.

7. The semiconductor structure of claim 1 further comprising a first dielectric layer between the debonding layer and the first substrate.

8. The semiconductor structure of claim 1 further comprising a second dielectric layer between the debonding layer and the second substrate.

9. The semiconductor structure of claim 1 further comprising a device metal layer, wherein the second substrate is disposed between the device metal layer and the debonding layer.

10. The semiconductor structure of claim 1, wherein the debonding layer comprises a buffer layer and a crystalline layer, and the buffer layer of the debonding layer is in contact with the first substrate.

11. The semiconductor structure of claim 1, wherein the second substrate comprises a first semiconductor layer and a second semiconductor layer between the first semiconductor layer and the debonding layer, and the first semiconductor layer and the second semiconductor layer are different in at least one of conductivity-type of dopant, dopant concentration, and composition of material.

12. A method for manufacturing a semiconductor structure, comprising: providing a first structure comprising a first substrate; providing a second structure comprising a semiconductor substrate; forming a debonding layer on the first structure; attaching the second structure to the first structure, such that the debonding layer is disposed between the first substrate and the semiconductor substrate; and removing a portion of the second structure and leaving a second substrate comprising semiconductor material and having a thickness in a range from about 5 nm to about 10 μm, wherein at least a portion of the debonding layer is detachable from the first substrate by applying light or heat to the debonding layer.

13. The method of claim 12, wherein the semiconductor substrate comprises an implanted ion layer, and removing the portion of the second structure comprises removing a portion of the semiconductor substrate from approximately the implanted ion layer.

14. The method of claim 12, wherein the second structure comprise a third substrate and an etch stop layer between the third substrate and the semiconductor substrate, and removing the portion of the second structure comprises removing the third substrate and the etch stop layer.

15. The method of claim 12, wherein removing the portion of the second structure comprises removing a portion of the semiconductor substrate.

16. The method of claim 12, wherein providing the first structure comprises forming a first dielectric layer on the first substrate.

17. The method of claim 12 comprising attaching the second structure to the first structure by a second dielectric layer.

18. The method of claim 12 further comprising forming a device metal layer on the second substrate after removing the portion of the second structure.

19. A method for manufacturing a memory device, comprising: providing a base substrate, the base substrate comprising a wiring layer; providing a semiconductor structure, the semiconductor structure comprising a first substrate, a second substrate on the first substrate, and a debonding layer between the first substrate and the second substrate, wherein the second substrate comprises semiconductor material and has a thickness in a range from about 5 nm to about 10 μm; bonding the semiconductor structure and the base substrate to form a bonded structure by bonding a first bonding metal layer over the wiring layer and a second bonding metal layer over the second substrate; detaching at least a portion of the debonding layer from the first substrate by applying light or heat to the debonding layer; and patterning the second substrate to form a plurality of devices.

20. The method of claim 19, wherein the debonding layer comprises compound semiconductor or polymer, and the method comprises detaching the at least a portion of the debonding layer from the first substrate by exposing the debonding layer to light passing through the first substrate.

21. The method of claim 19, wherein the debonding layer comprises polymer or germanium dioxide, and the method comprises detaching the at least a portion of the debonding layer from the first substrate by applying heat to the debonding layer.

22. The method of claim 19, wherein the wiring layer is in contact with the first bonding metal layer.

23. The method of claim 19 further comprising patterning the first bonding metal layer and the second bonding metal layer to form a plurality of metal bonding contacts.

24. The method of claim 19, wherein the semiconductor structure comprises a first dielectric layer between the debonding layer and the first substrate, and the method further comprisesremoving the first dielectric layer after detaching the at least a portion of the debonding layer from the first substrate.

25. The method of claim 19, wherein the semiconductor structure comprises a second dielectric layer between the debonding layer and the second substrate, and the method further comprises removing the second dielectric layer after detaching the at least a portion of the debonding layer from the first substrate.

26. The method of claim 19, wherein a plurality of memory units are disposed in the base substrate, and the plurality of devices are formed electrically connected to the plurality of memory units.

27. The method of claim 19 further comprising forming a plurality of memory units or electrodes electrically connected to the plurality of devices.

28. A memory device, comprising: a base substrate comprising a wiring layer; a first diode over the base substrate; a first metal bonding contact between the base substrate and the first diode, the first metal bonding contact comprising a first metal layer, a second metal layer, and a metal bonding interface between the first metal layer and the second metal layer; and a memory unit disposed in the base substrate or over the first diode; wherein the first metal layer of the first metal bonding contact is in contact with the wiring layer of the base substrate, and the second metal layer of the first metal bonding contact is in contact with the first diode.

29. The memory device of claim 28, wherein the first diode comprises single crystalline semiconductor material.

30. The memory device of claim 28, wherein the first metal layer and the second metal layer of the first metal bonding contact comprise the same material composition.

31. The memory device of claim 28, wherein the first metal bonding contact comprises aluminum (Al) or titanium nitride (TiN).

32. The memory device of claim 28, wherein the first diode is a vertical P-N diode or a vertical Schottky diode having a height in a range from about 5 nm to about 1 μm.

33. The memory device of claim 28, wherein a first cunent flows through the first diode when the memory unit is selected for a first writing operation.

34. The memory device of claim 28 further comprising an electrode disposed vertically between the memory unit and the first diode, wherein a first end of the first diode is electrically connected to a first word line, and a second end opposite to the first end of the first diode is electrically connected to the electrode.

35. The memory device of claim 34 further comprising: a second diode over the electrode; and a second metal bonding contact between the electrode and the second diode, the second metal bonding contact comprising a first metal layer, a second metal layer, and a metal bonding interface between the first metal layer and the second metal layer; wherein a first end of the second diode is electrically connected to the electrode, and a second end opposite to the first end of the second diode is electrically connected to a second word line; and wherein a second current flows through the second diode when the memory unit is selected for a second writing operation.

36. The memory device of claim 28 further comprising: a second diode over the base substrate; and a second metal bonding contact between the base substrate and the second diode, the second metal bonding contact comprising a first metal layer, a second metal layer, and a metal bonding interface between the first metal layer and the second metal layer; wherein the first metal layer of the second metal bonding contact is in contact with the wiring layer of the base substrate, and the second metal layer of the second metal bonding contact is in contact with the second diode; and wherein a second current flows through the second diode when the memory unit is selected for a second writing operation.

37. The memory device of claim 36 further comprising an electrode disposed vertically between the memory unit and the second diode, wherein a first end of the second diode is electrically connected to the electrode, and a second end opposite to the first end of the second diode is electrically connected to a second word line.

38. The memory device of claim 28, wherein the memory unit is disposed in the base substrate, a first end of the first diode is electrically connected to the memory unit through the first metal bonding contact, and a second end opposite to the first end of the first diode is electrically connected to a read line.

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