Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a base substrate (10), and a plurality of gate lines (22) and a plurality of data lines (24) provided on the base substrate (10); the plurality of gate lines (22) and the plurality of data lines (24) intersect each other to define a plurality of sub-pixel regions; a first transistor (10A), a first signal line (23), a first electrode (26), and a second electrode (27) are provided in a single sub-pixel region; a gate electrode of the first transistor is connected to a gate line (22), a first terminal of the first transistor is connected to a data line (24), and a second terminal (25) of the first transistor is connected to the second electrode; the orthographic projection of the first electrode (26) on the base substrate (10) and the orthographic projection of the second electrode (27) on the base substrate (10) at least partially overlap; the first electrode (26) is electrically connected to the first signal line (23); the first signal line (23) and the gate line (22) are in different layers.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, in particular to a display substrate and a display device. BACKGROUND

[0002] Liquid Crystal Display (LCD) has the characteristics of small volume, low power consumption, no radiation, etc., and has developed rapidly. The liquid crystal display panel includes a thin film transistor array (TFT) substrate and a color filter (CF) substrate of a cell. Liquid crystal (LC) molecules are arranged between the array substrate and the color filter substrate. By controlling the common electrode and the pixel electrode, an electric field for driving the liquid crystal to deflect is formed to realize gray scale display.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising: a substrate, and a plurality of gate lines and a plurality of data lines disposed on the substrate, the plurality of gate lines and the plurality of data lines intersecting each other to define a plurality of sub-pixel regions; a first transistor, a first signal line, a first electrode and a second electrode are disposed in a single sub-pixel region; wherein the gate electrode of the first transistor is connected with the gate line, the first electrode of the first transistor is connected with the data line, and the second electrode of the first transistor is connected with the second electrode; the orthographic projection of the first electrode on the substrate and the orthographic projection of the second electrode on the substrate at least partially overlap, and the first electrode and the first signal line are electrically connected; the first signal line and the gate line are in different layers.

[0006] In an exemplary embodiment, an auxiliary structure is further included, and the orthographic projection of the auxiliary structure on the substrate and the orthographic projection of the first transistor on the substrate at least partially overlap; the auxiliary structure is disposed in the same layer as the first signal line.

[0007] In an exemplary embodiment, the auxiliary structure and the first signal line are connected with each other.

[0008] In an exemplary embodiment, the extension direction of the auxiliary structure is the same as the extension direction of the gate line, and the orthographic projection of the gate line on the substrate and the orthographic projection of the auxiliary structure on the substrate at least partially overlap.

[0009] In an exemplary embodiment, a projection of the gate line on the substrate is located within a projection of the auxiliary structure on the substrate.

[0010] In an exemplary embodiment, a distance between an edge of the gate line and an adjacent side edge of the auxiliary structure is greater than or equal to 0.9 microns and less than or equal to 11 microns in a direction perpendicular to an extension direction of the auxiliary structure.

[0011] In an exemplary embodiment, the display substrate at least includes a first conductive layer, a second conductive layer and a third conductive layer on the substrate; the auxiliary structure and the first signal line are located on the first conductive layer, the gate line is located on the second conductive layer, and the data line is located on the third conductive layer.

[0012] In an exemplary embodiment, the display substrate further includes a first transparent conductive layer and a second transparent conductive layer arranged in sequence on a side of the third conductive layer away from the substrate; the second electrode is arranged on the first transparent conductive layer, and the first electrode is arranged on the second transparent conductive layer; or, the second electrode is arranged on the second transparent conductive layer, and the first electrode is arranged on the first transparent conductive layer.

[0013] In an exemplary embodiment, the second pole is located on the third conductive layer, and the second electrode is connected to the second pole through a via.

[0014] In an exemplary embodiment, the second pole and the second electrode are an integral structure.

[0015] In an exemplary embodiment, the first electrode is connected to the first signal line through a via.

[0016] In an exemplary embodiment, the third conductive layer further includes a first transfer electrode; the first electrode is connected to the first signal line through the first transfer electrode.

[0017] In an exemplary embodiment, the auxiliary structure includes a main body portion and a first extension portion connected to the main body portion; a projection of the main body portion on the substrate and a projection of the active layer of the first transistor on the substrate do not overlap; and a projection of the first extension portion on the substrate and a projection of the second pole on the substrate at least partially overlap.

[0018] In an exemplary embodiment, the second pole is connected to the active layer through a first via; a projection of the first via on the substrate is located within a projection of the first extension portion on the substrate.

[0019] In an exemplary embodiment, a distance between an edge of the first via and a same-side edge of the first extension is greater than or equal to 0.5 microns and less than or equal to 10 microns.

[0020] In an exemplary embodiment, the auxiliary structure further includes a second extension connected with the main body portion, the second extension configured to be connected with the first electrode.

[0021] In an exemplary embodiment, a distance between an edge of the second extension and a neighboring side edge of the gate line is greater than or equal to 1.5 microns and less than or equal to 17 microns.

[0022] In an exemplary embodiment, the display substrate further includes a second transistor, the second transistor including an active layer and a gate electrode, at least one of the active layer and the gate electrode of the second transistor being in the same layer as the first signal line.

[0023] In an exemplary embodiment, the display substrate includes a display area and a non-display area surrounding the display area, the first transistor being located in the display area, and the second transistor being located in the non-display area.

[0024] In an exemplary embodiment, the display substrate at least includes: a first semiconductor layer, a second conductive layer, and a third conductive layer sequentially disposed on the base; the auxiliary structure and the first signal line being located in the first semiconductor layer, the gate line being located in the second conductive layer, and the data line being located in the third conductive layer.

[0025] In an exemplary embodiment, the active layers of the first transistor and the second transistor are of the same material or different materials.

[0026] In an exemplary embodiment, the first signal line is of a material containing a silicon element, and the first signal line is in the same layer as the active layer of the second transistor.

[0027] In an exemplary embodiment, the auxiliary structure is of a material containing a silicon element, and the auxiliary structure is in the same layer as the first signal line and the active layer of the second transistor.

[0028] In an exemplary embodiment, a material of at least one of the second conductive layer and the third conductive layer includes copper.

[0029] In an exemplary embodiment, the material of the second conductive layer comprises copper; the thickness of the second conductive layer is greater than or equal to 135 nanometers and less than or equal to 1000 nanometers; the thickness of the second conductive layer is the distance between the side surface of the second conductive layer close to the substrate and the side surface of the second conductive layer away from the substrate; or, the material of the third conductive layer comprises copper; the thickness of the third conductive layer is greater than or equal to 135 nanometers and less than or equal to 1000 nanometers; the thickness of the third conductive layer is the distance between the side surface of the third conductive layer close to the substrate and the side surface of the third conductive layer away from the substrate.

[0030] In another aspect, the present disclosure provides a display device comprising the aforementioned display substrate.

[0031] Other aspects can become apparent from a review of the drawings and detailed description.

[0032] SUMMARY

[0033] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure, and should not be taken as limiting the present disclosure.

[0034] FIG. 1 is a schematic diagram of a cross-sectional structure of a display device;

[0035] FIG. 2 is a schematic diagram of a planar structure of an array substrate;

[0036] FIG. 3 is a cross-sectional view of the array substrate in FIG. 2 along the CC direction;

[0037] FIG. 4 is a top view of a single sub-pixel region of a display substrate according to at least one embodiment of the present disclosure;

[0038] FIG. 5 is a cross-sectional view of FIG. 4 along the FF direction in an exemplary embodiment;

[0039] FIG. 6 is a cross-sectional view of FIG. 4 along the FF direction in another exemplary embodiment;

[0040] FIG. 7 is a top view of a single sub-pixel region of a display substrate according to another exemplary embodiment;

[0041] FIG. 8 is a cross-sectional view of FIG. 7 along the FF direction in an exemplary embodiment;

[0042] FIG. 9 is a diagram of the orthographic projection relationship between the first extension and the first via on the substrate in an exemplary embodiment;

[0043] FIG. 10 is a top view of a single sub-pixel region of a display substrate according to another exemplary embodiment;

[0044] FIG. 11 is a cross-sectional view of FIG. 10 along the FF direction in an exemplary embodiment;

[0045] FIG. 12 is a cross-sectional view of FIG. 7 in the FF direction according to another exemplary embodiment.

[0046] DETAILED DESCRIPTION

[0047] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in various forms. It is obvious to those skilled in the art that the embodiments and features thereof can be changed or replaced without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the embodiments described below. The embodiments in the present disclosure and the features thereof can be combined each other without conflict.

[0048] In the drawings, the size, the thickness, or the region of one or more constituent elements may, in some cases, be exaggerated for the purpose of explanation and thus is not necessarily to scale with the actual size, thickness, or region. Therefore, the present disclosure should not be construed as being limited to the shape, the relative size, and the like as illustrated in the drawings. The embodiment of the present disclosure is not limited to the shape or the numerical value illustrated in the drawings, and the drawings are schematically illustrated ideal examples. The ratio of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and the interval of the film layer, and the width and the interval of the signal line can be adjusted according to the actual needs.

[0049] The ordinal numbers such as "first", "second", and "third" in the present specification are used to avoid confusion among constituent elements and are not intended to indicate or imply a relative importance of the constituent elements. The "a plurality of" in the present disclosure indicates a number of two or more.

[0050] In the present specification, the words "center", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like that indicate the orientation or positional relationship are used to describe the positional relationship of the constituent elements with reference to the drawings, and are used merely for convenience of description and simplification of the description, and thus cannot be understood as indicating or implying that the device or element indicated thereby must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be understood as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of the constituent elements described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0051] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", "connected" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or internal communication of two elements. For those skilled in the art, the meaning of the above terms in this disclosure can be understood according to the circumstances. Among them, "electrically connected" includes the case where the constituent elements are connected together through an element having a certain electrical effect. "Element having a certain electrical effect" is not particularly limited as long as it can transmit electrical signals between the connected constituent elements. Examples of "element having a certain electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.

[0052] In this specification, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain) and a source electrode (a source electrode terminal, a source region, or a source), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to a region where current flows mainly.

[0053] In this specification, in order to distinguish two poles of a transistor other than the gate, one of the poles is referred to as a first pole and the other is referred to as a second pole. For example, the first pole can be a drain electrode and the second pole can be a source electrode, or the first pole can be a source electrode and the second pole can be a drain electrode. In the case of using a transistor with opposite polarity or in the case where the direction of current flow is changed in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged, and the "source terminal" and the "drain terminal" can be interchanged.

[0054] In this specification, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus also includes a state in which the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus also includes a state in which the angle is greater than or equal to 85° and less than or equal to 95°.

[0055] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. There can be some small deformation due to tolerance, there can be a guide angle, an arc edge, and deformation, etc.

[0056] "About" in this specification means not strictly limited to the limit, allowing values within the range of process and measurement error.

[0057] In the present specification, A extends along a direction of B means that A can include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a bar-shaped body, the main part stretches along the direction of B, and the length of the main part stretching along the direction of B is greater than the length of the secondary part stretching along other directions. In the following description, A extending along the direction of B means that the main part of A extending along the direction of B.

[0058] In the present specification, A and B are arranged in the same layer means that A and B are formed at the same time by the same patterning process when the display substrate is prepared.

[0059] FIG. 1 is a schematic diagram of a cross-sectional structure of a display device. As shown in FIG. 1, the display device can include a first substrate 100 and a second substrate 200 arranged opposite to each other, and a liquid crystal layer 300 arranged between the first substrate 100 and the second substrate 200. The first substrate 100 can be referred to as an array substrate, and the second substrate 200 is an opposite substrate of the array substrate. The first substrate 100 can include a first structure layer 102 arranged on a side of a first base 101 facing the second substrate 200, and the second substrate 200 can include a second structure layer 202 arranged on a side of a second base 201 facing the first substrate 100. LCDs can be divided into twisted nematic (TN) display mode, in plane switching (IPS) display mode, fringe field switching (FFS) display mode, and advanced super dimension switch (ADS) display mode, etc. according to display modes. For the ADS display mode, in an exemplary embodiment, the first structure layer 102 can include a gate line, a data line, a first transistor, a first electrode and a second electrode. The first electrode can be a common electrode connected to a common voltage line, and the second electrode can be a pixel electrode. The first electrode and the second electrode are used to generate an electric field to control the deflection of liquid crystal molecules in the liquid crystal layer, thereby realizing the display of a specific gray scale. The first transistor can be electrically connected to the second electrode, the data line and the gate line, respectively. The scanning signal transmitted by the gate line can control the on-off of the first transistor. After the first transistor is turned on, the pixel voltage transmitted by the data line can be output to the second electrode to realize picture display. The second structure layer 202 can include a black matrix and a filter unit.

[0060] In the current technology, high-end notebook display screens and vehicle display screens use oxide thin film transistors (TFT) or low-temperature polysilicon thin film transistors. The active layer of the low-temperature polysilicon thin film transistor uses low-temperature polysilicon (LTPS). The low-temperature polysilicon thin film transistor has high mobility, low power consumption, and is easy to achieve a narrow frame, but has a leakage problem and can only be used for products with a screen refresh rate of 30 Hz or higher, which cannot meet the needs of low-frequency display. The active layer of the oxide thin film transistor uses oxide semiconductor. The oxide thin film transistor has a low leakage current (Ioff) and can be used in low-frequency display scenarios with a refresh rate of 10 Hz or lower, but the oxide thin film transistor has low mobility, high power consumption, and is not easy to achieve a narrow frame.

[0061] FIG. 2 is a schematic diagram of a planar structure of an array substrate. As shown in FIG. 2, in an example embodiment, the array substrate can include a display area AA and a non-display area, which can be disposed on at least one side of the display area AA. In an example embodiment, the non-display area can be disposed around the display area AA. The non-display area can include a circuit area, which can include a first circuit area BB1 and a second circuit area BB2. The first circuit area BB1 can be located on one side of the display area AA along a first direction X, and the second circuit area BB2 can be located on the side of the display area AA along the opposite direction of the first direction X. The display area AA can include at least one first wire extending along the first direction X, for example, a gate line, and at least one second wire extending along a second direction Y, for example, a data line. A first scan driver can be disposed in the first circuit area BB1, and a second scan driver can be disposed in the second circuit area BB2. The first scan driver and the second scan driver can provide a scan signal to the gate line in the display area AA. A data driver can provide a data signal to the data line in the display area AA.

[0062] In an example embodiment, as shown in FIG. 2, a plurality of gate lines (S1 to Sm) and a plurality of data lines (D1 to Dn) can cross to define a plurality of sub-pixel (Pxij) regions. Each sub-pixel region is provided with a first electrode, a second electrode, and a driving circuit connected to the second electrode. The driving circuit can include at least one first transistor. Taking the first transistor as an oxide thin film transistor as an example, the drain electrode of the oxide thin film transistor can be electrically connected to the second electrode, the source electrode can be electrically connected to the data line, and the gate electrode can be electrically connected to the gate line. The oxide thin film transistor is controlled by the scan signal transmitted by the gate line, and the pixel voltage transmitted by the data line is output to the second electrode by the driving circuit.

[0063] Fig. 3 is a sectional view of the array substrate in Fig. 2 along the CC direction. As shown in Fig. 3, the array substrate can include a substrate 10, a first transistor 10A disposed on the substrate 10, a gate line 22, a first signal line 23, and a data line 24, and the first transistor 10A can be an oxide transistor. In a direction away from the substrate 10, the array substrate can sequentially include a light shielding layer, a first insulating layer 11, a first semiconductor layer, a second insulating layer 12, a first conductive layer, a third insulating layer 13, a second conductive layer, a fourth insulating layer 14, a first planarization layer 15, a first transparent conductive layer, a fifth insulating layer 16, and a second transparent conductive layer. The first insulating layer 11 can be referred to as a buffer layer, the second insulating layer 12 can be referred to as a first gate insulating (GI) layer, the third insulating layer 13 can be referred to as a first interlayer insulating (ILD) layer, the fourth insulating layer 14 can be referred to as a first passivation (PVX) layer, and the fifth insulating layer 16 can be referred to as a second passivation layer.

[0064] In an exemplary embodiment, as shown in Fig. 3, the first semiconductor layer can include an active layer 21 of the first transistor 10A, the first conductive layer can include the gate line 22 and the first signal line 23, and the gate line 22 and the gate electrode of the connected first transistor 10A can be an integral structure. The second conductive layer can include the data line 24 and the second electrode 25, and the first electrode of the first transistor 10A and the adjacent data line 24 can be an integral structure. The first electrode of the first transistor 10A can be connected to one end of the active layer 21 through a via, and the second electrode 25 of the first transistor 10A can be connected to the other end of the active layer 21 through a via. The first transparent conductive layer can include a first electrode 26, and the first electrode 26 can be connected to the first signal line 23 through a via to receive a common voltage signal from the first signal line 23. For example, the first electrode 26 can be a sheet-shaped electrode located in a sub-pixel region defined by the intersection of the data line 24 and the gate line 22. The second transparent conductive layer can include a second electrode 27, and the second electrode 27 can be connected to the second electrode 25 of the first transistor 10A through a via to receive a data signal from the data line 24 after the first transistor 10A is turned on. The second electrode 27 can have a plurality of slits, the extension directions of the plurality of slits can be the same, the second electrode 27 can have slits of two different directions to form a dual-domain structure, and the second electrode 27 can also form a single-domain or multi-domain structure, which is not limited in the present embodiment. The light shielding layer can include an auxiliary structure 20, and the orthographic projection of the first transistor 10A on the substrate 10 can be located within the orthographic projection of the auxiliary structure 20 on the substrate 10.

[0065] The present inventors have found through research that, in the array substrate of the structure shown in Fig. 3, since the gate electrode of the first transistor 10A, the gate line 22, and the first signal line 23 are all located in the first conductive layer, the wiring pressure of the array substrate is large, which is not conducive to the aperture ratio of the sub-pixel and affects the resolution and display effect of the display device.

[0066] The display substrate provided by the example embodiments of the present disclosure comprises: a substrate, and a plurality of gate lines and a plurality of data lines arranged on the substrate, the plurality of gate lines and the plurality of data lines cross each other to define a plurality of sub-pixel regions; a first transistor, a first signal line, a first electrode and a second electrode are arranged in a single sub-pixel region; wherein the gate electrode of the first transistor is connected with the gate line, the first electrode of the first transistor is connected with the data line, and the second electrode of the first transistor is connected with the second electrode; the orthographic projection of the first electrode on the substrate and the orthographic projection of the second electrode on the substrate at least partially overlap, and the first electrode is electrically connected with the first signal line; the first signal line and the gate line are in different layers.

[0067] The display substrate provided by the example embodiments of the present disclosure breaks through the design idea of the traditional display substrate by arranging the first signal line and the gate line in different film layers, which can improve the wiring space of the display substrate, help to improve the sub-pixel aperture ratio of the display substrate, and improve the resolution and display effect of the display substrate.

[0068] In some example embodiments, an auxiliary structure is further included, and the orthographic projection of the auxiliary structure on the substrate and the orthographic projection of the first transistor on the substrate at least partially overlap; the auxiliary structure is arranged in the same layer as the first signal line. The auxiliary structure can play a role of shading the first transistor.

[0069] In example embodiments, the auxiliary structure is connected with the first signal line. In this example, by connecting the auxiliary structure with the first signal line, not only can the wiring space be saved and the sub-pixel aperture ratio be improved, but also the resistance of the first signal line can be reduced, thereby reducing the voltage drop of the common voltage signal in the transmission process and helping to avoid picture flicker of the display device.

[0070] In example embodiments, the display substrate at least comprises: a first conductive layer, a second conductive layer and a third conductive layer on the substrate; the auxiliary structure and the first signal line are located in the first conductive layer, the gate line is located in the second conductive layer, and the data line is located in the third conductive layer. For example, the first conductive layer, the second conductive layer and the third conductive layer can be arranged in sequence in a direction away from the substrate, and the present disclosure does not limit this.

[0071] In example embodiments, the second electrode and the second electrode are an integral structure. In this example, by arranging the second electrode and the second electrode as an integral structure, the second electrode can be omitted, and the proportion of the light-blocking material used by the display substrate can be reduced, further improving the aperture ratio of the sub-pixel.

[0072] In an exemplary embodiment, the third conductive layer further comprises a first transfer electrode; the first electrode is connected with the first signal line through the first transfer electrode. In this example, the first transfer electrode is arranged to help reduce the difficulty of punching and improve the stability of the overlap between the first electrode and the first signal line.

[0073] In an exemplary embodiment, the first electrode is connected with the first signal line through a via. In this example, the first electrode is directly connected with the first signal line through the via, which can reduce the use of light-blocking materials on the display substrate and further improve the aperture ratio of the sub-pixel.

[0074] In an exemplary embodiment, the auxiliary structure comprises a main body portion and a first extension portion connected with the main body portion, a projection of the main body portion on the substrate and a projection of the active layer of the first transistor on the substrate do not overlap, and a projection of the first extension portion on the substrate and a projection of the second electrode on the substrate at least partially overlap. In this example, the auxiliary structure comprises a main body portion and a first extension portion connected with the main body portion, the main body portion does not overlap with the active layer of the first transistor, and the first extension portion provides shading for the vicinity of the second electrode of the first transistor, which reduces the shading area of the auxiliary structure and helps improve the aperture ratio of the sub-pixel.

[0075] In an exemplary embodiment, the display substrate at least comprises: a first semiconductor layer, a second conductive layer and a third conductive layer arranged in sequence on the substrate; the auxiliary structure and the first signal line are located in the first semiconductor layer, the gate line is located in the second conductive layer, and the data line is located in the third conductive layer. In this example, the auxiliary structure and the first signal line are arranged in the first semiconductor layer, which can realize the functions of the auxiliary structure and the first signal line by using semiconductor materials. The light transmittance of semiconductor materials is higher than that of metal materials, which can further improve the aperture ratio of the sub-pixel.

[0076] In an exemplary embodiment, the material of at least one of the second conductive layer and the third conductive layer comprises copper. In this example, the use of copper process can reduce the resistance of the wiring in the film layer and reduce the voltage drop of the transmitted signal of the corresponding wiring, which helps improve the display quality.

[0077] The display substrate of the present disclosure is illustrated below through some exemplary embodiments.

[0078] FIG. 4 is a top view of a single sub-pixel region of a display substrate according to at least one embodiment of the present disclosure, with other structures omitted for illustrative purposes. In some examples, the display substrate can include auxiliary structures 20 extending along a first direction X, gate lines 22, data lines 24 extending along a second direction Y, and second electrodes 27 located between adjacent data lines 24. The second electrodes 27 can have a plurality of slits extending along the second direction Y. The first signal lines 23 and the auxiliary structures 20 are disposed in the same layer. The dashed oval in FIG. 4 outlines a first transistor 10A, and the dashed circles represent vias through which the first electrodes 26 can be connected to the first signal lines 23. The data lines 24 can be connected to the active layers 21 of the first transistors 10A through vias, and the second electrodes 25 of the first transistors can be connected to the active layers 21 of the first transistors 10A through vias. By disposing the first signal lines 23 and the gate lines 22 in different film layers, the design of the conventional display substrate is broken through, the wiring space of the display substrate can be improved, the sub-pixel aperture ratio of the display substrate can be improved, and the resolution and display effect of the display substrate can be improved.

[0079] In some examples, as shown in FIG. 4, the first signal lines 23 and the auxiliary structures 20 can be connected to each other, for example, can be an integrated structure.

[0080] In some examples, as shown in FIG. 4, the first transistor 10A can be an oxide thin film transistor, and the material of the active layer 21 of the first transistor 10A can include a metal oxide material and / or a metal nitride oxide material. The metal oxide material can include, but is not limited to, one or more of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), In-free OS, Ln-OS, zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O.

[0081] The metal nitride oxide material can include, but is not limited to, zinc nitride oxide, indium nitride oxide, gallium nitride oxide, tin nitride oxide, cadmium nitride oxide, aluminum nitride oxide, germanium nitride oxide, titanium nitride oxide, silicon nitride oxide, or a combination thereof.

[0082] The material of the active layer 21 can be in an amorphous, partially crystalline, single crystalline, or polycrystalline state, and can be a single layer or a multi-layer structure, and the embodiments of the present disclosure do not limit this.

[0083] In some examples, the circuit region of the non-display region can include a gate driving circuit, the gate driving circuit can include a second transistor, and the second transistor can be a low temperature poly-silicon thin film transistor. Since the low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current, the low temperature poly-silicon thin film transistor and the oxide thin film transistor are integrated on one display substrate to form a low temperature poly-crystalline oxide (LTPO) display substrate, the advantages of both can be utilized, low frequency driving can be achieved, power consumption can be reduced, narrow frame can be achieved, and display quality can be improved. In the embodiments of the present disclosure, the LTPO technology is applied to the display substrate of the notebook computer and the vehicle display screen size for the first time, and the size range of the display substrate using the LTPO technology is expanded.

[0084] In some examples, as shown in FIG. 4, the orthographic projection of the gate line 22 on the base 10 can be located within the range of the orthographic projection of the auxiliary structure 20 on the base 10. In the second direction Y, the distance between the edge of the gate line 22 and the adjacent side edge of the auxiliary structure 20 can be greater than or equal to 0.9 microns and less than or equal to 11 microns, for example, the distance between the edge of the gate line 22 and the adjacent edge of the auxiliary structure 20 can be greater than or equal to 1 micron and less than or equal to 10 microns, and the embodiments of the present disclosure do not limit this.

[0085] In some examples, as shown in FIG. 4, in the second direction Y, the edge of the gate line 22 and the edge of the adjacent auxiliary structure 20 can have a first distance d1 and a second distance d2, the first distance d1 and the second distance d2 can be set to be equal or unequal, and the embodiments of the present disclosure do not limit this.

[0086] FIG. 5 is a cross-sectional view of FIG. 4 along the FF direction in an exemplary embodiment, omitting other structures. As shown in FIG. 5, the display substrate can include the substrate 10, the first insulating layer 11 disposed on the substrate 10, the second insulating layer 12, the first conductive layer, the third insulating layer 13, the second semiconductor layer, the sixth insulating layer 31, the second conductive layer, the seventh insulating layer 32, the third conductive layer, the fourth insulating layer 14, the first planarization layer 15, the first transparent conductive layer, the fifth insulating layer 16, and the second transparent conductive layer. The sixth insulating layer 31 can be referred to as a second gate insulating layer, and the seventh insulating layer 32 can be referred to as a second interlayer insulating layer. The auxiliary structure 20 and the first signal line 23 can be located in the first conductive layer, the gate line 22 can be located in the second conductive layer, the data line 24 (first electrode) and the second electrode 25 can be located in the third conductive layer, the first electrode 26 can be located in the first transparent conductive layer, and the second electrode 27 can be located in the second transparent conductive layer. In other embodiments, the first electrode 26 can be located in the second transparent conductive layer, and the second electrode 27 can be located in the first transparent conductive layer, which is not limited in the embodiments of the present disclosure.

[0087] In some examples, the display substrate can further include a first semiconductor layer disposed between the first insulating layer 11 and the second insulating layer 12, the active layer of the second transistor of the gate driving circuit can be disposed in the first semiconductor layer, the active layer of the second transistor of the gate driving circuit can be low-temperature polysilicon, the gate electrode of the second transistor of the gate driving circuit can be disposed in the first conductive layer, and the first electrode and the second electrode of the second transistor of the gate driving circuit can be disposed in the third conductive layer, which is not limited in the embodiments of the present disclosure.

[0088] In some examples, the material of the active layer 21 of the first transistor 10A and the material of the active layer of the second transistor can be the same or different. The material of the active layer of the second transistor can be a silicon-containing material, for example, amorphous silicon (a-Si), LTPS, etc., and the material of the active layer of the second transistor can be in an amorphous, partially crystalline, single-crystal or polycrystalline state, and can also be a single-layer or multi-layer structure, which is not limited in the embodiments of the present disclosure.

[0089] In some examples, as shown in FIG. 5, the first electrode 26 can be directly connected with the first signal line 23 through a via.

[0090] In a liquid crystal display device, in order to prevent liquid crystal polarization, the voltage polarity of the second electrode needs to be periodically changed with the common voltage as the center, and when the absolute values of the positive and negative polarities of the voltage are not equal, the display brightness of the positive and negative frame pictures is different, resulting in a flicker phenomenon. The present inventors have found through research that the uniformity of the common voltage signal is not good, which is an important reason for the flicker phenomenon.

[0091] In some examples, as shown in FIG. 5, the first signal line 23 and the auxiliary structure 20 can be an integrated structure. By setting the first signal line 23 and the auxiliary structure 20 as an integrated structure, not only the wiring space can be saved, the aperture ratio of the sub-pixel can be improved, but also the resistance of the first signal line 23 can be reduced, so that the voltage drop of the common voltage signal in the transmission process can be reduced, and the display device can be prevented from flickering.

[0092] In some examples, the second conductive layer can be a single-layer structure, a double-layer structure, or a multi-layer composite structure, and the material of the second conductive layer can include metal copper (Cu), such as elemental copper or an alloy material of copper. By using an oxide transistor for the first transistor in the display area and metal copper for the gate line 22, the charging ratio of the liquid crystal display device can be improved, and the display effect can be improved. In the embodiment of the present disclosure, copper process is integrated into the display substrate of the LTPO process for the first time.

[0093] In some examples, as shown in FIG. 5, the thickness h1 of the second conductive layer can be greater than or equal to 135 nanometers and less than or equal to 1000 nanometers, for example, the thickness h1 of the second conductive layer can be greater than or equal to 150 nanometers and less than or equal to 900 nanometers. The thickness of the second conductive layer can be the distance between the side surface close to the substrate 10 and the side surface away from the substrate 10 of the second conductive layer, and the thickness of the second conductive layer can be the thickness of the wire located in the second conductive layer.

[0094] In some examples, the second conductive layer can include a first sub-layer and a second sub-layer arranged in sequence away from the substrate 10, the first sub-layer can include any one of the following materials: metal titanium (Ti), molybdenum-niobium alloy (MoNb), molybdenum-niobium-titanium alloy (MTD), and metal tungsten (W); and the second sub-layer can include metal copper. The materials and thicknesses of different sub-layers can be set as needed, and the embodiment of the present disclosure does not limit this.

[0095] In some examples, the second conductive layer can include a first sub-layer, a second sub-layer, and a third sub-layer arranged in sequence away from the substrate 10, the first sub-layer and the third sub-layer can include any one of the following materials: metal titanium (Ti), molybdenum-niobium alloy (MoNb), molybdenum-niobium-titanium alloy (MTD), and metal tungsten (W); and the second sub-layer can include metal copper. The materials of the first sub-layer and the third sub-layer can be the same, or the materials of the first sub-layer and the third sub-layer can be different. The materials and thicknesses of different sub-layers can be set as needed, and the embodiment of the present disclosure does not limit this.

[0096] In some examples, the third conductive layer can be a single-layer structure, a double-layer structure, or a multi-layer composite structure, and the material of the third conductive layer can include metal copper (Cu), such as elemental copper or an alloy material of copper.

[0097] In some examples, as shown in FIG. 5, the thickness h2 of the third conductive layer can be greater than or equal to 135 nanometers and less than or equal to 1000 nanometers, for example, the thickness h2 of the third conductive layer can be greater than or equal to 150 nanometers and less than or equal to 900 nanometers. The thickness of the third conductive layer can be the distance between the side surface close to the substrate 10 and the side surface away from the substrate 10 of the third conductive layer, and the thickness of the third conductive layer can be the thickness of the trace located in the third conductive layer.

[0098] In some examples, the third conductive layer can include a fourth sub-layer and a fifth sub-layer arranged in sequence in the direction away from the substrate 10, the fourth sub-layer can include any one of the following materials: metal titanium (Ti), molybdenum-niobium alloy (MoNb), molybdenum-niobium-titanium alloy (MTD), and metal tungsten (W); the fifth sub-layer can include metal copper. The materials and thicknesses of different sub-layers can be set as needed, and the embodiments of the present disclosure do not limit this.

[0099] In some examples, the third conductive layer can include a fourth sub-layer, a fifth sub-layer and a sixth sub-layer arranged in sequence in the direction away from the substrate 10, the fourth sub-layer and the sixth sub-layer can include any one of the following materials: metal titanium (Ti), molybdenum-niobium alloy (MoNb), molybdenum-niobium-titanium alloy (MTD), and metal tungsten (W); the fifth sub-layer can include metal copper. The materials of the fourth sub-layer and the sixth sub-layer can be the same, or the materials of the fourth sub-layer and the sixth sub-layer can be different. The materials and thicknesses of different sub-layers can be set as needed, and the embodiments of the present disclosure do not limit this.

[0100] FIG. 6 is a cross-sectional view of FIG. 4 along the FF direction in another example embodiment, and other structures are omitted. The difference between FIG. 6 and FIG. 5 is that the first electrode 26 is connected to the first signal line 23 through the first transfer electrode 33, and the first signal line 23 and the auxiliary structure 20 are not connected to each other, and the remaining structures can be referred to the description of FIG. 5 above, which will not be repeated here.

[0101] In some examples, as shown in FIG. 6, the first transfer electrode 33 can be located in the third conductive layer. By adding the first transfer electrode 33 on the display substrate, the difficulty of the via hole between the first electrode 26 and the first signal line 23 is reduced, and the stability of the overlap between the first electrode 26 and the first signal line 23 is improved. The via hole can be prepared together with other via holes before the third conductive layer is formed, such as the via hole at the first electrode of the first transistor 10A and the via hole at the second electrode, which helps to simplify the preparation process.

[0102] In some examples, the material of the first transfer electrode 33 can include metal copper, which has better conductive effect, which helps to reduce the resistance of the first signal line 23, reduce the voltage drop of the common voltage signal in the transmission process, avoid the display picture flickering, and improve the display effect.

[0103] In some examples, as shown in FIG. 6, the first signal line 23 and the auxiliary structure 20 can be arranged not to be connected with each other, and the arrangement can be made according to actual needs, which is not limited in the embodiments of the present disclosure.

[0104] FIG. 7 is a top view of a single sub-pixel region of a display substrate in another example embodiment, and other structures are omitted. FIG. 8 is a sectional view of FIG. 7 along the FF direction in an example embodiment, and other structures are omitted. The difference between FIG. 7 and FIG. 4 is the shape of the auxiliary structure 20, and the remaining structures can be referred to the descriptions of FIG. 4 to FIG. 6, which will not be repeated here.

[0105] In some examples, as shown in FIG. 7 and FIG. 8, the orthographic projection of the auxiliary structure 20 on the substrate 10 and the orthographic projection of the first transistor on the substrate 10 only exist overlapping near the second electrode 25. Compared with FIG. 4, the scheme of FIG. 7 reduces the shielding area of the sub-pixel under the premise of ensuring the light shielding effect, and further improves the aperture ratio of the display substrate.

[0106] In some examples, as shown in FIG. 7 and FIG. 8, the auxiliary structure 20 can be a linear shape extending along the first direction X, and the auxiliary structure 20 further includes a first extension 20-1 and a second extension 20-2 connected with the main body part. The first extension 20-1 can be used to shield light near the second electrode 25, and the second extension 20-2 can be connected with the first transfer electrode 33 to transmit the common voltage signal to the first electrode 26, that is, the second extension 20-2 realizes the function of the first signal line 23.

[0107] In some examples, as shown in FIG. 8, the second electrode 25 of the first transistor can be connected with the active layer 21 through the first via V1.

[0108] FIG. 9 is a diagram of a front projection relationship between the first extension and the first via on the base in an example embodiment, and other structures are omitted. As shown in FIG. 9, the front projection of the first via V1 on the base 10 can be located within the range of the front projection of the first extension 20-1 on the base 10, so that light leakage of the first via V1 can be prevented. The distance between the edge of the first via V1 and the same-side edge of the first extension 20-1 can be a third distance d3, which can be greater than or equal to 0.5 microns and less than or equal to 10 microns, for example, the third distance d3 can be greater than or equal to 1 micron and less than or equal to 5 microns, and the present embodiment is not limited thereto. In different side edges, the third distance d3 of the first extension 20-1 and the first via V1 can be equal, or in different side edges, the third distance d3 of the first extension 20-1 and the first via V1 can not be equal, and the present embodiment is not limited thereto. The size design of the present embodiment can minimize the light shielding area on the premise of ensuring the light shielding effect, so as to improve the aperture ratio of the sub-pixel.

[0109] In some examples, as shown in FIG. 7, in the second direction Y, the distance between the edge of the second extension 20-2 and the adjacent side edge of the gate line 22 is a fourth distance d4, which can be greater than or equal to 1.5 microns and less than or equal to 17 microns, for example, the fourth distance d4 can be greater than or equal to 2 microns and less than or equal to 15 microns. The size design of the present embodiment can minimize the light shielding area on the premise of ensuring the light shielding effect, so as to improve the aperture ratio of the sub-pixel.

[0110] FIG. 10 is a top view of a single sub-pixel region of a display substrate in yet another example embodiment, and other structures are omitted. FIG. 11 is a cross-sectional view of FIG. 10 in the FF direction in an example embodiment, and other structures are omitted. The difference between FIG. 10 and FIG. 7 is that the second electrode 25 and the first transfer electrode 33 are removed, the first electrode 26 is directly connected to the second extension 20-2 through a via, and the second electrode 27 is directly connected to the active layer 21 of the first transistor 10A through a via, and the remaining structures can be referred to the description of FIG. 7 above, and will not be described here.

[0111] In some examples, as shown in FIG. 10 and FIG. 11, the first transistor 10A can omit the second electrode 25, and the second electrode 27 is directly connected to one end of the active layer 21 through a via, and the second electrode 25 and the second electrode 27 can be considered as an integrated structure. Since the second electrode 25 is generally a light-proof metal material, and the second electrode 27 is generally a transparent conductive material, by setting the second electrode 25 and the second electrode 27 as an integrated structure, the proportion of light-proof material on the display substrate can be reduced, which is helpful to further improve the aperture ratio of the sub-pixel in the display substrate.

[0112] In some examples, as shown in FIGS. 10 and 11, the display substrate can remove the first transfer electrode 33, and the first electrode 26 can be directly connected to the second extension 20-2 through a via. Since the first transfer electrode 33 is generally a light-blocking metal material, and the first electrode 26 is generally a transparent conductive material, removing the first transfer electrode 33 can reduce the light-blocking material on the display substrate, which helps to further improve the aperture ratio of the sub-pixel in the display substrate.

[0113] FIG. 12 is a cross-sectional view of FIG. 7 along the FF direction in another example embodiment, and other structures are omitted. The difference between FIG. 12 and FIG. 8 is that the materials and film layers of the auxiliary structure 20 and the first signal line 23 are different, and the remaining structures can be referred to the description of FIG. 8 above, which will not be repeated here.

[0114] In some examples, as shown in FIG. 12, the display substrate includes a first semiconductor layer disposed between the first insulating layer 11 and the second insulating layer 12, and the auxiliary structure 20 and the first signal line 23 can be located in the first semiconductor layer. The materials of the auxiliary structure 20 and the first signal line 23 can be conductive polysilicon. Since the light transmittance of the conductive polysilicon material is higher than that of the metal material, this arrangement helps to increase the aperture ratio of the sub-pixel. In this embodiment, the auxiliary structure 20 and the first signal line 23 can be prepared together with the active layer of the second transistor of the gate drive circuit, which also helps to save process steps. In some examples, the display substrate in FIGS. 4-12 can remove the fourth insulating layer 14, and directly cover the third conductive layer with the first planar layer 15, so as to simplify the preparation process. The embodiments of the present disclosure are not limited in this regard.

[0115] In some examples, the schemes shown in FIGS. 4-12 can be combined with each other arbitrarily, and the embodiments of the present disclosure are not limited in this regard.

[0116] The present disclosure also provides a display device including the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, an LCD display, a notebook computer, a digital photo frame, a navigator, etc., and the embodiments of the present disclosure are not limited in this regard.

[0117] In some examples, the display device provided by the embodiments of the present disclosure can be a liquid crystal display device as shown in FIG. 1, and the display substrate in the above embodiments can serve as an array substrate of the liquid crystal display device.

[0118] Although the embodiments disclosed by the present disclosure are as above, the content described is only the embodiments adopted for the convenience of understanding the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A display substrate, comprising: A substrate, and a plurality of gate lines and a plurality of data lines disposed on the substrate, the plurality of gate lines and the plurality of data lines crossing each other to define a plurality of sub-pixel regions; A first transistor, a first signal line, a first electrode and a second electrode are disposed in a single one of the sub-pixel regions; wherein A gate electrode of the first transistor is connected to the gate line, a first electrode of the first transistor is connected to the data line, and a second electrode of the first transistor is connected to the second electrode; a normal projection of the first electrode on the substrate and a normal projection of the second electrode on the substrate at least partially overlap, and the first electrode and the first signal line are electrically connected; The first signal line and the gate line are in different layers. 2.The display substrate of claim 1, wherein, An auxiliary structure is further included, and a normal projection of the auxiliary structure on the substrate and a normal projection of the first transistor on the substrate at least partially overlap; The auxiliary structure is disposed in the same layer as the first signal line. 3.The display substrate of claim 2, wherein, The auxiliary structure and the first signal line are connected to each other. 4.The display substrate of claim 3, wherein, An extension direction of the auxiliary structure is the same as an extension direction of the gate line, and a normal projection of the gate line on the substrate and a normal projection of the auxiliary structure on the substrate at least partially overlap. 5.The display substrate of claim 4, wherein, The normal projection of the gate line on the substrate is located within a range of the normal projection of the auxiliary structure on the substrate. 6.The display substrate of claim 5, wherein, In a direction perpendicular to the extension direction of the auxiliary structure, a distance between an edge of the gate line and an adjacent side edge of the auxiliary structure is greater than or equal to 0.9 microns and less than or equal to 11 microns. 7.The display substrate of claim 5, wherein, The display substrate at least includes: a first conductive layer, a second conductive layer and a third conductive layer on the substrate; The auxiliary structure and the first signal line are located in the first conductive layer, the gate line is located in the second conductive layer, and the data line is located in the third conductive layer. 8.The display substrate of claim 7, wherein, The display substrate further includes: a first transparent conductive layer and a second transparent conductive layer disposed in sequence on a side of the third conductive layer away from the substrate; The second electrode is disposed in the first transparent conductive layer, and the first electrode is disposed in the second transparent conductive layer; or the second electrode is disposed in the second transparent conductive layer, and the first electrode is disposed in the first transparent conductive layer. 9.The display substrate of claim 8, wherein, The second electrode is connected to the second pole through a via. 10.The display substrate of claim 8, wherein, The second pole and the second electrode are an integral structure. 11.The display substrate of claim 8, wherein, The first electrode is connected to the first signal line through a via. 12.The display substrate of claim 8, wherein, The third conductive layer further includes a first transfer electrode; the first electrode is connected to the first signal line through the first transfer electrode. 13.The display substrate of claim 8, wherein, The auxiliary structure includes a main body portion and a first extension portion connected to the main body portion, a normal projection of the main body portion on the substrate and a normal projection of an active layer of the first transistor on the substrate do not overlap, and a normal projection of the first extension portion on the substrate and a normal projection of the second pole on the substrate at least partially overlap. 14.The display substrate of claim 13, wherein, The second pole is connected to the active layer through a first via; a normal projection of the first via on the substrate is located within a range of a normal projection of the first extension portion on the substrate. 15.The display substrate of claim 14, wherein, A distance between an edge of the first via and a same-side edge of the first extension is greater than or equal to 0.5 microns and less than or equal to 10 microns. 16.The display substrate of claim 14, wherein, The auxiliary structure further includes a second extension connected with the main body portion, the second extension configured to be connected with the first electrode. 17.The display substrate of claim 16, wherein, A distance between an edge of the second extension and an adjacent side edge of the gate line is greater than or equal to 1.5 microns and less than or equal to 17 microns. 18.The display substrate of claim 4, wherein, The display substrate further includes a second transistor including an active layer and a gate electrode, at least one of the active layer and the gate electrode of the second transistor being in the same layer as the first signal line.

19. The display substrate of claim 18, wherein, The display substrate includes a display area and a non-display area surrounding the display area, the first transistor being located in the display area, and the second transistor being located in the non-display area. 20.The display substrate of claim 18, wherein, The display substrate at least includes, in sequence on the base, a first semiconductor layer, a second conductive layer, and a third conductive layer; The auxiliary structure and the first signal line are located in the first semiconductor layer, the gate line is located in the second conductive layer, and the data line is located in the third conductive layer. 21.The display substrate of claim 19, wherein, The active layers of the first transistor and the second transistor are of the same material or different materials.

22. The display substrate of claim 21, wherein, The first signal line includes a silicon element, and the first signal line is in the same layer as the active layer of the second transistor.

23. The display substrate of claim 21, wherein, The auxiliary structure includes a silicon element, and the auxiliary structure is in the same layer as the first signal line and the active layer of the second transistor. 24.The display substrate of claim 7, wherein, At least one of the second conductive layer and the third conductive layer includes copper. 25.The display substrate of claim 24, wherein, The second conductive layer includes copper; a thickness of the second conductive layer is greater than or equal to 135 nanometers and less than or equal to 1000 nanometers; the thickness of the second conductive layer is a distance between a side surface of the second conductive layer close to the base and a side surface of the second conductive layer away from the base; or The third conductive layer includes copper; a thickness of the third conductive layer is greater than or equal to 135 nanometers and less than or equal to 1000 nanometers; the thickness of the third conductive layer is a distance between a side surface of the third conductive layer close to the base and a side surface of the third conductive layer away from the base.

26. A display device including the display substrate of any one of claims 1 to 25.

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