Pixel circuit, driving method, and display apparatus

Abstract

A pixel circuit, a driving method, and a display apparatus. The pixel circuit comprises: a light-emitting device (L); a driving transistor (M0) configured to generate, on the basis of a data voltage, a driving current for driving the light-emitting device (L) to emit light; a first control circuit (10) configured to respond to a signal of a first control signal end (CS1) at a reset stage (F1) to provide a signal of a first reference voltage signal end (VREF1) to a first node (N1); a second control circuit (20) configured to respond to a signal of a second control signal end (CS2) at a light-emitting stage (F3) to provide a signal of a second reference voltage signal end (VREF2) to the first node (N1); a third control circuit (30) configured to respond to a valid level of a signal of a third control signal end (CS3) at a data compensation stage (F2) to enable a gate and second electrode of the driving transistor (M0) to be connected; and a data write circuit (40) configured to respond to a valid level of a signal of a scan signal end (SS) at the data compensation stage (F2) to provide a data voltage of a data signal end DA to the first node (N1), wherein a duration of the valid level of the signal of the scan signal end (SS) is included within a duration of the valid level of the signal of the third control signal end (CS3).

Description

Pixel circuit, driving method and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a pixel circuit, a driving method and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED), Quantum Dot Light Emitting Diodes (QLED), Micro Light Emitting Diode (Micro LED), Mini Light Emitting Diode (Mini LED) and other light emitting devices have the advantages of self-luminescence, low energy consumption, etc., and are one of the hotspots in the field of application research of display devices today. Pixel circuits are used in general display devices to drive light emitting devices to emit light.

[0003] SUMMARY

[0004] The pixel circuit provided by the embodiments of the present disclosure has a working process including a reset stage, a data compensation stage and a light emitting stage.

[0005] The pixel circuit includes:

[0006] a light emitting device;

[0007] a driving transistor coupled with the light emitting device and configured to generate a driving current for driving the light emitting device to emit light according to a data voltage;

[0008] a first control circuit coupled with the first node and configured to provide a signal of a first reference voltage signal terminal to the first node in response to a signal of a first control signal terminal in the reset stage;

[0009] a second control circuit coupled with the first node and configured to provide a signal of a second reference voltage signal terminal to the first node in response to a signal of a second control signal terminal in the light emitting stage;

[0010] a third control circuit coupled with a gate and a second electrode of the driving transistor and configured to turn on the gate and the second electrode of the driving transistor in response to an effective level of a signal of a third control signal terminal in the data compensation stage;

[0011] a data writing circuit coupled with the first node and configured to provide the data voltage of a data signal terminal to the first node in response to an effective level of a signal of a scanning signal terminal in the data compensation stage;

[0012] a coupling control circuit coupled to the gate of the driving transistor and the first node, configured to couple the voltage of the first node to the gate of the driving transistor;

[0013] The active level time length of the signal of the scan signal end is contained in the active level time length of the signal of the third control signal end.

[0014] In some possible implementation manners, the first control circuit comprises a first transistor.

[0015] The gate of the first transistor is coupled to the first control signal end, the first pole of the first transistor is coupled to the first node, and the second pole of the first transistor is coupled to the first reference voltage signal end.

[0016] In some possible implementation manners, the second control circuit comprises a second transistor.

[0017] The gate of the second transistor is coupled to the second control signal end, the first pole of the second transistor is coupled to the first node, and the second pole of the second transistor is coupled to the second reference voltage signal end.

[0018] In some possible implementation manners, the third control circuit comprises a third transistor.

[0019] The gate of the third transistor is coupled to the third control signal end, the first pole of the third transistor is coupled to the gate of the driving transistor, and the second pole of the third transistor is coupled to the second pole of the driving transistor.

[0020] In some possible implementation manners, the data writing circuit comprises a fourth transistor.

[0021] The gate of the fourth transistor is coupled to the scan signal end, the first pole of the fourth transistor is coupled to the data signal end, and the second pole of the fourth transistor is coupled to the first node.

[0022] In some possible implementation manners, the coupling control circuit comprises a first capacitor.

[0023] The first pole of the first capacitor is coupled to the gate of the driving transistor, and the second pole of the first capacitor is coupled to the first node.

[0024] In some possible implementation manners, further comprising a reset circuit coupled to the gate of the driving transistor, configured to provide an initialization signal to the gate of the driving transistor in response to the signal of the reset signal end in the reset stage.

[0025] In some possible implementations, the reset circuit includes a fifth transistor.

[0026] A gate of the fifth transistor is coupled with the reset signal terminal, a first electrode of the fifth transistor is coupled with the gate of the driving transistor, and a second electrode of the fifth transistor is coupled with the initialization signal terminal.

[0027] In some possible implementations, the reset signal terminal and the first control signal terminal are the same signal terminal.

[0028] In some possible implementations, the pixel circuit further includes a light-emitting control circuit coupled with the second electrode of the driving transistor and the light-emitting device, and configured to turn on the second electrode of the driving transistor and the light-emitting device in response to a signal of a light-emitting control signal terminal in the light-emitting stage.

[0029] In some possible implementations, the light-emitting control circuit includes a sixth transistor.

[0030] A gate of the sixth transistor is coupled with the light-emitting control signal terminal, a first electrode of the sixth transistor is coupled with the second electrode of the driving transistor, and a second electrode of the sixth transistor is coupled with the light-emitting device.

[0031] In some possible implementations, the light-emitting control signal terminal and the second control signal terminal are the same signal terminal.

[0032] In some possible implementations, the pixel circuit further includes a switch control circuit located between the third control circuit, the reset circuit, and the gate of the driving transistor, and configured to turn on the reset circuit and the gate of the driving transistor in response to a signal of the light-emitting control signal terminal in the reset stage, and turn on the third control circuit and the gate of the driving transistor in response to the signal of the light-emitting control signal terminal in the data compensation stage.

[0033] In some possible implementations, the switch control circuit includes a switch transistor.

[0034] A gate of the switch transistor is coupled with the light-emitting control signal terminal, a first electrode of the switch transistor is coupled with the gate of the driving transistor, and a second electrode of the switch transistor is coupled with the third control circuit and the reset circuit.

[0035] In some possible implementations, the working process of the pixel circuit further includes a bias stage, the bias stage is located before the reset stage, and / or the bias stage is located between the reset stage and the data compensation stage.

[0036] The pixel circuit further includes a bias circuit coupled to the gate of the driving transistor and configured to provide a signal of a bias voltage signal terminal to the gate of the driving transistor in response to a signal of the fourth control signal terminal in the bias stage.

[0037] In some possible implementation manners, the bias circuit includes a seventh transistor.

[0038] The gate of the seventh transistor is coupled to the fourth control signal terminal, the first electrode of the seventh transistor is coupled to the bias voltage signal terminal, and the second electrode of the seventh transistor is coupled to the gate of the driving transistor.

[0039] In some possible implementation manners, the first reference voltage signal terminal and the second reference voltage signal terminal are the same signal terminal.

[0040] In some possible implementation manners, the data compensation stage includes a first capture stage and a second capture stage.

[0041] In the first capture stage, the third control circuit turns on the gate and the second electrode of the driving transistor in response to an effective level of a signal of the third control signal terminal; and in the second capture stage, the third control circuit turns on the gate and the second electrode of the driving transistor in response to an effective level of a signal of the third control signal terminal, and the data write circuit provides the data voltage of the data signal terminal to the first node in response to an effective level of a signal of the scan signal terminal.

[0042] In the first capture stage, the third control circuit turns on the gate and the second electrode of the driving transistor in response to an effective level of a signal of the third control signal terminal, and the data write circuit provides the data voltage of the data signal terminal to the first node in response to an effective level of a signal of the scan signal terminal; and in the second capture stage, the third control circuit turns on the gate and the second electrode of the driving transistor in response to an effective level of a signal of the third control signal terminal.

[0043] The display device provided by the embodiments of the present disclosure includes the pixel circuit described above.

[0044] The driving method of the pixel circuit described above provided by the embodiments of the present disclosure includes the following steps.

[0045] In the reset stage, the first control circuit provides a signal of the first reference voltage signal terminal to the first node in response to a signal of the first control signal terminal.

[0046] In the data compensation stage, the third control circuit turns on the gate and the second electrode of the driving transistor in response to the active level of the signal of the third control signal terminal; the data writing circuit provides the data voltage of the data signal terminal to the first node in response to the active level of the signal of the scanning signal terminal; and the coupling control circuit couples the voltage of the first node to the gate of the driving transistor.

[0047] In the light emitting stage, the second control circuit provides the signal of the second reference voltage signal terminal to the first node in response to the signal of the second control signal terminal; and the coupling control circuit couples the data voltage of the first node to the gate of the driving transistor. BRIEF DESCRIPTION OF DRAWINGS

[0048] Fig. 1 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0049] Fig. 2 is some signal timing diagrams provided by an embodiment of the present disclosure;

[0050] Fig. 3 is another structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0051] Fig. 4 is a flowchart of some driving methods of a pixel circuit provided by an embodiment of the present disclosure;

[0052] Fig. 5 is another signal timing diagram provided by an embodiment of the present disclosure;

[0053] Fig. 6 is still another structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0054] Fig. 7 is still another structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0055] Fig. 8 is still another signal timing diagram provided by an embodiment of the present disclosure;

[0056] Fig. 9 is still another structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0057] Fig. 10 is still another signal timing diagram provided by an embodiment of the present disclosure;

[0058] Fig. 11 is still another structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0059] Fig. 12 is still another signal timing diagram provided by an embodiment of the present disclosure;

[0060] Fig. 13 is still another signal timing diagram provided by an embodiment of the present disclosure;

[0061] Fig. 14 is still another signal timing diagram provided by an embodiment of the present disclosure;

[0062] Fig. 15 is still another structural schematic diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0063] FIG. 16 is another structure diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0064] FIG. 17 is another signal timing diagram provided by an embodiment of the present disclosure;

[0065] FIG. 18 is another structure diagram of a pixel circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. And the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present disclosure.

[0067] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as the common meanings of the terms to those of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second” and similar terms used in the present disclosure do not indicate any order, quantity or importance, but are used to distinguish different components. The terms “include”, “contain” and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms “connect” or “connected” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0068] It should be noted that the size and shape of each figure in the drawings do not reflect the true proportions, but only serve to illustrate the present disclosure. And the same or similar reference numbers represent the same or similar elements or elements with the same or similar functions throughout.

[0069] Currently, low temperature poly-crystal silicon thin film transistor (LTPS TFT) is commonly used as the main device of pixel circuit in active matrix organic light emitting diode (AMOLED) display panel. Due to the spatial variation and spatial variation non-uniformity of threshold voltage (Vth) of LTPS TFT, the pixel circuit generally needs to compensate the spatial variation of threshold voltage Vth of driving thin film transistor (DTFT). In the process of compensating the spatial variation of threshold voltage Vth of driving thin film transistor, the temporary variation of threshold voltage Vth of driving thin film transistor also has a certain influence. The temporary variation of threshold voltage Vth of driving thin film transistor involves multiple device physical mechanisms. For example, the border state defect level of gate insulating layer near the conductive channel interface can capture or release carriers or charges from or to the conductive channel with the change of gate-source voltage Vgs (i.e. gate bias or bias electric field) of driving thin film transistor, causing the change of threshold voltage Vth of driving thin film transistor. There are other mechanisms that can affect the control of conductive channel by gate electric field, such as the transport phenomenon of charged particles in flexible substrate, etc., and their common characteristics are that the time constant of the process of capturing, releasing or transporting related carriers or charges is large and sensitive to the intensity of gate-source voltage Vgs (bias electric field). For the conventional periodic working process of pixel circuit, the threshold voltage Vth of driving thin film transistor lags behind the shift or relaxation (recovery) process of gate-source voltage Vgs compared with the change process of gate-source voltage Vgs, which is called the hysteresis characteristic of threshold voltage Vth of driving thin film transistor.

[0070] For example, the hysteresis characteristic of the threshold voltage Vth of the driving transistor will have certain influence on the display picture, the first influence mechanism is the influence of the previous frame picture display on the next frame picture display; for example, a high brightness area of the display panel in a uniform background is changed to the same brightness as the background area, since the high brightness area is in high brightness display state before the change, the gate-source voltage Vgs of the driving transistor in the pixel circuit is lower, which makes the threshold voltage Vth of the driving transistor negatively offset and smaller; causing the same gate-source voltage Vgs of the driving transistor after the change, the display brightness of the changed high brightness area is lower than the brightness of the surrounding background area, thereby forming a dark area, with the hysteresis relaxation of the threshold voltage Vth of the driving transistor in the pixel circuit of the changed high brightness area to the level of the threshold voltage Vth of the driving transistor in the pixel circuit of the surrounding background area, the display brightness of the changed high brightness area also gradually reaches the same as the display brightness of the surrounding background area, and then the dark area disappears; similarly, the low brightness area display change will also have similar phenomenon, which is called (recoverable) image sticking (Image Sticking), that is, the hysteresis characteristic of the threshold voltage Vth of the driving transistor will cause the display panel to produce (recoverable) image sticking (Image Sticking), which will affect the display effect.

[0071] The second influencing mechanism is the influence of the working process of the pixel circuit in the signal refresh stage in the frame period on the driving current of the driving transistor and the brightness stability of the light emitting device in the light emitting stage. For example, in the reset stage in the signal refresh stage, the voltage of the gate of the driving transistor is involved in strong reverse bias, and the threshold voltage Vth of the driving transistor is quickly negatively shifted. In the light emitting stage, the amplitude of the reverse bias voltage of the gate of the driving transistor is reduced, the hysteresis relaxation recovery of the threshold voltage Vth of the driving transistor is recovered, and the driving current of the driving transistor gradually increases, causing the brightness of the light emitting device to gradually increase, that is, the display brightness of the display panel gradually increases. Due to the sensitive characteristics of human vision, when the frame frequency of the display panel is high, this periodic brightness instability phenomenon is not easy to be perceived, but with the application of low frame frequency energy saving technology, the flicker feeling under low frame frequency cannot be ignored, that is, the hysteresis characteristic of the threshold voltage Vth of the driving transistor will cause the display panel to flicker, affecting the display quality. Moreover, when the associated signal (Vref-Vda) of the pixel circuit and the threshold voltage Vth of the driving transistor are superimposed, the threshold voltage Vth of the driving transistor will also be additionally shifted, and the hysteresis relaxation recovery process of the threshold voltage Vth of the driving transistor will also affect the brightness stability of the light emitting device in the light emitting stage, so that the display panel will flicker. Although the transient process of the superposition of the associated signal (Vref-Vda) of the pixel circuit and the threshold voltage Vth of the driving transistor is synchronized with the light emitting stage at present, the essence is still the continuation of the signal refresh process, which belongs to the second influencing mechanism, that is, the hysteresis characteristic of the threshold voltage Vth of the driving transistor will cause the display panel to flicker, affecting the display quality.

[0072] Based on the above problems, the pixel circuit provided by the embodiments of the present disclosure is shown in FIGS. 1 and 2, and the working process of the pixel circuit includes a reset stage F1, a data compensation stage F2 and a light emitting stage F3.

[0073] The pixel circuit includes:

[0074] a light emitting device L;

[0075] a driving transistor M0 coupled with the light emitting device L and configured to generate a driving current for driving the light emitting device L to emit light according to a data voltage;

[0076] a first control circuit 10 coupled with the first node N1 and configured to provide a signal of a first reference voltage signal terminal VREF1 to the first node N1 in response to a signal of a first control signal terminal CS1 in the reset stage F1;

[0077] a second control circuit 20 coupled with the first node N1 and configured to provide a signal of a second reference voltage signal terminal VREF2 to the first node N1 in response to a signal of a second control signal terminal CS2 in the light emitting stage F3;

[0078] The third control circuit 30 is coupled to the gate and the second electrode of the driving transistor M0, and is configured to turn on the gate and the second electrode of the driving transistor M0 in response to the active level of the signal of the third control signal end CS3 in the data compensation stage F2.

[0079] The data writing circuit 40 is coupled to the first node N1, and is configured to provide the data voltage of the data signal end DA to the first node N1 in response to the active level of the signal of the scan signal end SS in the data compensation stage F2.

[0080] The coupling control circuit 50 is coupled to the gate of the driving transistor M0 and the first node N1, and is configured to couple the voltage of the first node N1 to the gate of the driving transistor M0.

[0081] The active level duration of the signal of the scan signal end SS is included in the active level duration of the signal of the third control signal end CS3.

[0082] The first control circuit 10, the second control circuit 20, the third control circuit 30, the data writing circuit 40, and the coupling control circuit 50 are cooperated with each other, the active level duration of the signal of the scan signal end is set to be included in the active level duration of the signal of the third control signal end, and the gate-source voltage Vgs of the driving transistor is biased by the threshold voltage Vth for a long time in the active level duration of the signal of the third control signal end, which also includes the threshold voltage Vth compensation time. By biasing the gate-source voltage Vgs of the driving transistor by the threshold voltage Vth for a long time, the threshold voltage Vth of the driving transistor can be recovered from the offset caused by the reset and the previous frame, so that the afterimage problem of the display panel can be improved, the brightness stability of the display panel can be improved, the flicker problem of the display panel can be improved, and the display quality can be improved. Moreover, the compensation effect of the threshold voltage Vth of the driving transistor can be improved, and the energy saving effect in the low frame frequency display state can be further improved.

[0083] Moreover, the first control circuit is separately set to provide the signal of the first reference voltage signal end to the first node in response to the signal of the first control signal end in the reset stage, so that the bias intensity of the driving transistor in the reset stage can be reduced and the offset amount of the threshold voltage Vth of the driving transistor in the reset stage can be reduced (i.e. the hysteresis effect can be reduced) by the optimized setting of the first reference voltage signal without affecting the threshold voltage Vth compensation effect (or without affecting the threshold voltage Vth compensation charging amplitude) before the threshold voltage Vth detection process of the driving transistor (i.e. the gate-source voltage Vgs of the driving transistor is biased by the threshold voltage Vth for a long time), so that the display effect can be further improved.

[0084] Exemplarily, as shown in FIG. 1, the first electrode of the driving transistor M0 is coupled with the first power supply end VDD. The driving transistor M0 can be configured as a P-type transistor; wherein the first electrode of the driving transistor M0 can be the source electrode thereof, the second electrode of the driving transistor M0 can be the drain electrode thereof, and when the driving transistor M0 is in a saturation state, the current flows from the source electrode to the drain electrode of the driving transistor M0. Of course, the driving transistor M0 can also be configured as an N-type transistor, which is not limited herein.

[0085] Exemplarily, as shown in FIG. 1, the second electrode of the light emitting device L is coupled with the second power supply end VSS; and exemplarily, the light emitting device L can be an electroluminescent diode. For example, the light emitting device L can include at least one of an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), a micro light emitting diode (Micro LED), a mini light emitting diode (Mini LED), etc. Exemplarily, the light emitting device L can include an anode, a light emitting layer, and a cathode which are stacked. Further, the light emitting layer can further include a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, etc. Of course, in actual application, the specific structure of the light emitting device L can be determined according to the actual application requirements, which is not limited herein.

[0086] In some embodiments of the present disclosure, as shown in FIG. 3, the first control circuit 10 includes a first transistor M1; wherein the gate electrode of the first transistor M1 is coupled with the first control signal end CS1, the first electrode of the first transistor M1 is coupled with the first node N1, and the second electrode of the first transistor M1 is coupled with the first reference voltage signal end VREF1.

[0087] Exemplarily, the first transistor M1 can be turned on under the control of the effective level of the first control signal transmitted on the first control signal end CS1, and can be turned off under the control of the ineffective level of the first control signal. For example, the first transistor M1 can be configured as an N-type transistor, and the effective level of the first control signal is high level and the ineffective level of the first control signal is low level. Alternatively, the first transistor M1 can be configured as a P-type transistor, and the effective level of the first control signal is low level and the ineffective level of the first control signal is high level.

[0088] In some embodiments of the present disclosure, as shown in FIG. 3, the second control circuit 20 comprises a second transistor M2; wherein a gate of the second transistor M2 is coupled with the second control signal terminal CS2, a first pole of the second transistor M2 is coupled with the first node N1, and a second pole of the second transistor M2 is coupled with the second reference voltage signal terminal VREF2.

[0089] For example, the second transistor M2 can be set as an N-type transistor, and the effective level of the second control signal is high level and the ineffective level of the second control signal is low level. Alternatively, the second transistor M2 can be set as a P-type transistor, and the effective level of the second control signal is low level and the ineffective level of the second control signal is high level.

[0090] In some embodiments of the present disclosure, as shown in FIG. 3, the third control circuit 30 comprises a third transistor M3; wherein a gate of the third transistor M3 is coupled with the third control signal terminal CS3, a first pole of the third transistor M3 is coupled with the gate of the driving transistor M0, and a second pole of the third transistor M3 is coupled with the second pole of the driving transistor M0.

[0091] For example, the third transistor M3 can be set as an N-type transistor, and the effective level of the third control signal is high level and the ineffective level of the third control signal is low level. Alternatively, the third transistor M3 can be set as a P-type transistor, and the effective level of the third control signal is low level and the ineffective level of the third control signal is high level.

[0092] In some embodiments of the present disclosure, as shown in FIG. 3, the data writing circuit 40 comprises a fourth transistor M4; wherein a gate of the fourth transistor M4 is coupled with the scanning signal terminal SS, a first pole of the fourth transistor M4 is coupled with the data signal terminal DA, and a second pole of the fourth transistor M4 is coupled with the first node N1.

[0093] For example, the fourth transistor M4 can be set as an N-type transistor, and the effective level of the scanning signal is high level and the ineffective level of the scanning signal is low level. Alternatively, the fourth transistor M4 can be set as a P-type transistor, and the effective level of the scanning signal is low level and the ineffective level of the scanning signal is high level.

[0094] In some embodiments of the present disclosure, as shown in FIG. 3, the coupling control circuit 50 comprises: a first capacitor C1; wherein a first electrode of the first capacitor C1 is coupled with the gate of the driving transistor M0, and a second electrode of the first capacitor C1 is coupled with the first node N1.

[0095] In some embodiments of the present disclosure, as shown in FIG. 1, further comprising: a reset circuit 60 coupled with the gate of the driving transistor M0, configured to provide a signal of an initialization signal terminal VINT to the gate of the driving transistor M0 in response to a signal of a reset signal terminal RE in a reset phase F1.

[0096] In some embodiments of the present disclosure, as shown in FIG. 3, the reset circuit 60 comprises: a fifth transistor M5; wherein a gate of the fifth transistor M5 is coupled with the reset signal terminal RE, a first electrode of the fifth transistor M5 is coupled with the gate of the driving transistor M0, and a second electrode of the fifth transistor M5 is coupled with the initialization signal terminal VINT.

[0097] For example, the fifth transistor M5 can be set as an N-type transistor, and the active level of the reset signal is high level and the inactive level of the reset signal is low level. Alternatively, the fifth transistor M5 can be set as a P-type transistor, and the active level of the reset signal is low level and the inactive level of the reset signal is high level.

[0098] In some embodiments of the present disclosure, as shown in FIG. 1, further comprising: a light emitting control circuit 70 coupled with the second electrode of the driving transistor M0 and the light emitting device L, configured to turn on the second electrode of the driving transistor M0 and the light emitting device L in response to a signal of a light emitting control signal terminal EM in a light emitting phase F3.

[0099] In some embodiments of the present disclosure, as shown in FIG. 3, the light emitting control circuit 70 comprises: a sixth transistor M6; wherein a gate of the sixth transistor M6 is coupled with the light emitting control signal terminal EM, a first electrode of the sixth transistor M6 is coupled with the second electrode of the driving transistor M0, and a second electrode of the sixth transistor M6 is coupled with the light emitting device L.

[0100] For example, the sixth transistor M6 can be set as an N-type transistor, and the active level of the light emitting control signal is high level and the inactive level of the light emitting control signal is low level. Alternatively, the sixth transistor M6 can be set as a P-type transistor, and the active level of the light emitting control signal is low level and the inactive level of the light emitting control signal is high level.

[0101] In some embodiments of the present disclosure, as shown in FIG. 2, the data compensation stage F2 includes a first acquisition stage F21 and a second acquisition stage F22; in the first acquisition stage F21, the third control circuit 30 turns on the gate and the second electrode of the driving transistor M0 in response to the active level of the signal of the third control signal end CS3; in the second acquisition stage F22, the third control circuit 30 turns on the gate and the second electrode of the driving transistor M0 in response to the active level of the signal of the third control signal end CS3, and the data writing circuit 40 provides the data voltage of the data signal end DA to the first node N1 in response to the active level of the signal of the scanning signal end SS.

[0102] Exemplarily, the first electrode of the transistor can be the source electrode thereof, and the second electrode can be the drain electrode thereof. Alternatively, the first electrode can be the drain electrode thereof, and the second electrode can be the source electrode thereof. No limitation is made herein.

[0103] Generally, the transistor with the low temperature poly-silicon (LTPS) material as the active layer has high mobility, can be made thinner and smaller, has lower power consumption, etc. In the specific implementation, the material of the active layer of the at least one transistor can be set as the low temperature poly-silicon material. In this way, the transistor can be set as an LTPS transistor, so that the pixel circuit has high mobility, can be made thinner and smaller, has lower power consumption, etc.

[0104] Generally, the transistor with the metal oxide semiconductor material as the active layer has small drain current. Therefore, in order to reduce the drain current, in some embodiments of the present disclosure, the material of the active layer of the at least one transistor can include the metal oxide semiconductor material, for example, can be IGZO (Indium Gallium Zinc Oxide), and of course, can be other metal oxide semiconductor materials, no limitation is made herein. In this way, the transistor can be set as an oxide transistor, so that the pixel circuit has small drain current.

[0105] Exemplarily, all the transistors can be set as LTPS transistors. Alternatively, all the transistors can be set as oxide transistors. Alternatively, part of the transistors can be set as oxide transistors, and the rest of the transistors can be set as LTPS transistors. By combining the processes of preparing the LTPS transistor and the oxide transistor to prepare the LTPO pixel circuit of low temperature poly-silicon oxide, the drain current of the gate of the driving transistor M0 can be small, and the power consumption can be low. Therefore, the pixel circuit is applied to the display panel, and when the display panel displays at a reduced refresh frequency, the uniformity of the display can be ensured.

[0106] For example, the first power supply end VDD can be configured to load a constant first power supply voltage Vdd, and the first power supply voltage Vdd is generally positive, and the second power supply end VSS can load a constant second power supply voltage Vss, and the second power supply voltage Vss can generally be a ground voltage or a negative value. In actual applications, the specific values of the first power supply voltage Vdd and the second power supply voltage Vss can be determined according to the actual application environment, which is not limited here. In the following, the first power supply voltage Vdd = 0 will be taken as an example for description.

[0107] The embodiment of the present disclosure provides a driving method of the pixel circuit, as shown in FIG. 4, comprising:

[0108] S100, in a reset stage, the first control circuit provides a signal of the first reference voltage signal end to the first node in response to a signal of the first control signal end;

[0109] S200, in a data compensation stage, the third control circuit turns on the gate and the second electrode of the driving transistor in response to an effective level of a signal of the third control signal end; the data writing circuit provides a data voltage of the data signal end to the first node in response to an effective level of a signal of the scanning signal end; and the coupling control circuit couples the voltage of the first node to the gate of the driving transistor;

[0110] S300, in a light emitting stage, the second control circuit provides a signal of the second reference voltage signal end to the first node in response to a signal of the second control signal end; and the coupling control circuit couples the data voltage of the first node to the gate of the driving transistor.

[0111] The working process of the pixel circuit provided by the embodiment of the present disclosure will be described below by taking the pixel circuit shown in FIG. 3 as an example and combining the signal timing diagram shown in FIG. 2. The working process of the pixel circuit in one display frame 1H will be taken as an example for description, wherein one display frame 1H can include a reset stage F1, a data compensation stage F2 and a light emitting stage F3.

[0112] As shown in FIG. 2, cs1 represents the first control signal of the first control signal end CS1, cs2 represents the second control signal of the second control signal end CS2, cs3 represents the third control signal of the third control signal end CS3, ss represents the scanning signal of the scanning signal end SS, re represents the reset signal of the reset signal end, and em represents the light emitting signal of the light emitting control signal end EM.

[0113] In the reset stage F1, the first transistor M1 is turned on under the control of the low level of the first control signal cs1; the second transistor M2 is turned off under the control of the high level of the second control signal cs2; the third transistor M3 is turned off under the control of the high level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned on under the control of the low level of the reset signal re; and the sixth transistor M6 is turned off under the control of the high level of the light-emitting control signal em. The turned-on first transistor M1 provides the signal of the first reference voltage signal terminal VREF1 to the first node N1, so that the voltage value VN1 of the first node N1 is Vref1, wherein Vref1 represents the voltage value of the signal of the first reference voltage signal terminal VREF1; the turned-on fifth transistor M5 provides the signal of the initialization signal terminal VINT to the gate of the driving transistor M0, so that the voltage value Vg of the gate of the driving transistor M0 is Vint, and the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, i.e., the gate-source voltage Vgs=Vg-Vs=Vint, and the driving transistor M0 is in a fully open state, wherein Vint represents the voltage value of the signal of the initialization signal terminal VINT; and the voltage value VC1 of the first capacitor C1 is Vg-VN1=Vint-Vref1.

[0114] In the first acquisition stage F21 (with multiple row periods) in the data compensation stage F2, the first transistor M1 is turned off under the control of the high level of the first control signal cs1; the second transistor M2 is turned off under the control of the high level of the second control signal cs2; the third transistor M3 is turned on under the control of the low level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the high level of the reset signal re; and the sixth transistor M6 is turned off under the control of the high level of the light-emitting control signal em. The turned-on third transistor M3 turns on the gate and the second electrode of the driving transistor M0, and the first power supply voltage Vdd charges the gate of the driving transistor M0 through the driving transistor M0 and the third transistor M3 (equivalent to charging the parasitic capacitor of the driving transistor M0 itself), so that in the first row period, the voltage value Vg of the gate of the driving transistor M0 is Vth1, and the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, i.e., the gate-source voltage Vgs=Vg-Vs=Vth1, wherein Vth1 represents the value of the threshold voltage of the driving transistor M0 acquired in one row period. Since the first acquisition stage F21 has a long time (with multiple row periods), the voltage value Vg of the gate of the driving transistor M0 gradually increases until it approaches the threshold voltage Vth of the driving transistor M0, so that the gate-source voltage Vgs of the driving transistor M0 saturates, i.e., the gate-source voltage Vgs=Vth, and the driving transistor M0 approaches to be turned off. The voltage value VN1 of the first node N1 changes from Vref1 to Vref1-Vint+Vth1; the voltage value of the first capacitor C1 remains unchanged, and the voltage value VC1 of the first capacitor C1 is Vg-VN1=Vint-Vref1. By acquiring the threshold voltage Vth of the driving transistor M0 for a long time, the hysteresis characteristic of the driving transistor and the corresponding negative effects can be effectively improved, and the display quality can be improved.

[0115] In the second acquisition stage F22 (with 1 row period) in the data compensation stage F2, the first transistor M1 is turned off under the control of the high level of the first control signal cs1; the second transistor M2 is turned off under the control of the high level of the second control signal cs2; the third transistor M3 is turned on under the control of the low level of the third control signal cs3; the fourth transistor M4 is turned on under the control of the low level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the high level of the reset signal re; and the sixth transistor M6 is turned off under the control of the high level of the light-emitting control signal em. The fourth transistor M4 that is turned on provides the data voltage of the data signal terminal DA to the first node N1, so the voltage value VN1 of the first node N1 is Vda, wherein Vda represents the voltage value of the data voltage; the first capacitor C1 couples the voltage of the first node N1 to the gate of the driving transistor M0, so the voltage value Vg of the gate of the driving transistor M0 is Vint-Vref1+Vda, the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, and the gate-source voltage Vgs is Vg-Vs=Vint-Vref1+Vda; the third transistor M3 that is turned on turns on the gate and the second electrode of the driving transistor M0, and the first power supply voltage Vdd charges the gate of the driving transistor M0 through the driving transistor M0 and the third transistor M3 (equivalent to charging the first capacitor C1), so the voltage value Vg of the gate of the driving transistor M0 and the gate-source voltage Vgs change, wherein Vg changes from Vint-Vref1+Vda to Vth1, and the gate-source voltage Vgs changes from Vint-Vref1+Vda to Vth1; and the voltage value VC1 of the first capacitor C1 changes from Vint-Vref1 to Vth1-Vda.

[0116] In the light emitting stage F3, the first transistor M1 is turned off under the control of the high level of the first control signal cs1; the second transistor M2 is turned on under the control of the low level of the second control signal cs2; the third transistor M3 is turned off under the control of the high level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the high level of the reset signal re; and the sixth transistor M6 is turned on under the control of the low level of the light emitting control signal em. The turned-on second transistor M2 provides the signal of the second reference voltage signal terminal VREF2 to the first node N1, and thus the voltage value VN1 of the first node N1 changes from Vda to Vref2, wherein Vref2 represents the voltage value of the signal of the second reference voltage signal terminal VREF2; the first capacitor C1 couples the voltage of the first node N1 to the gate of the driving transistor M0, and thus the voltage value Vg of the gate of the driving transistor M0 changes to Vth1-Vda+Vref2, the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, i.e., the gate-source voltage Vgs=Vg-Vs=Vth1-Vda+Vref2, and the voltage value VC1 of the first capacitor C1 remains unchanged and is still Vth1-Vda; the turned-on sixth transistor M6 turns on the second electrode of the driving transistor M0 and the light emitting device L, and drives the light emitting device L to emit light. The driving transistor M0 works in the saturation region, and the driving current I generated thereby can be represented as: wherein, μ represents the mobility of the driving transistor M0, Cox represents the unit area capacitance of the gate insulation layer of the driving transistor M0, and W / L represents the channel width-length ratio of the driving transistor M0.

[0117] In some other embodiments of the present disclosure, as shown in FIG. 5, in the first detection stage F21, the third control circuit 30 turns on the gate and the second electrode of the driving transistor M0 in response to the active level of the signal of the third control signal terminal CS3, and the data writing circuit 40 provides the data voltage of the data signal terminal DA to the first node N1 in response to the active level of the signal of the scanning signal terminal SS; and in the second detection stage F22, the third control circuit 30 turns on the gate and the second electrode of the driving transistor M0 in response to the active level of the signal of the third control signal terminal CS3.

[0118] The working process of the pixel circuit provided in the embodiments of the present disclosure will be described below by taking the pixel circuit shown in FIG. 3 as an example in combination with the signal timing diagram shown in FIG. 5. The working process of the pixel circuit in one display frame 1H will be described as an example, wherein one display frame 1H can include a reset stage F1, a data compensation stage F2, and a light emitting stage F3.

[0119] Wherein, as shown in Fig. 5, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, cs3 represents the third control signal of the third control signal terminal CS3, ss represents the scanning signal of the scanning signal terminal SS, re represents the reset signal of the reset signal terminal, and em represents the light emitting signal of the light emitting control signal terminal EM.

[0120] In the reset stage F1, the first transistor M1 is turned on under the control of the low level of the first control signal cs1; the second transistor M2 is turned off under the control of the high level of the second control signal cs2; the third transistor M3 is turned off under the control of the high level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned on under the control of the low level of the reset signal re; and the sixth transistor M6 is turned off under the control of the high level of the light emitting control signal em. The turned-on first transistor M1 provides the signal of the first reference voltage signal terminal VREF1 to the first node N1, so that the voltage value VN1 of the first node N1 is Vref1; the turned-on fifth transistor M5 provides the signal of the initialization signal terminal VINT to the gate of the driving transistor M0, so that the voltage value Vg of the gate of the driving transistor M0 is Vint, and the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, i.e. the gate-source voltage Vgs=Vg-Vs=Vint, and the driving transistor M0 is in the fully open state; and the voltage value VC1 of the first capacitor C1 is Vg-VN1=Vint-Vref1.

[0121] In the first pull-in stage F21 (with 1 row period) in the data compensation stage F2, the first transistor M1 is turned off under the control of the high level of the first control signal cs1; the second transistor M2 is turned off under the control of the high level of the second control signal cs2; the third transistor M3 is turned on under the control of the low level of the third control signal cs3; the fourth transistor M4 is turned on under the control of the low level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the high level of the reset signal re; and the sixth transistor M6 is turned off under the control of the high level of the light-emitting control signal em. The fourth transistor M4 that is turned on provides the data voltage of the data signal terminal DA to the first node N1, so the voltage value VN1 of the first node N1 is Vda, wherein Vda represents the voltage value of the data voltage; the first capacitor C1 couples the voltage of the first node N1 to the gate of the driving transistor M0, so the voltage value Vg of the gate of the driving transistor M0 is Vint-Vref1+Vda, the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, and the gate-source voltage Vgs is Vg-Vs=Vint-Vref1+Vda; the third transistor M3 that is turned on turns on the gate and the second electrode of the driving transistor M0, and the first power supply voltage Vdd charges the gate of the driving transistor M0 through the driving transistor M0 and the third transistor M3 (equivalent to charging the first capacitor C1), so the voltage value Vg of the gate of the driving transistor M0 and the gate-source voltage Vgs change, wherein Vg changes from Vint-Vref1+Vda to Vth1, and the gate-source voltage Vgs changes from Vint-Vref1+Vda to Vth1; and the voltage value VC1 of the first capacitor C1 changes from Vint-Vref1 to Vth1-Vda.

[0122] In the second acquisition stage F22 (with multiple row periods) in the data compensation stage F2, the first transistor M1 is turned off under the control of the high level of the first control signal cs1; the second transistor M2 is turned off under the control of the high level of the second control signal cs2; the third transistor M3 is turned on under the control of the low level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the high level of the reset signal re; and the sixth transistor M6 is turned off under the control of the high level of the light-emitting control signal em. The turned-on third transistor M3 turns on the gate and the second electrode of the driving transistor M0, and the first power supply voltage Vdd charges the gate of the driving transistor M0 through the driving transistor M0 and the third transistor M3 (equivalent to charging the parasitic capacitor of the driving transistor M0 itself), so that the voltage value Vg of the gate of the driving transistor M0 changes from Vth1 to Vth, and the gate-source voltage Vgs also changes from Vth1 to Vth. Since the second acquisition stage F22 has a long time (with multiple row periods), the voltage value Vg of the gate of the driving transistor M0 gradually increases until it approaches the threshold voltage Vth of the driving transistor M0, so that the gate-source voltage Vgs of the driving transistor M0 saturates, i.e., the gate-source voltage Vgs = Vth, and the driving transistor M0 approaches to be turned off; and the voltage value VN1 of the first node N1 remains unchanged and is still Vda, and the voltage value VC1 of the first capacitor C1 remains unchanged and is still Vth1-Vda. Through long-time acquisition of the threshold voltage Vth of the driving transistor M0, the hysteresis characteristic of the driving transistor and the corresponding negative effects can be effectively improved, and the display quality is improved.

[0123] In the light emitting stage F3, the first transistor M1 is turned off under the control of the high level of the first control signal cs1; the second transistor M2 is turned on under the control of the low level of the second control signal cs2; the third transistor M3 is turned off under the control of the high level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the high level of the reset signal re; and the sixth transistor M6 is turned on under the control of the low level of the light emitting control signal em. The turned-on second transistor M2 provides the signal of the second reference voltage signal terminal VREF2 to the first node N1, and thus the voltage value VN1 of the first node N1 changes from Vda to Vref2; the first capacitor C1 couples the voltage of the first node N1 to the gate of the driving transistor M0, and thus the voltage value Vg of the gate of the driving transistor M0 changes to Vth1-Vda+Vref2, the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, that is, the gate-source voltage Vgs=Vg-Vs=Vth1-Vda+Vref2, and the voltage value VC1 of the first capacitor C1 remains unchanged and is still Vth1-Vda; the turned-on sixth transistor M6 turns on the second electrode of the driving transistor M0 and the light emitting device L, and drives the light emitting device L to emit light. The driving transistor M0 works in the saturation region, and the driving current I generated thereby can be represented as:

[0124] The pixel circuit of the embodiment of the present disclosure provides another structural schematic diagram, as shown in FIG. 6, which is a variation of the implementation manner in the above-mentioned embodiment. The following only describes the difference between the present embodiment and the above-mentioned embodiment, and the same parts are not described herein.

[0125] In some other embodiments of the present disclosure, as shown in FIG. 6, the reset signal terminal RE and the first control signal terminal CS1 are the same signal terminal. The gate of the first transistor M1 and the gate of the fifth transistor M5 are coupled with the reset signal terminal RE. Such a setting can reduce the number of signal lines, reduce the wiring difficulty, and thus simplify the circuit.

[0126] In some other embodiments of the present disclosure, as shown in FIG. 6, the light emitting control signal terminal EM and the second control signal terminal CS2 are the same signal terminal. The gate of the second transistor M2 and the gate of the sixth transistor M6 are coupled with the light emitting control signal terminal EM. Such a setting can reduce the number of signal lines, reduce the wiring difficulty, and thus simplify the circuit.

[0127] It should be noted that the signal timing diagram corresponding to the pixel circuit shown in FIG. 6 can be FIG. 2 or FIG. 5. Moreover, the specific working process of the pixel circuit shown in FIG. 6 can be basically the same as that of the pixel circuit shown in FIG. 3, and thus is not described herein.

[0128] The present disclosure provides another structure diagram of the pixel circuit, as shown in FIG. 7, which is a variation of the implementation in the above-mentioned embodiment. The differences between the present embodiment and the above-mentioned embodiment are described below, and the same parts are not described here.

[0129] In some embodiments of the present disclosure, as shown in FIG. 7, some transistors (for example, the third transistor M3 and the fifth transistor M5 in FIG. 7) are configured as oxide transistors, and the rest of the transistors (for example, the first transistor M1, the second transistor M2, the fourth transistor M4, the sixth transistor M6 and the driving transistor M0 in FIG. 7) are configured as LTPS transistors. By combining the processes of preparing LTPS transistors and oxide transistors to prepare the LTPO pixel circuit of low-temperature polysilicon oxide, the leakage current of the gate of the driving transistor M0 can be small, and the power consumption can be low. Therefore, when the pixel circuit is applied to the display panel, the uniformity of the display can be ensured when the display panel displays at a reduced refresh frequency.

[0130] The working process of the pixel circuit provided by the present disclosure is described below by taking the pixel circuit shown in FIG. 7 as an example and combining the signal timing diagram shown in FIG. 8. The working process of the pixel circuit in one display frame 1H is taken as an example for description, wherein one display frame 1H can include a reset stage F1, a data compensation stage F2 and an emission stage F3.

[0131] As shown in FIG. 8, cs1 represents the first control signal of the first control signal end CS1, cs3 represents the third control signal of the third control signal end CS3, ss represents the scanning signal of the scanning signal end SS, re represents the reset signal of the reset signal end, and em represents the emission signal of the emission control signal end EM.

[0132] In the reset stage F1, the first transistor M1 is turned on under the control of the low level of the first control signal cs1; the second transistor M2 is turned off under the control of the high level of the light-emitting control signal em; the third transistor M3 is turned off under the control of the low level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned on under the control of the high level of the reset signal re; and the sixth transistor M6 is turned off under the control of the high level of the light-emitting control signal em. The turned-on first transistor M1 provides the signal of the first reference voltage signal terminal VREF1 to the first node N1, so that the voltage value VN1 of the first node N1 is Vref1; the turned-on fifth transistor M5 provides the signal of the initialization signal terminal VINT to the gate of the driving transistor M0, so that the voltage value Vg of the gate of the driving transistor M0 is Vint, and the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, i.e., the gate-source voltage Vgs=Vg-Vs=Vint, and the driving transistor M0 is in a fully open state; and the voltage value VC1 of the first capacitor C1 is Vg-VN1=Vint-Vref1.

[0133] In the first acquisition stage F21 (with multiple row periods) in the data compensation stage F2, the first transistor M1 is turned off under the control of the high level of the first control signal cs1; the second transistor M2 is turned off under the control of the high level of the light-emitting control signal em; the third transistor M3 is turned on under the control of the high level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the low level of the reset signal re; and the sixth transistor M6 is turned off under the control of the high level of the light-emitting control signal em. The turned-on third transistor M3 turns on the gate and the second electrode of the driving transistor M0, and the first power supply voltage Vdd charges the gate of the driving transistor M0 through the driving transistor M0 and the third transistor M3 (equivalent to charging the parasitic capacitor of the driving transistor M0 itself), so that in the first row period, the voltage value Vg of the gate of the driving transistor M0 is Vth1, and the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, i.e., the gate-source voltage Vgs=Vg-Vs=Vth1. Since the first acquisition stage F21 has a long time (with multiple row periods), the voltage value Vg of the gate of the driving transistor M0 gradually increases until it approaches the threshold voltage Vth of the driving transistor M0, so that the gate-source voltage Vgs of the driving transistor M0 saturates, i.e., the gate-source voltage Vgs=Vth, and the driving transistor M0 approaches to be turned off. The voltage value VN1 of the first node N1 changes from Vref1 to Vref1-Vint+Vth1, and the voltage value of the first capacitor C1 remains unchanged, i.e., the voltage value VC1 of the first capacitor C1=Vg-VN1=Vint-Vref1. By long-time acquisition of the threshold voltage Vth of the driving transistor M0, the hysteresis characteristic of the driving transistor and the corresponding negative effects can be effectively improved, and the display quality can be improved.

[0134] In the second detecting stage F22 (with 1 row period) in the data compensation stage F2, the first transistor M1 is turned off under the control of the high level of the first control signal cs1; the second transistor M2 is turned off under the control of the high level of the light emitting control signal em; the third transistor M3 is turned on under the control of the high level of the third control signal cs3; the fourth transistor M4 is turned on under the control of the low level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the low level of the reset signal re; and the sixth transistor M6 is turned off under the control of the high level of the light emitting control signal em. The fourth transistor M4 turned on provides the data voltage of the data signal terminal DA to the first node N1, so the voltage value VN1 of the first node N1 is Vda; the first capacitor C1 couples the voltage of the first node N1 to the gate of the driving transistor M0, so the voltage value Vg of the gate of the driving transistor M0 is Vint-Vref1+Vda, the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, and the gate-source voltage Vgs is Vg-Vs=Vint-Vref1+Vda; the third transistor M3 turned on turns on the gate and the second electrode of the driving transistor M0, and the first power supply voltage Vdd charges the gate of the driving transistor M0 through the driving transistor M0 and the third transistor M3 (equivalent to charging the first capacitor C1), so the voltage value Vg of the gate of the driving transistor M0 and the gate-source voltage Vgs change, wherein Vg changes from Vint-Vref1+Vda to Vth1, and the gate-source voltage Vgs changes from Vint-Vref1+Vda to Vth1; and the voltage value VC1 of the first capacitor C1 changes from Vint-Vref1 to Vth1-Vda.

[0135] In the light emitting stage F3, the first transistor M1 is turned off under the control of the high level of the first control signal cs1; the second transistor M2 is turned on under the control of the low level of the light emitting control signal em; the third transistor M3 is turned off under the control of the low level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the low level of the reset signal re; and the sixth transistor M6 is turned on under the control of the low level of the light emitting control signal em. The turned-on second transistor M2 provides the signal of the second reference voltage signal terminal VREF2 to the first node N1, and thus the voltage value VN1 of the first node N1 changes from Vda to Vref2; the first capacitor C1 couples the voltage of the first node N1 to the gate of the driving transistor M0, and thus the voltage value Vg of the gate of the driving transistor M0 changes to Vth1-Vda+Vref2, the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, that is, the gate-source voltage Vgs=Vg-Vs=Vth1-Vda+Vref2, and the voltage value VC1 of the first capacitor C1 remains unchanged and is still Vth1-Vda; the turned-on sixth transistor M6 turns on the second electrode of the driving transistor M0 and the light emitting device L, and drives the light emitting device L to emit light. The driving transistor M0 works in the saturation region, and the driving current I generated thereby can be represented as:

[0136] Some other structural schematic diagrams of the pixel circuit are provided in the embodiments of the present disclosure, as shown in FIG. 9, which are transformed for the implementation in the above-mentioned embodiments. Only the differences between the present embodiment and the above-mentioned embodiments are described below, and the same parts are not described herein.

[0137] In some other embodiments of the present disclosure, as shown in FIG. 9, the pixel circuit further includes a switch control circuit 80 located between the third control circuit 30, the reset circuit 60 and the gate of the driving transistor M0, and configured to turn on the reset circuit 60 and the gate of the driving transistor M0 in response to the signal of the light emitting control signal terminal EM in the reset stage F1, and turn on the third control circuit 30 and the gate of the driving transistor M0 in response to the signal of the light emitting control signal terminal EM in the data compensation stage F2.

[0138] In some other embodiments of the present disclosure, as shown in FIG. 9, the switch control circuit 80 includes a switch transistor M8; wherein the gate of the switch transistor M8 is coupled with the light emitting control signal terminal EM, the first electrode of the switch transistor M8 is coupled with the gate of the driving transistor M0, and the second electrode of the switch transistor M8 is coupled with the first electrode of the third transistor M3 in the third control circuit 30 and the first electrode of the fifth transistor M5 in the reset circuit 60.

[0139] Exemplarily, the switch transistor M8 can be turned on under the control of an effective level of the light-emitting control signal transmitted on the light-emitting control signal end EM, and can be turned off under the control of an ineffective level of the light-emitting control signal. For example, the switch transistor M8 can be set as an N-type transistor, and the effective level of the light-emitting control signal is a high level and the ineffective level of the light-emitting control signal is a low level. Alternatively, the switch transistor M8 can be set as a P-type transistor, and the effective level of the light-emitting control signal is a low level and the ineffective level of the light-emitting control signal is a high level.

[0140] Exemplarily, as shown in FIG. 9, some transistors (for example, the switch transistor M8 in FIG. 9) are set as oxide transistors, and the rest of the transistors (for example, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the driving transistor M0 in FIG. 7) are set as LTPS transistors. By combining the two processes of preparing transistors to prepare the LTPO pixel circuit of low-temperature polysilicon oxide through the LTPS transistors and the oxide transistors, the leakage current of the gate of the driving transistor M0 can be small, and the power consumption can be low. Therefore, when the pixel circuit is applied to the display panel, the uniformity of the display can be ensured when the display panel displays at a reduced refresh frequency.

[0141] Next, taking the pixel circuit shown in FIG. 9 as an example, the working process of the pixel circuit provided in the embodiments of the present disclosure is described in combination with the signal timing diagram shown in FIG. 10. The working process of the pixel circuit in one display frame 1H is taken as an example for description, wherein one display frame 1H can include a reset stage F1, a data compensation stage F2 and a light-emitting stage F3.

[0142] As shown in FIG. 10, cs3 represents a third control signal of a third control signal end CS3, ss represents a scanning signal of a scanning signal end SS, re represents a reset signal of a reset signal end, and em represents a light-emitting signal of a light-emitting control signal end EM.

[0143] In the reset stage F1, the first transistor M1 is turned on under the control of the low level of the reset signal re; the second transistor M2 is turned off under the control of the high level of the light-emitting control signal em; the third transistor M3 is turned off under the control of the low level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned on under the control of the high level of the reset signal re; the sixth transistor M6 is turned off under the control of the high level of the light-emitting control signal em; and the switch transistor M8 is turned on under the control of the high level of the light-emitting control signal em. The turned-on first transistor M1 provides the signal of the first reference voltage signal terminal VREF1 to the first node N1, so that the voltage value VN1 of the first node N1 is Vref1; the turned-on fifth transistor M5 and the switch transistor M8 provide the signal of the initialization signal terminal VINT to the gate of the driving transistor M0, so that the voltage value Vg of the gate of the driving transistor M0 is Vint, and the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, that is, the gate-source voltage Vgs=Vg-Vs=Vint, and the driving transistor M0 is in a fully open state; and the voltage value VC1 of the first capacitor C1 is Vg-VN1=Vint-Vref1.

[0144] In the first acquisition stage F21 (with multiple row periods) in the data compensation stage F2, the first transistor M1 is turned off under the control of the high level of the reset signal re; the second transistor M2 is turned off under the control of the high level of the light-emitting control signal em; the third transistor M3 is turned on under the control of the high level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the low level of the reset signal re; the sixth transistor M6 is turned off under the control of the high level of the light-emitting control signal em; and the switch transistor M8 is turned on under the control of the high level of the light-emitting control signal em. The turned-on third transistor M3 and switch transistor M8 turn on the gate and second electrode of the driving transistor M0, and the first power supply voltage Vdd charges the gate of the driving transistor M0 through the driving transistor M0 and the third transistor M3 (equivalent to charging the parasitic capacitor of the driving transistor M0 itself), so that in the first row period, the voltage value Vg of the gate of the driving transistor M0 is Vth1, and the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, i.e., the gate-source voltage Vgs=Vg-Vs=Vth1. Since the first acquisition stage F21 has a long time (with multiple row periods), the voltage value Vg of the gate of the driving transistor M0 gradually increases until it approaches the threshold voltage Vth of the driving transistor M0, so that the gate-source voltage Vgs of the driving transistor M0 saturates, i.e., the gate-source voltage Vgs=Vth, and the driving transistor M0 approaches to be turned off. The voltage value VN1 of the first node N1 changes from Vref1 to Vref1-Vint+Vth1, and the voltage value of the first capacitor C1 remains unchanged, i.e., the voltage value VC1 of the first capacitor C1=Vg-VN1=Vint-Vref1. By long-time acquisition of the threshold voltage Vth of the driving transistor M0, the hysteresis characteristic of the driving transistor and the corresponding negative effects can be effectively improved, and the display quality can be improved.

[0145] In the second acquisition stage F22 (with 1 row period) in the data compensation stage F2, the first transistor M1 is turned off under the control of the high level of the reset signal re; the second transistor M2 is turned off under the control of the high level of the light-emitting control signal em; the third transistor M3 is turned on under the control of the high level of the third control signal cs3; the fourth transistor M4 is turned on under the control of the low level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the low level of the reset signal re; the sixth transistor M6 is turned off under the control of the high level of the light-emitting control signal em; and the switch transistor M8 is turned on under the control of the high level of the light-emitting control signal em. The fourth transistor M4 that is turned on provides the data voltage of the data signal end DA to the first node N1, so that the voltage value VN1 of the first node N1 is Vda; the first capacitor C1 couples the voltage of the first node N1 to the gate of the driving transistor M0, so that the voltage value Vg of the gate of the driving transistor M0 is Vint-Vref1+Vda, the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, and the gate-source voltage Vgs is Vg-Vs=Vint-Vref1+Vda; the third transistor M3 and the switch transistor M8 that are turned on turn on the gate and the second electrode of the driving transistor M0, and the first power supply voltage Vdd charges the gate of the driving transistor M0 through the driving transistor M0 and the third transistor M3 (equivalent to charging the first capacitor C1), so that the voltage value Vg of the gate of the driving transistor M0 and the gate-source voltage Vgs change, wherein Vg changes from Vint-Vref1+Vda to Vth1, and the gate-source voltage Vgs changes from Vint-Vref1+Vda to Vth1; and the voltage value VC1 of the first capacitor C1 changes from Vint-Vref1 to Vth1-Vda.

[0146] In the light emitting stage F3, the first transistor M1 is turned off under the control of the high level of the reset signal re; the second transistor M2 is turned on under the control of the low level of the light emitting control signal em; the third transistor M3 is turned off under the control of the low level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the low level of the reset signal re; the sixth transistor M6 is turned on under the control of the low level of the light emitting control signal em; and the switch transistor M8 is turned off under the control of the low level of the light emitting control signal em. The second transistor M2 that is turned on provides the signal of the second reference voltage signal end VREF2 to the first node N1, and thus the voltage value VN1 of the first node N1 changes from Vda to Vref2; the first capacitor C1 couples the voltage of the first node N1 to the gate of the driving transistor M0, and thus the voltage value Vg of the gate of the driving transistor M0 changes to Vth1-Vda+Vref2, the voltage value Vs of the first pole of the driving transistor M0 is Vdd=0, that is, the gate-source voltage Vgs=Vg-Vs=Vth1-Vda+Vref2, and the voltage value VC1 of the first capacitor C1 remains unchanged and is still Vth1-Vda; the sixth transistor M6 that is turned on turns on the second pole of the driving transistor M0 and the light emitting device L, and drives the light emitting device L to emit light. The driving transistor M0 works in the saturation region, and the driving current I generated by the driving transistor M0 can be represented as:

[0147] The pixel circuit further includes a bias circuit 90, which is coupled to the gate of the driving transistor M0 and is configured to provide a signal of a bias voltage signal end VH to the gate of the driving transistor M0 in response to a signal of a fourth control signal end CS4 in the bias stage F4.

[0148] In some other embodiments of the present disclosure, as shown in FIGS. 11 and 12, the working process of the pixel circuit further includes a bias stage F4.

[0149] The pixel circuit further includes a bias circuit 90, which is coupled to the gate of the driving transistor M0 and is configured to provide a signal of a bias voltage signal end VH to the gate of the driving transistor M0 in response to a signal of a fourth control signal end CS4 in the bias stage F4.

[0150] In some other embodiments of the present disclosure, as shown in FIG. 11, the bias circuit 90 includes a seventh transistor M7, wherein the gate of the seventh transistor M7 is coupled to the fourth control signal end CS4, the first pole of the seventh transistor M7 is coupled to the bias voltage signal end VH, and the second pole of the seventh transistor M7 is coupled to the gate of the driving transistor M0.

[0151] Exemplarily, the seventh transistor M7 can be turned on under control of an effective level of the fourth control signal transmitted on the fourth control signal end CS4, and can be turned off under control of an ineffective level of the fourth control signal. For example, the seventh transistor M7 can be set as an N-type transistor, and the effective level of the fourth control signal is a high level and the ineffective level of the fourth control signal is a low level. Alternatively, the seventh transistor M7 can be set as a P-type transistor, and the effective level of the fourth control signal is a low level and the ineffective level of the fourth control signal is a high level.

[0152] In yet some embodiments of the present disclosure, as shown in FIG. 12, the bias stage F4 is located before the reset stage F1 and the bias stage F4 is located between the reset stage F1 and the data compensation stage F2.

[0153] In yet some embodiments of the present disclosure, as shown in FIG. 13, the bias stage F4 is located before the reset stage F1.

[0154] In yet some embodiments of the present disclosure, as shown in FIG. 14, the bias stage F4 is located between the reset stage F1 and the data compensation stage F2.

[0155] The working process of the pixel circuit provided in the embodiments of the present disclosure will be described below by taking the pixel circuit shown in FIG. 11 as an example in combination with the signal timing diagram shown in FIG. 12. The working process of the pixel circuit in one display frame 1H will be described as an example, wherein one display frame 1H can include: a bias stage F4, a reset stage F1, a data compensation stage F2 and an emitting stage F3.

[0156] As shown in FIG. 12, cs3 represents the third control signal of the third control signal end CS3, cs4 represents the fourth control signal of the fourth control signal end CS4, ss represents the scanning signal of the scanning signal end SS, re represents the reset signal of the reset signal end, and em represents the emitting signal of the emitting control signal end EM.

[0157] In the bias stage F4, the first transistor M1 is turned off under control of the high level of the reset signal re, the second transistor M2 is turned off under control of the high level of the emitting control signal em, the third transistor M3 is turned off under control of the high level of the third control signal cs3, the fourth transistor M4 is turned off under control of the high level of the scanning signal ss, the fifth transistor M5 is turned off under control of the high level of the reset signal re, the sixth transistor M6 is turned off under control of the high level of the emitting control signal em, and the seventh transistor M7 is turned on under control of the low level of the fourth control signal cs4. The turned-on seventh transistor M7 provides the signal of the bias voltage signal end VH to the gate of the driving transistor M0, and thus the voltage value Vg of the gate of the driving transistor M0 is Vh, wherein Vh represents the voltage value of the signal of the bias voltage signal end VH.

[0158] In the reset stage F1, the first transistor M1 is turned on under the control of the low level of the reset signal re; the second transistor M2 is turned off under the control of the high level of the light-emitting control signal em; the third transistor M3 is turned off under the control of the high level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned on under the control of the low level of the reset signal re; the sixth transistor M6 is turned off under the control of the high level of the light-emitting control signal em, and the seventh transistor M7 is turned off under the control of the high level of the fourth control signal cs4. The turned-on first transistor M1 provides the signal of the first reference voltage signal terminal VREF1 to the first node N1, so that the voltage value VN1 of the first node N1 is Vref1; the turned-on fifth transistor M5 provides the signal of the initialization signal terminal VINT to the gate of the driving transistor M0, so that the voltage value Vg of the gate of the driving transistor M0 changes from Vh to Vint, and the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, that is, the gate-source voltage Vgs=Vg-Vs=Vint, and the driving transistor M0 is in a fully open state; and the voltage value VC1 of the first capacitor C1 is Vg-VN1=Vint-Vref1.

[0159] In the first acquisition stage F21 (with 1 row period) in the data compensation stage F2, the first transistor M1 is turned off under the control of the high level of the reset signal re; the second transistor M2 is turned off under the control of the high level of the light-emitting control signal em; the third transistor M3 is turned on under the control of the low level of the third control signal cs3; the fourth transistor M4 is turned on under the control of the low level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the high level of the reset signal re; the sixth transistor M6 is turned off under the control of the high level of the light-emitting control signal em, and the seventh transistor M7 is turned off under the control of the high level of the fourth control signal cs4. The fourth transistor M4 turned on provides the data voltage of the data signal terminal DA to the first node N1, so that the voltage value VN1 of the first node N1 is Vda, wherein Vda represents the voltage value of the data voltage; the first capacitor C1 couples the voltage of the first node N1 to the gate of the driving transistor M0, so that the voltage value Vg of the gate of the driving transistor M0 is Vint-Vref1+Vda, the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, and the gate-source voltage Vgs is Vg-Vs=Vint-Vref1+Vda; the third transistor M3 turned on connects the gate and the second electrode of the driving transistor M0, and the first power supply voltage Vdd charges the gate of the driving transistor M0 through the driving transistor M0 and the third transistor M3 (equivalent to charging the first capacitor C1), so that the voltage value Vg of the gate of the driving transistor M0 and the gate-source voltage Vgs change, wherein Vg changes from Vint-Vref1+Vda to Vth1, and the gate-source voltage Vgs changes from Vint-Vref1+Vda to Vth1; and the voltage value VC1 of the first capacitor C1 changes from Vint-Vref1 to Vth1-Vda.

[0160] In the second acquisition stage F22 (with multiple row periods) in the data compensation stage F2, the first transistor M1 is turned off under the control of the high level of the reset signal re; the second transistor M2 is turned off under the control of the high level of the light-emitting control signal em; the third transistor M3 is turned on under the control of the low level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the high level of the reset signal re; the sixth transistor M6 is turned off under the control of the high level of the light-emitting control signal em, and the seventh transistor M7 is turned off under the control of the high level of the fourth control signal cs4. The turned-on third transistor M3 turns on the gate and the second electrode of the driving transistor M0, and the first power supply voltage Vdd charges the gate of the driving transistor M0 through the driving transistor M0 and the third transistor M3 (equivalent to charging the parasitic capacitor of the driving transistor M0 itself), so that the voltage value Vg of the gate of the driving transistor M0 changes from Vth1 to Vth, and the gate-source voltage Vgs also changes from Vth1 to Vth. Since the second acquisition stage F22 has a long time (with multiple row periods), the voltage value Vg of the gate of the driving transistor M0 gradually increases until it approaches the threshold voltage Vth of the driving transistor M0, so that the gate-source voltage Vgs of the driving transistor M0 saturates, i.e., the gate-source voltage Vgs = Vth, and the driving transistor M0 approaches to be turned off; and the voltage value VN1 of the first node N1 remains unchanged and is still Vda, and the voltage value VC1 of the first capacitor C1 remains unchanged and is still Vth1-Vda. Among them, by long-time acquisition of the threshold voltage Vth of the driving transistor M0, the hysteresis characteristic of the driving transistor and the corresponding negative effects can be effectively improved, and the display quality is improved.

[0161] In the light emitting stage F3, the first transistor M1 is turned off under the control of the high level of the reset signal re; the second transistor M2 is turned on under the control of the low level of the light emitting control signal em; the third transistor M3 is turned off under the control of the high level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the high level of the reset signal re; and the seventh transistor M7 is turned off under the control of the high level of the fourth control signal cs4. The turned-on second transistor M2 provides the signal of the second reference voltage signal terminal VREF2 to the first node N1, and thus the voltage value VN1 of the first node N1 changes from Vda to Vref2; the first capacitor C1 couples the voltage of the first node N1 to the gate of the driving transistor M0, and thus the voltage value Vg of the gate of the driving transistor M0 changes to Vth1-Vda+Vref2, the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, that is, the gate-source voltage Vgs=Vg-Vs=Vth1-Vda+Vref2, and the voltage value VC1 of the first capacitor C1 remains unchanged and is still Vth1-Vda; the turned-on sixth transistor M6 turns on the second electrode of the driving transistor M0 and the light emitting device L, and drives the light emitting device L to emit light. The driving transistor M0 works in the saturation region, and the driving current I generated by the driving transistor M0 can be represented as:

[0162] The pixel circuit provided in the embodiments of the present disclosure is illustrated in FIG. 15, which is a variation of the above-mentioned embodiments. The differences between the present embodiment and the above-mentioned embodiments are described below, and the same parts are not described herein.

[0163] In some other embodiments of the present disclosure, as shown in FIG. 15, the first reference voltage signal terminal VREF1 and the second reference voltage signal terminal VREF2 are the same signal terminal. The second electrode of the first transistor M1 and the second electrode of the second transistor M2 are both coupled with the second reference voltage signal terminal VREF2. Such a setting can reduce the number of signal lines, reduce the wiring difficulty, and thus simplify the circuit.

[0164] The working process of the pixel circuit provided in the embodiments of the present disclosure is described below by taking the pixel circuit shown in FIG. 15 as an example and in combination with the signal timing diagram shown in FIG. 10. The working process of the pixel circuit in one display frame 1H is taken as an example for description, wherein one display frame 1H can include a reset stage F1, a data compensation stage F2, and a light emitting stage F3.

[0165] In the reset stage F1, the first transistor M1 is turned on under the control of the low level of the reset signal re; the second transistor M2 is turned off under the control of the high level of the light-emitting control signal em; the third transistor M3 is turned off under the control of the low level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned on under the control of the high level of the reset signal re; and the sixth transistor M6 is turned off under the control of the high level of the light-emitting control signal em. The turned-on first transistor M1 provides the signal of the second reference voltage signal terminal VREF2 to the first node N1, so that the voltage value VN1 of the first node N1 is Vref2; the turned-on fifth transistor M5 and the switch transistor M8 provide the signal of the initialization signal terminal VINT to the gate of the driving transistor M0, so that the voltage value Vg of the gate of the driving transistor M0 is Vint, and the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, i.e. the gate-source voltage Vgs=Vg-Vs=Vint, and the driving transistor M0 is in a fully open state; and the voltage value VC1 of the first capacitor C1 is Vg-VN1=Vint-Vref2.

[0166] In the first acquisition stage F21 (with multiple row periods) in the data compensation stage F2, the first transistor M1 is turned off under the control of the high level of the reset signal re; the second transistor M2 is turned off under the control of the high level of the light-emitting control signal em; the third transistor M3 is turned on under the control of the high level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the low level of the reset signal re; and the sixth transistor M6 is turned off under the control of the high level of the light-emitting control signal em. The turned-on third transistor M3 and the switch transistor M8 turn on the gate and the second electrode of the driving transistor M0, and the first power supply voltage Vdd charges the gate of the driving transistor M0 through the driving transistor M0 and the third transistor M3 (equivalent to charging the parasitic capacitor of the driving transistor M0 itself), so that in the first row period, the voltage value Vg of the gate of the driving transistor M0 is Vth1, and the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, i.e., the gate-source voltage Vgs=Vg-Vs=Vth1. Since the first acquisition stage F21 has a long time (with multiple row periods), the voltage value Vg of the gate of the driving transistor M0 gradually increases until it approaches the threshold voltage Vth of the driving transistor M0, so that the gate-source voltage Vgs of the driving transistor M0 saturates, i.e., the gate-source voltage Vgs=Vth, and the driving transistor M0 approaches to be turned off. The voltage value VN1 of the first node N1 changes from Vref2 to Vref2-Vint+Vth1, and the voltage value of the first capacitor C1 remains unchanged, i.e., the voltage value VC1 of the first capacitor C1=Vg-VN1=Vint-Vref2. By long-time acquisition of the threshold voltage Vth of the driving transistor M0, the hysteresis characteristic of the driving transistor and the corresponding negative effects can be effectively improved, and the display quality can be improved.

[0167] In the second detecting stage F22 (with 1 row period) in the data compensation stage F2, the first transistor M1 is turned off under the control of the high level of the reset signal re; the second transistor M2 is turned off under the control of the high level of the light emitting control signal em; the third transistor M3 is turned on under the control of the high level of the third control signal cs3; the fourth transistor M4 is turned on under the control of the low level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the low level of the reset signal re; and the sixth transistor M6 is turned off under the control of the high level of the light emitting control signal em. The fourth transistor M4 that is turned on provides the data voltage of the data signal end DA to the first node N1, so the voltage value VN1 of the first node N1 is Vda; the first capacitor C1 couples the voltage of the first node N1 to the gate of the driving transistor M0, so the voltage value Vg of the gate of the driving transistor M0 is Vint-Vref2+Vda, the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, and the gate-source voltage Vgs is Vg-Vs=Vint-Vref2+Vda; the third transistor M3 and the switch transistor M8 that are turned on turn on the gate and the second electrode of the driving transistor M0, and the first power supply voltage Vdd charges the gate of the driving transistor M0 (equivalent to charging the first capacitor C1) through the driving transistor M0 and the third transistor M3, so the voltage value Vg of the gate of the driving transistor M0 and the gate-source voltage Vgs change, wherein Vg changes from Vint-Vref2+Vda to Vth1, and the gate-source voltage Vgs changes from Vint-Vref2+Vda to Vth1; and the voltage value VC1 of the first capacitor C1 changes from Vint-Vref2 to Vth1-Vda.

[0168] In the light emitting stage F3, the first transistor M1 is turned off under the control of the high level of the reset signal re; the second transistor M2 is turned on under the control of the low level of the light emitting control signal em; the third transistor M3 is turned off under the control of the low level of the third control signal cs3; the fourth transistor M4 is turned off under the control of the high level of the scanning signal ss; the fifth transistor M5 is turned off under the control of the low level of the reset signal re; and the sixth transistor M6 is turned on under the control of the low level of the light emitting control signal em. The turned-on second transistor M2 provides the signal of the second reference voltage signal terminal VREF2 to the first node N1, and thus the voltage value VN1 of the first node N1 changes from Vda to Vref2; the first capacitor C1 couples the voltage of the first node N1 to the gate of the driving transistor M0, and thus the voltage value Vg of the gate of the driving transistor M0 changes to Vth1-Vda+Vref2, the voltage value Vs of the first electrode of the driving transistor M0 is Vdd=0, that is, the gate-source voltage Vgs=Vg-Vs=Vth1-Vda+Vref2, and the voltage value VC1 of the first capacitor C1 remains unchanged and is still Vth1-Vda; the turned-on sixth transistor M6 turns on the second electrode of the driving transistor M0 and the light emitting device L, and drives the light emitting device L to emit light. The driving transistor M0 works in the saturation region, and the driving current I generated by the driving transistor M0 can be represented as:

[0169] The pixel circuit of some other structural schematic diagrams is provided in the embodiments of the present disclosure, as shown in FIG. 16, which is a transformation of the implementation in the above-mentioned embodiments. The differences between the present embodiment and the above-mentioned embodiments are described below, and the same parts are not described herein.

[0170] In some other embodiments of the present disclosure, as shown in FIG. 16, the third control signal terminal CS3 and the scanning signal terminal SS are the same signal terminal. The gate of the fourth transistor M4 and the gate of the third transistor M3 are both coupled with the scanning signal terminal SS. Such a setting can reduce the number of signal lines, reduce the wiring difficulty, and thus simplify the circuit.

[0171] For example, the signal timing diagram of the pixel circuit shown in FIG. 16 is shown in FIG. 17. The data compensation stage F2 in the pixel circuit includes a first compensation stage F23 and a second compensation stage F24, and the time length of the second compensation stage F24 is greater than that of the first compensation stage F23.

[0172] The present embodiment of the present disclosure uses the parasitic capacitance of the driving transistor M0 to maintain the threshold voltage of the driving transistor M0 through the longer second compensation stage F24, thereby improving the hysteresis effect of the driving transistor M0 and improving the display quality. For example, the channel size of the driving transistor M0 can be designed to be relatively wide, thereby ensuring the parasitic capacitance of the driving transistor M0.

[0173] The pixel circuit provided by the embodiments of the present disclosure is illustrated in FIG. 18, which is a variation of the implementation in the above embodiments. The differences between the present embodiment and the above embodiments are described below, and the same parts are not described herein.

[0174] In some embodiments of the present disclosure, as shown in FIG. 18, the pixel circuit further includes a second capacitor C2 configured to stabilize the voltage between the first electrode of the driving transistor M0 and the gate electrode of the driving transistor M0, wherein the first electrode of the second capacitor C2 is coupled to the first electrode of the driving transistor M0, and the second electrode of the second capacitor C2 is coupled to the gate electrode of the driving transistor M0.

[0175] For example, the signal timing diagram of the pixel circuit shown in FIG. 18 is shown in FIG. 17, and the data compensation phase F2 in the pixel circuit includes a first compensation phase F23 and a second compensation phase F24, and the duration of the second compensation phase F24 is greater than the duration of the first compensation phase F23.

[0176] Based on the same disclosure concept, the present disclosure also provides a display device including the pixel circuit provided by the embodiments of the present disclosure. The display device solves the problem in the same principle as the pixel circuit described above, and therefore the implementation of the display device can refer to the implementation of the pixel circuit described above, and the repeated parts are not described herein.

[0177] For example, the display device provided by the embodiments of the present disclosure can include a display panel. The display panel can include a substrate. The substrate can include a display area and a non-display area (i.e., an area of the substrate other than the area surrounded by the display area). The display area can include a plurality of pixel units arranged in an array. Each pixel unit can include sub-pixels of the same color or sub-pixels of different colors. For example, the pixel unit can include red sub-pixels, green sub-pixels, and blue sub-pixels, so that red, green, and blue can be mixed to achieve color display. Alternatively, the pixel unit can include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, so that red, green, blue, and white can be mixed to achieve color display. Of course, in actual applications, the light-emitting colors of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, which is not limited herein.

[0178] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by those skilled in the art, which are not described herein and should not be considered as a limitation on the present disclosure.

[0179] While the preferred embodiments of the disclosure have been described, additional variations and modifications can be employed by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to cover all such variations and modifications as fall within the scope of the disclosure.

[0180] Obviously, numerous modifications and variations of the present embodiments are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the present disclosure can be practiced otherwise than as specifically described.

Claims

1. A pixel circuit, wherein: The working process of the pixel circuit includes: a reset phase, a data compensation phase and a light emitting phase; The pixel circuit comprises: Light-emitting devices; a driving transistor coupled to the light emitting device and configured to generate a driving current for driving the light emitting device to emit light according to a data voltage; a first control circuit coupled to the first node and configured to provide a signal from a first reference voltage signal terminal to the first node in response to a signal from a first control signal terminal during the reset phase; a second control circuit coupled to the first node and configured to provide a signal from a second reference voltage signal terminal to the first node in response to a signal from a second control signal terminal during the light emitting phase; a third control circuit coupled to the gate and the second electrode of the driving transistor, and configured to turn on the gate and the second electrode of the driving transistor in response to an active level of a signal at a third control signal terminal during the data compensation phase; a data writing circuit coupled to the first node and configured to provide the data voltage of the data signal terminal to the first node in response to an active level of a signal of the scan signal terminal during the data compensation phase; a coupling control circuit coupled to the gate of the driving transistor and the first node, and configured to couple the voltage of the first node to the gate of the driving transistor; The effective level duration of the signal at the scanning signal end is included in the effective level duration of the signal at the third control signal end.

2. The pixel circuit according to claim 1, wherein: The first control circuit includes: a first transistor; A gate of the first transistor is coupled to the first control signal terminal, a first electrode of the first transistor is coupled to the first node, and a second electrode of the first transistor is coupled to the first reference voltage signal terminal.

3. The pixel circuit according to claim 1, wherein: The second control circuit includes: a second transistor; A gate of the second transistor is coupled to the second control signal terminal, a first electrode of the second transistor is coupled to the first node, and a second electrode of the second transistor is coupled to the second reference voltage signal terminal.

4. The pixel circuit according to claim 1, wherein: The third control circuit includes: a third transistor; The gate of the third transistor is coupled to the third control signal terminal, the first electrode of the third transistor is coupled to the gate of the driving transistor, and the second electrode of the third transistor is coupled to the second electrode of the driving transistor.

5. The pixel circuit according to claim 1, wherein: The data writing circuit includes: a fourth transistor; A gate of the fourth transistor is coupled to the scan signal terminal, a first electrode of the fourth transistor is coupled to the data signal terminal, and a second electrode of the fourth transistor is coupled to the first node.

6. The pixel circuit according to claim 1, wherein: The coupling control circuit includes: a first capacitor; A first electrode of the first capacitor is coupled to the gate of the driving transistor, and a second electrode of the first capacitor is coupled to the first node.

7. The pixel circuit according to any one of claims 1 to 6, wherein: Also includes: The reset circuit is coupled to the gate of the driving transistor and is configured to provide a signal of an initialization signal terminal to the gate of the driving transistor in response to a signal of the reset signal terminal during the reset phase.

8. The pixel circuit according to claim 7, wherein: The reset circuit includes: a fifth transistor; A gate of the fifth transistor is coupled to the reset signal terminal, a first electrode of the fifth transistor is coupled to the gate of the driving transistor, and a second electrode of the fifth transistor is coupled to the initialization signal terminal.

9. The pixel circuit according to claim 7, wherein: The reset signal terminal and the first control signal terminal are the same signal terminal.

10. The pixel circuit according to any one of claims 1 to 9, wherein: Also includes: The light emitting control circuit is coupled to the second electrode of the driving transistor and the light emitting device, and is configured to connect the second electrode of the driving transistor and the light emitting device in response to a signal at a light emitting control signal terminal during the light emitting phase.

11. The pixel circuit according to claim 10, wherein: The light emitting control circuit includes: a sixth transistor; The gate of the sixth transistor is coupled to the light emitting control signal terminal, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the light emitting device.

12. The pixel circuit according to claim 10, wherein: The light emitting control signal terminal and the second control signal terminal are the same signal terminal.

13. The pixel circuit according to any one of claims 1 to 12, wherein: Also includes: The switch control circuit is located between the third control circuit, the reset circuit and the gate of the driving transistor, and is configured to connect the reset circuit and the gate of the driving transistor in response to the signal at the light-emitting control signal end during the reset phase, and to connect the third control circuit and the gate of the driving transistor in response to the signal at the light-emitting control signal end during the data compensation phase.

14. The pixel circuit according to claim 13, wherein: The switch control circuit includes: a switch transistor; The gate of the switching transistor is coupled to the light emitting control signal terminal, the first electrode of the switching transistor is coupled to the gate of the driving transistor, and the second electrode of the switching transistor is coupled to the third control circuit and the reset circuit.

15. The pixel circuit according to any one of claims 1 to 14, wherein: The operation process of the pixel circuit further includes: a bias phase, the bias phase being located before the reset phase, and / or the bias phase being located between the reset phase and the data compensation phase; The pixel circuit further includes a bias circuit coupled to the gate of the driving transistor and configured to, in response to the signal of the fourth control signal terminal during the bias phase, bias the bias voltage signal terminal to the gate of the driving transistor. The signal is provided to the gate of the driving transistor.

16. The pixel circuit according to claim 15, wherein: The bias circuit includes: a seventh transistor; The gate of the seventh transistor is coupled to the fourth control signal terminal, the first electrode of the seventh transistor is coupled to the bias voltage signal terminal, and the second electrode of the seventh transistor is coupled to the gate of the driving transistor.

17. The pixel circuit according to any one of claims 1 to 16, wherein: The first reference voltage signal terminal and the second reference voltage signal terminal are the same signal terminal.

18. The pixel circuit according to any one of claims 1 to 17, wherein: The data compensation stage includes: a first capture stage and a second capture stage; In the first acquisition phase, the third control circuit turns on the gate and the second electrode of the driving transistor in response to the valid level of the signal at the third control signal terminal; in the second acquisition phase, the third control circuit turns on the gate and the second electrode of the driving transistor in response to the valid level of the signal at the third control signal terminal, and the data writing circuit provides the data voltage at the data signal terminal to the first node in response to the valid level of the signal at the scan signal terminal; or In the first acquisition phase, the third control circuit turns on the gate and the second electrode of the driving transistor in response to the effective level of the signal at the third control signal terminal, and the data write circuit provides the data voltage at the data signal terminal to the first node in response to the effective level of the signal at the scan signal terminal; in the second acquisition phase, the third control circuit turns on the gate and the second electrode of the driving transistor in response to the effective level of the signal at the third control signal terminal.

19. A display device, wherein: The method comprises the pixel circuit according to any one of claims 1 to 18.

20. A driving method for a pixel circuit according to any one of claims 1 to 18, wherein: include: In the reset phase, the first control circuit provides a signal from the first reference voltage signal terminal to the first node in response to a signal from the first control signal terminal; During the data compensation phase, the third control circuit responds to the effective level of the signal at the third control signal terminal. The gate and the second electrode of the driving transistor are turned on; the data writing circuit provides the data voltage of the data signal terminal to the first node in response to the effective level of the signal of the scanning signal terminal; The coupling control circuit couples the voltage of the first node to the gate of the driving transistor; During the light emitting phase, the second control circuit provides a signal from the second reference voltage signal terminal to the first node in response to a signal from the second control signal terminal; The coupling control circuit couples the data voltage of the first node to the gate of the driving transistor.

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