Micro-capacitor

Abstract

A micro-capacitor comprising: - a structured support comprising a substrate and micro-pillars disposed on one face of the substrate, - a first electrode disposed on the structured support, - a second electrode, and - an insulating material disposed between the first and second electrodes.

Description

[0001] DESCRIPTION

[0002] TITLE: Micro-capacitor

[0003] Technical field

[0004] The present invention relates to a micro-capacitor, an electronic system comprising said micro-capacitor, and a method of manufacturing said micro-capacitor.

[0005] State of the prior art

[0006] Miniaturized capacitors, also called microcapacitors, microcapacitors or integrated capacitors, are electronic components with a small physical size.

[0007] Such miniaturization is essential in the current development of electronic devices, in particular those known as embedded, portable or smart, such as for example integrated circuits, implantable or portable medical devices, smartphones, tablets, smartwatches, navigation systems, laptops, sensors, in particular embedded, connected objects, in particular of the loT type (for Internet of Things in English), and practically any equipment requiring compact integrated circuits and increasingly smaller electronic devices.

[0008] The current development of miniaturized capacitors faces various problems.

[0009] First, due to their small size, microcapacitors generally have reduced energy density and capacity.

[0010] It is therefore essential to find solutions to increase the energy density (i.e. the amount of energy that a micro-capacitor can provide in a given space) and the capacity of micro-capacitors in order to maintain high electrical performance in a small format, and this in a sustainable manner.

[0011] Furthermore, with the reduction in their dimensions, mechanical and thermal constraints can have a greater impact on the reliability and longevity of microcapacitors.

[0012] It is therefore necessary to develop more reliable and safer microcapacitors, particularly those free from the risk of short circuits, explosions or leaks, especially when used in implantable medical devices or other critical applications.

[0013] Furthermore, manufacturing miniaturized capacitors with high precision and high electrical performance can be difficult and expensive.

[0014] The manufacturing processes for micro-capacitors must therefore be adapted to avoid defects and guarantee constant performance, while having reduced costs.

[0015] The invention aims to further improve micro-capacitors, in particular by improving their electrical performance, their reliability and their manufacturing.

[0016] Statement of the invention

[0017] Micro-capacitor

[0018] The invention thus relates, according to a first of its aspects, to a microcapacitor comprising:

[0019] - an architectural support comprising a substrate and micro-pillars arranged on one side of the substrate,

[0020] - a first electrode placed on the architectural support,

[0021] - a second electrode, and

[0022] - an insulating material disposed between the first and second electrodes.

[0023] The term “architectural support” means a support comprising a structure on its surface, for example the presence of micro-structures and / or nano-structures, such as for example micro-pillars and / or nano-wires, in comparison with a support without a structure on its surface, generally called a “planar or two-dimensional (2D) support”.

[0024] Compared to a flat (2D) support, the use of the architectural support can make it possible to obtain a particularly large contact surface between the insulating material and the first and second electrodes, which is particularly advantageous insofar as the capacitance of the micro-capacitor is directly proportional to this contact surface.

[0025] Thus, the reduced size of the micro-capacitor is compensated by this large contact surface which is permitted by the use of the architectural support.

[0026] In the present application, the architectural support comprising said micro-pillars is a so-called three-dimensional (3D) architectural support.

[0027] Each micro-pillar may have a free surface. The architectural support may comprise nano-wires arranged on the free surface of at least a portion of the micro-pillars.

[0028] In the present application, the architectural support comprising both micropillars and nanowires is a so-called four-dimensional (4D) architectural support.

[0029] Thus, the architectural support can be a so-called three-dimensional (3D) architectural support or a so-called four-dimensional (4D) architectural support.

[0030] The face of the substrate can be free of nanowires.

[0031] This characteristic according to which said face of the substrate can be devoid of nano-wires can make it possible to simplify the manufacturing process of the support, in particular by eliminating a lithography step, and without significantly reducing the surface area developed by the support.

[0032] Indeed, the presence of nanowires on the face of the substrate only contributes marginally to the surface area developed by the support, in comparison with the nanowires arranged on the free surface of at least part of the micro-pillars.

[0033] Furthermore, when the support has nanowires on the face of the substrate, these nanowires present a risk of breakage, in particular when the support is used for the manufacture of a micro-energy storage device.

[0034] For example, the deposition of resin on the nanowires arranged on the face of the substrate during a lithography step can lead to damage or even breakage of these nanowires.

[0035] This may cause short circuits within the said micro energy storage device in which the medium is or will be integrated.

[0036] The characteristic according to which said face of the substrate can be devoid of nanowires can thus make it possible to limit, or even eliminate, this risk of short circuit, and thus improve the safety and reliability of said micro-energy storage device in which the support is or will be integrated.

[0037] The nanowires can be arranged on the free surface of each of the micro-pillars.

[0038] The nanowires can be arranged over the entire free surface of at least part of the micro-pillars, in particular over the entire free surface of each of the micro-pillars.

[0039] Alternatively, the nanowires are arranged only on a portion of the free surface of at least a portion of the micro-pillars, in particular only on a portion of the free surface of each of the micro-pillars.

[0040] Each micro-pillar may have a top face and one or more side faces. The side face(s) are preferably substantially perpendicular to the face of the substrate.

[0041] The upper face is preferably substantially parallel to the face of the substrate.

[0042] In an exemplary embodiment, the nanowires are arranged only on the lateral face(s) of at least part of the micro-pillars, in particular only on the lateral face(s) of each of the micro-pillars.

[0043] This therefore means that, in this embodiment, the upper faces of the micro-pillars are devoid of nano-wires.

[0044] This can simplify the support manufacturing process, in particular by eliminating a lithography step, without significantly reducing the surface area developed by the support.

[0045] Indeed, the presence of nanowires on the upper faces of the micro-pillars only contributes marginally to the surface area developed by the support, in comparison with the nanowires arranged on the lateral faces of the micro-pillars.

[0046] Furthermore, when the support has nanowires on the upper faces of the micro-pillars, these nanowires present a risk of breakage, in particular when the support is used for the manufacture of a micro-energy storage device.

[0047] For example, the deposition of resin on the nanowires arranged on the upper faces of the micro-pillars during a lithography step can lead to damage, or even breakage, of these nanowires.

[0048] This may cause short circuits within the said micro energy storage device in which the medium is or will be integrated.

[0049] The characteristic according to which the nanowires can be arranged only on the lateral face(s) of at least part of the micro-pillars, in particular only on the lateral face(s) of each of the micro-pillars, can thus make it possible to limit, or even eliminate, this risk of short circuit, and thus improve the safety and reliability of said micro-energy storage device in which the support is or will be integrated.

[0050] In an exemplary embodiment, each micro-pillar is solid, in particular over all or part of its height.

[0051] In an exemplary embodiment, each micro-pillar is hollow, in particular over all or part of its height. The presence of such micro-pillars can make it possible to further increase the surface area developed by the support.

[0052] Each micro-pillar may have a proximal end connected to the face of the substrate and a distal end. In an exemplary embodiment, each micro-pillar is hollow over a portion of its height, in particular at its distal end.

[0053] In an exemplary embodiment, each micro-pillar comprises a first solid part which is connected to the face of the substrate and which continues with a second hollow part. The presence of such micro-pillars can make it possible to further increase the surface area developed by the support.

[0054] Preferably, each micro-pillar has an elongated shape.

[0055] Preferably, each micro-pillar extends from the face of the substrate, in particular in a rectilinear manner, in particular in a manner substantially perpendicular to the face of the substrate.

[0056] Each micro-pillar may have a cylindrical, conical, truncated cone or any other shape, preferably cylindrical.

[0057] The term "cylindrical shape" refers to any type of cylinder such as a right circular cylinder, a square cylinder, or a rectangular cylinder.

[0058] In an exemplary embodiment, each micro-pillar comprises a first cylindrical part which is connected to the face of the substrate and which continues with a second conical or truncated conical part.

[0059] Each micro-pillar may have a circular, elliptical or polygonal cross-section, for example triangular, square, rectangular, pentagonal, hexagonal, cross-shaped, star-shaped, etc.

[0060] In an exemplary embodiment, each micro-pillar has a circular cross-section, for example with a diameter of between 2 pm and 6 pm, in particular between 3 pm and 5 pm.

[0061] In an exemplary embodiment, each micro-pillar has a triangular, square or rectangular cross-section, for example with sides each having a length of between 2 pm and 6 pm, in particular between 3 pm and 5 pm.

[0062] In a preferred embodiment, each micro-pillar has a square-shaped cross-section, for example with sides each having a length of between 2 μm and 6 μm, in particular between 3 μm and 5 μm. A square-shaped cross-section can make it possible to maximize the lateral surface area developed by the micro-pillars, and thus maximize the surface area developed by the support.

[0063] In a preferred embodiment, each micro-pillar has a cylindrical shape and has a square or rectangular cross-section, preferably square, with, for example, sides each having a length of between 2 pm and 6 pm, in particular between 3 pm and 5 pm.

[0064] In this preferred embodiment, each micro-pillar has a top face and four side faces.

[0065] In this embodiment, the nanowires are arranged only on the lateral faces of at least a portion of the micropillars, in particular of each of the micropillars. Thus, in this preferred embodiment, the upper faces of the micropillars are devoid of nanowires.

[0066] Each micro-pillar can have a cross-section with a surface area of ​​between 2 pm 2 and 40 pm 2 , preferably between 4 pm 2 and 36 pm 2, and more preferably between 9 pm 2 and 25 pm 2 .

[0067] Each micro-pillar may have a length greater than or equal to 10 pm, preferably greater than or equal to 20 pm, more preferably greater than or equal to 30 pm, and even more preferably greater than or equal to 40 pm.

[0068] The terms "length" and "height" are equivalent.

[0069] Each micro-pillar may have a length less than or equal to 400 pm, preferably less than or equal to 350 pm, more preferably less than or equal to 300 pm, and even more preferably less than or equal to 250 pm.

[0070] Each micro-pillar may have a length ranging from 10 pm to 400 pm, preferably ranging from 20 pm to 350 pm, more preferably ranging from 30 pm to 300 pm, and even more preferably ranging from 40 pm to 250 pm.

[0071] In an exemplary embodiment, each micro-pillar has a length greater than 200 pm, preferably greater than 200 pm and less than or equal to 350 pm, more preferably greater than 200 pm and less than or equal to 300 pm, even more preferably greater than 200 pm and less than or equal to 250 pm.

[0072] The micro-pillars can be arranged on the face of the substrate in rows, in particular each rectilinear, in particular parallel to each other.

[0073] In an exemplary embodiment, each row of micro-pillars comprises a space between two adjacent micro-pillars whose length is between 2 pm and 6 pm, in particular between 3 pm and 5 pm.

[0074] In an exemplary embodiment, two adjacent rows of micro-pillars are separated by a distance of between 0 pm and 6 pm, in particular between 0 pm and 5 pm, or even between 1 and 5 pm.

[0075] In one exemplary embodiment, two adjacent rows of micro-pillars are arranged in a staggered manner. In a preferred exemplary embodiment, the substrate and the micro-pillars are formed as a single piece.

[0076] . This feature has the following advantages:

[0077] - provides improved mechanical resistance due to better cohesion of the support,

[0078] - avoids the risk of cracking or detachment of the micro-pillars. Indeed, the micro-pillars are “hollowed” into the substrate and are thus laterally protected (see figures 1 and 2) significantly increases the reliability and lifespan of a device comprising such an architectural support simplifies the manufacturing process and contributes to improving its reproducibility on an industrial scale.

[0079] For example, micro-pillars are obtained by a deep reactive ion etching technique (also called DRIE for Deep Reactive Ion Etching in English) of a wafer, for example made of silicon.

[0080] The substrate and the micro-pillars may comprise, or even be made of, a material suitable for microfabrication techniques, particularly for microelectronics.

[0081] The substrate and the micro-pillars may comprise, or even be made of, a semiconductor material or an insulating material, in particular a dielectric.

[0082] The substrate and micro-pillars may comprise, or even be made of, a ceramic material.

[0083] The substrate and the micro-pillars comprise, or are made of, silicon (Si), silica (SiC>2), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), silicon nitride (SisN4) and / or indium phosphide (InP), preferably silicon (Si).

[0084] Each nanowire can contain a metal oxide or a mixture of metal oxides.

[0085] For example, each nanowire comprises silica (SiO2), zinc oxide (ZnO), titanium dioxide (TiO2), indium oxide (I n2O3), gallium oxide (Ga2Os), bismuth oxide (Bi20s) and / or tin dioxide (SnO2), preferably silica (SiO2), zinc oxide (ZnO) and / or titanium dioxide (TiO2), more preferably silica (SiO2) and / or zinc oxide (ZnO), and even more preferably silica (SiO2). Each nanowire may further comprise a metal or a metal alloy, preferably capable of being deposited by an atomic layer deposition technique (also called an ALD technique for Atomic Layer Deposition in English).

[0086] For example, each nanowire comprises platinum (Pt), gold (Au), silver (Ag), aluminum (Al) and / or gallium (Ga), preferably platinum (Pt), gold (Au) and / or silver (Ag), and more preferably platinum (Pt).

[0087] Preferably, each nanowire comprises silica (SiC>2), and in particular platinum (Pt).

[0088] In an exemplary embodiment, each nanowire is made of silica (SiO2) and platinum (Pt).

[0089] Each nanowire may have a proximal end, a distal end, and a body connecting the proximal end to the distal end.

[0090] The body can be full.

[0091] The body may have an elongated shape, particularly a cylindrical shape.

[0092] The body may have a curved shape.

[0093] The body may have a circular or elliptical cross-section, preferably circular.

[0094] The proximal end can be connected to the free surface of a micro-pillar.

[0095] The distal end may have a convex shape, including a spherical shape, for example a sphere, half-sphere, or portion-sphere shape.

[0096] The body may comprise, or even consist of, a metal oxide or a mixture of metal oxides, preferably capable of being deposited by a chemical vapor deposition technique (also called CVD technique for Chemical Vapor Deposition in English), preferably by a low-pressure chemical vapor deposition technique (also called LPCVD technique for Low Pressure Chemical Vapor Deposition in English) or by an atomic layer deposition technique (also called ALD technique for Atomic Layer Deposition in English).

[0097] For example, the body comprises, or is made of, silica (SiO2), zinc oxide (ZnO), titanium dioxide (TiC>2), indium oxide (I n2C>3), gallium oxide (Ga2Os), bismuth oxide (Bi2C>3) and / or tin dioxide (SnC>2), preferably silica (SiC>2), zinc oxide (ZnO) and / or titanium dioxide (TiO2), more preferably silica (SiO2) and / or zinc oxide (ZnO), and even more preferably silica (SiO2).

[0098] In a preferred embodiment, the body comprises, or is made of, silica (SiO2). The proximal end may comprise, or be made of, a metal oxide or a mixture of metal oxides.

[0099] For example, the proximal end comprises, or is made of, silica (SiC>2), zinc oxide (ZnO), titanium dioxide (TiC>2), indium oxide (I n2C>3), gallium oxide (Ga2Os), bismuth oxide (Bi2Os) and / or tin dioxide (SnO2), preferably silica (SiO2), zinc oxide (ZnO) and / or titanium dioxide (TiO2), more preferably silica (SiO2) and / or zinc oxide (ZnO), and even more preferably silica (SiO2).

[0100] In a preferred embodiment, the proximal end comprises, or is made of, silica (SiO2).

[0101] The distal end may comprise, or even be made of, a metal or a metal alloy, preferably capable of being deposited by an atomic layer deposition technique (also called ALD technique for Atomic Layer Deposition in English).

[0102] For example, the distal end comprises, or is made of, platinum (Pt), gold (Au), silver (Ag), aluminum (Al) and / or gallium (Ga), preferably platinum (Pt), gold (Au) and / or silver (Ag), and more preferably platinum (Pt).

[0103] In a preferred embodiment, the distal end comprises, or is made of, platinum (Pt).

[0104] Each nanowire may have a length greater than or equal to 100 nm, preferably greater than or equal to 200 nm, more preferably greater than or equal to 300 nm, even more preferably greater than or equal to 400 nm, and in particular greater than or equal to 500 nm.

[0105] In an exemplary embodiment, each nanowire has a length greater than or equal to 1 pm.

[0106] Each nanowire may have a length less than or equal to 10 pm, preferably less than or equal to 9 pm, more preferably less than or equal to 8 pm, even more preferably less than or equal to 7 pm, and in particular less than or equal to 6 pm.

[0107] In an exemplary embodiment, each nanowire has a length less than or equal to 5 pm.

[0108] Each nanowire may have a length ranging from 100 nm to 10 pm, preferably ranging from 200 nm to 9 pm, more preferably ranging from 300 nm to 8 pm, even more preferably ranging from 400 nm to 7 pm, and in particular ranging from 500 nm to 6 pm. In an exemplary embodiment, each nanowire has a length ranging from 1 pm to 5 pm.

[0109] Each nanowire may have a cross-section whose largest dimension is greater than or equal to 20 nm, preferably greater than or equal to 30 nm, more preferably greater than or equal to 40 nm, and even more preferably greater than or equal to 50 nm.

[0110] Each nanowire may have a cross-section whose largest dimension is less than or equal to 250 nm, preferably less than or equal to 240 nm, more preferably less than or equal to 230 nm, even more preferably less than or equal to 220 nm, and in particular less than or equal to 210 nm.

[0111] Each nanowire may have a cross-section whose largest dimension is between 20 nm and 250 nm, preferably between 30 nm and 240 nm, more preferably between 40 nm and 230 nm, and even more preferably between 50 nm and 220 nm.

[0112] In an exemplary embodiment, each nanowire has a cross-section whose largest dimension is between 20 nm and 200 nm, and preferably between 30 nm and 190 nm.

[0113] The density of nanowires can be between 10 million nanowires / mm 2 and 50 million nanowires / mm 2 , preferably between 10 million nanowires / mm 2 and 40 million nanowires / mm 2 , more preferably between 10 million nano-wires / mm 2 and 30 million nanowires / mm 2 , and even more preferably between 10 million nanowires / mm 2 and 25 million nanowires / mm 2 .

[0114] Such a density of nanowires is particularly advantageous insofar as it can allow particularly high gains to be obtained in terms of surface area developed by the support.

[0115] Each nanowire can be oriented randomly.

[0116] Nanowires can be entangled.

[0117] Each nanowire may comprise a first part which is connected to the free surface of a micro-pillar and which is rectilinear and orthogonal to said free surface, this first part continuing with a second part which is curved.

[0118] The face of the substrate may have a square or rectangular shape, in particular with sides each having a length of between 50 pm and 20 mm, preferably between 100 pm and 2.5 mm.

[0119] The face of the substrate may have a surface area of ​​between 2500 pm 2 and 400 mm 2 , preferably between 10000 pm 2 and 6.25 mm 2 Such surface values ​​correspond to the face of the substrate without micro-pillars and nano-wires.

[0120] The first electrode, the second electrode and the insulating material may each be in the form of a thin layer, in particular having a thickness ranging from 1 nm to 250 nm, and preferably ranging from 2 nm to 225 nm.

[0121] The first electrode, the second electrode and the insulating material may each have a thickness less than or equal to 250 nm, preferably less than or equal to 225 nm.

[0122] The first electrode, the second electrode and the insulating material may each have a thickness greater than or equal to 1 nm, preferably greater than or equal to 2 nm.

[0123] The first electrode can cover the architectural support.

[0124] The insulating material may surround or cover the first electrode.

[0125] The second electrode may surround or cover the insulating material.

[0126] When the architectural support is said to be three-dimensional (3D), the first electrode can be arranged on the micro-pillars of the architectural support, in particular can surround or cover each micro-pillar, in particular can surround or cover the free surface of each micro-pillar.

[0127] When the architectural support is said to be four-dimensional (4D), the first electrode can be arranged on the nanowires and micropillars of the architectural support, in particular can surround or cover each nanowire and each micropillar, in particular can surround or cover the proximal end, the distal end and the body of each nanowire and the free surface of each micropillar.

[0128] The first electrode and the second electrode can each be made of an electronically conductive material, in particular metallic.

[0129] For example, the electronically conductive material is a material that can be deposited using a chemical vapor deposition (CVD) technique, more preferably using an atomic layer deposition (ALD) technique.

[0130] For example, the electronically conductive material comprises, or is even made of, a metal, in particular a transition metal, or a metal alloy, in particular of transition metals.

[0131] For example, the electronically conductive material comprises, or is made of, platinum (Pt), gold (Au), silver (Ag), copper (Cu) or a mixture thereof, preferably platinum (Pt). Preferably, the first electrode and the second electrode are each electronically conductive, in particular metallic.

[0132] The first electrode and the second electrode may each have a thickness ranging from 10 to 50 nm, preferably ranging from 15 nm to 45 nm, and more preferably ranging from 20 nm to 40 nm.

[0133] The first electrode and the second electrode can each be deposited by a chemical vapor deposition (CVD) technique, more preferably by an atomic layer deposition (ALD) technique.

[0134] The first electrode can be in direct contact with the architectural support.

[0135] When the architectural support is said to be three-dimensional (3D), the first electrode can be in direct contact with the micro-pillars, in particular in direct contact with the free surface of each micro-pillar.

[0136] When the architectural support is said to be four-dimensional (4D), the first electrode may be in direct contact with the nanowires and micropillars of the architectural support, in particular in direct contact with the proximal end, the distal end and the body of each nanowire and in direct contact with the free surface of each micropillar.

[0137] The first electrode and the second electrode may comprise, or even be made of, the same material.

[0138] The first electrode and the second electrode can have the same thickness.

[0139] The insulating material is preferably a dielectric insulating material.

[0140] The insulating material can have a relative permittivity (c r) greater than or equal to 8.0, preferably greater than or equal to 8.1, more preferably greater than or equal to 8.2, even more preferably greater than or equal to 8.3, and in particular greater than or equal to 8.4, or even greater than or equal to 8.5.

[0141] For example, the insulating material may have a relative permittivity (c r ) greater than or equal to 15, 20, 25, 40, 100, 120, 1000, 4000, 5000, or greater than or equal to 10000.

[0142] Such values ​​of relative permittivity (c r ) are advantageous because they allow to obtain a micro-capacitor with a high capacitance. Indeed, the capacitance of the micro-capacitor is directly proportional to the relative permittivity (c r ) of the insulating material.

[0143] The relative permittivity (c r) can be measured at room temperature, particularly at frequencies within the radio spectrum. For example, the insulating material is a material that can be deposited using a chemical vapor deposition (CVD) technique, more preferably using an atomic layer deposition (ALD) technique.

[0144] The insulating material is preferably a ceramic material.

[0145] The insulating material may include, or even consist of, a metal oxide or a mixture of metal oxides.

[0146] The metal oxide can be a simple oxide (i.e., having only one type of metal or metal cation bound to oxygen) or a mixed oxide (i.e., having more than one type of metal or metal cation bound to oxygen).

[0147] For example, the insulating material comprises, or is made of, titanium dioxide (TiO2), silica (SiC>2), alumina (AI2O3), hafnium dioxide (HfC>2), barium (meta)titanate (BaTiOs) or a mixture thereof.

[0148] Preferably, the insulating material comprises, or is made of, alumina (AI2O3).

[0149] Indeed, alumina (AI2O3) has a high breakdown voltage, a high relative permittivity (c r ) and can be easily deposited using a chemical vapor deposition (CVD) technique, more preferably using an atomic layer deposition (ALD) technique.

[0150] The insulating material may have a thickness ranging from 1 nm to 250 nm, preferably ranging from 1 nm to 225 nm, more preferably ranging from 1 nm to 200 nm, and even more preferably ranging from 2 nm to 200 nm.

[0151] The thickness of the insulating material influences not only the capacitance but also the breakdown voltage of the microcapacitor. The objective is to obtain a microcapacitor with not only a high capacitance but also a high breakdown voltage. However, the capacitance increases when the thickness of the insulating material decreases while the breakdown voltage increases when the thickness of the insulating material increases. Thus, the thickness of the insulating material is preferably chosen so as to obtain a compromise between breakdown voltage and capacitance.

[0152] The insulating material may be deposited by a chemical vapor deposition (CVD) technique, more preferably by an atomic layer deposition (ALD) technique. The insulating material may be in direct contact with at least one of the first and second electrodes, in particular with the first electrode and with the second electrode.

[0153] In an example of implementation,

[0154] - the first electrode and the second electrode are each made of an electronically conductive material, in particular metallic, comprising, or even consisting of, platinum (Pt), and the insulating material comprises, or even consists of, alumina (AI2O3).

[0155] In an example of implementation,

[0156] - the first electrode is placed on the architectural support,

[0157] - the insulating material is placed on the first electrode, and

[0158] - the second electrode is placed on the insulating material.

[0159] In an example of implementation,

[0160] - the first electrode covers the architectural support,

[0161] - the insulating material covers or surrounds the first electrode, and

[0162] - the second electrode covers or surrounds the insulating material.

[0163] In an exemplary embodiment in which the architectural support is said to be three-dimensional (3D),

[0164] - the first electrode is arranged on the micro-pillars of the architectural support, in particular covers or surrounds each micro-pillar, in particular covers or surrounds the free surface of each micro-pillar,

[0165] - the insulating material is arranged on the first electrode, in particular covers or surrounds the first electrode, and

[0166] - the second electrode is arranged on the insulating material, in particular covers or surrounds the insulating material.

[0167] In an exemplary embodiment in which the architectural support is said to be four-dimensional (4D),

[0168] - the first electrode is arranged on the nanowires and micropillars of the architectural support, in particular surrounds or covers each nanowire and each micropillar, in particular surrounds or covers the proximal end, the distal end and the body of each nanowire and the free surface of each micropillar,

[0169] - the insulating material is arranged on the first electrode, in particular covers or surrounds the first electrode, and

[0170] - the second electrode is arranged on the insulating material, in particular covers or surrounds the insulating material. The micro-capacitor is preferably a metal-insulator-metal type micro-capacitor (also called MIM for Metal-Insulator-Metal in English).

[0171] The microcapacitor can have a capacitance between 0.38 pF / cm 2 and 3.8 mF / cm 2 .

[0172] For example, for a so-called four-dimensional (4D) architectural support presenting a developed surface gain compared to a flat (2D) substrate of 1000 (i.e. AEF = 1000, for Area Enlargement Factor in English), the capacity of the micro-capacitor is equal to 3.8 mF / cm 2 for a thickness of 2 nm of insulating material AI2O3, and is equal to

[0173] 37 pF / cm 2 for a thickness of 200 nm of AI2O3 insulating material.

[0174] For example, for a so-called four-dimensional (4D) architectural support presenting a developed surface gain compared to a flat (2D) substrate of 10 (i.e. AEF = 10, for Area Enlargement Factor in English), the capacity of the micro-capacitor is equal to

[0175] 38 pF / cm 2 for a thickness of 2 nm of insulating material AI2O3, and is equal to 0.38 pF / cm 2 for a thickness of 200 nm of AI2O3 insulating material.

[0176] The micro-capacitor can have a breakdown voltage between 1 V and 170 V, especially between 1.7 V and 160 V.

[0177] For example, for a 2 nm thickness of AI2O3 insulating material, the breakdown voltage is 1.7 V.

[0178] For example, for a thickness of 200 nm of AI2O3 insulating material, the breakdown voltage is 160 V.

[0179] The micro-capacitor may comprise at least one contact orifice passing through the second electrode and the insulating material so as to expose a contact zone, in particular predefined, of the first electrode.

[0180] The contact orifice may allow electrical contact to be made with the first electrode at said contact area.

[0181] The contact orifice can extend along an axis substantially perpendicular to the face of the substrate of the architectural support (i.e. along an axis substantially parallel to the extension axis of the micro-pillars).

[0182] The contact orifice may comprise a first portion passing through the second electrode and a second portion passing through the insulating material.

[0183] The contact area is preferably located at an area of ​​the substrate face that does not have micro-pillars.

[0184] This can eliminate the risk of breakage of the micro-pillars when the contact zone is located on the micro-pillars. The micro-capacitor can include at least one protective layer, in particular thermal, arranged between the architectural support and the first electrode.

[0185] The protective layer can be placed on the architectural support.

[0186] The first electrode can be arranged on the protective layer.

[0187] When the architectural support is said to be three-dimensional (3D), the protective layer can be arranged on the micro-pillars of the architectural support, in particular can surround or cover each micro-pillar, in particular can surround or cover the free surface of each micro-pillar.

[0188] When the architectural support is said to be four-dimensional (4D), the protective layer can be arranged on the nanowires and micropillars of the architectural support, in particular can surround or cover each nanowire and each micropillar, in particular can surround or cover the proximal end, the distal end and the body of each nanowire and the free surface of each micropillar.

[0189] The protective layer can cover the architectural support.

[0190] The first electrode may cover or surround the protective layer.

[0191] The protective layer can be in direct contact with the architectural support and with the first electrode.

[0192] The protective layer can be deposited using a chemical vapor deposition (CVD) technique, more preferably using an atomic layer deposition (ALD) technique.

[0193] The protective layer may have a thickness ranging from 10 nm to 80 nm, preferably ranging from 20 nm to 70 nm, more preferably ranging from 30 nm to 60 nm, and even more preferably ranging from 35 nm to 55 nm.

[0194] The protective layer may include, or even be made of, an insulating material.

[0195] For example, the insulating material is a material that can be deposited using a chemical vapor deposition (CVD) technique, more preferably using an atomic layer deposition (ALD) technique.

[0196] The insulating material is preferably a ceramic material.

[0197] The insulating material may include, or even consist of, a metal oxide or a mixture of metal oxides.

[0198] For example, the insulating material comprises, or is even made of, alumina (AI2O3). The protective layer can protect the architectural support, in particular the so-called four-dimensional (4D) architectural support, against high temperatures, in particular greater than or equal to 400°C, preferably greater than or equal to 500°C, more preferably greater than or equal to 600°C, and even more preferably greater than or equal to 700°C.

[0199] Such temperature values ​​may be necessary, for example, to form a layer of a mixed metal oxide (e.g., BaTiOs) on the structured support by ALD from several layers of simple oxides (e.g., BaO and TiC^), particularly deposited sequentially. Such heat treatments are crystallization annealing.

[0200] However, the exposure of the architectural support, in particular the so-called four-dimensional (4D) architectural support, to such temperature values ​​may, for example, alter the structure and / or the composition of the architectural support, in particular the so-called four-dimensional (4D) architectural support.

[0201] For example, exposure of the architectural support, in particular the so-called four-dimensional (4D) architectural support, to such temperature values ​​can cause the diffusion of platinum (Pt) from the nanowires into the silicon (Si) of the micro-pillars and / or the substrate, thus forming a non-conductive SiPt alloy.

[0202] Thus, when the architectural support, in particular the so-called four-dimensional (4D) architectural support, is exposed to such temperature values, the structure and / or composition of the architectural support, in particular the so-called four-dimensional (4D) architectural support, can be preserved thanks to the presence of the protective layer.

[0203] Electronic system comprising a micro-capacitor

[0204] The invention also relates, according to another of its aspects, to an electronic system comprising a micro-capacitor as defined above.

[0205] The electronic system may include at least one data reception system, in particular wireless.

[0206] The electronic system may include at least one data transmission system, in particular wireless.

[0207] The electronic system may include at least one data processing system, such as for example a microcontroller or microprocessor.

[0208] The electronic system may include at least one data storage system. The electronic system may include at least one data sensor.

[0209] Preferably, the electronic system is energy self-sufficient.

[0210] Preferably, the electronic system operates in real time.

[0211] Preferably, the electronic system is embedded, portable and / or intelligent.

[0212] For example, the electronic system is chosen from an integrated circuit (also called an electronic chip or microchip in English), an implantable or portable medical device, a smartphone, a tablet, a connected watch, a navigation system, a laptop, a sensor, in particular an embedded one, a connected object, in particular of the loT type (for Internet of Things in English), etc.

[0213] Manufacturing process of a micro-capacitor

[0214] The invention also relates, according to another of its aspects, to a method for manufacturing a micro-capacitor as defined above, comprising at least the following steps: a) providing an architectural support comprising a substrate and micro-pillars arranged on one face of the substrate, b) depositing a first electrode in the form of a thin layer on the architectural support, c) depositing an insulating material in the form of a thin layer on the first electrode, d) depositing a second electrode in the form of a thin layer on the insulating material.

[0215] The architectural support, the first electrode, the insulating material and the second electrode may each have one or more of the characteristics described above.

[0216] Preferably, step b) is implemented so as to cover the architectural support.

[0217] Preferably, step c) is carried out so as to cover or surround the first electrode.

[0218] Preferably, step d) is carried out so as to cover or surround the insulating material.

[0219] Each micro-pillar can have a free surface.

[0220] The architectural support may comprise nanowires arranged on the free surface of at least a portion of the micro-pillars. Thus, the architectural support may be a so-called three-dimensional (3D) architectural support or a so-called four-dimensional (4D) architectural support.

[0221] The first electrode, the second electrode and the insulating material may each have a thickness less than or equal to 250 nm, preferably less than or equal to 225 nm.

[0222] The first electrode, the second electrode and the insulating material may each have a thickness greater than or equal to 1 nm, preferably greater than or equal to 2 nm.

[0223] The first electrode, the second electrode and the insulating material may each have a thickness ranging from 1 nm to 250 nm, and preferably ranging from 2 nm to 225 nm.

[0224] The first electrode and the second electrode may each have a thickness ranging from 10 to 50 nm, preferably ranging from 15 nm to 45 nm, and more preferably ranging from 20 nm to 40 nm.

[0225] The insulating material may have a thickness ranging from 1 nm to 250 nm, preferably ranging from 1 nm to 225 nm, more preferably ranging from 1 nm to 200 nm, and even more preferably ranging from 2 nm to 200 nm.

[0226] The first electrode and the second electrode can each be made of an electronically conductive material, in particular metallic.

[0227] For example, the electronically conductive material comprises, or is even made of, a metal, in particular a transition metal, or a metal alloy, in particular of transition metals.

[0228] For example, the electronically conductive material comprises, or is made of, platinum (Pt), gold (Au), silver (Ag), copper (Cu) or a mixture thereof,

[0229] Preferably, the electronically conductive material comprises, or is made of, platinum (Pt).

[0230] Preferably, the first electrode and the second electrode are each electronically conductive, in particular metallic.

[0231] At least one of steps b), c) and d), in particular each of steps b), c) and d), may be implemented by a thin-film deposition technique, preferably by a chemical vapor deposition (CVD) technique, more preferably by an atomic layer deposition (ALD) technique, for example at a temperature ranging from 150°C to 550°C, preferably ranging from 200°C to 500°C, and more preferably ranging from 250°C to 450°C. For example, the atomic layer deposition (ALD) technique is implemented using a “PICOSUN® R-200 Advanced” reactor.

[0232] The use of the atomic layer deposition (ALD) technique is advantageous in that it can allow the deposition of thin layers with perfect control of the thickness deposited.

[0233] Indeed, the thickness of the layer deposited by ALD increases linearly with the number of cycles, and given that each cycle deposits a fixed quantity of material in a perfectly predictable and reproducible manner, the thickness of the layer deposited is thus perfectly controlled by the number of cycles carried out.

[0234] The use of the atomic layer deposition (ALD) technique is also advantageous in that it can allow the deposition of thin layers with perfect uniformity, even on large surfaces and surfaces with complex topography such as the surface of the architectural support.

[0235] This makes it possible to obtain thin layers whose thickness is extremely uniform across the entire structured support.

[0236] For example, since the thickness of the insulating material is inversely proportional to the capacitance of the micro-capacitor, controlling the thickness and uniformity of the deposited layer of insulating material is essential to control the electrical performance of the micro-capacitor, particularly in terms of capacitance.

[0237] At least one of steps b) and d), in particular each of steps b) and d), may be implemented by an atomic layer deposition (ALD) technique, for example at a temperature of between 150°C and 550°C, preferably between 200°C and 500°C, more preferably between 200°C and 450°C, even more preferably between 200°C and 400°C, and in particular between 250°C and 350°C, using: at least one gas, preferably ozone (O3), and at least one precursor of an electronically conductive material, in particular a metal, preferably a precursor of a metal, in particular a transition metal.

[0238] For example, the precursor is chosen from a platinum (Pt), gold (Au), silver (Ag) and / or copper (Cu) precursor, preferably a platinum (Pt) precursor.

[0239] The precursor may be chosen from an organometallic complex comprising platinum (Pt), gold (Au), silver (Ag) and / or copper (Cu), preferably platinum (Pt) - The precursor is preferably solid or liquid at room temperature.

[0240] The precursor can be chosen from:

[0241] - trimethyl(methylcyclopentadienyl)platinum(IV) (MeCpPtMes),

[0242] - dimethyl(cyclooctadiene)platinum(ll) (Me2PtCOD),

[0243] - dimethylgold(lll)acetylacetonate (Me2Au(acac)), dimethylgold(lll)trimethylphosphine, silver(l) hexafluoroacetylacetonate (Ag(hfac)), a silver complex with p-diketonate ligands, copper(ll) hexafluoroacetylacetonate vaporized with hydrogen formate or water,

[0244] - a copper complex with hexafluoroacetylacetone (hfac) and 1,5-cyclooctadiene (cod) ((hfac)Cu(1,5-cod)), and

[0245] - one of their blends.

[0246] Trimethyl(methylcyclopentadienyl)platinum(IV) (MeCpPtMes) and dimethyl(cyclooctadiene)platinum(ll) (Me2PtCOD) are examples of precursors used to form platinum (Pt) thin films by ALD.

[0247] Dimethylgold(III)acetylacetonate (Me2Au(acac)) and dimethylgold(III)trimethylphosphine are examples of precursors used to form gold (Au) thin films by ALD.

[0248] Silver(l) hexafluoroacetylacetonate (Ag(hfac)) and silver complex with p-diketonate ligands are examples of precursors used to form silver (Ar) thin films by ALD.

[0249] Copper(ll) hexafluoroacetylacetonate vaporized with hydrogen formate or water, and the copper complex with hexafluoroacetylacetone (hfac) and 1,5-cyclooctadiene (cod) ((hfac)Cu(1,5-cod)) are examples of precursors used to form thin copper (Cu) films by ALD.

[0250] Preferably, the precursor is chosen from:

[0251] - trimethyl(methylcyclopentadienyl)platinum(IV) (MeCpPtMes),

[0252] - dimethyl(cyclooctadiene)platinum(ll) (Me2PtCOD), and

[0253] - one of their blends.

[0254] More preferably, the precursor is trimethyl(methylcyclopentadienyl)platinum(IV) (MeCpPtMes).

[0255] In a preferred embodiment, steps b) and d) are each carried out by ALD, for example at a temperature of about 300°C, using ozone (Os) as the gas and trimethyl(methylcyclopentadienyl)platinum(IV) (MeCpPtMes) as the precursor.

[0256] The insulating material is preferably a dielectric insulating material.

[0257] The insulating material can have a relative permittivity (c r ) greater than or equal to 8.0, preferably greater than or equal to 8.1, more preferably greater than or equal to 8.2, even more preferably greater than or equal to 8.3, and in particular greater than or equal to 8.4, or even greater than or equal to 8.5.

[0258] For example, the insulating material may have a relative permittivity (c r ) greater than or equal to 15, 20, 25, 40, 100, 120, 1000, 4000, 5000, or greater than or equal to 10000.

[0259] The relative permittivity (cr ) can be measured at room temperature, particularly at frequencies within the radio spectrum.

[0260] The insulating material is preferably a ceramic material.

[0261] The insulating material may include, or even consist of, a metal oxide or a mixture of metal oxides.

[0262] The metal oxide can be a simple oxide (i.e., having only one type of metal or metal cation bound to oxygen) or a mixed oxide (i.e., having more than one type of metal or metal cation bound to oxygen).

[0263] For example, the insulating material comprises, or is made of, titanium dioxide (TiO2), silica (SiC>2), alumina (AI2O3), hafnium dioxide (HfC>2), barium (meta)titanate (BaTiOs) or a mixture thereof.

[0264] Preferably, the insulating material comprises, or is made of, alumina (AI2O3).

[0265] Step c) may be implemented by an atomic layer deposition (ALD) technique, for example at a temperature of between 150°C and 550°C, preferably between 200°C and 500°C, more preferably between 250°C and 500°C, even more preferably between 300°C and 500°C, and in particular between 350°C and 450°C, using:

[0266] - at least one oxidizing agent, and at least one precursor of an insulating material, in particular dielectric, preferably a precursor of a metal oxide, in particular simple or mixed.

[0267] Such temperature values ​​can make it possible to densify the deposited thin layer of insulating material and increase its relative permittivity. The oxidizing agent can be chosen from water (H2O), ethanol (C2H5OH), hydrogen peroxide (H2O2), ozone (O3), and a mixture thereof.

[0268] Preferably, the oxidizing agent is ozone (O3).

[0269] The precursor may be chosen from a titanium dioxide precursor (TiC>2), a silica precursor (SiC>2), an alumina precursor (AI2O3), a hafnium dioxide precursor (HfC>2) and a barium (meta)titanate precursor (BaTiOs), preferably an alumina precursor (AI2O3).

[0270] For example, the precursor is chosen from a precursor comprising titanium (Ti), silicon (Si), aluminum (Al), hafnium (Hf) and / or barium (Ba), preferably aluminum (Al).

[0271] The precursor is preferably solid or liquid at room temperature.

[0272] The precursor can be chosen from:

[0273] - titanium tetraisopropoxide (TTIP),

[0274] - titanium tetraethoxide (TEOT),

[0275] - titanium tetrachloride,

[0276] - silicon tetraethoxide (TEOS),

[0277] - trichlorosilane (TCS), trimethylaluminium (TMA), triethylaluminium (TEA),

[0278] - hafnium tetra(isopropoxide) (TIPO),

[0279] - hafnium tetraethoxide (TEOH),

[0280] - barium tetramethylheptanedionate (Ba(thd)2), and

[0281] - one of their blends.

[0282] Titanium tetraisopropoxide (TTIP), titanium tetraethoxide (TEOT), and titanium tetrachloride are examples of precursors used to form thin films of titanium dioxide (TO2) by ALD.

[0283] Silicon tetraethoxide (TEOS) and trichlorosilane (TCS) are examples of precursors used to form thin films of silica (SiO2) by ALD.

[0284] Trimethylaluminum (TMA) and triethylaluminum (TEA) are examples of precursors used to form thin films of alumina (AI2O3) by ALD.

[0285] Hafnium tetra(isopropoxide) (TIPO) and hafnium tetraethoxide (TEOH) are examples of precursors used to form thin films of hafnium dioxide (HfO2) by ALD.

[0286] Barium tetramethylheptanedionate (Ba(thd)2) is an example of a precursor used to form thin layers of barium oxide (BaO) by ALD. Step c), in particular when the insulating material comprises, or even consists of, a mixed oxide, such as for example barium (meta)titanate (BaTiOs), can be implemented by ALD using several precursors, in particular alternately.

[0287] For example, when the insulating material comprises, or even consists of, a mixed oxide, such as for example barium (meta)titanate (BaTiOs), it may be necessary to sequentially deposit layers of BaO and TiOs by ALD, then to carry out a high-temperature heat treatment in order to form a thin layer of BaTiOs from the layers of BaO and TiOs.

[0288] It may therefore be necessary to use several precursors alternately in order to form the BaO and TiOs layers.

[0289] To form the BaO layer(s), a precursor such as barium tetramethylheptanedionate (Ba(thd)s) can be used.

[0290] To form the TiOs layer(s), precursors such as, for example, titanium tetraisopropoxide (TTIP), titanium tetraethoxide (TEOT) or titanium tetrachloride can be used.

[0291] Preferably, the precursor is chosen from: trimethylaluminum (TMA), triethylaluminum (TEA), and

[0292] - one of their blends.

[0293] More preferably, the precursor is trimethylaluminium (TMA).

[0294] In a preferred embodiment, step c) is carried out by ALD, for example at a temperature of about 400°C, using ozone (O3) as an oxidizing agent and trimethylaluminum (TMA) as a precursor.

[0295] The use of ozone (O3) as an oxidizing agent is particularly advantageous compared to other oxidizing agents, such as water (H2O) for example, because it can increase the relative permittivity value (e r ) of the deposited insulating material, in particular the deposited alumina (AI2O3).

[0296] Indeed, using trimethylaluminium (TMA) as a precursor and water (H2O) as an oxidizing agent, the alumina deposited as a thin layer by ALD on the first electrode has a relative permittivity (e r ) equal to 7.5.

[0297] In contrast, using trimethylaluminium (TMA) as a precursor and ozone (O3) as an oxidizing agent, the alumina deposited as a thin film by ALD on the first electrode has a relative permittivity (e r ) equal to 8.5. The method may comprise a step e) of forming at least one contact orifice which passes through the second electrode and the insulating material so as to expose a contact zone, in particular predefined, of the first electrode.

[0298] The contact orifice may allow electrical contact to be made with the first electrode at said contact area.

[0299] The contact orifice can extend along an axis substantially perpendicular to the face of the substrate of the architectural support (i.e. along an axis substantially parallel to the extension axis of the micro-pillars).

[0300] Step e) can be implemented sequentially.

[0301] Step e) may comprise a sub-step e1) of etching the second electrode on a portion corresponding to said contact zone of the first electrode.

[0302] Step e) may include a sub-step e2) of etching the insulating material on a portion corresponding to said contact zone of the first electrode.

[0303] Preferably, substep e2) is implemented after substep e1).

[0304] The contact orifice may comprise a first portion passing through the second electrode and a second portion passing through the insulating material.

[0305] Substep e1) may allow the formation of the first part of the contact orifice.

[0306] Substep e2) may allow the formation of the second part of the contact orifice.

[0307] The etching sub-step e1) is preferably carried out using a reactive ion beam etching (or RIBE) technique.

[0308] For example, the reactive ion beam etching technique is implemented using a "Meyer Burger lonSys 500" device.

[0309] The etching sub-step e1) can be carried out at a speed of between 5 nm / min and 15 nm / min, preferably between 8 nm / min and 12 nm / min, more preferably between 9 nm / min and 11 nm / min, and in particular at an angle of 0°.

[0310] The etching sub-step e2) is preferably carried out using a reactive ion etching (RIE) technique.

[0311] For example, the reactive ion etching technique is implemented using an “Oxford Plasmalab 80+” device.

[0312] Etching sub-step e2) can be carried out with a mixture of gases, in particular a mixture of methane (CH4) and trifluoromethane (CHF3).

[0313] This may allow selective etching of the insulating material relative to the second electrode. This may allow "over-etching" of the insulating material to be carried out in order to be certain of etching it completely at the level of its portion corresponding to said contact zone of the first electrode, and thus exposing said contact zone of the first electrode.

[0314] Step e) may be preceded by a lithography step, in particular photolithography.

[0315] In particular, the lithography step can be carried out after step d) and before step e).

[0316] The lithography step can be implemented using a resin, in particular a positive one, for example the “AZ10XT” resin.

[0317] The lithography step can be implemented using a resin thickness of between 5 pm and 15 pm, preferably between 8 pm and 12 pm, and more preferably between 9 pm and 11 pm.

[0318] Step e) may be followed by a step of removing the resin used during the lithography step.

[0319] The resin removal step can be implemented by immersing the microcapacitor in a solvent, in particular organic, for example an “SVC14” solvent, in particular heated, for example to a temperature between 65°C and 95°C, in particular for a period of one hour, then by rinsing the microcapacitor with one or more solvents, in particular organic, for example with acetone then with isopropyl alcohol (IPA).

[0320] The method may include a step of depositing a protective layer, in particular thermal, in the form of a thin layer on the architectural support.

[0321] Preferably, this step of depositing the protective layer is carried out after step a) and before step b).

[0322] Preferably, this step of depositing the protective layer is implemented using a chemical vapor deposition technique (or CVD for Chemical Vapor Deposition in English).

[0323] More preferably, this step of depositing the protective layer is implemented by an atomic layer deposition (ALD) technique, for example at a temperature between 200°C and 400°C, preferably between 250°C and 350°C, more preferably between 275°C and 325°C, even more preferably between 290°C and 310°C.

[0324] This step of depositing the protective layer can be carried out using a precursor comprising aluminum and an oxidizing agent. The oxidizing agent can be chosen from water (H2O), ethanol (C2H5OH), hydrogen peroxide (H2O2), ozone (O3), and a mixture thereof.

[0325] Preferably, the oxidizing agent is water (H2O).

[0326] The precursor containing aluminum can be trimethylaluminum (TMA).

[0327] In a preferred embodiment in which the protective layer comprises, or even consists of, alumina (AI2O3), the step of depositing the protective layer is carried out by ALD, for example at a temperature of approximately 300°C, using a precursor comprising aluminum, such as for example trimethylaluminum (TMA), and water as an oxidizing agent.

[0328] Preferably, step b) is implemented after step a).

[0329] Preferably, step c) is implemented after step b).

[0330] Preferably, step d) is carried out after step c).

[0331] Preferably, step e) is carried out after step d).

[0332] Brief description of the figures

[0333] Figure 1 A) illustrates a silicon substrate intended for the production of the architectural support according to the invention.

[0334] Figure 1 B) represents the step of deposition and exposure under UV of a photosensitive resin on the flat silicon substrate, allowing the subsequent definition of the micropillars by etching the substrate.

[0335] Figure 1 C) represents the successive steps of etching the silicon by the Bosch process, followed by the removal of the photosensitive resin by oxygen plasma cleaning (O2), resulting in a substrate comprising a plurality of micro-pillars extending from one face of said substrate.

[0336] Figure 1 D) represents an image obtained by scanning electron microscopy (SEM) showing a perspective view of a set of substantially parallel micro-pillars formed on the substrate by an etching technique (e.g. DRIE). This image shows the regular spatial distribution of the micro-pillars down to the base of the substrate.

[0337] Figure 2 A) illustrates the step of covering the architectured substrate: by a thin layer of silicon oxide (SiO2) obtained by low pressure chemical vapor deposition (LPCVD) or by atomic layer deposition (ALD) then, by a layer of platinum (Pt) deposited by ALD, covering the face of the substrate and the micro-pillars. Figure 2 B) represents the step of etching the platinum by reactive ion etching (RIE), in order to eliminate the platinum layer present on the surface of the substrate while keeping this layer on the surface of the micro-pillars.

[0338] Figure 2 C) illustrates the growth step of SiO2 nanowires using a vapor-liquid-solid (VLS) growth mechanism on the surface of platinum-coated micropillars, leading to a significant increase in the specific surface area of ​​said micropillars.

[0339] Figure 3 A) represents a scanning electron microscopy (SEM) image of a set of substantially parallel micro-pillars, made on a substrate. These micro-pillars, with a high aspect ratio, are arranged in a regular and periodic manner. Each micro-pillar appears covered, on its lateral surface, with nanowires extending radially from the surface. The image makes it possible to visualize the homogeneity of the structuring at the microscopic scale, as well as the good distribution of the nanowires over the entire network of micro-pillars.

[0340] Figure 3 B) represents a SEM image (at a higher magnification than that of Figure 3 A) in close-up view of several micro-pillars from the same structure as that illustrated in Figure 3 A). This detailed view highlights the density and uniformity of the nanowire deposition on the lateral surface of the micro-pillars. The nanowires are oriented in a generally radial manner with respect to the longitudinal axis of the micro-pillars, and form a coating with a three-dimensional structure considerably increasing the specific surface area. This configuration is particularly suitable for electrochemical devices, such as micro-batteries or micro-supercapacitors.

[0341] Figure 4 (A) B) and C) shows the structure of a micro-capacitor according to an embodiment of the invention, obtained by successive atomic layer deposition (ALD) on the architectural support, of a first platinum electrode (Pt), an insulator (AI2O3), and a second platinum electrode. The images obtained by SEM show that the micro-pillars are conformally covered by the different layers.

[0342] Figure 5 illustrates a photolithography step consisting of coating the surface of the device with a photosensitive resin, followed by exposure under UV radiation. This step makes it possible to define the areas (patterns) where the second electrode and the insulator must subsequently be etched, in particular in order to open accesses to the first electrode and to achieve separation between adjacent components.

[0343] Figure 6 illustrates the selective etching step by RI BE (Reactive Ion Beam Etching) of the second electrode and the insulator, following the patterns defined in the previous step. This step is followed by cleaning of the resin.

Claims

CLAIMS 1. Micro-capacitor comprising: - an architectural support comprising a substrate and micro-pillars arranged on one face of the substrate, the substrate and the micro-pillars being formed in a single piece, - a first electrode placed on the architectural support, - a second electrode, and - an insulating material disposed between the first and second electrodes.

2. Micro-capacitor according to claim 1, each micro-pillar having a cylindrical shape and comprising a cross-section of square or rectangular shape, preferably square, with in particular sides each having a length of between 2 pm and 6 pm, in particular between 3 pm and 5 pm.

3. Micro-capacitor according to claim 1 or 2, each micro-pillar having a length ranging from 10 pm to 400 pm, preferably ranging from 20 pm to 350 pm, more preferably ranging from 30 pm to 300 pm, even more preferably ranging from 40 pm to 250 pm.

4. Micro-capacitor according to any one of the preceding claims, the substrate and the micro-pillars comprising, or even being made of, a semiconductor material or an insulating material, in particular dielectric.

5. Micro-capacitor according to any one of the preceding claims, each micro-pillar having a free surface, and the structured support comprising nano-wires arranged on the free surface of at least part of the micro-pillars.

6. Micro-capacitor according to claim 5, each nano-wire having a length ranging from 100 nm to 10 pm, preferably ranging from 200 nm to 9 pm, more preferably ranging from 300 nm to 8 pm, even more preferably ranging from 400 nm to 7 pm, and in particular ranging from 500 nm to 6 pm.

7. Micro-capacitor according to claim 5 or 6, each nano-wire having a cross-section whose largest dimension is between 20 nm and 200 nm, and preferably between 30 nm and 190 nm.

8. Micro-capacitor according to any one of claims 5 to 7, each nano-wire comprising a metal oxide or a mixture of metal oxides, and in particular a metal or a metal alloy.

9. Micro-capacitor according to any one of the preceding claims, the first electrode, the second electrode and the insulating material each being in the form of a thin layer, having in particular a thickness ranging from 1 nm to 250 nm, and preferably ranging from 2 nm to 225 nm.

10. Micro-capacitor according to claim 9, the first electrode and the second electrode each having a thickness ranging from 10 to 50 nm, preferably ranging from 15 nm to 45 nm, and more preferably ranging from 20 nm to 40 nm.

11. Micro-capacitor according to claim 9 or 10, the insulating material having a thickness ranging from 1 nm to 250 nm, preferably ranging from 1 nm to 225 nm, more preferably ranging from 1 nm to 200 nm, and even more preferably ranging from 2 nm to 200 nm.

12. Micro-capacitor according to any one of the preceding claims, the first electrode and the second electrode each being made of an electronically conductive material, in particular metallic.

13. Micro-capacitor according to claim 12, the electronically conductive material comprising, or even being made of, a metal, in particular a transition metal, or a metal alloy, in particular of transition metals.

14. Micro-capacitor according to claim 12 or 13, the electronically conductive material comprising, or even consisting of, platinum (Pt), gold (Au), silver (Ag), copper (Cu) or one of their mixtures, preferably platinum (Pt).

15. Micro-capacitor according to any one of the preceding claims, the insulating material comprising, or even consisting of, a metal oxide or a mixture of metal oxides.

16. Micro-capacitor according to claim 15, the insulating material comprising, or even consisting of, titanium dioxide (TiC^), silica (SiO2), alumina (AI2O3), hafnium dioxide (HfC^), barium (meta)titanate (BaTiOs) or one of their mixtures, preferably alumina (AI2O3).

17. Micro-capacitor according to any one of the preceding claims, the micro-capacitor comprising at least one protective layer, in particular thermal, arranged between the architectural support and the first electrode.

18. A microcapacitor according to any preceding claim, the microcapacitor having a capacitance of between 0.38 pF / cm 2 and 3.8 mF / cm 2 .

19. Micro-capacitor according to any one of the preceding claims, the micro-capacitor having a breakdown voltage of between 1 V and 170 V, in particular between 1.7 V and 160 V.

20. Micro-capacitor according to any one of the preceding claims, the micro-capacitor comprising at least one contact orifice passing through the second electrode and the insulating material so as to expose a contact zone, in particular predefined, of the first electrode.

21. A microcapacitor according to any preceding claim, the microcapacitor being a metal-insulator-metal type microcapacitor.

22. Electronic system comprising a micro-capacitor according to any one of claims 1 to 21.

23. Electronic system according to claim 22, the electronic system being on-board, portable and / or intelligent.

24. Method for manufacturing a micro-capacitor according to any one of claims 1 to 21, comprising at least the following steps: a) providing an architectural support comprising a substrate and micro-pillars arranged on one face of the substrate, b) depositing a first electrode in the form of a thin layer on the architectural support, c) depositing an insulating material in the form of a thin layer on the first electrode, d) depositing a second electrode in the form of a thin layer on the insulating material.

25. Method according to claim 24, in which at least one of steps b), c) and d), in particular each of steps b), c) and d), is carried out by a chemical vapor deposition technique.

26. Method according to claim 25, in which at least one of steps b), c) and d), in particular each of steps b), c) and d), is carried out by an atomic layer deposition technique, in particular at a temperature ranging from 150°C to 550°C, preferably ranging from 200°C to 500°C, and more preferably ranging from 250°C to 450°C.

27. Method according to claim 26, in which at least one of steps b) and d), in particular each of steps b) and d), is implemented using: - at least one gas, preferably ozone (O3), and - at least one precursor of an electronically conductive material, in particular metallic, preferably a precursor of a metal, in particular transition metal.

28. The method of claim 26 or 27, wherein step c) is carried out using: - at least one oxidizing agent, and - at least one precursor of an insulating material, in particular dielectric, preferably a precursor of a metal oxide, in particular simple or mixed.

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