Photosensitive element, semiconductor photomultiplier comprising the same, and method for manufacturing the same

Abstract

A photosensitive element for a semiconductor photomultiplier (PM) is provided, which comprises a semiconductor layer on a substrate, with an open cavity formed in the semiconductor layer. The open cavity has a bottom and one or more sidewalls surrounding the bottom. The bottom is provided with an antireflective material, preferably, b-Si. The semiconductor layer is doped such that there is an embedded or induced p-n junction provided under the bottom of the open cavity. The photosensitive element further comprises a metal electrode extending on top of the sidewall(s) of the open cavity and a resistive layer arranged so as to provide a contact between the metal electrode and the p-n junction. The photosensitive element thus configured allows increasing the geometrical fill factor of the semiconductor PM.

Description

[0001] PHOTOSENSITIVE ELEMENT , SEMICONDUCTOR PHOTOMULTIPLIER COMPRISING THE SAME , AND METHOD FOR MANUFACTURING THE SAME

[0002] TECHNICAL FIELD

[0003] The present disclosure relates generally to the field of photonics . More particularly, the present disclosure relates to a photosensitive element , a semiconductor photomultiplier comprising an array of such photosensitive elements , and a method for manufacturing the photosensitive element .

[0004] BACKGROUND

[0005] A silicon photomultiplier ( SiPM) is a photodetector which can provide a gain comparable to the one achieved by using a conventional photomultiplier tube . The SiPM comprises an array of pixels ( also referred to as photosensitive elements or cells ) connected in parallel , with each pixel comprising a series connection of a Geiger-mode avalanche photodiode (APD) and a quenching res istor . The Geiger-mode APD is also known as a Single Photon Avalanche Diode ( SPAD) which operates with a reverse bias voltage greater than its breakdown voltage , and by maintaining a dark count rate ( DCR) at a sufficiently low level . When the pixel of the SiPM absorbs a photon, an electron-hole pair forms , with one of the charge carriers drifting to an avalanche region where it can initiate an avalanche event . The current generated by the avalanche event must be quenched by an appropriate current limiting circuit such that the device can recover and reset after the avalanche event . Such a current limiting circuit is typically implemented as the quenching resistor configured to quench avalanche by lowering the reverse bias voltage to or below the breakdown voltage . All the pixels in the SiPM are usually square , of the same si ze , and arranged in a rectangular (tiled) pattern . The total area occupied by the pixels is known as an active area . The active area can range from l x l mm2to 6 X 6 mm2. However, some regions of each pixel have no photosensitivity, for which reason only some fraction of the active area is sensitive to light . This fraction is referred to as a geometrical fill factor . For example , such non-photosensitive regions include those covered by quenching resistors .

[0006] Given the above , more engineering is required to increase the geometrical fill factor of semiconductor PMs , including SiPMs .

[0007] SUMMARY

[0008] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description . This summary is not intended to identify key features of the present disclosure , nor is it intended to be used to limit the scope of the present disclosure .

[0009] The obj ective of the present disclosure is to provide a technical solution for increasing the geometrical fill factor of semiconductor PMs (e . g . , SiPMs ) .

[0010] The obj ective above is achieved by the features of the independent claims in the appended claims . Further embodiments and examples are apparent from the dependent claims , the detailed description, and the accompanying drawings .

[0011] According to a first aspect , a photosensitive element for a semiconductor PM is provided . The photosensitive element comprises a substrate and a semiconductor layer provided on the substrate . The semiconductor layer has an open cavity formed therein . The open cavity has a bottom and at least one s idewall surrounding the bottom . The bottom of the open cavity has an antiref lective material provided thereon . The semiconductor layer is doped such that an embedded or induced p-n j unction is provided under the open cavity in the semiconductor layer . The photosensitive element further comprises a metal electrode extending on top of the at least one sidewall and a resistive layer arranged to provide a contact between the metal electrode and the p-n j unction . The photosensitive element thus configured is a SPAD structure , in which the bottom of the open cavity in the semiconductor layer serves as a unit active area ( i . e . , the one on which photons mainly hit ) and the resistive layer serves as a quenching resistor . Since the resistive layer provides the contact between the metal electrode (which is provided on top of the sidewall ( s ) ) and the p-n j unction (which is provided under the bottom of the open cavity) , it should extend along (either on or underneath) the sidewall ( s ) . This means that the resistive layer substantially does not cover or overlap the unit active area, thereby increasing the geometrical fill factor of the semiconductor PM comprising the array of such photosensitive elements .

[0012] In one exemplary embodiment of the first aspect , the at least one sidewall of the open cavity is at least partly coated with a passivation layer extending from the metal electrode to the bottom of the open cavity . In this embodiment , the resistive layer is a surface inversion layer extending underneath the passivation layer . The resistive layer as the surface inversion layer may be used in combination with the embedded or induced p-n j unction .

[0013] In an alternative exemplary embodiment of the first aspect , the semiconductor layer is again doped such that the embedded p-n j unction is provided under the open cavity in the semiconductor layer . However, in this embodiment , the at least one s idewal l of the open cavity is at least partly coated with an insulation layer extending from the metal electrode to the bottom of the open cavity, and the resistive layer extends on the insulation layer from the metal electrode to the bottom of the open cavity .

[0014] In one other alternative exemplary embodiment of the first aspect , the semiconductor layer is doped such that the induced p-n j unction is provided under the open cavity in the semiconductor layer . In this embodiment , the resistive layer at least partly covers the at least one sidewall of the open cavity and extends from the metal electrode to the bottom of the open cavity .

[0015] The above-mentioned three alternative embodiments may provide flexibility in manufacturing the photosensitive element according to the first aspect . Each of the alternative embodiments may be used depending on the capabilities of the available fabrication equipment .

[0016] In one exemplary embodiment of the first aspect , the resistive layer i s shaped as a straight or curved strip . By using the strip-like resistive layer, it is poss ible to effectively control the operation of the photosensitive element . Moreover, the strip-like resistive layer implies that not the entire area of the sidewall ( s ) is coated by it , which may also provide les s material consumption .

[0017] In one exemplary embodiment of the first aspect , the antiref lective material comprises black silicon (b-Si ) . The black silicon is characteri zed by low reflectivity and correspondingly high absorption of visible ( and infrared) light , which may enhance the performance of the photosensitive element .

[0018] In one exemplary embodiment of the first aspect , the black silicon is coated with a passivation layer (e . g . , made of I2O3 , HfCy , etc . ) . By using thi s layer, it is possible to perform efficient surface passivation of the black silicon .

[0019] In one exemplary embodiment of the first aspect , the at least one sidewall has a surface region under the metal electrode that is doped so as to provide an ohmic contact between the metal electrode and the semiconductor layer . This embodiment may be useful when the material of the metal electrode is such that it naturally does not form a proper ohmic contact to the material of the semiconductor layer (e . g . , silicon) .

[0020] According to a second aspect , a semiconductor photomultiplier comprising an array of photosensitive elements according to the f irst aspect i s provided . In the semiconductor photomultiplier, the photosensitive elements are arranged adj acent to each other and connected in parallel using the metal electrodes . The semiconductor photomultiplier thus configured is characteri zed by an increased geometrical fill factor .

[0021] According to a third aspect , a method for manufacturing the photosensitive element according to the first aspect is provided . The method starts with the steps of providing the substrate and providing the semiconductor layer on the substrate . Then, the method proceeds to the step of etching the semiconductor layer to form the open cavity . Further, the method goes on to the step of doping the semiconductor layer such that the embedded or induced p-n j unction is provided under the bottom of the open cavity in the semiconductor layer . The method subsequently proceeds to the step of providing the antiref lective material on the bottom of the open cavity . Next , the method goes on to the step of depositing the metal electrode on top of the at least one sidewall of the open cavity . After that , the next step is performed, in which the resistive layer is formed such that the metal electrode and the embedded or induced p-n j unction are in contact with each other through the resistive layer . By doing so , it is possible to manufacture the photosensitive element in which the resistive layer extending along the sidewall ( s ) and serving as the quenching resistor substantially does not cover or overlap the unit active area of the photosensitive element , thereby increasing the geometrical fill factor of the semiconductor PM comprising the array of such photosensitive elements .

[0022] Other features and advantages of the present disclosure will be apparent upon reading the following detailed description and reviewing the accompanying drawings .

[0023] BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present disclosure is explained below with reference to the accompanying drawings in which :

[0025] FIG . 1 shows a schematic isometric view of a semiconductor photomultiplier ( PM) in accordance with one exemplary embodiment ;

[0026] FIG . 2 shows a schematic cross-section view of one photosensitive element included in the semiconductor PM of FIG . 1 in accordance with a first exemplary embodiment ;

[0027] FIG . 3 shows a schematic cross-section view of a photosensitive element included in the semiconductor PM of FIG . 1 in accordance with a second exemplary embodiment ;

[0028] FIG . 4 shows a schematic cross-section view of a photosensitive element included in the semiconductor PM of FIG . 1 in accordance with a third exemplary embodiment ; and

[0029] FIG . 5 shows a flowchart of a method for manufacturing the photosensitive element of any of FIGs . 2 to 4 in accordance with one exemplary embodiment . DETAILED DESCRIPTION

[0030] Various embodiments of the present disclosure are further described in more detail with reference to the accompanying drawings . However, the present disclosure may be embodied in many other forms and should not be construed as limited to any certain structure or function discussed in the following description . In contrast , these embodiments are provided to make the description of the present disclosure detailed and complete .

[0031] According to the detailed description, it will be apparent to the ones skilled in the art that the scope of the present disclosure encompasses any embodiment thereof , which is disclosed herein, irrespective of whether this embodiment is implemented independently or in concert with any other embodiment of the present disclosure . For example , the apparatuses and method disclosed herein may be implemented in practice using any numbers of the embodiments provided herein . Furthermore , it should be understood that any embodiment of the present disclosure may be implemented using one or more of the elements presented in the appended claims .

[0032] The word "exemplary" is used herein in the meaning of "used as an illustration" . Unless otherwise stated, any embodiment described herein as "exemplary" should not be construed as preferable or having an advantage over other embodiments .

[0033] Any positioning terminology, such as "left" , "right" , "top" , "bottom" , "above" "below" , "upper" , "lower" , etc . , may be used herein for convenience to describe one element' s or feature ' s relationship to one or more other elements or features in accordance with the figures . It should be apparent that the positioning terminology is intended to encompass different orientations of the apparatus disclosed herein, in addition to the orientation ( s ) depicted in the figures . As an example , if one imaginatively rotates the apparatus in the figures 90 degrees clockwise , elements or features described as "left" and "right" relative to other elements or features would then be oriented, respectively, "above" and "below" the other elements or features . Therefore , the positioning terminology used herein should not be construed as any limitation of the present disclosure .

[0034] Although the numerative terminology, such as "first", "second", etc . , may be used herein to describe various embodiments, elements or features , these embodiments , elements or features should not be limited by this numerative terminology . This numerative terminology is used herein only to distinguish one embodiment , element or feature from another embodiment , element or feature .

[0035] As used in the embodiments disclosed herein, a photomultiplier ( PM) may refer to a semiconductor photon sensitive device comprising an array of independent Geiger-mode APD pixels or photosensitive elements ( also referred to as SPADs in the art ) with quenching resistors . The APD pixels are connected in paral lel to each other to form one larger device with one signal output . The avalanche area of each APD pixel is formed by a planar p-n j unction with great attention to the uniformity of an electric field over the central j unction area and the suppres sion of edge breakdown outside this area .

[0036] In the exemplary embodiments disclosed herein, the term "layer" may refer to a continuous piece of material covering ( a part of ) a surface or body . Additionally or alternatively, the layer may refer to one of a series of superimposed, overlaid or stacked substantially sheet-like elements . The layer itself may also comprise a plurality of sub-layers each made of the same or different material . The layer may have different shapes (sheet-like, strip-like, etc.) , depending on the purposes of its application.

[0037] As used in the embodiments disclosed herein, the term "black silicon" (or b-Si for short) may refer to a surface modification of silicon where a micro- or nano-scale surface structure is formed through etching. The resulting micro- or nano-scale structure provides an extremely low reflectivity close to 0% (and correspondingly an extremely high absorption of visible and infrared light) . As a rule, b-Si is formed as a needle-shaped surface structure where needles are made of single-crystal silicon and have a height of at least 100 nm and a diameter less than 1 pm. By using the needle-shaped b-Si, it is possible to reduce the high reflectivity of silicon, which is usually 20-30% for quasi-normal incidence, to about 0-2%. This is due to the formation of a so-called effective medium by the needles. Within this medium, there is no sharp interface, but a continuous change of a refractive index that reduces Fresnel reflection. When the depth of such an index graded layer is roughly equal to the wavelength of light in silicon (about one-quarter its wavelength in vacuum) , the reflection is reduced to about 2%; deeper grades produce even "blacker" silicon. For low reflectivity values, the b-Si needles producing the index graded layer must be smaller than the wavelength of the incident light to avoid scattering.

[0038] The exemplary embodiments disclosed herein provide a technical solution that allows increasing the geometrical fill factor of semiconductor PMs (e.g., SiPMs) . For this purpose, a photosensitive element for a semiconductor PM is provided, which comprises a semiconductor layer provided on a substrate, with an open cavity formed in the semiconductor layer. The open cavity has a bottom and one or more sidewalls surrounding the bottom. The bottom is provided with an antiref lective material, preferably, b-Si. The semiconductor layer is doped such that an embedded or induced p-n junction is provided under the bottom of the open cavity. The photosensitive element further comprises a metal electrode extending on top of the sidewall (s) of the open cavity and a resistive layer arranged so as to provide a contact between the metal electrode and the p-n junction.

[0039] FIG. 1 shows a schematic isometric view of a semiconductor PM 100 in accordance with one exemplary embodiment. The PM 100 comprises four square photosensitive elements 102 of the same size, which are arranged adjacent to each other in a tiled pattern. Each of the photosensitive elements 102 is implemented as a (multi- ) layered structure comprising an underlaying layer or substrate 104 and a semiconductor layer 106 provided on the substrate 104, with an open cavity 108 formed in the semiconductor layer 106. It should be noted that the number and square shape of the photosensitive elements 102, which are shown in FIG. 1, are selected for illustrative purposes only and should not be construed as any limitation of the present disclosure; in some other embodiments, the PM 100 may comprise much more (e.g., dozens, hundreds, etc.) photosensitive elements (as is the case in practice) which are shaped similarly or differently (e.g., they may have any polygonal shape, such as triangular, rectangular, pentagonal, etc., or curved shape, such as oval, circular, etc.) .

[0040] The substrate 104 and the semiconductor layer 106 may be made of Si, Ge, InGaAs, GaN, or any other suitable (for APD formation) semiconductor material. The semiconductor layer 106 is assumed to be doped in such a way as to form, under the bottom of the open cavity 108, an APD having a p-n junction in which a depletion region has a relatively large width (e.g., compared to the one formed in a Zener diode) . Because of this large depletion region, a reverse breakdown (also referred to as an avalanche breakdown) takes place at higher voltages in the p-n j unction of the APD . Thus , the breakdown voltage of the APD may be accurately set by controlling a doping level in its manufacturing process . Some exemplary doping patterns will be discussed later with reference to FIGs . 2 -4 . It should be also noted that the substrate 104 may be implemented as either a single-layer substrate (e . g . , single-crystal Si substrate ) or a multi-layered substrate . Furthermore , although the substrate 104 and the semiconductor layer 106 are shown to be common to all the photosensitive elements 102 , this should not be construed as any limitation of the present disclosure ; in some other embodiments , the photosensitive elements 102 may be manufactured independently from each other, whereupon al l the photosens itive elements 102 may be attached to each other to form a single PM structure .

[0041] In FIG . 1 , the bottom of each of the open cavities 108 is assumed to be surrounded by four sidewalls 110 and is assumed to be hit by photons ( i . e . , serves as a unit active area) . Therefore , the bottom of each open cavity 108 is coated with an antiref lective material 112 . The antiref lective material 112 may be represented by an antireflection coating configured to reduce reflection . The antireflection coating may be implemented, for example , as a thin layer of dielectric material , with a specially chosen thickness and refractive index such that interference effects in the antireflection coating cause the wave reflected from the top surface of the antireflection coating to be out-of- phase with the wave reflected from the semiconductor surface on which the antireflection coating is provided . Alternatively, the antiref lective material 112 may be implemented as a properly texturi zed structure that "captures" light and generally does not let it "exit" , such as b-Si . Those ski lled in the art would recogni ze that the shape of each open cavity 108 depends on the number of the sidewalls 110 surrounding it and may be square, triangular, circular (i.e., if there is only one circular sidewall 110) , etc.

[0042] As also shown in FIG. 1, the PM 100 further comprises a resistive layer 114 in each photosensitive element 102. The resistive layer 114 is arranged to provide a contact between the p-n junction under the bottom of the open cavity 108 and a metal electrode 116 extending on top of the sidewalls 110. In FIG. 1, the resistive layer 114 in each photosensitive element 102 is shown to extend along one of the sidewalls 110 of the open cavity 108. In some other embodiments, the resistive layer 114 may extend along some or each of the sidewalls 110 in each photosensitive element 102, if required and depending on applications of the PM 100. The specifics of this and other exemplary embodiments of the resistive layer 114 will be discussed below with reference to FIGs. 2-4.

[0043] FIG. 2 shows a schematic cross-section view of one photosensitive element 102 included in the PM 100 in accordance with a first exemplary embodiment. In this embodiment, the antiref lective material 112 is implemented as a needle-shaped b-Si structure 200. Since the b-Si structure 200 has a large surface area, this can lead to a high surface recombination velocity and, therefore, efficient surface passivation is desirable. For this reason, the b-Si structure 200 is coated with a passivation layer 202 which may be made, for example, of AI2O3. Furthermore, in the embodiment shown in FIG. 2, it is assumed that the semiconductor layer 106 is doped so as to induce the p-n junction under the bottom of the open cavity 108. For example, the semiconductor layer 106 may be n-doped. In this case, the resistive layer 114 is a coating extending from the metal electrode 116 to the bottom of the open cavity 108. For example, the resistive layer 114 may be made of a ceramic material, such as AI2O3, A1OX, SiO, and AIN, or may be any other negative-charge layer. The resistive layer 114 may be shaped as a straight or curved (e.g., meanderlike) stripe extending from the upper edge of the sidewall 110 to its lower edge (i.e., to the bottom of the open cavity 108) . The length of the strip-like resistive layer 114 may be selected such that it has a desired resistance. Furthermore, the resistive layer 114 may be designed such that it has a resistance value equal to at least [50 kOhm] / V, where V is a bias voltage applied to the metal (e.g., Al, Cu, Au, etc.) electrode 116 formed on the upper edge of each sidewall 110 and brought into contact with the p-n junction through the resistive layer 114 in each photosensitive element 102. Also, other embodiments are possible, in which the resistive layer 114 covers the entire sidewall 110 or a certain portion thereof (in the latter case, the other portion may be passivated, for example) .

[0044] In the first exemplary embodiment, the open cavity 108 may have a depth equal to about 75-80% of a thickness of the semiconductor layer 106. For example, the semiconductor layer 106 may have a thickness of 2- 20 microns to provide avalanche with a reasonable voltage .

[0045] In FIG. 2, one can also see a dashed line 204 which schematically delimits an optional heavily p-doped surface region under the metal electrode 116. This heavily doped surface region may be required to provide a proper ohmic contact between the metal electrode 116 and the material of the semiconductor layer 106.

[0046] As also follows from FIG. 2, the cross-section of the open cavity 108 may be trapezoidal, so that the surfaces of the sidewalls 110 which carry the resistive layers 114 are not strictly perpendicular to the bottom of the open cavity 108 but are angled thereto. Such trapezoidal cross-sections are caused by the capabilities of the existing etching techniques. It should be obvious to those skilled in the art that the doping pattern used in the first exemplary embodiment and shown in FIG . 2 may be "inverted" , so that the semiconductor layer 106 is p-doped, the resistive layer 114 is a positive-charge layer, and the surface region under the metal electrode 116 is heavily n-doped .

[0047] FIG . 3 shows a schematic cross-section view of one photosensitive element 102 included in the PM 100 in accordance with a second exemplary embodiment . Like in the first exemplary embodiment , the antiref lective material 112 is again implemented as a needle-shaped b- Si structure 300 which is coated with an optional passivation layer 302 (e . g . , made of AI2O3 ) . Unlike the first exemplary embodiment , a different doping pattern is used in the second exemplary embodiment , which leads to an embedded p-n j unction under the bottom of the open cavity 108 . For example , the semiconductor layer 106 may be initially n-doped, whereupon the p-region may be formed under the bottom of the open cavity 108 . In this case , the ( right ) sidewall 110 is ( at least partly) coated with an insulation (e . g . , dielectric) layer 304 extending from the metal electrode 116 to the bottom of the open cavity 108 , and the resistive layer 114 is configured to extend on the insulation layer 304 from the metal electrode 116 to the bottom of the open cavity 108 . Thus , in the second exemplary embodiment , the resistive layer 114 is not in contact with the material of the semiconductor layer 106. For example , in the second exemplary embodiment , the resistive layer 114 may be made of a semiconductor material .

[0048] The insulation layer 304 and, consequently, the resistive layer 114 extending thereon may cover the entire area of the sidewall 110 or only a part thereof . For example , the insulation layer 304 and the resistive layer 114 may be both shaped as straight or curved (e . g . , meander-like ) stripes extending from the upper edge of the sidewall 110 to its lower edge ( i . e . , to the bottom of the open cavity 108 ) . Again, their lengths may be selected based on a desired resistance to be achieved .

[0049] In FIG . 3 , one can also see a dashed line 306 which schematically delimits an optional heavily p-doped surface region under the metal electrode 116 . This heavily doped surface region is used for the same reason as the one discussed above with reference to FIG . 2 .

[0050] It should be again obvious to those skilled in the art that the doping pattern used in the second exemplary embodiment and shown in FIG . 3 may be "inverted" , so that there is an n-region under the bottom of the open cavity 106 which is in contact with a p-region provided below the n-region, and the surface region under the metal electrode 116 is heavily n-doped .

[0051] FIG . 4 shows a schematic cross-section view of one photosensitive element 102 included in the PM 100 in accordance with a third exemplary embodiment . Like in the first and second exemplary embodiments , the antiref lective material 112 is again implemented as a needle-shaped b-Si structure 400 which is coated with an optional passivation layer 402 (e . g . , made of AI2O3 ) . Unlike the first exemplary embodiment , a different doping pattern is used in the third exemplary embodiment , which leads to an embedded p-n j unction under the bottom of the open cavity 108 . For example , the semiconductor layer 106 may be initially n-doped, whereupon the p-region may be formed under the bottom of the open cavity 108 . In this case , the ( right ) sidewall 110 is ( at least partly) coated with a passivation layer 404 extending from the metal electrode 116 to the bottom of the open cavity 108 , and the resistive layer 114 is configured as a surface inversion layer extending underneath the passivation layer 404 in the semiconductor layer 106 . Preferably, the passivation layer 404 is an AI2O3 layer or any other negative-charge layer . It should be noted that the third exemplary embodiment (i.e., the resistive layer 114 as the surface inversion layer) may also be used when the semiconductor layer 106 is doped so as to provide an induced p-n junction under the bottom of the open cavity 108.

[0052] The passivation layer 404 may cover the entire area of the sidewall 110 or only a part thereof. For example, the passivation layer 404 may be shaped as a straight or curved (e.g., meander-like) stripe extending from the upper edge of the sidewall 110 to its lower edge (i.e., to the bottom of the open cavity 108) . Correspondingly, its length may be selected based on a desired resistance to be achieved by the inversion resistive layer 114 formed underneath the passivation layer 404 and substantially repeating its shape.

[0053] In FIG. 4, one can also see a dashed line 406 which schematically delimits an optional heavily p-doped surface region under the metal electrode 116. This heavily doped surface region is used for the same reason as the one discussed above with reference to FIG. 2. If this surface region is present, the resistive layer 114 extends from it to the p-n junction, as schematically shown in FIG. 4. If this surface region is not used, the resistive layer 114 should extend from the metal electrode 116 to the p-n junction underneath the passivation layer 404.

[0054] It should be again obvious to those skilled in the art that the doping pattern used in the second exemplary embodiment and shown in FIG. 4 may be "inverted", so that there is an n-region under the bottom of the open cavity 106 which is in contact with a p-region provided below the n-region, and the surface region under the metal electrode 116 is heavily n-doped. In this case, the passivation layer 404 should be made of any positive-charge layer.

[0055] FIG. 5 shows a flowchart of a method 500 for manufacturing the photosensitive element 102 in accordance with one exemplary embodiment. The method 500 starts with a step S502 , in which the substrate 104 is provided .

[0056] Then, the method 500 proceeds to a step S504 , in which the semiconductor layer 106 is provided (e . g . , epitaxially grown) on the substrate 104 . For example , the layered structure composed of the substrate 104 and the semiconductor layer 106 may be considered as the so- called epi-wafer .

[0057] Further, the method 500 proceeds to a step S506 , in which the semiconductor layer 106 is etched to form the open cavity 108 . The step S506 may be performed using any suitable etching technique , such as wet etching and / or dry etching .

[0058] Next , the method 500 goes on to a step S508 , in which the semiconductor layer 106 i s doped so as to provide the embedded or induced p-n j unction under the bottom of the open cavity 108 .

[0059] After that , the method 500 proceeds to a step S510 , in which the antiref lective material 112 is provided on the bottom of the open cavity 108 . The step S510 may be performed differently, depending on what type of the antiref lective material 112 is required to obtain . I f it is required to obtain the antiref lective material 112 in the form of b-Si , then reactive-ion etching or metal assisted chemical etching (MACE ) may be used, for example . When the antiref lective material 112 is required to be an antireflection coating, different deposition techniques may be used .

[0060] After the step S510 , the method 500 proceeds to a step S512 , in which the metal electrode 116 is deposited on top of each sidewall 110 of the open cavity 108 . The step S512 may be performed using, for example , atomic layer deposition (ALD) , Chemical Vapor Deposition (CVD) , Ultra-High Vacuum CVD (UHV-CVD) , sputtering, etc .

[0061] After the step S512 , a next step S514 is performed, in which the resistive layer 114 is formed such that the metal electrode 116 and the p-n j unction are in contact with each other through the resistive layer 114. The step S514 may be performed differently, depending on which of the first to third exemplary embodiments of the resistive layers 114 is used. If the first exemplary embodiment shown in FIG. 2 is used, the step S514 may involve depositing the resistive layer 114 on the sidewall 110 by using the same or similar deposition technique (s) as the one(s) used in the step S510. If the second exemplary embodiment shown in FIG. 3 is used, the step S514 may involve deposing the insulation layer 304 first and then depositing the resistive layer 114 on the insulation layer 304 by using the same or similar deposition technique (s) as the one(s) used in the step S510. If the third exemplary embodiment shown in FIG. 4 is used, the step S514 may involve deposing the passivation layer 404 by using the same or similar deposition technique (s) as the one(s) used in the step S510.

[0062] To form the strip-like resistive layer 114, the method 500 may comprise one or more additional steps, in which the resistive layer 114 deposited on the sidewall 110 in accordance with the first exemplary embodiment is further subjected to a suitable lithography technique (e.g., photolithography, electron lithography, etc.) or a suitable etching technique to remove or etch some part thereof from the sidewall 110. In the meantime, the portion of the sidewall 110 from which the deposited resistive layer 114 has been removed (e.g., etched) may be further passivated to reduce recombination losses. In the second and third exemplary embodiments, the same or similar lithography or etching techniques may be used to properly shape the insulation layer 304 or the passivation layer 404.

[0063] Although the exemplary embodiments of the present disclosure are described herein, it should be noted that various changes and modifications could be made in these embodiments, without departing from the scope of legal protection which is defined by the appended claims . In the appended claims , the word "comprising" does not exclude other elements or operations , and the indefinite article "a" or "an" does not exclude a plurality . The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage .

Claims

CLAIMS1 . A photosensitive element for a semiconductor photomultiplier, comprising : a substrate ; and a semiconductor layer provided on the substrate , the semiconductor layer having an open cavity formed therein, the open cavity having a bottom and at least one sidewall surrounding the bottom, the bottom having an antiref lective material provided thereon, the semiconductor layer being doped such that an embedded or induced p-n j unction is provided under the open cavity in the semiconductor layer ; a metal electrode extending on top of the at least one sidewall ; and a resistive layer arranged to provide a contact between the metal electrode and the p-n j unction .2 . The photosensitive element of claim 1 , wherein the at least one sidewall of the open cavity is at least partly coated with a passivation layer extending from the metal electrode to the bottom of the open cavity, and wherein the resistive layer is a surface inversion layer extending underneath the passivation layer .3 . The photosensitive element of claim 1 , wherein the semiconductor layer is doped such that the embedded p-n j unction i s provided under the open cavity in the semiconductor layer, wherein the at least one sidewall of the open cavity is at least partlycoated with an insulation layer extending from the metal electrode to the bottom of the open cavity, and wherein the resistive layer extends on the insulation layer from the metal electrode to the bottom of the open cavity .4 . The photosensitive element of claim 1 , wherein the semiconductor layer is doped such that the induced p-n j unction is provided under the open cavity in the semiconductor layer, and wherein the resistive layer at least partly covers the at least one sidewall of the open cavity and extends from the metal electrode to the bottom of the open cavity .5 . The photosens itive element of any one of claims 2 to 4 , wherein the resistive layer is shaped as a straight or curved strip .6 . The photosens itive element of any one of claims 1 to 5 , wherein the antiref lective material comprises black silicon .7 . The photosensitive element of claim 6 , wherein the black silicon is coated with a passivation layer .8 . The photosens itive element of any one of claims 1 to 7 , wherein the at least one sidewall has a surface region under the metal electrode that is doped so as to provide an ohmic contact between the metal electrode and the semiconductor layer .9 . A semiconductor photomultiplier comprising an array of photosensitive elements according to any one of claims 1 to 8 , wherein the photosensitive elements are arranged adj acent to each other and connected in parallel using the metal electrodes .10 . A method for manufacturing the photosensitive element according to any one of claims 1 to 8 , comprising : providing the substrate ; providing the semiconductor layer on the substrate ; etching the semiconductor layer to form the open cavity; doping the semiconductor layer such that the embedded or induced p-n j unction is provided under the bottom of the open cavity in the semiconductor layer ; providing the antiref lective material on the bottom of the open cavity; depositing the metal electrode on top of the at least one sidewall ; and forming a res istive layer such that the metal electrode and the embedded or induced p-n j unction are in contact with each other through the resistive layer .

Images