Semiconductor device

Abstract

Provided is a semiconductor device which exhibits favorable electrical properties. This semiconductor device comprises an oxide semiconductor layer, a first insulating layer, a conductive layer having a portion overlapping the oxide semiconductor layer with the first insulating layer interposed therebetween, and a second insulating layer having a portion overlapping the first insulating layer with the oxide semiconductor layer interposed therebetween. The oxide semiconductor layer contains indium. The thermal expansion coefficient of the second insulating layer is less than the thermal expansion coefficient of the oxide semiconductor layer. The first insulating layer has a function of capturing oxygen and hydrogen, and the second insulating layer has a region containing excess oxygen.

Description

Semiconductor Devices

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0005] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a low-power central processing unit (CPU) that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of a transistor using an oxide semiconductor.

[0006] Examples of oxide semiconductors that can be used for the active layer of a transistor include indium oxide, indium gallium zinc oxide, etc. Non-Patent Document 1 discloses a thin-film transistor that uses hydrogenated polycrystalline indium oxide formed by low-temperature solid-phase crystallization for the active layer.

[0007] JP 2012-257187 A JP 2011-151383 A

[0008] Y. Magari et al. , “High-mobility hydrogenated polycrystalline In▲2▼O▲3▼(In▲2▼O▲3▼:H) thin-film transistors”, nature COMMUNICATIONS, 13, 1078 (2022)

[0009] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a transistor with high on-state current.An object of one embodiment of the present invention is to provide a transistor with low parasitic capacitance.An object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, memory device, or display device.An object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device, memory device, or display device with low power consumption.An object of one embodiment of the present invention is to provide a memory device with high operating speed.An object of one embodiment of the present invention is to provide a display device with high definition or a high aperture ratio.An object of one embodiment of the present invention is to provide a manufacturing method of the transistor, semiconductor device, memory device, or display device.

[0010] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0011] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer, a first insulating layer, a conductive layer having a portion overlapping with the oxide semiconductor layer with the first insulating layer sandwiched therebetween, and a second insulating layer having a portion overlapping with the first insulating layer with the oxide semiconductor layer sandwiched therebetween. The oxide semiconductor layer contains indium. The thermal expansion coefficient of the second insulating layer is smaller than that of the oxide semiconductor layer.

[0012] In the above semiconductor device, the first insulating layer preferably has a function of capturing oxygen and hydrogen, and the second insulating layer preferably has a region containing excess oxygen.

[0013] In the above semiconductor device, it is preferable that the first insulating layer includes a hafnium oxide film, and the second insulating layer includes a silicon oxide film.

[0014] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer, an oxide layer in contact with the oxide semiconductor layer, an insulating layer having a portion overlapping with the oxide layer with the oxide semiconductor layer sandwiched therebetween, and a conductive layer having a portion overlapping with the oxide semiconductor layer with the insulating layer sandwiched therebetween. The oxide semiconductor layer contains indium. The oxide semiconductor layer includes first crystal grains. The oxide layer includes at least one element that can become a trivalent cation. The oxide layer includes second crystal grains. The first crystal grains and the second crystal grains each have a cubic crystal structure. The crystal orientation of the first crystal grains and the crystal orientation of the second crystal grains are identical or substantially identical.

[0015] In the semiconductor device, the oxide layer preferably contains yttrium and zirconium.

[0016] In the semiconductor device, the oxide layer preferably has a yttrium content of 2 atomic % or more and 15 atomic % or less.

[0017] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer, an oxide layer in contact with the oxide semiconductor layer, an insulating layer having a portion overlapping with the oxide layer with the oxide semiconductor layer sandwiched therebetween, and a conductive layer having a portion overlapping with the oxide semiconductor layer with the insulating layer sandwiched therebetween. The oxide semiconductor layer contains indium. The oxide semiconductor layer includes first crystal grains. The oxide layer includes indium, gallium, and zinc. The oxide layer includes second crystal grains. The first crystal grains have a cubic crystal structure. The second crystal grains have a hexagonal or trigonal crystal structure. The c-axes of the second crystal grains are perpendicular or approximately perpendicular to a surface or a surface on which the oxide layer is formed. The crystal orientation of the first crystal grains with respect to the surface or a surface on which the oxide semiconductor layer is formed is <111>.

[0018] In the semiconductor device, the oxide layer preferably has an atomic ratio of In:Ga:Zn=1:1:1 or a composition therearound, or an atomic ratio of In:Ga:Zn=1:3:2 or a composition therearound.

[0019] In the above semiconductor device, the insulating layer preferably has a stacked structure in which a hafnium oxide film, a silicon oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer side.

[0020] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer, an oxide layer in contact with the oxide semiconductor layer, an insulating layer having a portion overlapping with the oxide layer with the oxide semiconductor layer sandwiched therebetween, a first conductive layer having a portion overlapping with the oxide semiconductor layer with the insulating layer sandwiched therebetween, and a second conductive layer in contact with the oxide layer. The oxide semiconductor layer contains indium. The oxide semiconductor layer has first crystal grains. The oxide layer contains zirconium. The second conductive layer contains indium, tin, and oxygen. The second conductive layer has second crystal grains. The first crystal grains and the second crystal grains each have a cubic crystal structure.

[0021] In the semiconductor device, it is preferable that the crystal orientation of the first crystal grains and the crystal orientation of the second crystal grains coincide or substantially coincide with each other.

[0022] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with large on-state current can be provided. According to one embodiment of the present invention, a transistor with small parasitic capacitance can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, memory device, or display device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device, memory device, or display device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided. According to one embodiment of the present invention, a display device with high definition or a high aperture ratio can be provided. According to one embodiment of the present invention, a manufacturing method of the above transistor, semiconductor device, memory device, or display device can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0024] 1A to 1E are cross-sectional schematic diagrams showing an example of a semiconductor device. FIGS. 2A1 to 2D2 are diagrams illustrating the crystal structure of a metal oxide. FIGS. 3A and 3B are perspective schematic diagrams showing an example of a semiconductor device. FIG. 4A is a plan view showing an example of a semiconductor device. FIGS. 4B to 4D are cross-sectional diagrams showing an example of a semiconductor device. FIGS. 5A and 5B are cross-sectional diagrams showing an example of a semiconductor device. FIGS. 6A and 6B are cross-sectional diagrams showing an example of a semiconductor device. FIG. 7 is a cross-sectional diagram showing an example of a semiconductor device. FIGS. 8A and 8B are cross-sectional diagrams showing an example of a semiconductor device. FIG. 9A is a diagram illustrating changes in metal-oxygen bond length with respect to atomic ratio. FIG. 9B is a diagram illustrating the ionic radius dependence of metal-oxygen bond length. FIG. 9C is a diagram illustrating changes in metal-oxygen bond length with respect to molar ratio. FIGS. 10A and 10B are cross-sectional diagrams showing an example of a semiconductor device. FIGS. 11A to 11D are cross-sectional diagrams showing an example of a semiconductor device. FIGS. 12A and 12B are cross-sectional diagrams showing an example of a semiconductor device. FIGS. 13A and 13B are cross-sectional diagrams showing an example of a semiconductor device. FIG. 14A is a plan view showing an example of a semiconductor device. FIGS. 14B and 14C are cross-sectional views showing an example of a semiconductor device. FIGS. 15A and 15B are cross-sectional views showing an example of a semiconductor device. FIG. 16A is a plan view showing an example of a semiconductor device. FIGS. 16B to 16D are cross-sectional views showing an example of a semiconductor device. FIGS. 17A and 17B are cross-sectional views showing an example of a semiconductor device. FIGS. 18A and 18B are cross-sectional views showing an example of a semiconductor device. FIG. 19 is a cross-sectional view showing an example of a semiconductor device. FIG. 20A is a plan view showing an example of a semiconductor device. FIGS. 20B to 20D are cross-sectional views showing an example of a semiconductor device. FIGS. 21A and 21B are cross-sectional views showing an example of a semiconductor device. FIG. 22A is a plan view showing an example of a semiconductor device. FIGS. 22B to 22D are cross-sectional views showing an example of a semiconductor device. FIG. 23A is a plan view showing an example of a semiconductor device. FIGS. 23B and 23C are cross-sectional views showing an example of a semiconductor device. FIGS. 24A to 24C are schematic perspective views showing an example of a semiconductor device. FIG. 25A is a plan view showing an example of a semiconductor device. 25B to 25D are cross-sectional views showing an example of a semiconductor device.FIG. 26A is a plan view showing an example of a semiconductor device. FIGS. 26B and 26C are cross-sectional views showing an example of a semiconductor device. FIG. 27A is a plan view showing an example of a semiconductor device. FIGS. 27B and 27C are cross-sectional views showing an example of a semiconductor device. FIG. 28A is a plan view showing an example of a semiconductor device. FIGS. 28B to 28D are cross-sectional views showing an example of a semiconductor device. FIGS. 29A and 29B are cross-sectional views showing an example of a semiconductor device. FIGS. 30A to 30C are cross-sectional views showing an example of a semiconductor device. FIG. 31A is a plan view showing an example of a semiconductor device. FIGS. 31B to 31D are cross-sectional views showing an example of a semiconductor device. FIG. 32A is a plan view showing an example of a semiconductor device. FIGS. 32B to 32D are cross-sectional views showing an example of a semiconductor device. FIGS. 33A to 33C are cross-sectional views showing an example of a semiconductor device. FIG. 34A is a plan view showing an example of a semiconductor device. FIGS. 34B to 34D are cross-sectional views showing an example of a semiconductor device. FIG. 35 is a cross-sectional view showing an example of a semiconductor device. FIG. 36A is a plan view showing an example of a memory device. 36B and 36C are cross-sectional views showing an example of a memory device. FIGS. 37A to 37C are cross-sectional views showing an example of a memory device. FIG. 38A is a plan view showing an example of a memory device. FIGS. 38B and 38C are cross-sectional views showing an example of a memory device. FIGS. 39A and 39B are cross-sectional views showing an example of a memory device. FIG. 40A is a plan view showing an example of a memory device. FIG. 40B is a cross-sectional view showing an example of a memory device. FIG. 41 is a cross-sectional view showing an example of a memory device. FIG. 42 is a cross-sectional view showing an example of a memory device. FIG. 43 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 44A to 44G are diagrams illustrating an example of a circuit configuration of a memory cell. FIGS. 45A and 45B are perspective views illustrating an example of a configuration of a semiconductor device. FIG. 46 is a block diagram illustrating a CPU. FIGS. 47A and 47B are perspective views of a semiconductor device. FIGS. 48A and 48B are perspective views of a semiconductor device. FIG. 49 is a conceptual diagram illustrating the layers of a memory device. FIGS. 50A and 50B are perspective views showing an example of a display device. FIG. 51 is a cross-sectional view showing an example of a display device. FIG. 52 is a cross-sectional view showing an example of a display device.53A and 53B are diagrams showing an example of an electronic component. FIGS. 54A to 54C are diagrams showing an example of a mainframe computer. FIG. 54D is a diagram showing an example of space equipment. FIG. 54E is a diagram showing an example of a storage system applicable to a data center. FIGS. 55A to 55F are diagrams showing an example of electronic equipment. FIGS. 56A to 56G are diagrams showing an example of electronic equipment. FIGS. 57A to 57F are diagrams showing an example of electronic equipment. FIGS. 58A and 58B are results of SIMS analysis of samples according to the example. FIG. 59 is a diagram showing evaluation results of reliability tests on transistors. FIGS. 60A to 60C are diagrams showing evaluation results of reliability tests on transistors.

[0025] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0026] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0027] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0028] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0029] A transistor is a type of semiconductor element that can amplify current or voltage, and perform a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0030] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0031] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0032] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0033] In this specification and the like, the term "content" refers to the ratio of a component contained in a film. For example, when an oxide semiconductor layer contains a metal element X, a metal element Y, and a metal element Z, the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is expressed as A Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A ＺIn addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the oxide semiconductor layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0034] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0035] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0036] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0037] In this specification, when two nodes are connected via an insulator such as a dielectric of a capacitive element, a gate insulating film of a transistor, or an interlayer insulating film, this is not considered to be an "electrical connection."

[0038] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0039] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0040] In this specification and the like, a cubic crystal structure may be referred to as a cubic crystal, a cubic crystal structure, etc. The same applies to other crystal systems (hexagonal, trigonal, tetragonal, orthorhombic, monoclinic, and triclinic).

[0041] Embodiment 1 In this embodiment, a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention includes a transistor.

[0042] 1A is a schematic cross-sectional view of a semiconductor device according to one embodiment of the present invention, which includes a semiconductor layer 30, an insulating layer 50, and a conductive layer 60 that overlaps with the semiconductor layer 30 with the insulating layer 50 sandwiched therebetween.

[0043] In the transistor according to one embodiment of the present invention, the conductive layer 60 functions as a gate electrode, and the insulating layer 50 functions as a gate insulating layer. The semiconductor layer 30 has a channel formation region. At least part of a region of the semiconductor layer that overlaps with the conductive layer 60 with the insulating layer 50 interposed therebetween functions as the channel formation region.

[0044] A transistor according to one embodiment of the present invention includes a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor in a semiconductor layer 30 including a channel formation region. That is, the transistor can be referred to as an OS transistor. Note that in this specification and the like, a semiconductor layer including an oxide semiconductor can be referred to as an oxide semiconductor layer.

[0045] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) may generate electrons that serve as carriers. Therefore, if the channel formation region in the oxide semiconductor contains oxygen vacancies, the OS transistor is likely to be normally on. Therefore, it is preferable that oxygen vacancies and impurities be reduced as much as possible in the channel formation region in the oxide semiconductor. It is also preferable that hydrogen be reduced as much as possible in the channel formation region in the oxide semiconductor. In other words, it is preferable that the carrier concentration in the channel formation region in the oxide semiconductor be reduced and the channel formation region in the oxide semiconductor be made i-type (intrinsic) or substantially i-type.

[0046] Furthermore, when an excessive amount of oxygen is supplied to the semiconductor layer 30, electron traps due to the excess oxygen are formed in the insulating layer 50. This makes the OS transistor more susceptible to positive drift degradation in a +GBT (gate bias-temperature) stress test. In other words, the amount of positive drift degradation in the +GBT stress test increases.

[0047] Therefore, in the semiconductor device of one embodiment of the present invention, the hydrogen concentration in the semiconductor layer 30 is preferably low. Furthermore, an appropriate amount of oxygen is preferably supplied to the semiconductor layer 30. Furthermore, it is preferable to reduce the amount of excess oxygen in the semiconductor layer 30.

[0048] The semiconductor layer 30 preferably includes indium oxide. In this case, the semiconductor layer 30 includes indium and oxygen. For example, the semiconductor layer 30 preferably includes an indium oxide film. The higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements included in the metal oxide, the higher the field-effect mobility of the transistor. Therefore, by using indium oxide for the semiconductor layer 30, the transistor can achieve a large on-state current and high frequency characteristics.

[0049] Furthermore, the indium oxide film preferably has crystallinity. For example, the indium oxide film preferably has crystal grains. Examples of the film having crystal grains include a single crystal film, a polycrystalline film, and an amorphous film containing crystal grains.

[0050] The indium oxide film is preferably single crystal. Since single crystal does not have grain boundaries, carrier scattering at the grain boundaries can be suppressed, and a transistor with high field-effect mobility and high reliability can be realized.

[0051] The indium oxide film may be polycrystalline or amorphous containing crystal grains. In this case, it is preferable that no crystal grain boundaries are observed in the channel formation region or that the grain boundary components are small. For example, by locating one crystal grain in the channel formation region, a structure in which no crystal grain boundaries are observed in the channel formation region can be achieved. Even in such a structure, the same effects as in a structure in which the indium oxide film is single crystal can be achieved.

[0052] Furthermore, two or more crystal grains may be located in the channel formation region. For example, when first and second crystal grains are located in the channel formation region, it is preferable that the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide. When the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide, a crystal grain boundary may not be observed at the boundary between the first crystal grain and the second crystal grain. By ensuring that the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide, the formation of a crystal grain boundary between the first crystal grain and the second crystal grain can be suppressed. Therefore, even with this configuration, the same effects as those of a configuration in which the indium oxide film is single crystal can be achieved. The fact that the crystal orientations of the first crystal grains and the second crystal grains are aligned or substantially aligned can sometimes be confirmed, for example, by a high-resolution transmission electron microscope (TEM) image. Specifically, this can be confirmed by the fact that the lattice fringes of the first crystal grains and the lattice fringes of the second crystal grains are continuously connected at the boundary between the first crystal grains and the second crystal grains in the high-resolution TEM image.

[0053] In this specification, the term "grain boundary" refers to, for example, a boundary between adjacent crystal grains with different crystal orientations. Therefore, in this specification, the term "grain boundary" does not include a boundary between adjacent crystal grains with the same crystal orientation. For example, even if a boundary between two crystal grains is observed in a high-resolution TEM image, if the crystal orientations of the two crystal grains are the same or nearly the same, the boundary may not be called a grain boundary.

[0054] The crystal orientation can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). Alternatively, it can be evaluated by a pattern (also called an FFT pattern) obtained by performing fast Fourier transform (FFT) processing on a TEM image. The FFT pattern reflects the same reciprocal lattice space information as the diffraction pattern.

[0055] For example, when the difference in angle between the FFT patterns of the first crystal grain and the second crystal grain is −5 degrees or more and 5 degrees or less, preferably −3 degrees or more and 3 degrees or less, more preferably −2 degrees or more and 2 degrees or less, it can be said that the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide. Note that, for example, the angle of the FFT pattern in the

[111] orientation refers to the acute angle formed by the approximation line between the spot resulting from the (222) plane or the spot resulting from the (−2-2-2) plane and the central spot, and a reference line (for example, a line extending in the vertical direction).

[0056] In a crystalline film, for example, crystal grains can be confirmed in a high-resolution TEM image. In addition, in a crystalline film, for example, crystal grain boundaries can be confirmed in a high-resolution TEM image. That is, crystal grains and crystal grain boundaries can be observed in a high-resolution TEM image of a crystalline film. The total magnification when acquiring a TEM image is preferably 2,000,000 times or more, and more preferably 4,000,000 times or more.

[0057] The degree of polycrystallinity of an indium oxide film can be evaluated by the grain size of the crystal grains. The grain size can be calculated, for example, by calculating the area of ​​the crystal grain and assuming a perfect circle corresponding to the calculated area as the diameter of the circle. The diameter in this case is sometimes called the area-equivalent diameter or the like.

[0058] The degree of polycrystallinity of an indium oxide film can also be evaluated by the extension length of the grain boundaries. The extension length of the grain boundaries can be calculated, for example, by extracting a field of view of a specific area from a TEM image of the film acquired at a total magnification at which the grain boundaries can be observed, and calculating the total length of the grain boundaries observed in that field of view. An indium oxide film with a grain boundary extension length of 0 nm can be considered to be single crystalline. Furthermore, the longer the extension length of the grain boundaries, the more grain boundary components there are.

[0059] The extension length of the grain boundaries in the indium oxide film is preferably 0 nm or more and 1500 nm or less, more preferably 0 nm or more and 1000 nm or less, and even more preferably 0 nm or more and 800 nm or less. By having the indium oxide film with an extension length of the grain boundaries in the above range in the semiconductor layer 30, a configuration in which no crystal grain boundaries are observed or the grain boundary components are small can be realized in the channel formation region. Note that, unless otherwise specified in this specification, the area of ​​the field of view used to calculate the extension length of the grain boundaries is 90 nm square.

[0060] The thickness of the semiconductor layer 30 is preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, even more preferably 2.5 nm to 20 nm, even more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. It is sufficient that at least a portion of the semiconductor layer 30 has a region with the above-described thickness. For example, it is sufficient that the channel formation region of the semiconductor layer 30 has a region with the above-described thickness. By setting the thickness of the semiconductor layer 30 within the above range, the crystallinity of the semiconductor layer 30 can be improved. By improving the crystallinity of the semiconductor layer 30, the semiconductor layer 30 can have crystal grains.

[0061] When a metal oxide contains indium and zinc, the metal oxide may have high crystallinity, for example, a c-axis aligned crystalline (CAAC) structure. The CAAC structure has fewer grain boundaries in the a-b plane than a polycrystalline structure. Examples of metal oxides containing indium and zinc include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)) and indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO).

[0062] In an oxide semiconductor layer with high crystallinity, an indium oxide film is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO film. Therefore, it can be said that an indium oxide film is a film through which one or both of hydrogen and oxygen are more easily supplied and from which one or both of hydrogen and oxygen are more easily discharged than, for example, an IGZO film. Note that it can be said that an indium oxide film is a film with high permeability to one or both of hydrogen and oxygen compared to, for example, an IGZO film. In other words, it can be said that an indium oxide film is a film with low barrier properties against one or both of hydrogen and oxygen compared to, for example, an IGZO film.

[0063] The indium oxide film is heated at a temperature of 400° C. for 8 hours, and the oxygen concentration is 1×10 ２０ atoms / cm ３ 2x10 or more ２１ atoms / cm ３ Below 2 × 10, preferably ２０ atoms / cm ３ 1x10 or more ２１ atoms / cm ３ Furthermore, the indium oxide film can transmit, for example, 1×10 ２０ atoms / cm ３ 2 x 10 or more ２１ atoms / cm ３ Below 2 × 10, preferably ２０ atoms / cm ３ 1x10 or more ２１ atoms / cm ３ It is preferable that the following oxygen has the property of diffusing within the crystal grains.

[0064] Oxygen in the indium oxide film diffuses through the crystal grains and grain boundaries, and V present in the crystal grains or grain boundaries is removed. Ｏ and V Ｏ H can be reduced. Therefore, the transistor can be prevented from becoming normally on. This means that the negative shift of the threshold voltage of the transistor can be theoretically eliminated.

[0065] The permeability of the membrane to oxygen and hydrogen can be evaluated by calculation using a method called Nudged Elastic Band (NEB). Specifically, the permeability can be evaluated by calculating the migration barrier of oxygen atoms and hydrogen atoms using the NEB method. The smaller the migration barrier value, the easier it is for the atoms to move (permeate).

[0066] An example of the calculation results is shown in Table 1. ２ O ３ is a crystal model of indium oxide, and IGZO shown in Table 1 is a crystal model of In—Ga—Zn oxide.

[0067]

[0068] From Table 1, the barriers to the movement of oxygen, hydrogen, and excess oxygen are large in the crystal model of In-Ga-Zn oxide and small in the crystal model of indium oxide. This suggests that oxygen and hydrogen move more easily (permeate more easily) in an indium oxide film than in an In-Ga-Zn oxide film. It also suggests that an indium oxide film has higher permeability to oxygen atoms and hydrogen atoms than an In-Ga-Zn oxide film. Therefore, it is presumed that an indium oxide film is a film into which hydrogen and oxygen are easily supplied and from which hydrogen and oxygen are easily discharged. In addition, the V that occurred in the +GBT test Ｏ It is expected that this will have the effect of filling the gap with oxygen, thereby enabling the realization of highly reliable transistors.

[0069] The crystallinity of the semiconductor layer 30 can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these techniques may be used for analysis.

[0070] The content of the first element in the semiconductor layer 30 is preferably low. Furthermore, the concentration of the first element in the semiconductor layer 30 is preferably low. In particular, the concentration of the first element in the channel formation region is preferably low. Here, the first element is at least one of boron, carbon, aluminum, silicon, zinc, and gallium. That is, in the semiconductor layer 30, the concentration of any one of boron, carbon, aluminum, silicon, zinc, and gallium is preferably low, the concentrations of two selected from boron, carbon, aluminum, silicon, zinc, and gallium are more preferably low, and the concentrations of all of boron, carbon, aluminum, silicon, zinc, and gallium are even more preferably low. The concentration of the first element in the semiconductor layer 30 is, for example, preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less. The preferred concentration of the first element in the semiconductor layer 30 can also be said to be the preferred concentration of the first element in the channel formation region.

[0071] Furthermore, as will be described later, by using a precursor that has been distilled one or more times, it is possible to set the concentration of the first element in the semiconductor layer 30 to 0.01 atomic % (100 ppm) or less, 0.0001% (1 ppm) or less, 0.00001% (0.1 ppm or 100 ppb) or less, or 0.0000001% (0.001 ppm or 1 ppb) or less. In other words, the content (purity) of indium excluding oxygen in the semiconductor layer 30 can be set to 99.99 atomic % or more (4N), 99.9999 atomic % or more (6N), 99.99999 atomic % or more (7N), or 99.9999999 atomic % or more (9N), which may enable the formation of a semiconductor layer 30 having a purity comparable to the purity (10N) of silicon used in the semiconductor layer.

[0072] By reducing the concentrations of boron, carbon, aluminum, and silicon in the semiconductor layer 30, the crystallinity of the semiconductor layer 30 can be improved.

[0073] When the semiconductor layer 30 contains gallium atoms, the gallium atoms bond with excess oxygen atoms to form a Ga—O structure. The Ga—O structure functions as an acceptor that traps electrons. Therefore, a transistor having a semiconductor layer 30 containing gallium atoms and excess oxygen atoms exhibits a large variation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test. Therefore, by lowering the gallium concentration in the semiconductor layer 30, the variation in threshold voltage in the PBTS test can be reduced. This results in a transistor with high reliability against positive bias application. Note that the same phenomenon as when the semiconductor layer 30 contains zinc atoms may occur.

[0074] Furthermore, aluminum atoms, gallium atoms, and zinc atoms have stronger bonding strength with oxygen atoms than indium atoms, so that by reducing the concentrations of aluminum, gallium, and zinc in the indium oxide film, it is possible to prevent the oxygen permeability from decreasing.

[0075] Furthermore, impurities such as the first element contained in the indium oxide film can become crystal nuclei. Reducing the impurities in the indium oxide film as much as possible reduces the number of crystal nuclei, which can promote the growth of large crystal grains, as described below.

[0076] Furthermore, by reducing the impurities in the indium oxide film, it is possible to suppress impurity scattering. Therefore, a transistor with high field-effect mobility can be realized. For example, by setting the concentration of the first element in the semiconductor layer 30 within the above-mentioned preferable range, the field-effect mobility of the transistor can be increased to 100 cm ２ / (V·s) or more, preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0077] The concentration of the first element can be measured by, for example, inductively coupled plasma mass spectrometry (ICP-MS), XPS, secondary ion mass spectrometry (SIMS), time-of-flight secondary ion mass spectrometry (ToF-SIMS), Auger electron spectroscopy (AES), energy dispersive X-ray spectrometry (EDX), or the like. The evaluation can be performed using, for example, inductively coupled plasma-atomic emission spectroscopy (ICP-AES), or inductively coupled plasma-atomic emission spectroscopy (ICP-AES).

[0078] The band gap of indium oxide is greater than or equal to 2.5 eV and less than or equal to 3.7 eV. By using indium oxide with a wide band gap for the semiconductor layer 30, the off-state current of the transistor can be reduced, and the power consumption of the semiconductor device can be sufficiently reduced.

[0079] An OS transistor is an accumulation-type transistor in which electrons serve as majority carriers. That is, the carriers in an OS transistor are electrons. Assuming that the relaxation time of carriers is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility (carrier mobility). That is, by using a metal oxide film with a small effective mass of electrons for the semiconductor layer of a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0080] Here, the effective mass of the electron in the semiconductor material (m ＊ ｅ ), the effective mass of the hole (m ＊ ｈ ), and band gap (E ｇ ) are shown in Table 2. The semiconductor materials shown in Table 2 are indium oxide (here, In ２ O ３), In—Ga—Zn oxide (IGZO), and silicon (Si). ＊ ｅ and m ＊ ｈ is a value calculated by first-principles electronic structure calculation, and Eg shown in Table 2 is a value calculated by actual measurement. Note that Eg of silicon in Table 2 shows a representative actual measurement value.

[0081]

[0082] As shown in Table 2, the effective mass of electrons in indium oxide is small. Therefore, by using indium oxide, which has a small effective mass of electrons, for the semiconductor layer 30, it is possible to realize a transistor with a large on-state current, a transistor with high field-effect mobility, and a transistor with high frequency characteristics (also referred to as f characteristics). Furthermore, the effective mass of electrons in indium oxide is smaller than the effective mass of electrons in, for example, silicon. Therefore, from the perspective of the effective mass of electrons, the f characteristics of a transistor using indium oxide in the channel formation region are higher than the f characteristics of a Si transistor.

[0083] As shown in Table 2, the effective mass of holes in indium oxide is large. Therefore, by using indium oxide, which has a large effective mass of holes, for the semiconductor layer 30, a transistor with an extremely small off-state current can be realized. Furthermore, the effective mass of holes in indium oxide is larger than the effective mass of holes in, for example, silicon. Therefore, in terms of the effective mass of holes, the off-state current of a transistor using indium oxide for a channel formation region is sufficiently smaller than the off-state current of a Si transistor.

[0084] In a transistor using indium oxide for the semiconductor layer 30, the off-state current value per 1 μm of channel width at room temperature (25° C.) is 1×10 −１７ A / μm or less, preferably 1×10 −１８ A / μm or less, more preferably 1×10 −１９ The off-state current value at 85° C. per 1 μm of channel width can be reduced to 1×10 −１６ A / μm or less, preferably 1×10 −１７ A / μm or less, more preferably 1×10 −１８It is possible to make it less than A / μm.

[0085] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. For example, the cutoff frequency (fT) of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be set to 50 GHz or higher, preferably 100 GHz or higher, and more preferably 150 GHz or higher at room temperature (25° C.).

[0086] The channel tends to flow in a region of the semiconductor layer 30 that is 1 nm deep from the surface on the insulating layer 50 side. Therefore, the channel formation region may refer to a region of the semiconductor layer 30 that overlaps with the conductive layer 60 and is 1 nm deep or less from the surface on the insulating layer 50 side. The channel formation region may also refer to a region of the semiconductor layer 30 that overlaps with the conductive layer 60 and is 1 nm deep or less from the interface with the insulating layer 50.

[0087] The interface between the semiconductor layer 30 and the insulating layer 50 can be confirmed by, for example, a cross-sectional TEM image, a cross-sectional scanning transmission electron microscope (STEM) image, etc. The interface between the semiconductor layer 30 and the insulating layer 50 can sometimes be confirmed by using SIMS or by performing line analysis of the composition by EDX on the interface between the semiconductor layer 30 and the insulating layer 50 and its vicinity.

[0088] For example, EDX line analysis is performed on the interface and its vicinity, with the direction perpendicular to the surface on which the semiconductor layer 30 is formed as the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., aluminum) that is the main component of the insulating layer 50 but is not the main component of the semiconductor layer 30 becomes half-value can be defined as the interface. Alternatively, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., indium) that is the main component of the semiconductor layer 30 but is not the main component of the insulating layer 50 becomes half-value can be defined as the interface.

[0089] The indium oxide film may contain one or more metal elements having a large period number in the periodic table, provided that the film has crystallinity. The greater the overlap of the orbitals of the metal elements, the greater the carrier conduction. Therefore, by including a metal element having a large period number in the periodic table, the field-effect mobility of the transistor may be improved. Examples of metal elements having a large period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, and light rare earth elements (lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium).

[0090] The insulating layer 50 preferably has a function of supplying oxygen to the semiconductor layer 30. The insulating layer 50 preferably has a region containing oxygen that is desorbed by heating (hereinafter, may be referred to as excess oxygen), for example. When the insulating layer having the region containing excess oxygen is in contact with the semiconductor layer 30, oxygen can be supplied to the semiconductor layer 30. The oxygen supplied to the semiconductor layer 30 repairs oxygen vacancies, and the amount of oxygen vacancies in the semiconductor layer 30 can be reduced. Examples of insulating materials that easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0091] The insulating layer 50 preferably has a function of capturing or fixing oxygen (also referred to as gettering). As described above, an indium oxide film is a film through which oxygen easily moves. Therefore, when the insulating layer 50 has the function of capturing or fixing oxygen, excess oxygen in the semiconductor layer 30 can be diffused to the insulating layer 50 and the oxygen can be captured or fixed. Therefore, the OS transistor can suppress positive drift degradation in a +GBT stress test caused by excess oxygen. Examples of insulating materials having a function of capturing or fixing oxygen include aluminum oxide, hafnium oxide, hafnium zirconium oxide, and an oxide containing hafnium and silicon (hafnium silicate).

[0092] Aluminum oxide, hafnium oxide, hafnium zirconium oxide, and hafnium silicate have the function of capturing or fixing hydrogen. As described above, an indium oxide film is a film through which hydrogen easily moves. Therefore, since the insulating layer 50 has the function of capturing or fixing hydrogen, hydrogen in the semiconductor layer 30 can be diffused into the insulating layer 50 and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 30 (particularly the hydrogen concentration in the channel formation region) can be reduced. Therefore, the V in the channel formation region Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0093] It is preferable to use a highly conductive material such as tungsten for the conductive layer 60. It is also preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion for the conductive layer 60. Examples of such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 60.

[0094] Furthermore, the conductive layer 60 preferably uses a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. For example, one or more selected from indium tin oxide (In-Sn oxide, also referred to as ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In-Zn oxide, and indium tin oxide containing silicon oxide (also referred to as ITSO) may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an insulating layer outside the transistor may be captured.

[0095] As shown in FIG. 1B , an oxide layer 27 can be provided so as to be in contact with at least a portion of the surface of the semiconductor layer 30 facing the surface on the insulating layer 50 side. The oxide layer 27 has a portion that overlaps with the insulating layer 50, with the semiconductor layer 30 sandwiched therebetween. In other words, the insulating layer 50 has a portion that overlaps with the oxide layer 27, with the semiconductor layer 30 sandwiched therebetween. The semiconductor layer 30 is provided on the oxide layer 27 and has a region that contacts the oxide layer 27. The oxide layer 27 is a layer that causes crystal grains contained in the semiconductor layer 30 to grow from below, or a layer that does not inhibit the crystal grains contained in the semiconductor layer 30 from growing from above. When the oxide layer 27 has the function of causing crystal grains contained in the semiconductor layer 30 to grow from below, the oxide layer 27 can be called a seed layer.

[0096] The crystal structure of indium oxide is cubic (bixbyite type). When indium oxide is used for the semiconductor layer 30, it is preferable to use an oxide having a cubic crystal structure for the oxide layer 27. When the oxide layer 27 has the same crystal structure as the semiconductor layer 30, the semiconductor layer 30 can be epitaxially grown using the oxide layer 27 as a nucleus, thereby improving the crystallinity of the semiconductor layer 30. Note that the crystal structure of an oxide containing a Group 3 element in the periodic table is likely to be cubic. Furthermore, the Group 3 element in the crystal is mainly present as a trivalent cation. Therefore, it is preferable that the oxide layer 27 contains at least one element that can become a trivalent cation. The element that can become a trivalent cation contained in the oxide layer 27 is preferably scandium, yttrium, cerium, gadolinium, erbium, ytterbium, or the like.

[0097] For example, an oxide containing one or both of yttrium and zirconium, erbium oxide, etc. can be used as the oxide layer 27. Examples of oxides containing one or both of yttrium and zirconium include yttrium oxide, zirconium oxide, and yttrium zirconium oxide.

[0098] When the semiconductor layer 30 and the oxide layer 27 have the same crystal structure, it is preferable that the crystal orientation of the crystal of the semiconductor layer 30 and the crystal orientation of the crystal of the oxide layer 27 are the same or substantially the same. Note that the crystal orientation of the crystal of the oxide layer 27 is not particularly limited. For example, it may be <100>, <110>, or <111>. In this specification and the like, the crystal orientation of a crystal refers to the direction relative to the surface of a film containing the crystal or the surface on which the crystal is to be formed. Therefore, for example, a crystal with a crystal orientation of <100> can be said to be a crystal whose (100) plane is parallel to the surface of a film containing the crystal or the surface on which the crystal is to be formed.

[0099] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, due to formatting constraints, in this specification, instead of adding a bar above the numbers, they may be expressed by adding a minus sign (-) before the numbers. Furthermore, individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent directions are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0100] It is preferable that the difference (also referred to as lattice mismatch) between the lattice constant or unit lattice vector of the crystal of the oxide layer 27 and the lattice constant or unit lattice vector of the crystal of the semiconductor layer 30 is small. By using an oxide that reduces the lattice mismatch for the oxide layer 27, the crystallinity of the semiconductor layer 30 can be improved.

[0101] One method for evaluating the degree of lattice mismatch is to use the lattice mismatch value shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, an indium oxide film) with respect to the crystals of the seed layer is calculated by the following mathematical formula (1). Hereinafter, the lattice mismatch Δa of the crystals of the formed film with respect to the crystals of the seed layer may be simply referred to as the lattice mismatch Δa of the formed film with respect to the seed layer.

[0102]

[0103] In formula (1), L １ is the lattice constant or the length of the unit lattice vector of the crystal of the formed film, and L ２ is the lattice constant or the length of the unit lattice vector of the crystal of the seed layer.

[0104] The lattice mismatch Δa of the crystal grains of the semiconductor layer 30 with respect to the crystal grains of the oxide layer 27 is preferably −10% to 10%, more preferably −5% to 5%, and even more preferably −3% to 3%. By using a material for the oxide layer 27 that reduces the lattice mismatch with the semiconductor layer 30, the crystallinity of the semiconductor layer 30 can be improved.

[0105] For example, the lattice constant of indium oxide crystal (bixbyite type) is said to be 1.01194 nm. Furthermore, the lattice constant of yttrium oxide crystal (bixbyite type) is said to be 1.05976 nm. Therefore, the lattice mismatch of indium oxide crystal with respect to yttrium oxide crystal is −4.5%. Therefore, when indium oxide is used for the semiconductor layer 30, yttrium oxide can be used for the oxide layer 27.

[0106] FIG. 2A1 shows the indium oxide crystal viewed from a direction parallel to the (100) plane, and FIG. 2A2 shows the yttrium oxide crystal viewed from a direction parallel to the (100) plane. Also, FIG. 2B1 shows the indium oxide crystal viewed from a direction parallel to the (111) plane, and FIG. 2B2 shows the yttrium oxide crystal viewed from a direction parallel to the (111) plane. The lattice mismatch of the indium oxide crystal with respect to the yttrium oxide crystal is -4.5% in both cases where the bonding surfaces are (100) planes and where the bonding surfaces are (111) planes. Furthermore, the cross-sectional area is 1.604 nm when the bonding surfaces are (100) planes. ２ When the bonding surfaces are (111) faces, it is 1.843 nm. ２In this specification and the like, the cross-sectional area calculated together with the lattice mismatch refers to the area of ​​the junction (superlattice) between the seed layer and the formed film, and indicates the area of ​​the junction on the side of the formed film. Since the formed film grows epitaxially around the junction, a material with a small junction area is preferable as a base for epitaxial growth.

[0107] For example, the lattice constant of erbium oxide crystal (bixbyite type) is said to be 1.0582 nm. Therefore, the lattice mismatch of indium oxide crystal with erbium oxide crystal is −4.4%. Therefore, when indium oxide is used for the semiconductor layer 30, erbium oxide can be used for the oxide layer 27.

[0108] Figure 2C1 shows the indium oxide crystal viewed from a direction parallel to the (100) plane, and Figure 2C2 shows a view from a direction parallel to the erbium oxide crystal. Figure 2D1 shows the indium oxide crystal viewed from a direction parallel to the (111) plane, and Figure 2D2 shows the erbium oxide crystal viewed from a direction parallel to the (111) plane. The lattice mismatch of the indium oxide crystal with the erbium oxide crystal is -4.4% both when the bonding surfaces are (100) planes and when the bonding surfaces are (111) planes. Furthermore, the cross-sectional area is 1.123 nm when the bonding surfaces are (100) planes. ２ When the bonding surfaces are (111) faces, it is 1.945 nm. ２ is.

[0109] For example, Zr, which is an example of yttrium zirconium oxide, ０．９ Y ０．１ O １．９５ The lattice constant of the crystal (fluorite type) is 0.51481 nm (see ICSD coll.code.248790). ０．９ Y ０．１ O １．９５The lattice mismatch of indium oxide crystal with indium oxide crystal is −1.7%. Therefore, when indium oxide is used for the semiconductor layer 30, yttrium zirconium oxide can be suitably used for the oxide layer 27. Note that yttrium zirconium oxide contains yttrium, zirconium, and oxygen.

[0110] Adding yttrium or yttrium oxide to zirconium oxide, that is, increasing the yttrium content in yttrium zirconium oxide to greater than 0 atomic%, can stabilize the crystalline structure of zirconium oxide. However, if the content is too high, the crystalline structure of yttrium zirconium oxide may change from a cubic system to another system, so it is preferable that the content is not too high. Therefore, for example, the yttrium content in yttrium zirconium oxide is preferably 2 atomic% or more and 20 atomic% or less, more preferably 2 atomic% or more and 15 atomic% or less, and more preferably 5 atomic% or more and 10 atomic% or less.

[0111] When yttrium zirconium oxide is used as the oxide layer 27 and indium oxide is used as the semiconductor layer 30, a buffer layer containing indium and zirconium may be formed at the interface between the oxide layer 27 and the semiconductor layer 30. Since the ionic radii of indium and zirconium are different, it is presumed that the lattice constant or unit lattice vector of the crystal of the buffer layer will be a value between the lattice constant or unit lattice vector of the crystal of yttrium zirconium oxide and the lattice constant or unit lattice vector of the crystal of indium oxide. Therefore, by forming the buffer layer, it is possible to reduce the lattice mismatch between the oxide layer 27 and the semiconductor layer 30, and improve the crystallinity of the semiconductor layer 30.

[0112] The element added to stabilize the crystal structure of zirconium oxide is not limited to yttrium. For example, a rare earth element (specifically, scandium, lanthanum, cerium, erbium, etc.) to which yttrium belongs, or an oxide thereof, may be added to zirconium oxide. Alternatively, an alkaline earth metal such as magnesium or calcium, or an oxide thereof, may be added to zirconium oxide.

[0113] Note that oxides that can have a cubic crystal structure, such as erbium oxide and yttrium oxide, may have a barrier property against hydrogen or a function of capturing or fixing hydrogen. By using such oxides for the oxide layer 27, it is possible to suppress diffusion of hydrogen from below the semiconductor layer 30 or to reduce the hydrogen concentration in the semiconductor layer 30.

[0114] Note that the crystal orientation of the oxide layer 27 and the crystal orientation of the semiconductor layer 30 may not necessarily be the same. For example, an oxide layer 27 having hexagonal or trigonal crystals can be provided under the semiconductor layer 30. In this case, by setting the crystal orientation of the surface of the oxide layer 27 to <001>, the semiconductor layer 30 having crystals with a crystal orientation of <111> can be formed. When the crystal orientation of the surface of the oxide layer 27 is <001>, the c-axis of the crystals of the oxide layer 27 is perpendicular or approximately perpendicular to the surface of the oxide layer 27 or the surface on which it is formed. Note that hexagonal or trigonal crystals can sometimes be referred to as crystals with a layered structure. Therefore, the above structure can be considered as a structure in which a semiconductor layer having cubic crystals is formed on an oxide layer having crystals with a layered structure. In other words, it can also be considered as a stacked structure manufactured using a heteroepitaxial growth technique or a technique similar to heteroepitaxial growth.

[0115] Specific examples of the oxide layer 27 that can be used include zinc oxide, indium gallium oxide (In—Ga oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), In—Ga—Zn oxide, and indium tin zinc oxide (In—Sn—Zn oxide). When In—Ga—Zn oxide is used as the oxide layer 27, the oxide layer 27 contains indium, gallium, and zinc. Specifically, the oxide layer 27 may have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition therearound, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition therearound. The term "nearby composition" includes a range of ±30% of the desired atomic ratio.

[0116] In—Ga—Zn oxide, In—Sn—Zn oxide, and the like tend to have a CAAC structure. When an oxide having a CAAC structure is used for the oxide layer 27, the c-axis of the crystals of the oxide layer 27 is perpendicular or approximately perpendicular to the surface of the oxide layer 27 or the surface on which it is formed. In this case, the indium oxide film provided on the oxide layer 27 can have crystal grains with a <111> crystal orientation. In other words, crystal growth, typically with a <111> crystal orientation, can be promoted on the oxide layer 27 having the CAAC structure.

[0117] Note that the material used for the oxide layer 27 is not limited to oxide as long as the lattice mismatch with the semiconductor layer 30 is small. For example, a semiconductor such as silicon may be used for the oxide layer 27, and single-crystal silicon may be used, for example. The lattice mismatch of indium oxide crystal with single-crystal silicon is 3.3%. Therefore, when indium oxide is used for the semiconductor layer 30, silicon may be used for the oxide layer 27.

[0118] Furthermore, the material used for the oxide layer 27 is not limited to the above, as long as it does not hinder the crystal grains contained in the semiconductor layer 30 from growing from above. For example, gallium oxide, aluminum oxide, etc. may also be used.

[0119] There are no particular limitations on the material that can be used for the oxide layer 27. An insulating material or a semiconductor material may be used for the oxide layer 27. When a semiconductor material is used for the oxide layer 27, the oxide layer 27 may be considered as part of the semiconductor layer 30.

[0120] The oxide layer 27 preferably has a thin film thickness. For example, the oxide layer 27 preferably has a thinner film thickness than the semiconductor layer 30. When the semiconductor layer 30 is in contact with a source electrode or a drain electrode via the oxide layer 27, an increase in contact resistance between the semiconductor layer 30 and the source electrode or the drain electrode can be suppressed. Specifically, the oxide layer 27 preferably has a region with a film thickness of 0.1 nm or more and less than 2 nm, and more preferably has a region with a film thickness of 0.5 nm or more and less than 2 nm. Note that the oxide layer 27 may be layered or granular as long as it can enhance the crystal growth of the semiconductor layer 30.

[0121] As described above, if the semiconductor layer 30 contains gallium atoms, the reliability of the transistor may be reduced. Therefore, when an oxide containing gallium, such as an In—Ga—Zn oxide, is used as the oxide layer 27, it is preferable to provide a layer 28 between the oxide layer 27 and the semiconductor layer 30 (see FIG. 1C ).

[0122] The layer 28 preferably contains a metal that has a stronger bond with oxygen than indium. For example, aluminum oxide is preferably used for the layer 28. In this case, the layer 28 contains aluminum and oxygen. As described above, aluminum oxide is also an insulating material that has the function of capturing or fixing oxygen. By providing the layer 28 containing aluminum oxide, it is possible to suppress the diffusion of gallium contained in the oxide layer 27 into the semiconductor layer 30. Furthermore, excess oxygen in the semiconductor layer 30 can diffuse into the layer 28 and be captured or fixed.

[0123] It is preferable that the film thickness of layer 28 is thin. For example, layer 28 preferably has a region where the film thickness is equal to or greater than 1 and equal to or less than 5 atomic layers, and more preferably has a region where the film thickness is equal to or greater than 1 and equal to or less than 3 atomic layers. By making layer 28 thin, it is possible to form semiconductor layer 30 having crystal grains that reflect the crystal structure of oxide layer 27.

[0124] Because the film thickness of the layer 28 is very thin, it may be difficult to clearly detect the interface between the oxide layer 27 and the layer 28 and the interface between the layer 28 and the semiconductor layer 30. The presence or absence of interfaces between layers can be confirmed by, for example, cross-sectional TEM, cross-sectional STEM, or the like.

[0125] 1A shows an example in which the semiconductor layer 30 has a single-layer structure. The semiconductor layer 30 can have a stacked structure of two or more layers. FIG. 1D shows an example in which the semiconductor layer 30 has a two-layer structure including a semiconductor layer 30_1 and a semiconductor layer 30_2 on the semiconductor layer 30_1. The semiconductor layer 30_2 is in contact with the insulating layer 50.

[0126] It is preferable to use a metal oxide (typically indium oxide) applicable to the semiconductor layer 30 described above as the semiconductor layer 30_1, and a metal oxide whose conduction band minimum is located closer to the vacuum level than the conduction band minimum of the semiconductor layer 30_1 as the semiconductor layer 30_2. In this case, the semiconductor layer 30_1 can mainly function as a current path (channel). That is, the semiconductor layer 30_1 has a channel formation region on the surface on the semiconductor layer 30_2 side and in the vicinity thereof.

[0127] The above-described structure can reduce carriers trapped at the interface of the semiconductor layer 30_1 and in the vicinity thereof. In addition, the channel can be located away from the surface of the insulating layer 50, reducing the influence of surface scattering. This can increase the field-effect mobility of the transistor.

[0128] Furthermore, when the oxide layer 27 is formed using a semiconductor material, the semiconductor layer 30_1 is sandwiched between the oxide layer 27 and the semiconductor layer 30_2, both of which have a large band gap, and the semiconductor layer 30_1 functions mainly as a current path (channel). By sandwiching the semiconductor layer 30_1 between the oxide layer 27 and the semiconductor layer 30_2, trap levels at the interface of the semiconductor layer 30_1 and its vicinity can be reduced. This allows for a buried channel transistor in which the channel is spaced away from the insulating layer interface, thereby increasing field-effect mobility. Furthermore, the influence of interface states that may form on the back channel side can be reduced, suppressing photodegradation (e.g., photodegradation due to negative bias current) of the transistor and improving the reliability of the transistor.

[0129] Furthermore, the semiconductor layer 30_2 is preferably made of a material with high oxygen permeability. With such a structure, excess oxygen in the semiconductor layer 30_1 can be discharged to the insulating layer 50. Note that reducing the thickness of the semiconductor layer 30_2 increases the oxygen permeability of the semiconductor layer 30_2. Therefore, the same effect can be achieved even when the thickness of the semiconductor layer 30_2 is reduced. The thickness of the semiconductor layer 30_2 is, for example, 0.1 nm to 3 nm, preferably 0.1 nm to 2 nm, more preferably 0.1 nm to 1 nm, and even more preferably 0.1 nm to 0.5 nm.

[0130] Examples of metal oxides that can be used for the semiconductor layer 30_2 include In—Ga oxide, In—Zn oxide, ITO, indium titanium oxide (In—Ti oxide), In—Al—Zn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, indium titanium zinc oxide (In—Ti—Zn oxide), ITSO, etc. Alternatively, zinc oxide, aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), aluminum tin oxide (Al—Sn oxide), etc. can be used.

[0131] Specifically, the In—Zn oxide used in the semiconductor layer 30_2 can have a composition of In:Zn=1:1 (atomic ratio) or thereabouts, In:Zn=2:1 (atomic ratio) or thereabouts, or In:Zn=4:1 (atomic ratio) or thereabouts. Furthermore, the IGZO used in the semiconductor layer 30_2 can have a composition of In:Ga:Zn=1:1:1 (atomic ratio) or thereabouts, In:Ga:Zn=1:3:2 (atomic ratio) or thereabouts, or In:Ga:Zn=1:3:4 (atomic ratio) or thereabouts.

[0132] The crystallinity of the metal oxide included in the semiconductor layer 30_2 is not particularly limited. For example, the semiconductor layer 30_2 may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part).

[0133] FIG. 1A shows an example in which the insulating layer 50 has a single layer structure. The insulating layer 50 can have a stacked structure of two or more layers. When the insulating layer 50 has a stacked structure of two or more layers, it is preferable to use the insulating material (typically, aluminum oxide) applicable to the insulating layer 50 described above as the layer in contact with the semiconductor layer 30 among the two or more layers included in the insulating layer 50. With such a structure, oxygen can be supplied to the semiconductor layer 30, and the amount of oxygen vacancy can be reduced. Furthermore, excess oxygen in the semiconductor layer 30 can be discharged to the insulating layer 50. Furthermore, hydrogen in the semiconductor layer 30 can be captured or fixed.

[0134] 1E, an insulating layer 20 can be provided that has a portion overlapping with the insulating layer 50, sandwiching the semiconductor layer 30 therebetween. The insulating layer 20 preferably has a function of supplying oxygen to the semiconductor layer 30. For example, the insulating layer 20 preferably has a region containing excess oxygen. The insulating layer 50 preferably has a function of capturing or fixing oxygen. With this configuration, oxygen can be pushed into the semiconductor layer 30 from the insulating layer 20 side, reducing the amount of oxygen vacancy in the semiconductor layer 30, and further, excess oxygen in the semiconductor layer 30 can be pulled from the insulating layer 50 side, reducing the excess amount of oxygen in the semiconductor layer 30. Therefore, a semiconductor device with excellent reliability can be provided.

[0135] Furthermore, it is preferable to use a material for the insulating layer 20 that has a smaller thermal expansion coefficient than the metal oxide used for the semiconductor layer 30. For example, a material for the insulating layer 20 that has a smaller thermal expansion coefficient than indium oxide can be used. Specifically, the thermal expansion coefficient of the insulating layer 20 is 0.01×10 −６ K −１ 5.5 x 10 −６ K −１ Preferably, it is less than 0.01 × 10 −６ K −１ Above 5.0 x 10 −６ K −１ Preferably, it is less than 0.01 × 10 −６ K −１ Above 3.0 x 10 −６ K −１ More preferably, 0.01 x 10 or less −６ K −１ Above 1.0 x 10 −６ K −１ The following is even more preferable. With this configuration, the semiconductor layer 30 containing indium oxide is in contact with or located near the insulating layer 20, which has a small thermal expansion coefficient, and tensile stress is applied to the indium oxide when the temperature drops, making the indium oxide energetically unstable. As a result, the indium oxide becomes a cubic crystal, which is more energetically stable. This promotes crystal growth, allowing the formation of cubic crystals with large grain sizes. Silicon oxide is suitable for the insulating layer 20 because it has a smaller thermal expansion coefficient than indium oxide.

[0136] 1E shows an example in which the insulating layer 20 has a single layer structure. The insulating layer 20 can have a stacked structure of two or more layers. When the insulating layer 20 has a stacked structure of two or more layers, it is preferable to use the insulating material (typically silicon oxide) applicable to the insulating layer 20 described above as the layer in contact with the semiconductor layer 30 among the two or more layers included in the insulating layer 20. By using such a structure, the crystallinity of the semiconductor layer 30 can be improved.

[0137] 1A shows a structure in which a semiconductor layer 30, an insulating layer 50, and a conductive layer 60 are stacked in this order. However, the present invention is not limited to this. For example, the conductive layer 60, the insulating layer 50, and the semiconductor layer 30 may be stacked in this order. In such a structure, it is preferable that an oxide layer 27 is provided between the insulating layer 50 and the semiconductor layer 30.

[0138] 1A shows a configuration in which the semiconductor layer 30, the insulating layer 50, and the conductive layer 60 are stacked in a direction perpendicular or approximately perpendicular to the substrate surface (not shown). However, the present invention is not limited to this. For example, the semiconductor layer 30, the insulating layer 50, and the conductive layer 60 can be stacked in a direction parallel or approximately parallel to the substrate surface (not shown). Furthermore, for example, an opening or a groove can be formed in the insulating layer 20, and the semiconductor layer 30, the insulating layer 50, and the conductive layer 60 can be provided in the opening or the groove.

[0139] <Example of Manufacturing Method of Semiconductor Device> The insulating layer 20, the oxide layer 27, the layer 28, the semiconductor layer 30, the insulating layer 50, and the conductive layer 60 can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. In particular, the insulating layer 20, the semiconductor layer 30, and the insulating layer 50 are preferably formed by an ALD method.

[0140] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings or grooves with high aspect ratios.

[0141] Some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Quantitative determination of these elements can be performed using XPS or SIMS. When the ALD method is used, the amount of carbon and chlorine contained in the film may be lower by adopting a high substrate temperature during film formation and / or by performing an impurity removal process, compared to when the ALD method is used without these procedures.

[0142] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0143] In a film forming apparatus using the ALD method, a first source gas (sometimes called a precursor, precursor, or metal precursor) and a second source gas (sometimes called a reactant, reactant, oxidizer, or non-metal precursor) for the reaction are alternately introduced into a chamber, and film formation is performed by repeating the introduction of these source gases. Note that the introduction of the source gases can be switched by, for example, switching the respective switching valves (sometimes called high-speed valves). In addition, when introducing the source gases, nitrogen (N ２An inert gas such as argon (Ar), argon (Ar), or helium (He) may be introduced into the chamber together with the source gas as a carrier gas. By using a carrier gas, even if the source gas has low volatility or a low vapor pressure, it is possible to suppress the source gas from being adsorbed inside the piping and the valve, and to introduce the source gas into the chamber. This also improves the uniformity of the film formed, which is preferable.

[0144] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0145] First, the insulating layer 20 is formed on a structure (not shown). That is, the structure includes a surface on which the insulating layer 20 is to be formed. The surface on which the insulating layer 20 is to be formed may have a flat shape, or may have a convex portion, a convex curved surface, a concave curved surface, a recessed portion, an opening, or the like.

[0146] The insulating layer 20 can be formed, for example, by sputtering in an atmosphere containing oxygen. By using a sputtering method that does not require the use of hydrogen-containing molecules in the film-forming gas, the hydrogen concentration in the insulating layer 20 can be reduced. Furthermore, by forming the insulating layer 20 by sputtering in an atmosphere containing oxygen, oxygen can be added to the insulating layer 20. Oxygen is supplied from the insulating layer 20 to the semiconductor layer 30 by heat or the like applied after the formation of the semiconductor layer 30, and oxygen vacancies and V Ｏ H can be reduced.

[0147] Heat treatment is preferably performed before forming the semiconductor layer 30. The heat treatment is performed at a temperature of, for example, 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, and more preferably 320° C. or higher and 450° C. or lower.

[0148] The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas content is preferably about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the heat treatment as described above, impurities such as hydrogen or water contained in the insulating layer 20 or the like can be reduced before the semiconductor layer 30 is formed.

[0149] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed into the insulating layer 20 and the like as much as possible.

[0150] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas.

[0151] Furthermore, it is preferable to perform a process of supplying oxygen before forming the semiconductor layer 30. This allows oxygen to be supplied to the insulating layer 20, and oxygen can be supplied from the insulating layer 20 to the semiconductor layer 30 by heat or the like applied after the formation of the semiconductor layer 30.

[0152] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer 20 by forming an oxide film (preferably a metal oxide film) by sputtering in an oxygen-containing atmosphere. The formed oxide film may be removed immediately after deposition or may be left as it is. When the formed oxide film is left as it is, the oxide film can be used as part of the semiconductor layer 30. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２ The atmosphere includes a gas containing a compound gas containing oxygen such as oxygen (O). The substrate temperature during the plasma treatment is set to be equal to or higher than room temperature (25° C.) and equal to or lower than 450° C.

[0153] Next, the semiconductor layer 30 is formed on the insulating layer 20. The semiconductor layer 30 is preferably formed using an ALD method. A first precursor and a first oxidizing agent can be used to form the semiconductor layer 30. The first precursor preferably contains indium. In this case, an indium oxide film is formed as the semiconductor layer 30. That is, an oxide film containing a single element other than oxygen is formed. Note that when the first precursor contains indium, a thermal ALD method can be used as the ALD method.

[0154] Examples of precursors that can be used that contain indium include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolato)indium.

[0155] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the indium-containing precursor. Examples of the inorganic precursor containing indium include halogen-based indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film formation can be performed by the ALD method while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0156] It is preferable to use a precursor with a low impurity concentration, i.e., a high purity, in the method for forming the semiconductor layer 30. For example, by using a precursor with a purity of 3N (99.9%) or higher, preferably 4N (99.99%) or higher, more preferably 5N (99.999%) or higher, and even more preferably 6N (99.9999%) or higher, it is possible to reduce the impurities in the semiconductor layer 30.

[0157] The gallium content and aluminum content of the indium-containing precursor are each preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, even more preferably 50 ppm or less, even more preferably 10 ppm or less, and even more preferably 1 ppm or less. By using a precursor with a low gallium content, the gallium concentration in the semiconductor layer 30 can be reduced, thereby improving the reliability of the transistor. Furthermore, by using a precursor with a low aluminum content, the aluminum concentration in the semiconductor layer 30 can be reduced, thereby improving the crystallinity of the semiconductor layer 30.

[0158] Furthermore, as the precursor used in this embodiment, it is preferable to use a precursor purified by performing distillation (also referred to as rectification or precision distillation) two or more times. By using such a precursor, it is easy to form a metal oxide film with few impurities, which is preferable. By performing distillation multiple times, it is possible to further suppress impurities originating from the starting materials used in the precursor production from remaining in the precursor, which is preferable. Note that the present invention is not limited to the above, and a precursor purified by one distillation, i.e., simple distillation, may also be used. By using simple distillation, it is possible to reduce production costs, which is preferable.

[0159] By performing distillation one or more times, the aluminum content of the indium-containing precursor can be reduced to 100 ppm or less, 1 ppm or less, or 1 ppb (0.001 ppm) or less. By using the indium-containing precursor, it is possible to form an indium oxide film having a purity similar to that of silicon (10N) used in the semiconductor layer.

[0160] As the first oxidant, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) or the like can be used. The first oxidizing agent preferably contains at least one of ozone and oxygen. By using ozone, oxygen, or the like that does not contain hydrogen as the first oxidizing agent, the amount of hydrogen that gets mixed into the insulating layer 20 can be reduced.

[0161] In this specification and the like, unless otherwise specified, when ozone, oxygen, or water is used as an oxidizing agent, it is not limited to the gas or molecular state, but also includes the plasma state, radical state, or ion state.

[0162] The pulse time for introducing the first oxidizing agent is preferably 0.1 seconds or more and 30 seconds or less, more preferably 0.3 seconds or more and 15 seconds or less, and even more preferably 0.3 seconds or more and 10 seconds or less. By shortening the pulse time for introducing the first oxidizing agent and reducing the amount of the first oxidizing agent introduced, more hydrogen contained in the first precursor remains in the film. By leaving more hydrogen in the film, it is possible to suppress the generation of crystal nuclei and eliminate some of the crystal nuclei in the film, thereby reducing the number of crystal nuclei in the film. By growing a small number of crystal nuclei, it is possible to promote the enlargement of the crystal grain size.

[0163] Here, the substrate heating temperature when introducing the first precursor into the reaction chamber is preferably set to a temperature corresponding to the decomposition temperature of the first precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, the substrate heating temperature can be set to, for example, 100°C or higher and 350°C or lower, preferably 150°C or higher and 300°C or lower. When the oxide layer 27 is provided, the first temperature can be set to, for example, room temperature (25°C) or higher and 300°C or lower, preferably room temperature or higher and 200°C or lower, and more preferably room temperature or higher and 150°C or lower. By providing the oxide layer 27, the semiconductor layer 30 having crystallinity can be formed even under conditions of low substrate heating temperature.

[0164] When the indium oxide film included in the semiconductor layer 30 is formed using the ALD method, the edges of the indium oxide are presumably passivated because they are terminated with oxygen. It is presumed that the passivation of the edges results in fewer defects in the edges of the indium oxide film. Therefore, it is presumed that a highly reliable transistor can be realized.

[0165] The semiconductor layer 30 can also be formed by sputtering in an atmosphere containing oxygen. In this case, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the semiconductor layer 30 can be reduced. For example, oxygen or a mixed gas of oxygen and a noble gas may be used as the sputtering gas.

[0166] Alternatively, hydrogen (H２ It is possible to use a gas containing water (H ２ O) or hydrogen peroxide (H ２ O ２ ) can also be used. By introducing hydrogen when forming the semiconductor layer 30 by sputtering, it is possible to suppress the generation of crystal nuclei or promote the annihilation of crystal nuclei during the formation of the semiconductor layer 30. Note that if there are many crystal nuclei, the grown crystals collide with each other, suppressing the increase in grain size. In other words, the crystals will have a small grain size. However, as described above, by suppressing the generation of crystal nuclei and annihilating some of the crystal nuclei in the film to reduce the number of crystal nuclei and promote crystal growth from the reduced number of crystal nuclei, it is possible to increase the size of the crystal grains in the semiconductor layer 30.

[0167] By suppressing the formation of crystal nuclei in the semiconductor layer 30, the number of crystal nuclei can be reduced, and further, by applying tensile stress to the indium oxide film when the temperature is lowered from the substrate heating temperature to room temperature, the In-O bond can be destabilized, thereby promoting crystallization (enlarging the crystal grain size).

[0168] When the semiconductor layer 30 has a stacked structure, the semiconductor layer 30 can also be formed using, for example, a sputtering method and an ALD method. For example, in the configuration shown in FIG. 1D , the semiconductor layer 30_1 can be formed by an ALD method, and the semiconductor layer 30_2 can be formed by a sputtering method. Because the ALD method is a film formation method with superior coverage compared to the sputtering method, forming the semiconductor layer 30_1 by the ALD method can improve the coverage of the semiconductor layer 30. Therefore, the oxide semiconductor layer can be well coated on steps, openings, and the like with a high aspect ratio. Furthermore, because the ALD method causes little damage to the surface on which the oxide layer 27 is formed, forming the semiconductor layer 30_1 by the ALD method can promote epitaxial growth of the semiconductor layer 30_1 when providing the oxide layer 27. Furthermore, forming the semiconductor layer 30_2 by the sputtering method can improve productivity. Furthermore, a semiconductor layer 30 with high crystallinity or high film density can be formed.

[0169] Alternatively, the semiconductor layer 30_1 may be formed by a sputtering method, and the semiconductor layer 30_2 may be formed by an ALD method. An oxide semiconductor layer formed by a sputtering method is likely to have crystallinity. Therefore, by providing a crystalline oxide semiconductor layer as the semiconductor layer 30_1, the crystallinity of the semiconductor layer 30_2 can be improved. Even if pinholes or discontinuities are formed in the semiconductor layer 30_1 formed by a sputtering method, the portions overlapping the pinholes or discontinuities can be filled with the semiconductor layer 30_2 formed by an ALD method, which has good coverage.

[0170] Note that sputtering is a deposition method that causes relatively large damage to the surface on which the semiconductor layer 30_1 is formed. Therefore, when the semiconductor layer 30_1 is deposited by sputtering, a mixed layer with low crystallinity may be formed between the layer that forms the surface on which the semiconductor layer 30_1 is formed (insulating layer 20 in FIG. 1E) and the semiconductor layer 30_1, or in the semiconductor layer 30_1 near the layer (insulating layer 20 in FIG. 1E). However, in the present invention, it is sufficient that the crystallinity of the channel formation region is high. Therefore, by increasing the film thickness of the semiconductor layer 30 within the above-mentioned range, a configuration can be achieved in which a mixed layer is not formed in the channel formation region. Therefore, the crystallinity of the channel formation region can be improved.

[0171] Note that, before forming the semiconductor layer 30, the oxide layer 27 may be formed on the insulating layer 20. The oxide layer 27 can be formed using a sputtering method, a CVD method, a vacuum deposition method, an MBE method, a PLD method, an ALD method, or the like.

[0172] The oxide layer 27 is preferably formed using an ALD method. By forming the oxide layer 27 using an ALD method, the coverage of the oxide layer 27 can be improved. Furthermore, when the oxide layer 27 and the semiconductor layer 30 are formed using the same film formation method, it is preferable to form the oxide layer 27 and the semiconductor layer 30 successively without exposing them to the atmosphere. By successively forming the two types of films without exposing them to the atmosphere, it is possible to increase productivity. Furthermore, it is possible to reduce impurities (typically moisture, etc.) that are introduced into the interface between the two types of films and the vicinity thereof.

[0173] The oxide layer 27 can also be formed by a sputtering method. Forming the oxide layer 27 by a sputtering method can improve the crystallinity of the semiconductor layer 30. Furthermore, forming the oxide layer 27 by a sputtering method in an atmosphere containing oxygen can add oxygen to the insulating layer 20.

[0174] When the oxide layer 27 is provided and the semiconductor layer 30 has a two-layer structure of the semiconductor layer 30_1 and the semiconductor layer 30_2, it is preferable that the oxide layer 27 is formed by a sputtering method, the semiconductor layer 30_1 is formed by an ALD method, and the semiconductor layer 30_2 is formed by a sputtering method. With such a structure, the semiconductor layer 30_1 can be epitaxially grown from the oxide layer 27, and the crystallinity of the semiconductor layer 30_1 can be improved. For example, the oxide layer 27 can be formed using an yttrium zirconium oxide film formed by a sputtering method, the semiconductor layer 30_1 can be formed using an indium oxide film formed by an ALD method, and the semiconductor layer 30_2 can be formed using an IGZO film formed by a sputtering method. In this case, for example, it is preferable that the oxide layer 27 has a region with a thickness of 1 nm or more and 5 nm or less, the semiconductor layer 30_1 has a region with a thickness of 5 nm or more and 7 nm or less, and the semiconductor layer 30_2 has a region with a thickness of 3 nm or more and 5 nm or less.

[0175] After the semiconductor layer 30 is formed, a process of supplying oxygen to the semiconductor layer 30 may be performed. This allows oxygen to be supplied to the semiconductor layer 30 by heat or the like applied after this process. Note that the above description can be referred to for details of the process of supplying oxygen.

[0176] Next, heat treatment is preferably performed. By performing the heat treatment, impurities such as hydrogen or water contained in the semiconductor layer 30 can be reduced. The temperature of the heat treatment is preferably 100° C. or higher and 650° C. or lower, more preferably 250° C. or higher and 600° C. or lower, and even more preferably 300° C. or higher and 500° C. or lower, or 350° C. or higher and 550° C. or lower. The above description can be referred to for details of the heat treatment.

[0177] Furthermore, it is preferable that the gas used in the heat treatment is highly purified. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the semiconductor layer 30 as much as possible.

[0178] When the insulating layer 20 contains oxygen, the heat treatment described above can supply oxygen from the insulating layer 20 to the semiconductor layer 30. The supplied oxygen reacts with carbon in the semiconductor layer 30 to produce carbon monoxide (CO) or carbon dioxide (CO ２ ), and the carbon can be removed from the semiconductor layer 30 as the carbon oxide. In addition, the supplied oxygen reacts with hydrogen in the semiconductor layer 30 to form H ２ O and convert the hydrogen to H ２ O can be removed from the semiconductor layer 30. In addition, the supplied oxygen may react with carbon and hydrogen in the oxide semiconductor layer to form a carbonyl compound, a hydroxy compound, or the like, and the carbon and hydrogen can be removed from the semiconductor layer 30 as a carbonyl compound, a hydroxy compound, or the like. In addition, the supplied oxygen can eliminate oxygen vacancies and V Ｏ H can be reduced.

[0179] As described above, impurities such as carbon, hydrogen, or water in the semiconductor layer 30 can be reduced. By reducing the impurities in the film in this way, the crystallinity of the semiconductor layer 30 can be improved, resulting in a denser, more compact structure. This increases the crystalline regions in the semiconductor layer 30, reducing the in-plane variation of the crystalline regions in the semiconductor layer 30. This reduces the in-plane variation of the electrical characteristics of the transistor. Furthermore, the reliability of the transistor can be improved. This method of improving the crystallinity of the semiconductor layer 30 while reducing the impurities in the semiconductor layer 30 can be called solid phase purification.

[0180] Furthermore, by performing the heat treatment using an RTA apparatus, tensile stress may be applied to the semiconductor layer 30 during temperature drop or slow cooling, which may promote crystal growth from the crystal nuclei. In this case as well, the crystallinity of the semiconductor layer 30 can be improved.

[0181] In forming the semiconductor layer 30 containing indium oxide, a first step of suppressing the generation of crystal nuclei and a second step of increasing the In-O distance by utilizing the difference in contraction with a material having a low thermal expansion coefficient, such as silicon oxide, during cooling, and then stabilizing the material energetically to promote crystal growth can be included to form large-grain crystals. In the second step, the crystal nuclei grow laterally (also referred to as lateral growth), promoting crystal growth from the sides of the crystal nuclei, thereby increasing the grain size of the crystals. The crystal growth through the first and second steps can be referred to as two-step growth. Furthermore, the crystal growth in the indium oxide film described in this embodiment can be said to include a lamination technique or a crystallization technique that takes thermal expansion into consideration.

[0182] Furthermore, by performing a heat treatment after the formation of the semiconductor layer 30, the energetically stable crystals absorb the energetically unstable crystals located nearby, resulting in larger grain sizes. In other words, the crystals are further joined and recrystallized to form a single crystal, reducing the number of grain boundaries. This allows for greater field-effect mobility.

[0183] Note that microwave plasma treatment may be performed after the formation of the semiconductor layer 30. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the semiconductor layer 30 can be reduced. Furthermore, a crystalline region of the semiconductor layer 30 may grow.

[0184] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0185] By performing microwave plasma treatment in an atmosphere containing oxygen, the impurity concentration in the semiconductor layer 30 can be reduced. Examples of impurities include hydrogen and carbon. While the above example illustrates a configuration in which microwave plasma treatment is performed on the semiconductor layer 30 in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the semiconductor layer 30 in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may enhance the crystallinity of the semiconductor layer 30.

[0186] The microwave plasma treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, more preferably from 50 to 700 Pa, and even more preferably from 100 to 400 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and can be from 400 to 450°C.

[0187] When microwave plasma treatment is performed, the substrate may be heated. The substrate is preferably heated to a temperature above room temperature (25°C), above 100°C, above 200°C, above 300°C, or above 400°C, and below 500°C or below 450°C. For example, the substrate is preferably heated to a temperature above room temperature and below 500°C, more preferably above 100°C and below 450°C, more preferably above 200°C and below 450°C, more preferably above 300°C and below 450°C, and even more preferably above 400°C and below 450°C.

[0188] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. In the microwave plasma treatment using oxygen gas and argon gas, the main oxygen radical is triplet oxygen (O( ３ P ｊ )), singlet oxygen (O( １ D ２ )), and oxygen ions (O ２ ＋) can take three states. Note that oxygen ions act effectively in reducing the hydrogen concentration in the oxide film by microwave plasma processing. The amount of oxygen radicals in each state varies depending on the oxygen flow rate ratio or pressure in microwave plasma processing. For example, under conditions where the oxygen flow rate ratio is low and the pressure is low, the amount of oxygen ions tends to increase. On the other hand, if the oxygen flow rate ratio or pressure is excessively low, there is a concern that the control of the oxygen flow rate becomes unstable, making it difficult to stabilize the discharge, and that the oxide film may be etched. Therefore, for example, when the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and not greater than 10%, more preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

[0189] The shorter the processing time of the microwave plasma treatment, the higher the productivity. Therefore, for example, the processing time of the microwave plasma treatment is preferably from 1 minute to 60 minutes, more preferably from 1 minute to 30 minutes, and even more preferably from 1 minute to 10 minutes.

[0190] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and oxygen radicals generated by converting the oxygen gas into plasma can act on the oxide semiconductor layer. Ｏ By splitting H into oxygen vacancies and hydrogen, it is possible to remove hydrogen as an impurity from the oxide semiconductor layer. Ｏ H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, by supplying the oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0191] Furthermore, a reaction occurs between part of oxygen present in the oxide semiconductor before the microwave plasma treatment and hydrogen in the oxide semiconductor. In other words, the reaction proceeds as follows: 2H + O → H ２ O↑” reaction occurs, converting the hydrogen to H ２ O (also called dehydration or dehydrogenation). ２ Since O is one of the factors that hinder improvement of crystallinity, it is preferable to remove O from the oxide semiconductor. ２ The hydrogen concentration in the oxide semiconductor can be reduced by removing the hydrogen as O, which can also promote improvement in crystallinity. Note that the hydrogen concentration in the oxide semiconductor can be further reduced by increasing the temperature during the microwave plasma treatment.

[0192] After the microwave plasma treatment, a heat treatment may be performed without exposing the substrate to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0193] It should be noted that the crystallinity can be improved by plasma treatment containing oxygen gas instead of microwave plasma treatment.

[0194] Oxygen supplied to the oxide semiconductor layer can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions with an unpaired electron). Note that the oxygen injected into the oxide semiconductor layer is preferably in one or more of the above forms, and is particularly preferably in the form of oxygen radicals.

[0195] Subsequently, an insulating layer 50 is formed on the semiconductor layer 30. The insulating layer 50 is preferably formed using an ALD method. A second precursor and a second oxidizing agent can be used to form the insulating layer 50. The second precursor preferably contains one of aluminum and hafnium. In this case, an aluminum oxide film or a hafnium oxide film is formed as the insulating layer 50. In other words, an oxide film containing a single element other than oxygen is formed. Note that when the second precursor contains one of aluminum and hafnium, a thermal ALD method can be used as the ALD method.

[0196] Examples of precursors that can be used include aluminum chloride and trimethylaluminum, and examples of precursors that can be used include hafnium tetrachloride and tetrakis(ethylmethylamido)hafnium (TEMAHf).

[0197] The second oxidizing agent may be any of the materials that can be used for the second oxidizing agent described above. Note that the first oxidizing agent and the second oxidizing agent may be the same oxidizing agent or different oxidizing agents.

[0198] In the ALD process, a precursor is introduced into a chamber and adsorbed onto the substrate surface. The adsorption of the precursor onto the substrate surface activates a self-limiting mechanism for the surface chemical reaction, preventing further adsorption of the precursor onto the precursor layer on the substrate. The appropriate substrate temperature range within which the self-limiting mechanism for the surface chemical reaction operates is also referred to as the ALD window. The ALD window is determined by the precursor's temperature characteristics, vapor pressure, decomposition temperature, and other factors. In other words, the ALD window varies depending on the precursor. Therefore, when depositing an oxide film containing multiple elements other than oxygen, it is necessary to adjust the film formation conditions taking into account the ALD window of each precursor. On the other hand, when depositing an oxide film containing a single element other than oxygen, such as indium oxide or aluminum oxide, the film formation conditions can be adjusted by considering only the ALD window of one precursor, which facilitates the adjustment of the film formation conditions and allows for the formation of a high-quality oxide film.

[0199] Furthermore, when the insulating layer 20 and the semiconductor layer 30 are formed using the same film formation method, it is preferable to form the insulating layer 20 and the semiconductor layer 30 consecutively without exposing them to the atmosphere. Alternatively, when the semiconductor layer 30 and the insulating layer 50 are formed using the same film formation method, it is preferable to form the semiconductor layer 30 and the insulating layer 50 consecutively without exposing them to the atmosphere. Alternatively, when the insulating layer 20, the semiconductor layer 30, and the insulating layer 50 are formed using the same film formation method, it is preferable to form the insulating layer 20, the semiconductor layer 30, and the insulating layer 50 consecutively without exposing them to the atmosphere. By forming two or more types of films consecutively without exposing them to the atmosphere, it is possible to increase productivity. Furthermore, it is possible to reduce impurities (typically moisture, etc.) that are introduced into the interface between the two types of films and their vicinity.

[0200] As an example, it is preferable to form the semiconductor layer 30 using a thermal ALD method, and then continuously form the insulating layer 50 using a thermal ALD method without exposing the process to the atmosphere. In this case, by using the same oxidizing agent for the first oxidizing agent and the second oxidizing agent and using a reaction chamber into which the first precursor and the second precursor can be introduced, the semiconductor layer 30 and the insulating layer 50 can be formed without carrying in and out the substrate, thereby improving productivity.

[0201] It is preferable to perform microwave plasma treatment after the formation of the insulating layer 50. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the semiconductor layer 30 can be reduced. For details of the microwave plasma treatment, refer to the above description.

[0202] Subsequently, the conductive layer 60 is formed on the insulating layer 50 .

[0203] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0204] The detailed configuration of the semiconductor device will be described below.

[0205] <Structural Example 1 of Semiconductor Device> A structural example of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 3A to 27C. FIG.

[0206] 3A and 3B are schematic perspective views of a semiconductor device having a transistor 200A. Fig. 3B is a perspective view in which a part of Fig. 3A is cut away. In Fig. 3A and 3B, only the outlines of some components (such as interlayer insulating layers) are indicated by dashed lines.

[0207] 3A and 3B, the X, Y, and Z directions are indicated by arrows. Note that although the same X, Y, and Z symbols are used in both Fig. 3A and Fig. 3B, the directions do not necessarily have to match.

[0208] Fig. 4A is a plan view of a semiconductor device having a transistor 200A. Fig. 4B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 4A. Fig. 4C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 4A. Fig. 4D is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 4B. Note that some elements are omitted in the plan view of Fig. 4A for clarity. Some elements may also be omitted in the subsequent plan views.

[0209] Fig. 5A is a cross-sectional view taken along dashed lines A1-A2 in Fig. 4A. Fig. 5B is a cross-sectional view taken along dashed lines A5-A6 in Fig. 4B. Fig. 5A and Fig. 5B correspond to examples of enlarged views of Fig. 4B and Fig. 4D, respectively.

[0210] The semiconductor device shown in FIGS. 4A to 4D includes an insulating layer 210 on a substrate (not shown), a transistor 200A on the insulating layer 210, and an insulating layer 280 on the insulating layer 210.

[0211] [Transistor 200A] The transistor 200A includes a conductive layer 220, a conductive layer 240 on an insulating layer 280, a semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. The insulating layer 280 is located on the conductive layer 220.

[0212] 4B and 4C show an example in which the conductive layer 220 has a two-layer structure of a conductive layer 220_1 and a conductive layer 220_2 on the conductive layer 220_1, the conductive layer 240 has a two-layer structure of a conductive layer 240_1 and a conductive layer 240_2 on the conductive layer 240_1, and the conductive layer 260 has a two-layer structure of a conductive layer 260_1 and a conductive layer 260_2 on the conductive layer 260_1.

[0213] The semiconductor layer 230, insulating layer 280, insulating layer 250, and conductive layer 260 included in the transistor 200A correspond to the semiconductor layer 30, insulating layer 20, insulating layer 50, and conductive layer 60, respectively. Therefore, the configurations (materials, film thicknesses, etc.), formation methods, etc. of the semiconductor layer 230, insulating layer 280, insulating layer 250, and conductive layer 260 can refer to the configurations (materials, film thicknesses, etc.), formation methods, etc. of the semiconductor layer 30, insulating layer 20, insulating layer 50, and conductive layer 60. Similarly, hereinafter, the configurations (materials, film thicknesses, etc.), formation methods, etc. of any one of the semiconductor layer 30, insulating layer 20, insulating layer 50, and conductive layer 60 can be referred to for the layers corresponding to any one of the semiconductor layer 30, insulating layer 20, insulating layer 50, and conductive layer 60.

[0214] The conductive layer 220 functions as one of a source electrode and a drain electrode of the transistor 200A, and the conductive layer 240 functions as the other of the source electrode and the drain electrode of the transistor 200A. The conductive layer 260 has a region that functions as a gate wiring.

[0215] As shown in FIGS. 4B and 4C, an opening 290 is provided in the insulating layer 280 and the conductive layer 240, reaching the conductive layer 220.

[0216] The openings 290 include an opening in the insulating layer 280 and an opening in the conductive layer 240. The shape and size of the openings 290 in a plan view may differ depending on the layer. When the top surface shape of the openings 290 is circular, the openings in each layer may or may not be concentric.

[0217] Each of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 is arranged so that at least a portion thereof is located within the opening 290. Furthermore, the portions of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 that are arranged within the opening 290 are provided so as to reflect the shape of the opening 290.

[0218] The semiconductor layer 230 is provided so as to cover the bottom and sidewalls of the opening 290. The semiconductor layer 230 also has a recess that reflects the shape of the opening 290. The semiconductor layer 230 has a portion that contacts the upper surface of the conductive layer 240 and a portion that contacts the upper surface of the conductive layer 220 within the opening 290.

[0219] The insulating layer 250 is provided so as to cover the semiconductor layer 230. Moreover, the insulating layer 250 is provided on the insulating layer 280 so as to cover the top surface and side surfaces of the semiconductor layer 230 and the side surfaces of the conductive layer 240. Moreover, the insulating layer 250 has a recess that reflects the shape of the recess that the semiconductor layer 230 has.

[0220] The conductive layer 260 is provided so as to fill at least a part of the recessed portion of the insulating layer 250. The conductive layer 260 has a region in the opening 290 that overlaps with the semiconductor layer 230 with the insulating layer 250 sandwiched therebetween.

[0221] The semiconductor layer 230 has a region that overlaps with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least a part of this region functions as a channel formation region of the transistor 200A. One of the region of the semiconductor layer 230 near the conductive layer 220 and the region of the semiconductor layer 230 near the conductive layer 240 functions as a source region, and the other functions as a drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

[0222] The semiconductor layer 230 is provided inside the opening 290. The transistor 200A has a structure in which one of the source electrode and the drain electrode (the conductive layer 220 here) is located below and the other of the source electrode and the drain electrode (the conductive layer 240 here) is located above, allowing current to flow vertically. That is, a channel is formed along the side surface of the opening 290. This allows the transistor 200A to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased. Note that the channel length direction of the transistor 200A can be said to have a component in the height direction (vertical direction); therefore, the transistor 200A can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0223] As shown in FIG. 6A , the semiconductor layer 230 may have a different ratio between the film thickness (hereinafter referred to as the first film thickness) of a portion where the top surface of the conductive layer 240 or the conductive layer 220 is to be formed and the film thickness (hereinafter referred to as the second film thickness) of a portion where the sidewall of the opening 290 is to be formed. For example, when a portion of the semiconductor layer 230 is formed by sputtering, the semiconductor layer 230 may have a different ratio between the first film thickness and the second film thickness. For example, as shown in FIG. 6A , the ratio of the second film thickness to the first film thickness may be less than 1, less than 0.8, or less than 0.5. In particular, the closer the angle θ 280 (described later) is to 90 degrees, the smaller the ratio of the second film thickness to the first film thickness in the semiconductor layer 230 tends to be.

[0224] As shown in FIG. 5A , the conductive layer 220 has a recess that overlaps with the opening 290. Specifically, the recess is provided in the conductive layer 220_2 at a position that overlaps with the opening 290. When the conductive layer 220_2 has the recess, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the opening 290 can be lower than the height of the top surface of the conductive layer 220_2 that is in contact with the insulating layer 280, compared to when the conductive layer 220_2 does not have the recess. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Here, the top surface of the insulating layer 210 is used as the reference. The surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the top surface of a substrate on which a transistor or a semiconductor device is provided may be used as the reference.

[0225] The semiconductor layer 230 is in contact with the bottom and side surfaces of the recessed portion of the conductive layer 220_2. The recessed portion of the conductive layer 220_2 can increase the area where the semiconductor layer 230 and the conductive layer 220_2 are in contact with each other. Therefore, the contact resistance between the semiconductor layer 230 and the conductive layer 220_2 can be reduced.

[0226] The recess of the conductive layer 220_2 can have a curved portion as shown in FIG. 6B . When the recess has a curved portion, the portions of the semiconductor layer 230, the insulating layer 250, and the like provided on the recess near the recess may also have a curved portion. In other words, the portion may have a curved or concave surface in cross-sectional view. Furthermore, the portion may not have a corner (right angle or acute angle) in cross-sectional view. This reduces electric field concentration on the insulating layer 250 near the recess, improves the breakdown voltage of the transistor 200A, and suppresses electrostatic breakdown of the transistor 200A. Therefore, the reliability of the semiconductor device can be improved.

[0227] 4B shows a structure in which the end of the conductive layer 240 and the end of the semiconductor layer 230 are aligned or substantially aligned outside the opening 290. The conductive layer 240 and the semiconductor layer 230 can be fabricated by processing using the same mask. This is preferable because it reduces the number of masks required to fabricate a semiconductor device. Note that the present invention is not limited to this. For example, a structure may be adopted in which any one of the end of the semiconductor layer 230, the end of the conductive layer 240_1, and the end of the conductive layer 240_2 is located inside or outside the other in the X direction or Y direction.

[0228] 4A , the transistor 200A is provided at the intersection of a conductive layer 260 extending in the X direction and a conductive layer 240 extending in the Y direction. As shown in FIG. 4A , the diameter of the opening 290 can be made smaller than both the width of the short side of the conductive layer 240 and the width of the short side of the conductive layer 260. In this way, the transistor 200A can be said to have a structure that allows for high integration and miniaturization.

[0229] As shown in FIG. 5B , by forming the opening 290 so that it has a circular shape in a plan view, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. Therefore, the side surface of the conductive layer 260 located at the center of the opening 290 faces the side surface of the semiconductor layer 230 via the insulating layer 250. In other words, in a plan view, the entire periphery of the semiconductor layer 230 becomes a channel formation region. In this case, for example, the channel width of the transistor 200A is determined by the outer periphery of the semiconductor layer 230. In other words, the channel width of the transistor 200A can be determined by the width of the opening 290 (or the diameter if the opening 290 is circular in a plan view). In FIGS. 5A and 5B , the width D of the opening 290 is shown, and in FIG. 5B , the channel width W of the transistor 200A is shown.

[0230] Furthermore, by arranging the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 concentrically, the distance between the conductive layer 260 and the semiconductor layer 230 becomes approximately uniform, so that a gate electric field can be applied to the semiconductor layer 230 approximately uniformly.

[0231] Increasing the width D of the opening 290 increases the channel width per unit area, thereby increasing the on-state current. Meanwhile, the area occupied by the transistor 200A, for example, the area of ​​the transistor 200A in a plan view, is roughly determined by the width of the opening 290. Reducing the width D of the opening 290 reduces the area occupied by the transistor 200A, thereby enabling a semiconductor device to be highly integrated.

[0232] The width D of the opening 290 may vary in the depth direction. Here, the shortest distance between the two side surfaces of the conductive layer 240 on the opening side in a cross-sectional view is used as the width D. In other words, the minimum width of the opening in the conductive layer 240 is used as the width D of the opening 290. Alternatively, the width of the opening at the highest position in the conductive layer 240, the width of the opening at the lowest position, the width of the opening at a midpoint between these, or the average value of these three widths may be used as the width D. Here, an example is shown in which the width D of the opening 290 is determined using the width of the opening in the conductive layer 240, but the method for determining the width D is not particularly limited. For example, the shortest distance between the two side surfaces of the insulating layer 280 on the opening side may be used as the width D. Alternatively, the width of the opening at the highest position in the insulating layer 280, the width of the opening at the lowest position, the width of the opening at a midpoint between these, or the average value of these three widths may be used as the width D of the opening 290.

[0233] The width D of the opening 290 is set by the film thickness of each of the semiconductor layer 230, insulating layer 250, and conductive layer 260 provided in the opening 290. The width D of the opening 290 is, for example, preferably 5 nm to 100 nm, more preferably 10 nm to 60 nm, more preferably 20 nm to 50 nm, more preferably 20 nm to 40 nm, and even more preferably 20 nm to 30 nm. When the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D × π".

[0234] In this embodiment, an example is shown in which the opening 290 is circular in plan view. By using a circular shape, the processing accuracy during the formation of the opening can be improved, allowing for the formation of openings of minute sizes. However, the present invention is not limited to this. In plan view, the opening 290 can be, for example, a circle or a substantially circular shape such as an ellipse, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a polygonal shape with rounded corners. Note that the circle is not limited to a perfect circle. Furthermore, the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).

[0235] The channel length of the transistor 200A is the distance between the source region and the drain region. In other words, the channel length of the transistor 200A is determined by the thickness of the insulating layer 280 on the conductive layer 220. Therefore, the channel length of the transistor 200A does not affect the area occupied by the transistor 200A, for example, the area of ​​the transistor 200A in a planar view. In FIG. 5A , the channel length L of the transistor 200A is indicated by a dashed double-headed arrow. Note that the channel length L can be considered as the distance between the edge of the region where the semiconductor layer 230 and the conductive layer 220 contact each other and the edge of the region where the semiconductor layer 230 and the conductive layer 240 contact each other in a cross-sectional view. In this case, the channel length L corresponds to the length of the side surface of the insulating layer 280 on the opening 290 side in a cross-sectional view.

[0236] The channel length of the transistor 200A can be, for example, 500 nm or less, 300 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and can be 0.1 nm or more, 1 nm or more, or 5 nm or more. Typically, the channel length can be 1 nm or more and 300 nm or less, preferably 5 nm or more and 100 nm or less. This can improve productivity and yield in forming the insulating layer 280, forming the opening 290 in the insulating layer 280, and the like. Furthermore, the on-state current of the transistor 200A can be increased, thereby improving frequency characteristics.

[0237] The channel length L of the transistor 200A is preferably at least shorter than the channel width W of the transistor 200A. The channel length L of the transistor 200A is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 200A. With such a structure, a transistor with good electrical characteristics and high reliability can be realized.

[0238] 5A shows an example in which the semiconductor layer 230 has a single-layer structure. The semiconductor layer 230 can have a stacked structure of two or more layers. As shown in FIG. 7, the semiconductor layer 230 can have a two-layer structure of a semiconductor layer 230_1 and a semiconductor layer 230_2 on the semiconductor layer 230_1. The semiconductor layers 230_1 and 230_2 correspond to the semiconductor layers 30_1 and 30_2 described above, respectively. Therefore, the structures (materials, film thicknesses, etc.), formation methods, etc. of the semiconductor layers 230_1 and 230_2 can be referenced to the structures, formation methods, etc. of the semiconductor layers 30_1 and 30_2 described above.

[0239] Since the insulating layer 210 functions as an interlayer film, it is preferable to use a material with a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance occurring between wirings can be reduced.

[0240] The insulating layer 210 preferably has a barrier property against hydrogen. When the insulating layer 210 provided below the semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 200A to the semiconductor layer 230 can be suppressed.

[0241] The insulating layer 210 preferably has a function of capturing or fixing hydrogen. When the insulating layer 210 has the function of capturing or fixing hydrogen, hydrogen in the semiconductor layer 230 can be diffused to the insulating layer 210 through the conductive layer 220 and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0242] The concentration of impurities such as hydrogen or water in the insulating layer 210 is preferably reduced, which can prevent impurities such as hydrogen or water from entering the channel formation region of the semiconductor layer 230.

[0243] 5A shows an example in which the insulating layer 210 has a single-layer structure. The insulating layer 210 can have a stacked structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, it is preferable that the first insulating layer has a barrier property against hydrogen, and the second insulating layer has a function of capturing or fixing hydrogen. Specifically, it is preferable to use silicon nitride as the first insulating layer and aluminum oxide, hafnium oxide, hafnium zirconium oxide, or hafnium silicate as the second insulating layer.

[0244] Since the insulating layer 280 functions as an interlayer film, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0245] As described above, by using silicon oxide, which has a small thermal expansion coefficient, for the insulating layer 280 provided before the formation of the semiconductor layer 230, it is possible to promote the crystal growth of indium oxide formed by the ALD method inside the opening of the insulating layer 280.

[0246] The concentration of impurities such as hydrogen or water in the insulating layer 280 is preferably reduced. This can prevent impurities such as hydrogen or water from entering the channel formation region of the semiconductor layer 230.

[0247] 8A , an oxide layer 227 can be provided below the semiconductor layer 230. The oxide layer 227 corresponds to the oxide layer 27 described above. Therefore, the configuration (material, film thickness, etc.), formation method, etc. of the oxide layer 227 can refer to the configuration, formation method, etc. of the oxide layer 27 described above. For example, yttrium zirconium oxide can be used as the oxide layer 227.

[0248] 9A is a diagram illustrating the change in metal-oxygen bond length with respect to the atomic ratio. FIG. 9B is a diagram illustrating the ionic radius dependence of the metal-oxygen bond length. FIG. 9C is a diagram illustrating the change in metal-oxygen bond length with respect to the molar ratio. Since the ionic radius of yttrium is larger than that of zirconium, in yttrium zirconium oxide, when the ratio of the number of yttrium atoms to the sum of the number of yttrium atoms and the number of zirconium atoms (Y / (Y+Zr)) and the molar ratio of yttrium oxide are increased, the bond length between the metal atom and the oxygen atom (M-O bond length) becomes slightly longer (see FIGS. 9A and 9C). However, in the yttrium oxide crystal (here, Y ２ O ３ ) and erbium oxide crystal (here, Er ２ O ３ ), compared with yttrium zirconium oxide crystal (herein YZrO Ｘ Since the bond length between the metal atom and the oxygen atom in the indium oxide crystal (here, In) is small (see FIG. 9B), the lattice mismatch can be reduced by using yttrium zirconium oxide for the oxide layer 227. ２ O ３ ), ytterbium oxide crystal (here Yb ２ O ３ ), gadolinium oxide crystal (here Gd ２ O ３ ), samarium oxide crystal (herein Sm ２ O ３ ), and neodymium oxide crystal (herein Nd ２ O ３ ) and the respective M-O bond lengths are also shown.

[0249] 9A and 9C, in yttrium zirconium oxide, the lower the yttrium content, the shorter the M-O bond length. Therefore, the yttrium zirconium oxide with the closest M-O bond length to that of indium oxide is yttrium zirconium oxide that does not contain yttrium (i.e., zirconium oxide). Therefore, by using zirconium oxide, which has an M-O bond length closer to that of indium oxide, for the oxide layer 27, the crystallinity of the semiconductor layer 30 may be improved.

[0250] As will be described later, ITO can be used for at least one of the conductive layer 240_2 and the conductive layer 220_2. ITO is an oxide conductor with high crystallinity and can have a cubic crystal structure. For example, by using ITO having crystal grains with a cubic crystal structure for at least one of the conductive layer 240_2 and the conductive layer 220_2, the oxide layer 227 in contact with the top surfaces of the conductive layer 240_2 and the conductive layer 220_2 can grow epitaxially using the ITO as a nucleus, thereby increasing the crystallinity of the oxide layer 227.

[0251] Zirconium oxide can have a monoclinic, tetragonal, or cubic crystal structure, but the monoclinic crystal structure is considered to be stable at room temperature. When zirconium oxide is used for the oxide layer 227, using ITO having crystal grains with a cubic crystal structure for at least one of the conductive layer 240_2 and the conductive layer 220_2 may promote epitaxial growth of the oxide layer 227 using the ITO as a nucleus, thereby providing the oxide layer 227 with a cubic crystal structure. Furthermore, the semiconductor layer 230 can be epitaxially grown from the oxide layer 227, thereby improving the crystallinity of the semiconductor layer 230. In this case, the crystal orientation of the crystal grains in the semiconductor layer 230 coincides or substantially coincides with the crystal orientation of the crystal grains in the ITO.

[0252] Here, Fig. 8B shows a cross-sectional view of the semiconductor device shown in Fig. 8A as seen from the Y direction. In Fig. 8B, arrows in the drawing indicate oxygen diffusion paths.

[0253] 8B , even when the oxide layer 227 has a function of suppressing oxygen diffusion, oxygen can be supplied from the insulating layer 280 to the semiconductor layer 230 through the insulating layer 250 by heat treatment, thereby reducing oxygen vacancies in the semiconductor layer 230. Furthermore, by using an indium oxide film with high oxygen permeability for the semiconductor layer 230, excess oxygen in the semiconductor layer 230 can be discharged to the insulating layer 250, thereby reducing the amount of excess oxygen in the semiconductor layer 230. Therefore, the electrical characteristics and reliability of the transistor 200A can be improved.

[0254] Note that when the oxide layer 227 has a function of transmitting oxygen, oxygen can be supplied from the insulating layer 280 to the semiconductor layer 230 through the oxide layer 227 or the insulating layer 250 by heat treatment, thereby reducing oxygen vacancies in the semiconductor layer 230. Furthermore, by using an indium oxide film with high oxygen permeability for the semiconductor layer 230, excess oxygen in the semiconductor layer 230 can be discharged to the insulating layer 250, thereby reducing the amount of excess oxygen in the semiconductor layer 230. Therefore, the electrical characteristics and reliability of the transistor 200A can be improved.

[0255] The oxide layer 227 can be formed by a sputtering method. Damage caused by sputtering results in the formation of a layer in which components contained in the oxide layer 227 and components contained in the conductive layer 220 are mixed. The insulating properties of this layer are lower than the insulating properties of the oxide layer 227, and therefore, an increase in contact resistance between the conductive layer 220 and the semiconductor layer 230 can be suppressed. The same applies to the contact resistance between the conductive layer 240 and the semiconductor layer 230.

[0256] As shown in FIG. 10A, by providing an oxide layer 227 and forming a semiconductor layer 230 into a two-layer structure, a buried channel transistor can be realized.

[0257] 10B , a layer 228 can be provided between the oxide layer 227 and the semiconductor layer 230. The layer 228 corresponds to the above-described layer 28. Therefore, the structure (material, film thickness, etc.), formation method, etc. of the layer 228 can be determined by referring to the structure, formation method, etc. of the above-described layer 28.

[0258] 5A shows an example in which the insulating layer 250 has a single layer structure. The insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 using two or more types of films, the insulating layer 250 can be provided with multiple functions. Examples of the functions of the insulating layer 250 include a function of extracting excess oxygen from the semiconductor layer 230, a function of extracting hydrogen from the semiconductor layer 230, and a function of suppressing diffusion of hydrogen into the semiconductor layer 230.

[0259] 11A to 11D are enlarged views of the insulating layer 250 and its vicinity, which are also enlarged views of the region P surrounded by the dashed line in FIG. 5A.

[0260] 11A shows an example in which the insulating layer 250 has a three-layer structure including an insulating layer 250_1, an insulating layer 250_2 over the insulating layer 250_1, and an insulating layer 250_3 over the insulating layer 250_2. In this case, the insulating layer 250_1 is in contact with the semiconductor layer 230.

[0261] The insulating layer 250_1 can be formed using any of the materials applicable to the insulating layer 50. For example, when the insulating layer 250_1 includes an insulating layer having a function of capturing or fixing oxygen, an excess amount of oxygen in the semiconductor layer 230 can be reduced. In addition, an insulating layer having a function of capturing or fixing oxygen may also have a function of capturing or fixing hydrogen, which may reduce the hydrogen concentration in the semiconductor layer 230. Therefore, a highly reliable transistor can be realized.

[0262] Furthermore, a high-k material with a high dielectric constant can be used for the insulating layer 250_1. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulating layer 250_1 makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0263] For the above reasons, it is preferable to use an oxide containing one or both of aluminum and hafnium for the insulating layer 250_1, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. Aluminum oxide having an amorphous structure is preferably used because an amorphous film can be formed relatively easily using an ALD method. Aluminum oxide is suitable for the insulating layer 250_1 because it has the function of capturing or fixing oxygen and hydrogen. Alternatively, hafnium oxide is suitable for the insulating layer 250_1 because it has a high function of capturing or fixing oxygen and hydrogen.

[0264] For example, the insulating layer 250_2 preferably includes a material with a low dielectric constant, such as a silicon oxide film or a silicon oxynitride film.

[0265] Silicon oxide or silicon nitride is an insulating material with high dielectric strength. This can reduce the leakage current of a transistor. Furthermore, a silicon oxide film or a silicon oxynitride film is also a film with high hydrogen permeability. Therefore, as shown in FIG. 11B , the insulating layer 250 may have a three-layer structure including an insulating layer 250_2, an insulating layer 250_1 on the insulating layer 250_2, and an insulating layer 250_3 on the insulating layer 250_1. With this structure, hydrogen in the semiconductor layer 230 can diffuse into the insulating layer 250_1 through the insulating layer 250_2 and be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0266] The insulating layer 250_3 preferably has a barrier property against hydrogen. With such a structure, diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Furthermore, the insulating layer 250_3 preferably has a barrier property against oxygen. The insulating layer 250_3 is provided between the channel formation region of the semiconductor layer 230 and the conductive layer 260. With such a structure, oxygen contained in the channel formation region of the semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region of the semiconductor layer 230. Furthermore, oxygen contained in the semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The insulating layer 250_3 is preferably at least less permeable to oxygen than the insulating layer 250_2. Furthermore, the insulating layer 250_3 preferably has a function of suppressing diffusion of hydrogen. This can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230. For example, silicon nitride is preferably used as the insulating layer 250_3.

[0267] 11C , a structure in which an insulating layer 250_4 is provided over the insulating layer 250_2 may be used. The insulating layer 250_4 can be formed using an insulating material that can be used for the insulating layer 250_1. For example, by providing the insulating layer 250_4 having a function of capturing or fixing hydrogen between the insulating layer 250_3 and the insulating layer 250_2, hydrogen contained in the insulating layer 250_2 or the like can be captured or fixed.

[0268] Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. With such a structure, hydrogen in the semiconductor layer 230 can be diffused to the insulating layer 250_1 or the insulating layer 250_4 and captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0269] The insulating layer 250 is preferably a thin film. For example, the subthreshold swing value (also referred to as S value) can be reduced by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage held constant in the subthreshold region.

[0270] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-described thickness in at least a portion thereof.

[0271] Typically, the thicknesses of the insulating layer 250_1, the insulating layer 250_2, the insulating layer 250_4, and the insulating layer 250_3 are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have favorable electrical characteristics even when miniaturized or highly integrated.

[0272] Note that the insulating layer 250 having a four-layer structure may not include the insulating layer 250_3 (see FIG. 11D ). For example, an insulating layer having a function of capturing or fixing oxygen may be used as the insulating layer 250_1, an insulating layer containing a material with a low dielectric constant may be used as the insulating layer 250_2, and an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 250_4. Specifically, the insulating layer 250 may have a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the semiconductor layer 230 side.

[0273] The insulating layer 250 can have a three-layer structure in which a hafnium oxide film, a silicon oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. The thicknesses of the hafnium oxide film, the silicon oxide film, and the silicon nitride film are set to 2 nm, 2 nm, and 1 nm, respectively. This structure allows excess oxygen in the semiconductor layer 230 to be discharged to the insulating layer 250, thereby reducing the amount of excess oxygen in the semiconductor layer 230. Furthermore, hydrogen in the semiconductor layer 230 can be captured or fixed. Therefore, the electrical characteristics and reliability of the transistor 200A can be improved.

[0274] In order to thin the insulating layers 250_1 to 250_4 as described above, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method. In addition, in order to form the insulating layers 250_1 to 250_4 in the opening 290 with good coverage, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method.

[0275] It is preferable to use the ALD process two or more times in forming the insulating layer 250 having a stacked structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, for example, it is possible to increase productivity by successively forming two or more types of insulating films using the ALD process.

[0276] Although the insulating layer 250 has been described above as having a three-layer structure or a four-layer structure, the present invention is not limited to this. The insulating layer 250 can have a structure including at least one of the insulating layers 250_1 to 250_4. By forming the insulating layer 250 using one, two, or three of the insulating layers 250_1 to 250_4, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0277] FIG. 5A illustrates an example in which the insulating layer 280 has a single-layer structure. The insulating layer 280 can have a stacked structure of two or more layers. For example, as shown in FIG. 12A , the insulating layer 280 can have a three-layer structure including an insulating layer 280_1, an insulating layer 280_2 on the insulating layer 280_1, and an insulating layer 280_3 on the insulating layer 280_2. In this case, it is preferable to use a material with a low dielectric constant as the insulating layer 280_2, and to use oxygen barrier insulating layers as the insulating layers 280_1 and 280_3. This can prevent the conductive layer 220 and the conductive layer 240 from being oxidized and thus prevent high resistance. In the configuration shown in FIG. 12A , the insulating layer 280_2 corresponds to the insulating layer 20.

[0278] For example, it is preferable to use silicon nitride or aluminum oxide for the insulating layer 280_1 and the insulating layer 280_3, and to use silicon oxide for the insulating layer 280_2. Note that each of the insulating layer 280_1 and the insulating layer 280_3 may have a stacked structure of two or more layers.

[0279] The conductive layer 220 and the conductive layer 240 are preferably made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, because they are in contact with the semiconductor layer 230. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0280] By using a conductive material containing oxygen for the conductive layer 220 and the conductive layer 240, the conductive layer 220 and the conductive layer 240 can maintain their conductivity even if they absorb oxygen. Furthermore, even when an insulator containing oxygen such as hafnium oxide is used for the insulating layer 210, the conductive layer 220 is preferable because it can maintain its conductivity. For example, ITO, ITSO, In—Zn oxide, or the like is preferably used for each of the conductive layer 220 and the conductive layer 240.

[0281] When the conductive layer 220 and the conductive layer 240 each have a stacked structure, the contact resistance between the conductive layer 220 and the semiconductor layer 230 and between the conductive layer 240 and the semiconductor layer 230 can be reduced by using a conductive material containing oxygen for the layer in the stacked structure that has the largest contact area with the semiconductor layer 230.

[0282] 12A shows an example in which the conductive layer 220_1 has a two-layer structure including a conductive layer 220_11 and a conductive layer 220_12 over the conductive layer 220_11. In other words, the conductive layer 220 shown in FIG. 12A has a three-layer structure including a conductive layer 220_11, a conductive layer 220_12 over the conductive layer 220_11, and a conductive layer 220_2 over the conductive layer 220_12. In this case, for example, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 220_11, a material with high conductivity as the conductive layer 220_12, and a conductive material containing oxygen (more preferably an oxide conductor) as the conductive layer 220_2. Specifically, it is preferable to use titanium nitride for the conductive layer 220_11, tungsten for the conductive layer 220_12, and an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 220_2. In this case, the titanium nitride film is in contact with the insulating layer 210, and the oxide conductive film is in contact with the semiconductor layer 230. Furthermore, the oxide conductor is used in the layer closest to the channel formation region of the semiconductor layer 230. Compared to tungsten, the oxide conductor has lower contact resistance with the semiconductor layer 230, so that the current path between the source and drain can be shortened, and the on-current of the transistor 200A can be increased. With such a structure, the conductive layer 220 can maintain conductivity even when in contact with the semiconductor layer 230. Furthermore, when an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220 by the insulating layer 210 can be suppressed. Furthermore, when a metal material (tungsten here) having higher conductivity than an oxide conductor and titanium nitride is used for the conductive layer 220_12, the conductivity of the conductive layer 220 can be increased.

[0283] The conductive layer 240 shown in FIG. 5A has a two-layer structure including a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240_2 and a material having higher conductivity than the conductive layer 240_1 for the conductive layer 240_2. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 240_2 and tungsten for the conductive layer 240_1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 240_1. By using an oxide conductor for the conductive layer 240_2 that is mainly in contact with the semiconductor layer 230, the contact resistance with the semiconductor layer 230 can be reduced. Furthermore, by using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 240, the conductivity of the conductive layer 240 can be increased.

[0284] Note that a conductive material containing oxygen can be used for the conductive layer 240_1, and a material having higher conductivity than that of the conductive layer 240_1 can be used for the conductive layer 240_2. In this case, an oxide conductor is used for the layer of the conductive layer 240 that is closest to the channel formation region of the semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200A can be increased.

[0285] 5A has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. In this case, for example, it is preferable to use titanium nitride for the conductive layer 260_1 and tungsten for the conductive layer 260_2. Alternatively, it is preferable to use tantalum nitride for the conductive layer 260_1 and copper for the conductive layer 260_2. Such a structure can increase the conductivity of the conductive layer 260.

[0286] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0287] 12A, an insulating layer 283 may be provided over the transistor 200A. Specifically, the insulating layer 283 may be provided over the conductive layer 260 and the insulating layer 250.

[0288] A barrier insulating layer against hydrogen is preferably used for the insulating layer 283. With such a structure, diffusion of hydrogen from above the transistor 200A to the semiconductor layer 230 can be suppressed.

[0289] 5A , both the conductive layer 260_1 and the conductive layer 260_2 are located in the opening 290. Depending on the width of the opening 290 and the thicknesses of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260_1, the conductive layer 260_1 may be provided in the opening 290, and the conductive layer 260_2 may be provided so as to overlap with the opening 290 (see FIG. 12B ).

[0290] It is preferable that the side surface of the conductive layer 240 and the side surface of the insulating layer 280 coincide or substantially coincide within the opening 290. With such a configuration, the opening 290 can be formed simultaneously in the conductive layer 240 and the insulating layer 280. Furthermore, the film thickness distribution of the semiconductor layer 230 and the like provided within the opening 290 can be made uniform. Furthermore, it is possible to prevent the semiconductor layer 230 and the like from being divided by a step or the like between the conductive layer 240 and the insulating layer 280.

[0291] It should be noted that the present invention is not limited to the above configuration. For example, within the opening 290, the side surface of the conductive layer 240 and the side surface of the insulating layer 280 may be discontinuous. Furthermore, within the opening 290, the inclination of the side surface of the conductive layer 240 and the inclination of the side surface of the insulating layer 280 may differ from each other. In this case, part of the side wall of the opening 290 has a tapered shape.

[0292] FIG. 13A shows an example in which the side surface of the conductive layer 240 in the opening 290 is tapered, and FIG. 13B shows an example in which the side surface of the conductive layer 240 and the side surface of the insulating layer 280 in the opening 290 are both tapered.

[0293] By tapering the sidewalls of the opening 290, the coverage of the semiconductor layer 230, the insulating layer 250, etc. can be improved, and defects such as voids can be reduced. When the sidewalls of the opening 290 are tapered, for example, the taper angle (angle θ240) of the side surface of the conductive layer 240 in the opening 290 and the taper angle (angle θ280) of the side surface of the insulating layer 280 in the opening 290 are preferably 45 degrees or more and less than 90 degrees. Specifically, an angle of 80 degrees or more and less than 90 degrees is preferable, as this allows for miniaturization or high integration of the semiconductor device. Alternatively, an angle of 45 degrees or more and less than 80 degrees, or 50 degrees or more and less than 75 degrees is preferable, as this improves the coverage of the film formed in the opening 290.

[0294] Also, for example, it is preferable that angle θ240 is smaller than angle θ280. With such a configuration, the coverage of the semiconductor layer 230 and the like on the side surface of the conductive layer 240 in the opening 290 is improved, and defects such as voids can be reduced. Furthermore, when the insulating layer 280 has a laminated structure, the inclination of the side surface of each layer in the opening 290 may be different. Similarly, when the conductive layer 240 has a laminated structure, the inclination of the side surface of each layer in the opening 290 may be different.

[0295] 14A to 27C, examples of transistor configurations that are partially different from the transistor 200A will be described. Note that descriptions of parts that overlap with the above will be omitted, and only the differences will be described in detail. Furthermore, even if components differ in position or shape, if their functions are the same, they may be assigned the same reference numerals and their descriptions may be omitted.

[0296] [Transistor 200B] Fig. 14A is a plan view of a semiconductor device having transistor 200B. Fig. 14B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 14A. Fig. 14C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 14A. Note that Fig. 4D can be referred to for a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 14B. Fig. 15A shows an enlarged view of Fig. 14B.

[0297] The semiconductor device shown in FIGS. 14A to 14C differs from the semiconductor device shown in FIGS. 4A to 4D in that it includes a conductive layer 265, an insulating layer 284, and an insulating layer 285.

[0298] In the transistor 200B, the stacked structure from the conductive layer 220 to the insulating layer 250 is similar to that of the transistor 200A described above, and therefore detailed description thereof will be omitted.

[0299] 14B and 14C , insulating layer 284 is provided so as to be located on insulating layer 250. Furthermore, insulating layer 284 is provided with openings 270 that reach insulating layer 250 at positions that overlap openings 290.

[0300] The conductive layer 260 is provided to fill the openings 290 and 270. The conductive layer 260 is provided on the insulating layer 250 and contacts the insulating layer 250 within the opening 270. The conductive layer 260 has a portion that faces the semiconductor layer 230 with the insulating layer 250 interposed therebetween within the opening 290, and a portion that is located within the opening 270.

[0301] 14B and 14C show an example in which both the conductive layer 260_1 and the conductive layer 260_2 are provided in the opening 290. Note that when the width of the opening 290 and the width of the opening 270 are small, only the conductive layer 260_1 may be provided in the opening 290, and the conductive layer 260_1 and the conductive layer 260_2 may be provided in the opening 270. Alternatively, only the conductive layer 260_1 may be provided in the opening 270.

[0302] 15A shows an example in which the width of opening 270 is smaller than the width D of opening 290. The smaller the width of opening 270, the greater the physical distance between conductive layer 240 and conductive layer 260 can be, and the smaller the parasitic capacitance that occurs between conductive layer 240 and conductive layer 260 can be, which is preferable. For example, the width of opening 270 is preferably the same as or smaller than the width of opening 290.

[0303] The conductive layer 265 is provided over the conductive layer 260 and is in contact with the top surface of the conductive layer 260. It can also be said that the conductive layer 260 and the conductive layer 265 are connected to each other. The conductive layer 265 may be considered a component of the transistor 200B. The height of the top surface of the conductive layer 260 and the height of the top surface of the insulating layer 285 are the same or approximately the same.

[0304] The conductive layer 265 functions as a gate wiring. The conductive layer 265 can be formed using a material that can be used for the conductive layer 260. For example, a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, can be used for the conductive layer 265. Alternatively, a low-resistance conductive material, such as aluminum or copper, can be used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0305] The portion of the conductive layer 265 that does not overlap with the opening 290 is mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240 via the insulating layers 284 and 285. This makes it possible to increase the physical distance between the conductive layer 265 and the conductive layer 240, and to reduce the parasitic capacitance that occurs between the conductive layer 265 and the conductive layer 240. Note that the conductive layer 240 and the conductive layer 265 may have an overlapping portion without the insulating layer 285 being therebetween.

[0306] The transistor 200B has a structure in which parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0307] In this embodiment, an example in which the opening 270 is circular in plan view has been shown, but the present invention is not limited to this. Shapes that can be applied to the opening 270 are the same as the shapes that can be applied to the opening 290 described above.

[0308] The width of the opening 270 may vary in the depth direction. In particular, the width of the opening 270 used here is the maximum width of the opening 270 provided in the insulating layer 284 in a cross-sectional view.

[0309] The insulating layer 284 preferably has a function of capturing or fixing hydrogen. With such a structure, diffusion of hydrogen from above the insulating layer 284 to the semiconductor layer 230 can be suppressed, and further, hydrogen contained in the semiconductor layer 230 can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced. The insulating layer 284 can be made of aluminum oxide, hafnium oxide, hafnium zirconium oxide, hafnium silicate, or the like.

[0310] The insulating layer 284 can also be a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen from above the insulating layer 284 into the semiconductor layer 230. Silicon nitride and silicon nitride oxide are suitable for the insulating layer 284 because they are less permeable to oxygen and hydrogen, respectively.

[0311] When the insulating layer 284 includes a silicon nitride film, the silicon nitride film is preferably formed by a sputtering method. The sputtering method does not require the use of hydrogen-containing molecules in the film formation gas, and therefore can reduce the hydrogen concentration in the insulating layer 284. Furthermore, by forming the insulating layer 284 by a sputtering method, a silicon nitride film with high density can be formed.

[0312] Alternatively, the insulating layer 284 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 284 may have a stacked structure of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0313] The insulating layer 285 functions as an interlayer film, and therefore is preferably made of the above-mentioned material having a low relative dielectric constant. For example, the insulating layer 285 preferably includes a silicon oxide film.

[0314] Note that a structure similar to that of the transistor 200A can also be applied to the transistor 200B. An example in which the structure shown in Fig. 12A is applied to the semiconductor device shown in Fig. 15A is shown in Fig. 15B. In Fig. 15B, the insulating layer 283 is provided over the insulating layer 285 and the conductive layer 265.

[0315] [Transistor 200C] Fig. 16A is a plan view of a semiconductor device having transistor 200C. Fig. 16B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 16A. Fig. 16C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 16A. Fig. 16D is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 16B.

[0316] 16B is shown in FIG. 17A, and an enlarged view of FIG. 16D is shown in FIG. 17B. Also, FIGS. 18A and 18B are cross-sectional views taken along dashed line A1-A2 in FIG. 16A. Each of FIGS. 18A and 18B corresponds to an example of an enlarged view of FIG. 16B, and shows an example of the configuration of each layer in more detail.

[0317] The transistor 200C shown in FIGS. 16A to 16D differs from the transistor 200A shown in FIGS. 4A to 4D in that an insulating layer 225 is provided between the insulating layer 280 and the semiconductor layer 230.

[0318] The insulating layer 225 of the transistor 200C corresponds to the above-described insulating layer 20 or the oxide layer 27. Therefore, the structure (material, film thickness, etc.), formation method, etc. of the insulating layer 225 can refer to the structure, formation method, etc. of the insulating layer 20 or the oxide layer 27.

[0319] The insulating layer 225 is preferably formed by a CVD method or an ALD method, and more preferably by an ALD method, since it is a layer provided in the opening 290. This allows the insulating layer 225 to be provided with good coverage.

[0320] As shown in FIG. 16B and other figures, the conductive layer 220_2 has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. In other words, the bottom surface of the first recess is located lower (closer to the insulating layer 210) than the bottom surface of the second recess. Furthermore, the side surface of the second recess coincides or substantially coincides with the side surface of the insulating layer 280 in the opening 290, and the side surface of the first recess coincides or substantially coincides with the surface of the insulating layer 225 facing the semiconductor layer 230. Hereinafter, the first recess and the second recess may be collectively referred to as recesses.

[0321] 16B and other figures, the insulating layer 225 is in contact with the bottom surface and side surfaces of the second recessed portion of the conductive layer 220, and is in contact with the side surfaces of the insulating layer 280 and the conductive layer 240 within the opening 290. The semiconductor layer 230 is in contact with the bottom surface and side surfaces of the first recessed portion of the conductive layer 220, the insulating layer 225, and the top surface of the conductive layer 240_2. The insulating layer 250 is located inside the semiconductor layer 230 within the opening 290, and the conductive layer 260 is located inside the insulating layer 250 within the opening 290.

[0322] 17A , the shortest distance Tc from the top surface of the insulating layer 210 to the top surface of the conductive layer 220_2 that contacts the insulating layer 280 is preferably longer than the shortest distance Ta from the top surface of the insulating layer 210 to the bottom surface of the insulating layer 250. This increases the area where the side surface of the conductive layer 220_2 contacts the semiconductor layer 230, thereby reducing the contact resistance between the conductive layer 220_2 and the semiconductor layer 230. This suppresses a decrease in the on-state current of the transistor 200C that is caused by the contact resistance between the conductive layer 220_2 and the semiconductor layer 230. Note that the shortest distance Ta can be determined based on the bottom surface of the insulating layer 250 within the opening 290.

[0323] 17A , the shortest distance Tc is preferably equal to or greater than the shortest distance Tb from the top surface of the insulating layer 210 to the bottom surface of the conductive layer 260, and more preferably longer than the shortest distance Tb. This makes it easier to apply a gate electric field to the channel formation region of the semiconductor layer 230, thereby improving the electrical characteristics of the transistor 200C. Furthermore, the gate electric field is also easier to apply to the region of the semiconductor layer 230 in contact with the conductive layer 220_2, thereby increasing the on-state current of the transistor 200C. Furthermore, whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor 200C can be improved. The shortest distance Tb can be determined based on the bottom surface of the conductive layer 260 in the opening 290.

[0324] Here, as shown in FIG. 17A, the width (film thickness) of the insulating layer 225 is set to width T ＳＷ17B also shows the channel width W of the transistor 200C. When the opening 290 is circular in plan view, the channel width W is "(D-2×T ＳＷ ) × π”. ＳＷ By reducing the width T ＳＷ By increasing the width T ＳＷ is, for example, preferably 1 nm or more and 20 nm or less, more preferably 2 nm or more and 15 nm or less, and even more preferably 3 nm or more and 10 nm or less.

[0325] The channel length of the transistor 200C can be regarded as the distance between the source region and the drain region, and can be referred to as the length L shown in FIG.

[0326] 17A illustrates a configuration in which the conductive layer 220_2 has a first recess and a second recess, but the present invention is not limited to this. For example, as shown in FIG. 18A , the transistor 200C may have a configuration in which only the first recess is provided in the conductive layer 220_2. In this case, the insulating layer 225 contacts the side surface of the insulating layer 280, the side surface of the conductive layer 240, and the top surface of the conductive layer 220_2 within the opening 290. Furthermore, the semiconductor layer 230 contacts the bottom and side surfaces of the recess of the conductive layer 220_2.

[0327] A recess can be formed in the conductive layer 220_2 in one or both of the steps of forming the opening 290 and forming the insulating layer 225. The transistor 200C illustrated in Figure 17A illustrates an example in which a recess is formed in the conductive layer 220_2 in both steps, whereas the transistor 200C illustrated in Figure 18A illustrates an example in which a recess is not formed in the conductive layer 220_2 in the step of forming the opening 290, but is formed in the step of forming the insulating layer 225.

[0328] The transistor 200C may have a structure in which the insulating layer 225 does not cover at least a part of the side surface of the conductive layer 240_2. In this case, the side surface of the conductive layer 240_2 that is not covered with the insulating layer 225 is in contact with the semiconductor layer 230. Therefore, the contact resistance between the semiconductor layer 230 and the conductive layer 240 can be reduced. Furthermore, by having the insulating layer 225 not cover at least a part of the side surface of the conductive layer 240_1, the contact resistance can be further reduced. FIG. 18B illustrates a structure in which the insulating layer 225 is in contact with a part of the side surface of the conductive layer 240_1 but is not in contact with the side surface of the conductive layer 240_2 in the opening 290.

[0329] 17A shows an example in which the insulating layer 225 has a single-layer structure. Note that the insulating layer 225 can have a stacked structure of two or more layers. For example, as shown in FIG. 19, the insulating layer 225 can have a two-layer structure of an insulating layer 225_1 and an insulating layer 225_2. The insulating layer 225_1 is in contact with the side surface of the insulating layer 280 in the opening 290, and the insulating layer 225_2 is located between the insulating layer 225_1 and the semiconductor layer 230. It can be said that the insulating layer 225 shown in FIG. 19 has a two-layer structure of the insulating layer 225_1 and the insulating layer 225_2 over the insulating layer 225_1.

[0330] The insulating layer 225_1 can be formed using an insulating material described in the "Insulating Layer" section below, and the insulating layer 225_2 can be formed using a material applicable to the insulating layer 20 or the oxide layer 27. For example, the insulating layer 225_1 can be formed using a barrier insulating layer against hydrogen, and the insulating layer 225_2 can be formed using an insulating layer having a region containing excess oxygen. With such a structure, oxygen vacancies and / or hydrogen in the semiconductor layer 230 can be reduced. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be enhanced. For example, it is preferable to use silicon nitride for the insulating layer 225_1 and silicon oxide or silicon oxynitride for the insulating layer 225_2. The thicknesses of the insulating layers 225_1 and 225_2 are 2 nm and 2 nm, respectively.

[0331] Note that the same structure as at least one of the transistor 200A and the transistor 200B can also be applied to the transistor 200C.

[0332] [Transistor 200D] Fig. 20A is a plan view of a semiconductor device having transistor 200D. Fig. 20B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 20A. Fig. 20C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 20A. Fig. 20D is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 20B. Fig. 21A shows an enlarged view of Fig. 20B.

[0333] 20A to 20D differ from the semiconductor device shown in Figures 4A to 4D mainly in that the semiconductor device includes an insulating layer 225, a conductive layer 255, and an insulating layer 281. The transistor 200D shown in Figures 20A to 20D also differs from the transistor 200C shown in Figures 16A to 16D mainly in that the transistor 200D includes the conductive layer 255 and the insulating layer 281.

[0334] The conductive layer 255 is located over the insulating layer 280, and the insulating layer 281 is located over the conductive layer 255 and the insulating layer 280. In addition, the conductive layer 240_1 is located over the insulating layer 281.

[0335] As shown in FIG. 21A, an opening 290 reaching the conductive layer 220 is provided in the insulating layer 280 , the conductive layer 255 , the insulating layer 281 , and the conductive layer 240 .

[0336] The semiconductor layer 230, the insulating layer 250, and the conductive layer 260 included in the transistor 200D correspond to the semiconductor layer 30, the insulating layer 50, and the conductive layer 60, respectively. Alternatively, the semiconductor layer 230, the insulating layer 225, and the conductive layer 255 included in the transistor 200D may correspond to the semiconductor layer 30, the insulating layer 50, and the conductive layer 60, respectively.

[0337] The semiconductor layer 230 has a region that overlaps with the conductive layer 255 with the insulating layer 225 interposed therebetween and with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least part of the region functions as a channel formation region of the transistor 200D.

[0338] In the transistor 200D, the conductive layer 260 serves as a first gate electrode, the insulating layer 250 serves as a first gate insulating layer, the conductive layer 255 serves as a second gate electrode, and the insulating layer 225 serves as a second gate insulating layer.

[0339] In the transistor 200D, one of the conductive layer 255 and the conductive layer 260 can be used as a gate electrode, and the other can be used as a back gate electrode. The transistor 200D may have a particularly preferable structure in which the conductive layer 260 is used as a gate electrode and the conductive layer 255 is used as a back gate electrode. By using the conductive layer 260, which has a wider region facing the semiconductor layer 230 than the conductive layer 255, as the gate electrode, a gate electric field can be applied to the semiconductor layer 230 more efficiently, which may improve the electrical characteristics of the transistor. Note that when the conductive layer 260 functions as a gate electrode and the conductive layer 255 functions as a back gate electrode, the insulating layer 250 functions as a gate insulating layer, and the insulating layer 225 functions as a back gate insulating layer.

[0340] Since the transistor 200D includes a conductive layer that functions as a backgate electrode, the threshold voltage of the transistor 200D can be controlled by the potential applied to the conductive layer. Therefore, by controlling the threshold voltage, a normally-off transistor can be easily realized.

[0341] The conductive layer 255 can be made of a conductive material that can be used for the conductive layer 260 .

[0342] The insulating layer 281 functions as an interlayer film. The insulating layer 281 can be formed using an insulating material that can be used for the insulating layer 280.

[0343] Note that the same structure as at least one of the transistors 200A to 200C can also be applied to the transistor 200D. An example in which the structure shown in FIG. 12A is applied to the semiconductor device shown in FIG. 21A is shown in FIG.

[0344] FIG. 21A shows an example in which the insulating layer 281 has a single-layer structure. Note that the insulating layer 281 can have a stacked structure of two or more layers. For example, as shown in FIG. 21B, the insulating layer 281 can have a three-layer structure including an insulating layer 281_1, an insulating layer 281_2 on the insulating layer 281_1, and an insulating layer 281_3 on the insulating layer 281_2. In this case, it is preferable to use the above-described material with a low relative dielectric constant for the insulating layer 281_2, and to use barrier insulating layers against oxygen for the insulating layers 281_1 and 281_3. This can prevent the conductive layer 255 and the conductive layer 240 from being oxidized and prevent high resistance.

[0345] Although the transistors 200A to 200D each have a configuration in which at least some of the components of the transistor are provided in the opening 290 that is circular in plan view, the present invention is not limited to this. At least some of the components of the transistor can be provided in a groove that is formed to extend.

[0346] In this specification and the like, a groove can be rephrased as a slit or a trench. Also, a groove portion can be rephrased as a slit portion or a trench portion. Note that a groove portion may also be rephrased as a slit or a trench.

[0347] [Transistor 200E] Fig. 22A is a plan view of a semiconductor device including transistor 200E. Fig. 22B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 22A. Fig. 22C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 22A. Fig. 22D is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 22B.

[0348] 22A to 22D differ from the semiconductor device shown in Figures 4A to 4D in that the semiconductor device includes a conductive layer 243a, a conductive layer 243b, and a conductive layer 246. A transistor 200E shown in Figures 22A to 22D differs from the transistor 200A shown in Figures 4A to 4D in that some of the components are provided in a groove 291 instead of an opening 290. The transistor 200E also differs from the transistor 200A shown in Figures 4A to 4D in that the conductive layer 240 is separated into a conductive layer 240a and a conductive layer 240b by the groove 291.

[0349] 22A to 22D includes an insulating layer 283 over the transistor 200E, similar to the semiconductor device illustrated in Fig. 12A. The semiconductor device also includes an insulating layer 285, similar to the semiconductor device illustrated in Fig. 14A to 14C. The insulating layer 285 is provided over the insulating layer 284.

[0350] 22A to 22D , a groove 291 is provided in the insulating layer 280, reaching the conductive layer 220. The groove 291 extends in the X direction. The semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are each disposed such that at least a portion thereof is located within the groove 291.

[0351] The semiconductor layer 230 is provided in an island shape. The semiconductor layer 230 is provided so as to follow part of the bottom and part of the sidewall of the groove 291. The semiconductor layer 230 has a portion in contact with the top surface of the conductive layer 240, a portion in contact with the side surface of the conductive layer 240 on the groove 291 side, and a portion in contact with the bottom surface and side surface of the recess of the conductive layer 220 within the groove 291.

[0352] The insulating layer 250 is provided to cover the semiconductor layer 230. The insulating layer 250 is also provided on the insulating layer 280 to cover the top and side surfaces of the semiconductor layer 230 and the side surfaces of the conductive layer 240.

[0353] The conductive layer 260 is provided so as to fill at least a part of the groove 291. Therefore, the conductive layer 260 is provided so as to extend in the direction in which the groove 291 extends.

[0354] The conductive layer 220 functions as one of a source electrode and a drain electrode of the transistor 200E, and the conductive layer 240a and the conductive layer 240b function as the other of the source electrode and the drain electrode of the transistor 200E. A channel is also formed along the sidewall of the groove 291 in the transistor 200E.

[0355] Openings reaching the conductive layer 240a are provided in the insulating layer 285, the insulating layer 283, the insulating layer 250, and the semiconductor layer 230, and a conductive layer 243a is provided in the openings. Openings reaching the conductive layer 240b are provided in the insulating layer 285, the insulating layer 283, the insulating layer 250, and the semiconductor layer 230, and a conductive layer 243b is provided in the openings. The conductive layer 243a is in contact with the conductive layer 240a, and the conductive layer 243b is in contact with the conductive layer 240b.

[0356] The conductive layer 246 is provided on the insulating layer 285. The conductive layer 246 is connected to the conductive layer 240a via the conductive layer 243a and to the conductive layer 240b via the conductive layer 243b. The conductive layer 246 functions as the other of the source wiring and the drain wiring. The conductive layer 246 extends in the Y direction. In other words, the direction in which the conductive layer 246 extends intersects with the direction in which the groove portion 291 extends.

[0357] In the transistors 200A to 200D, the width of the conductive layer 240 in the X direction (short side) needs to be larger than the width D of the opening 290 in order to provide the conductive layer 240 in an extended state. On the other hand, in the transistor 200E, the conductive layer 240a and the conductive layer 240b, which function as the other of the source electrode and the drain electrode, are connected through the conductive layer 246. This allows the widths of the conductive layer 240a and the conductive layer 240b in the X direction to be reduced, thereby enabling miniaturization of the semiconductor device. For example, the widths of the conductive layer 240a and the conductive layer 240b in the X direction can be smaller than the width D1 of the groove 291 (see FIG. 22D ).

[0358] On the other hand, in the transistors 200A to 200D, it is not necessary to process the semiconductor layer 230 in the opening 290, which makes it easier to process the semiconductor layer 230 and improves the productivity of the semiconductor device.

[0359] In a plan view, the side surface of the conductive layer 260 provided in the groove 291 has a portion facing the side surface of the semiconductor layer 230 with the insulating layer 250 interposed therebetween. Therefore, the channel width of the transistor 200E is determined by the width D2 of the semiconductor layer 230 (see FIG. 22D ). The channel width of the transistor 200E can be calculated as "2×D2."

[0360] 22D , in a plan view of the transistor 200E, the portion of the semiconductor layer 230 located in the groove 291 does not have a curved surface. Therefore, distortion is less likely to occur in the region of the semiconductor layer 230 near the insulating layer 250, and deterioration of the crystallinity of the region can be suppressed. Note that the region includes a channel formation region.

[0361] On the other hand, in a plan view of the transistors 200A to 200D, a portion of the semiconductor layer 230 located at the opening 290 has a curved surface. However, the curvature of the curved surface can be reduced (the radius of curvature of the curved surface can be increased) by increasing the width of the opening 290 or by reducing the film thickness of the semiconductor layer 230. Therefore, distortion occurring in a region of the semiconductor layer 230 near the insulating layer 250 can be reduced, and deterioration of the crystallinity of the region can be suppressed.

[0362] Similarly, when the semiconductor layer 230 is formed in the groove portion 291, silicon oxide having a small thermal expansion coefficient is used for the insulating layer 280 provided before the formation of the semiconductor layer 230, and tensile stress is applied to the indium oxide from the bottom and sidewalls of the groove portion 291 when the temperature is lowered, thereby promoting crystal growth on the surface of the semiconductor layer 230.

[0363] 22A to 22D shows a configuration in which the height of the top surface of the conductive layer 260 is higher than the height of the top surface of the insulating layer 250. Note that the present invention is not limited to this. The height of the top surface of the conductive layer 260 may be the same as or approximately the same as the height of the top surface of the insulating layer 250, or may be lower than the height of the top surface of the insulating layer 250.

[0364] 23A to 23C will be used to describe a modification of the transistor 200E described with reference to FIGS. 22A to 22D. FIG. 23A is a plan view of a semiconductor device including the transistor 200E. FIG. 23B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 23A. FIG. 23C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 23A. Note that FIG. 22D can be referred to for a cross-sectional view taken along dashed-dotted line A5-A6 in FIG. 23B.

[0365] The transistor 200E shown in FIGS. 23A to 23C differs from the transistor 200E shown in FIGS. 22A to 22D in that the height of the top surface of the conductive layer 260 is lower than the height of the top surface of the insulating layer 250.

[0366] By configuring the top surface of the conductive layer 260 to be lower than the top surface of the insulating layer 250, the area where the conductive layer 260 faces the conductive layer 240a or the conductive layer 240b can be reduced, and the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240a or the conductive layer 240b can be reduced. Furthermore, by configuring the above, the physical distance between the conductive layer 260 and the conductive layer 246 can be increased, and the parasitic capacitance generated between the conductive layer 260 and the conductive layer 246 can be reduced. Therefore, the frequency characteristics of a circuit using the transistor can be improved.

[0367] 22A to 22D, the cross-sectional area of ​​the conductive layer 260 functioning as a gate wiring can be increased, leading to reduced wiring resistance. Thus, the power consumption of the semiconductor device can be reduced.

[0368] 24A and 24B are schematic perspective views of a semiconductor device including the transistor 200E shown in FIGS. 23A to 23C. Fig. 24B is a perspective view of a portion cut away from Fig. 24A. In Fig. 24A and 24B, only the outlines of some components (such as interlayer insulating layers) are indicated by dashed lines.

[0369] 24C is a perspective view taken along the plane indicated by the dashed dotted line in Fig. 24A. In Fig. 24C, an oxide layer 227 is provided between a semiconductor layer 230 and an insulating layer 280. In Fig. 24C, arrows indicate oxygen diffusion paths.

[0370] 24C , even when the oxide layer 227 has a function of suppressing oxygen diffusion, oxygen can be supplied from the insulating layer 280 to the semiconductor layer 230 through the insulating layer 250 by heat treatment, thereby reducing oxygen vacancies in the semiconductor layer 230. Furthermore, impurities in the semiconductor layer 230 can be reduced, and the crystallinity can be improved. Furthermore, by using an indium oxide film with high oxygen permeability for the semiconductor layer 230, excess oxygen in the semiconductor layer 230 can be discharged to the insulating layer 250, thereby reducing the amount of excess oxygen in the semiconductor layer 230. Therefore, the electrical characteristics and reliability of the transistor 200E can be improved.

[0371] Note that if the oxide layer 227 has a function of transmitting oxygen, oxygen can be supplied from the insulating layer 280 to the semiconductor layer 230 through the oxide layer 227 or the insulating layer 250 by heat treatment, thereby reducing oxygen vacancies in the semiconductor layer 230. Furthermore, by using an indium oxide film with high oxygen permeability for the semiconductor layer 230, excess oxygen in the semiconductor layer 230 can be discharged to the insulating layer 250, thereby reducing the amount of excess oxygen in the semiconductor layer 230. Therefore, the electrical characteristics and reliability of the transistor 200E can be improved.

[0372] 22A to 22D illustrate a configuration in which the extension direction of the groove 291 coincides with the extension direction of the conductive layer 260 functioning as the gate wiring, but the present invention is not limited to this. For example, the extension direction of the groove 291 may intersect with the extension direction of the gate wiring.

[0373] [Transistor 200F] Fig. 25A is a plan view of a semiconductor device having a transistor 200F. Fig. 25B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 25A. Fig. 25C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 25A. Fig. 25D is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 25B.

[0374] 25A to 25D differ from the semiconductor device shown in Figures 22A to 22D mainly in that it has a conductive layer 265 and does not have an insulating layer 283, a conductive layer 243a, a conductive layer 243b, or a conductive layer 246. It also differs from the semiconductor device shown in Figures 22A to 22D mainly in that the conductive layer 260 is provided in an island shape and that the conductive layers 240a and 240b are provided in an extended manner.

[0375] The conductive layer 265 is provided on the insulating layer 285 and is in contact with the conductive layer 260. The conductive layer 265 is provided to extend in the Y direction. The conductive layers 240a and 240b are provided to extend in the X direction.

[0376] The conductive layer 260 is provided in an island shape. In a plan view, the outer periphery of the conductive layer 260 is located inside the outer periphery of the semiconductor layer 230. Note that in a plan view, the outer periphery of the conductive layer 260 may overlap with a part of the outer periphery of the semiconductor layer 230, or may be located outside the part of the outer periphery of the semiconductor layer 230.

[0377] In the YZ plane including the semiconductor layer 230, the end of the semiconductor layer 230 outside the groove portion 291 is located more inward than the end of the conductive layer 240 outside the groove portion 291 (see FIG. 25B ). Note that in the YZ plane including the semiconductor layer 230, the end of the semiconductor layer 230 outside the groove portion 291 may coincide or approximately coincide with the end of the conductive layer 240 outside the groove portion 291, or may be located more outward than the end of the conductive layer 240 outside the groove portion 291.

[0378] The insulating layer 285 is provided on the insulating layer 250. The insulating layer 285 is also provided so as to fill in the portion of the groove 291 where the conductive layer 260 is not located.

[0379] 25A to 25D , the physical distance between the conductive layer 260 and the conductive layer 240a or 240b can be increased, and the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240a or 240b can be reduced. Furthermore, the physical distance between the conductive layer 265 and the conductive layer 240a or 240b can be increased, and the parasitic capacitance generated between the conductive layer 265 and the conductive layer 240a or 240b can be reduced. Therefore, the frequency characteristics of a circuit using the transistor can be improved.

[0380] 25A to 25D illustrate a configuration in which the conductive layer 260 has a region facing the side surface of the conductive layer 240a across the semiconductor layer 230 and a region facing the side surface of the conductive layer 240b across the semiconductor layer 230, but the present invention is not limited to this. For example, a first conductive layer facing the side surface of the conductive layer 240a across the semiconductor layer 230 and a second conductive layer facing the side surface of the conductive layer 240b across the semiconductor layer 230 may be provided.

[0381] [Transistor 200Ga and Transistor 200Gb] Fig. 26A is a plan view of a semiconductor device including transistor 200Ga and transistor 200Gb. Fig. 26B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 26A. Fig. 26C is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 26B.

[0382] The semiconductor device shown in Figures 26A to 26C differs from the semiconductor device shown in Figures 25A to 25C in that the conductive layer 220, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are each separated in and near the groove portion 291.

[0383] The transistor 200Ga has a conductive layer 220a, a conductive layer 240a on the insulating layer 280, a semiconductor layer 230a, an insulating layer 250a on the semiconductor layer 230a, and a conductive layer 260a on the insulating layer 250a. The transistor 200Gb has a conductive layer 220b, a conductive layer 240b on the insulating layer 280, a semiconductor layer 230b, an insulating layer 250b on the semiconductor layer 230b, and a conductive layer 260b on the insulating layer 250b.

[0384] In the transistor 200Ga, the semiconductor layer 230a functions as a semiconductor layer, the conductive layer 260a functions as a gate electrode, the insulating layer 250a functions as a gate insulating layer, the conductive layer 220a functions as one of a source electrode and a drain electrode, and the conductive layer 240a functions as the other of the source electrode and drain electrode. In the transistor 200Gb, the semiconductor layer 230b functions as a semiconductor layer, the conductive layer 260b functions as a gate electrode, the insulating layer 250b functions as a gate insulating layer, the conductive layer 220b functions as one of a source electrode and a drain electrode, and the conductive layer 240b functions as the other of the source electrode and drain electrode.

[0385] By providing the transistor 200Ga in contact with one sidewall of the groove 291 and the transistor 200Gb in contact with the other sidewall, miniaturization and high integration of semiconductor devices can be promoted.

[0386] Although FIGS. 26A to 26C illustrate a configuration in which the insulating layer 250 is separated into insulating layers 250a and 250b, the present invention is not limited to this.

[0387] 27A to 27C will be used to describe modifications of the two transistors described using FIGS. 26A to 26C. FIG. 27A is a plan view of a semiconductor device having two transistors 200. FIG. 27B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 27A. FIG. 27C is a cross-sectional view taken along dashed dotted line A5-A6 in FIG. 27A.

[0388] 27A to 27C differ from the semiconductor device shown in FIGS. 26A to 26C in that an insulating layer 250 covers the semiconductor layer 230a and the semiconductor layer 230b. By covering the semiconductor layer 230a and the semiconductor layer 230b with the insulating layer 250, the side surface of the semiconductor layer 230a on the groove 291 side and the side surface of the semiconductor layer 230b on the groove 291 side can be covered. This makes it possible to suppress the diffusion of hydrogen into the semiconductor layer 230a and the semiconductor layer 230b. This makes it possible to realize a highly reliable transistor.

[0389] Note that a structure similar to that of at least one of the transistors 200A to 200D can also be applied to the transistors 200E, 200F, 200Ga, and 200Gb. In each of the transistors 200E, 200F, 200Ga, and 200Gb, an oxide layer 227 can be provided below the semiconductor layer 230. A layer 228 can be provided between the oxide layer 227 and the semiconductor layer 230.

[0390] <Structural Example 2 of Semiconductor Device> Another structural example of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 28A to 30C . FIG. 28A is a plan view of a semiconductor device including a transistor 200H. FIG. 28B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 28A , which is also a cross-sectional view of the transistor 200H in the channel length direction. FIG. 28C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 28A , which is also a cross-sectional view of the transistor 200H in the channel width direction. FIG. 28D is a cross-sectional view of a portion indicated by a dashed dotted line A5-A6 in FIG. 28A . Also, FIGS. 29A to 30C show enlarged cross-sectional views of the transistor 200H in the channel length direction.

[0391] The transistor 200H has a conductive layer 205, an insulating layer 221 on the conductive layer 205, an insulating layer 222 on the insulating layer 221, an insulating layer 224 on the insulating layer 222, a semiconductor layer 230 on the insulating layer 224, conductive layers 242a and 242b on the semiconductor layer 230, an insulating layer 271a on the conductive layer 242a, an insulating layer 271b on the conductive layer 242b, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0392] The semiconductor layer 230, the insulating layer 224, the insulating layer 250, and the conductive layer 260 included in the transistor 200H correspond to the semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, respectively. Alternatively, the semiconductor layer 230, the insulating layer 250, the insulating layer 224, and the conductive layer 205 included in the transistor 200H may correspond to the semiconductor layer 30, the insulating layer 20, the insulating layer 50, and the conductive layer 60, respectively.

[0393] In the transistor 200H, the conductive layer 260 functions as a first gate electrode (which can also be referred to as an upper gate electrode or a top gate electrode), and the insulating layer 250 functions as a first gate insulating layer. The conductive layer 205 functions as a second gate electrode (which can also be referred to as a lower gate electrode or a bottom gate electrode), and the insulating layers 224, 222, and 221 each function as a second gate insulating layer. The conductive layer 242a functions as one of a source electrode and a drain electrode, and the conductive layer 242b functions as the other of the source electrode and the drain electrode.

[0394] An insulating layer 275 is provided on the insulating layer 271a and the insulating layer 271b, and an insulating layer 280 is provided on the insulating layer 275. An opening 289 is formed in the insulating layer 280 and the insulating layer 275, reaching the insulating layer 222 and the semiconductor layer 230, and the opening 289 overlaps the region between the conductive layer 242a and the conductive layer 242b. In a plan view, the side surface of the insulating layer 280 in the opening 289 coincides or substantially coincides with the side surface of the conductive layer 242a and the side surface of the conductive layer 242b. The insulating layer 250 and the conductive layer 260 are disposed inside the opening 289. An insulating layer 282 is provided in contact with the top surface of the insulating layer 280, the upper end of the insulating layer 250, and the top surface of the conductive layer 260. An insulating layer 283 is provided on the insulating layer 282. Further, an insulating layer 216 is provided under the insulating layer 221, an insulating layer 214 is provided under the insulating layer 216 and the conductive layer 205, and an insulating layer 212 is provided under the insulating layer 214. The insulating layer 212, the insulating layer 214, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0395] Openings reaching the conductive layer 242a are formed in the insulating layers 285, 283, 282, 280, 275, and 271a, and conductive layers 243a and 241a are provided in the openings. An insulating layer 241a is provided in contact with the sidewall of the opening, and the conductive layer 243a is provided inside the insulating layer 241a. Furthermore, openings reaching the conductive layer 242b are formed in the insulating layers 285, 283, 282, 280, 275, and 271b, and conductive layers 243b and 241b are provided in the openings. An insulating layer 241b is provided in contact with the sidewall of the opening, and the conductive layer 243b is provided inside the insulating layer 241b. The conductive layers 243a and 243b function as vias that connect a wiring or the like provided over the transistor 200H to the source or drain of the transistor 200H.

[0396] The semiconductor layer 230 includes a channel formation region and a source region and a drain region sandwiching the channel formation region, as in the transistor 200H. That is, the semiconductor layer 230 includes a channel formation region, a source region, and a drain region. At least a portion of the channel formation region overlaps with the conductive layer 260. The source region overlaps with the conductive layer 242a, and the drain region overlaps with the conductive layer 242b. Note that the source region and the drain region can be interchanged. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region. The semiconductor layer 230 may have a single-layer structure or a stacked structure of two or more layers.

[0397] The semiconductor layer 230 is physically separated between adjacent transistors 200H in the channel length direction. This configuration can prevent the Row Hammer effect and the Passing Gate effect when the transistor 200H is used in a memory cell. The Row Hammer effect refers to a phenomenon in which, in a configuration in which the word lines (conductive layers 260) of two transistors are adjacent and the channel formation regions of the two transistors are connected, accumulated charge leaks to the adjacent word line, causing malfunction. The Passing Gate effect refers to a phenomenon in which charge moves to a floating gate or gate insulating layer, resulting in the formation of an unintended current path or a change in characteristics such as a threshold voltage fluctuation.

[0398] An insulating layer containing excess oxygen is provided near the oxide semiconductor layer, and heat treatment is performed to supply oxygen from the insulating layer to the oxide semiconductor layer, thereby eliminating oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor 200H may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if the amount of oxygen supplied from the insulating layer to the oxide semiconductor layer becomes excessively large, this may adversely affect the electrical characteristics and reliability of the transistor. Furthermore, oxygen may diffuse into conductive layers such as the gate electrode, source electrode, and drain electrode, oxidizing the conductive layers and impairing their conductivity.

[0399] First, at least one of an insulating layer having a barrier property against hydrogen and an insulating layer having a function of capturing or fixing hydrogen is formed near the semiconductor layer 230, and V in the channel formation region of the semiconductor layer 230 and its vicinity is formed. Ｏ It is preferable to reduce H.

[0400] At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against hydrogen. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against impurities. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against oxygen. Note that all of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 do not necessarily need to be provided. As long as the insulating layer has sufficient barrier properties against hydrogen, impurities, oxygen, and the like, the insulating layer can be formed by appropriately selecting from the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283. For example, a structure can be used in which the insulating layer 216 and the conductive layer 205 are formed in contact with the upper surface of the insulating layer 212 without providing the insulating layer 214.

[0401] The insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 preferably have a function of suppressing diffusion of hydrogen. For example, the insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 may be formed using silicon nitride, which has a higher hydrogen barrier property.

[0402] The insulating layer 214, the insulating layer 222, and the insulating layer 282 preferably have a function of capturing or fixing hydrogen. For example, aluminum oxide may be used for the insulating layer 214 and the insulating layer 282. For example, hafnium oxide, which is a high-k material, is preferably used for the insulating layer 222, which functions as the second gate insulating layer.

[0403] 29A , by providing an insulating layer 212 having a function of suppressing hydrogen diffusion under the transistor 200H, it is possible to suppress diffusion of hydrogen from layers below the transistor 200H. Furthermore, by providing an insulating layer 214 having a function of capturing or fixing hydrogen, it is possible to capture or fix hydrogen contained in the insulating layer 216 or the like in the insulating layer 214. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0404] Furthermore, by providing the insulating layer 221 having a function of suppressing hydrogen diffusion under the semiconductor layer 230, it is possible to suppress diffusion of hydrogen from below the semiconductor layer 230. Furthermore, by providing the insulating layer 222 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 224 or the like can be captured or fixed in the insulating layer 222. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0405] Furthermore, by providing an insulating layer 275 having the function of suppressing the diffusion of hydrogen so as to cover the semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc., it is possible to suppress the diffusion of hydrogen from the insulating layer 280 to the semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc.

[0406] Furthermore, by providing the insulating layer 283 having a function of suppressing hydrogen diffusion over the transistor 200H, it is possible to suppress diffusion of hydrogen from above the transistor 200H. Furthermore, by providing the insulating layer 282 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 280 or the like can be captured or fixed in the insulating layer 282. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0407] In this way, by using a structure in which the transistor 200H is surrounded by barrier insulating layers against hydrogen from above and below, diffusion of hydrogen into the oxide semiconductor is reduced, and the V Ｏ H can be reduced. This can improve the electrical characteristics and reliability of the transistor 200H.

[0408] Furthermore, excess oxygen is preferably contained in the insulating layer 280. By supplying the oxygen to the semiconductor layer 230 through the insulating layer 250 by heat treatment, oxygen vacancies in the channel formation region can be reduced.

[0409] The insulating layer 282 is preferably formed by a sputtering method in an atmosphere containing oxygen gas, which allows oxygen to be added to the insulating layer 280. The insulating layer 282 may have a single-layer structure or a stacked structure of two or more layers.

[0410] As described above, by performing heat treatment on the insulating layer 280 containing excess oxygen, a suitable amount of oxygen can be supplied to the semiconductor layer 230 through the insulating layer 250. In the heat treatment, the insulating layers 282 and 283 having a barrier property against oxygen are formed over the insulating layer 280, so that the oxygen contained in the insulating layer 280 can be prevented from diffusing excessively from the insulating layer 280. Furthermore, the insulating layer 275 having a barrier property against oxygen is formed between the insulating layer 280 and the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b, so that the oxygen contained in the insulating layer 280 can be prevented from diffusing excessively from the insulating layer 280. Furthermore, by performing the heat treatment with openings formed in parts of the insulating layer 280, the insulating layer 282, and the insulating layer 283, part of the oxygen contained in the insulating layer 280 can be diffused outward, and the amount of oxygen supplied from the insulating layer 280 to the semiconductor layer 230 can be adjusted.

[0411] 29B , an oxide layer 227 can be provided between the insulating layer 224 and the semiconductor layer 230. The oxide layer 227 corresponds to the oxide layer 27 described above. Therefore, the configuration (material, film thickness, etc.), formation method, etc. of the oxide layer 227 can be determined by referring to the configuration, formation method, etc. of the oxide layer 27 described above.

[0412] 29A shows an example in which the semiconductor layer 230 has a single-layer structure. Note that the semiconductor layer 230 can have a stacked structure of two or more layers. As shown in FIG. 30A , the semiconductor layer 230 can have a two-layer structure of a semiconductor layer 230_1 and a semiconductor layer 230_2 on the semiconductor layer 230_1. The semiconductor layers 230_1 and 230_2 correspond to the semiconductor layers 30_1 and 30_2 described above, respectively. Therefore, the structures (materials, film thicknesses, etc.), formation methods, etc. of the semiconductor layers 230_1 and 230_2 can be referenced to the structures, formation methods, etc. of the semiconductor layers 30_1 and 30_2 described above.

[0413] 30A illustrates a structure in which the insulating layer 250 is in contact with the top surface of the semiconductor layer 230_2, but the present invention is not limited to this. For example, as shown in FIG. 30B, the semiconductor layer 230_2 can be removed from a region overlapping with the opening 289, and the insulating layer 250 can be in contact with the side surface of the semiconductor layer 230_2 and the top surface of the semiconductor layer 230_1. With this structure, the distance between the conductive layer 260 and the semiconductor layer 230_1 can be shortened. Therefore, an electric field from the gate electrode can be suitably applied to the semiconductor layer 230_1.

[0414] The insulating layer 250 preferably has a structure that allows oxygen to diffuse from the insulating layer 280 to the semiconductor layer 230 and prevents the conductive layers 242a, 242b, and 260 from being oxidized.

[0415] The insulating layer 250 is formed within the opening 289 in contact with the top surface of the insulating layer 222, the side surface of the insulating layer 224, the side surface and top surface of the semiconductor layer 230, the side surface of the conductive layer 242a, the side surface of the conductive layer 242b, the side surface of the insulating layer 271a, the side surface of the insulating layer 271b, the side surface of the insulating layer 275, and the side surface of the insulating layer 280.

[0416] 29A , the insulating layer 250 preferably has a stacked-layer structure of an insulating layer 250_1 in contact with the semiconductor layer 230, an insulating layer 250_2 over the insulating layer 250_1, and an insulating layer 250_3 over the insulating layer 250_2. Alternatively, as shown in FIG. 30C , an insulating layer 250_4 may be provided over the insulating layer 250_2. The structures (materials, film thicknesses, etc.), formation methods, and the like of the insulating layers 250_1 to 250_4 described above in <Structural Example 1 of Semiconductor Device> can be referred to, respectively.

[0417] For example, the insulating layer 250_1, which has regions in contact with the side surfaces of the conductive layer 242a and the conductive layer 242b, has a function of capturing or fixing oxygen, which can prevent the side surfaces of the conductive layer 242a and the conductive layer 242b from being oxidized and oxide films from being formed on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200H. Furthermore, this structure can reduce the amount of oxygen in the insulating layer 250_2 that is absorbed by the conductive layer 242a and the conductive layer 242b. Therefore, an appropriate amount of oxygen can be supplied from the insulating layer 250_2 to the semiconductor layer 230, and oxygen vacancies in the channel formation region of the semiconductor layer 230 can be reduced.

[0418] Furthermore, by providing the insulating layer 250_1 between the insulating layer 280 and the insulating layer 250_2 and between the insulating layer 250_2 and the semiconductor layer 230, excessive supply of oxygen from the insulating layer 280 to the semiconductor layer 230 can be suppressed, and an appropriate amount of oxygen can be supplied to the semiconductor layer 230. Therefore, the amount of oxygen in the channel formation region of the semiconductor layer 230 and its vicinity can be controlled to an appropriate amount, which can prevent the transistor 200H from becoming excessively normally off and improve reliability. Furthermore, excessive oxidation of the source and drain regions can be suppressed, which can cause a decrease in on-state current or a decrease in field-effect mobility of the transistor 200H.

[0419] By adopting the above-described structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, by adopting the above-described structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200H can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0420] The conductive layer 205 is disposed so as to overlap with the semiconductor layer 230 and the conductive layer 260. The conductive material described in the below-described [Conductive Layer] can be used for the conductive layer 205. Here, the conductive layer 205 is provided so as to be embedded in an opening formed in the insulating layer 216. Furthermore, as shown in FIGS. 28A and 28C , the conductive layer 205 is preferably provided so as to extend in the channel width direction. With such a structure, when a plurality of transistors are provided, the conductive layer 205 functions as a wiring.

[0421] 29A , the conductive layer 205 preferably includes a conductive layer 205_1 and a conductive layer 205_2. The conductive layer 205_1 is provided in contact with the bottom surface and sidewall of the opening. The conductive layer 205_2 is provided so as to fill a recess in the conductive layer 205_1 formed along the opening. Here, the height of the top surface of the conductive layer 205 is the same as or approximately the same as the height of the top surface of the insulating layer 216.

[0422] Here, the conductive layer 205_1 contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0423] By using a conductive material that can reduce hydrogen diffusion for the conductive layer 205_1, impurities such as hydrogen contained in the conductive layer 205_2 can be prevented from diffusing into the semiconductor layer 230 through the insulating layer 216 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductive layer 205_1, oxidation of the conductive layer 205_2 and a decrease in conductivity can be suppressed. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205_1 can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layer 205_1 preferably contains titanium nitride.

[0424] The conductive layer 205_2 is preferably formed using a conductor with high conductivity. For example, the conductive layer 205_2 is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductive layer 205_2 preferably contains tungsten.

[0425] The conductive layer 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200H can be controlled by changing the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260. In particular, applying a negative potential to the conductive layer 205 can increase the Vth of the transistor 200H and reduce its off-state current. Therefore, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential applied to the conductive layer 260 is 0 V, compared to when a negative potential is not applied.

[0426] 29A shows a stacked structure of the conductive layer 205_1 and the conductive layer 205_2, the present invention is not limited thereto, and the conductive layer 205 may have a single-layer structure or a stacked structure of three or more layers. For example, the conductive layer 205_1 may have a two-layer structure of a tantalum nitride film and a titanium nitride film on the tantalum nitride film, and the conductive layer 205_2 having a tungsten film may be provided on the conductive layer 205_1. With such a structure, impurities such as hydrogen and metal impurities such as copper contained in the lower layer of the transistor 200H can be prevented from diffusing into the conductive layer 205.

[0427] The insulating layer 224 functions as a second gate insulating layer together with the insulating layers 221 and 222 .

[0428] The insulating layer 224 in contact with the semiconductor layer 230 can be made of an insulating material applicable to the insulating layer 20 described above. The insulating layer 224 preferably includes, for example, a silicon oxide film or a silicon oxynitride film. This allows oxygen to be supplied from the insulating layer 224 to the semiconductor layer 230, thereby reducing oxygen vacancies. Note that the insulating layer 224 may have a stacked structure of two or more layers. In this case, the insulating layer 224 is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0429] Furthermore, the insulating layer 224 is preferably processed into an island shape, similar to the semiconductor layer 230. As a result, when a plurality of transistors 200H are provided, each transistor 200H has an insulating layer 224 of approximately the same size. As a result, the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 in each transistor 200H becomes approximately the same. Therefore, variation in the electrical characteristics of the transistors 200H within the substrate surface can be suppressed.

[0430] Furthermore, by providing the insulating layer 224 in an island shape, at least a part of the lower surface of the conductive layer 260 can be provided below the lower surface of the semiconductor layer 230 (see FIG. 28C ). This allows the conductive layer 260 to be provided facing the upper surface and side surface of the semiconductor layer 230, and therefore the electric field of the conductive layer 260 can be applied to the upper surface and side surface of the semiconductor layer 230.

[0431] However, the insulating layer 224 does not necessarily have to be processed into an island shape. For example, as shown in Figures 31A to 31D, the insulating layer 224 may not be formed into an island shape, but may have a shape in which an opening is formed in part. Figures 31A to 31D correspond to Figures 28A to 28D, respectively, and are the same as Figures 28A to 28D except that the shape of the insulating layer 224 is different.

[0432] 31A to 31D, the insulating layer 224 has a thickness smaller in a region that does not overlap with the semiconductor layer 230 than in a region that overlaps with the semiconductor layer 230. In addition, an opening is formed in a region that does not overlap with the semiconductor layer 230 and overlaps with the insulating layer 250. When multiple transistors are provided on the same substrate, by forming the insulating layer 224 in this manner, the semiconductor layer 230 of each transistor is formed on the same insulating layer 224. This can reduce variations in the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 of each transistor. Therefore, variations in the electrical characteristics of each transistor can be reduced.

[0433] In the insulating layer 224 shown in Figures 31A to 31D, an opening is formed in the region that does not overlap with the semiconductor layer 230 and overlaps with the insulating layer 250, but a configuration without such an opening may be used.

[0434] The conductive layers 242a and 242b can be formed using the conductive materials described in the section "Conductive Layer" below. In particular, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion for the conductive layers 242a and 242b. Examples of such a conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 242a and 242b.

[0435] For the conductive layers 242a and 242b, it is preferable to use a metal nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. For example, tantalum nitride can be used for the conductive layers 242a and 242b. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain their conductivity even when they absorb oxygen.

[0436] Alternatively, each of the conductive layers 242a and 242b may have a stacked structure. In this case, the conductive material may be used for the lower layers of the conductive layers 242a and 242b, and a conductive material with higher conductivity may be used for the upper layers of the conductive layers 242a and 242b. For example, tantalum nitride may be used for the lower layer, and tungsten may be used for the upper layer.

[0437] The insulating layers 271a and 271b are inorganic insulating layers that function as etching stoppers and protect the conductive layers 242a and 242b when processing the conductive layers 242a and 242b. Furthermore, since the insulating layers 271a and 271b are in contact with the conductive layers 242a and 242b, they are preferably inorganic insulators that are less likely to oxidize the conductive layers 242a and 242b. Therefore, each of the insulating layers 271a and 271b preferably has a two-layer structure. Here, the lower layers of the insulating layers 271a and 271b are preferably made of a nitride insulator that can be used for the insulating layer 250_3, and preferably made of silicon nitride, in order to prevent the conductive layers 242a and 242b from being oxidized. The insulating layer 271a and the insulating layer 271b are each preferably formed using an oxide insulator, which can be used for the insulating layer 250_2, and preferably using silicon oxide, so as to function as an etching stopper.

[0438] The insulating layers that are the basis for the insulating layers 271a and 271b function as masks for the conductive layers that are the basis for the conductive layers 242a and 242b, so that the conductive layers 242a and 242b do not have curved surfaces between their side surfaces and top surfaces, as shown in FIG. 28D . As a result, the conductive layers 242a and 242b have angular edges where their side surfaces and top surfaces intersect. The angular edges where their side surfaces and top surfaces intersect increase the cross-sectional areas of the conductive layers 242a and 242b compared to when the edges have curved surfaces. As a result, the resistance of the conductive layers 242a and 242b is reduced, thereby increasing the on-state current of the transistor.

[0439] The conductive layer 260 is provided in the opening 289 so as to cover the upper surface of the insulating layer 222, the side surface of the insulating layer 224, and the side and upper surface of the semiconductor layer 230 via the insulating layer 250. The height of the upper surface of the conductive layer 260 is the same as or approximately the same as the height of the upper end of the insulating layer 250 and the height of the upper surface of the insulating layer 280.

[0440] The sidewall of the opening 289 may be perpendicular or approximately perpendicular to the upper surface of the insulating layer 222, or may be tapered. By tapering the sidewall, the coverage of the insulating layer 250 provided in the opening 289 is improved, and defects such as voids can be reduced.

[0441] 28A and 28C, the conductive layer 260 is preferably provided so as to extend in the channel width direction. With this configuration, when a plurality of transistors are provided, the conductive layer 260 functions as a wiring.

[0442] 28C , in a cross-sectional view of the transistor 200H in the channel width direction, a curved surface may be formed between the side surface of the semiconductor layer 230 and the top surface of the semiconductor layer 230. In other words, the end of the side surface and the end of the top surface may be curved.

[0443] 29A, the conductive layer 260 preferably has a two-layer structure. Here, the conductive layer 260 preferably includes a conductive layer 260_1 and a conductive layer 260_2 disposed on the conductive layer 260_1. For example, the conductive layer 260_1 is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 260_2.

[0444] The structures (materials, film thicknesses, etc.), formation methods, and the like of the conductive layers 260_1 and 260_2 can be referred to the structures, formation methods, and the like of the conductive layers 260_1 and 260_2 described above in <Structure Example 1 of Semiconductor Device>. For example, the conductive layer 260_1 has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductive layer 260_2 by oxygen contained in the insulating layer 280 or the like.

[0445] The insulating layer 216, the insulating layer 280, and the insulating layer 285 preferably have a lower relative dielectric constant than the insulating layer 222. By using a material with a low relative dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0446] For example, the insulating layer 216, the insulating layer 280, and the insulating layer 285 can each be made of a material with a low dielectric constant, which will be described later in the section [Insulating Layer]. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. Furthermore, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferable because they can easily form a region containing excess oxygen.

[0447] Furthermore, the upper surfaces of the insulating layer 216 and the insulating layer 280 may each be flattened.

[0448] It is preferable that the concentration of impurities such as water and hydrogen is reduced in the insulating layer 280. For example, it is preferable that the insulating layer 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0449] The conductive layers 243a and 243b can be formed using the conductive materials described in the section "Conductive Layer" below. The conductive layers 243a and 243b are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component, for example. The conductive layers 243a and 243b may have a stacked structure.

[0450] 29A , the conductive layer 243a and the conductive layer 243b may have a two-layer laminated structure. The conductive layer 243a includes a conductive layer 243a1 formed along the opening and a conductive layer 243a2 formed inside the conductive layer 243a1. The conductive layer 243b includes a conductive layer 243b1 formed along the opening and a conductive layer 243b2 formed inside the conductive layer 243b1.

[0451] The conductive layer 243a1 and the conductive layer 243b1 can be formed as a single layer or a stacked layer using a conductive material applicable to the conductive layer 205_1. By providing the conductive layer 243a1 and the conductive layer 243b1, impurities such as water and hydrogen can be prevented from entering the semiconductor layer 230 through the conductive layer 243a2 and the conductive layer 243b2. Note that the conductive layer 243a2 and the conductive layer 243b2 may be formed using a conductive material applicable to the conductive layer 243a and the conductive layer 243b.

[0452] 28B, the height of the upper surfaces of conductive layers 243a and 243b is the same or approximately the same as the height of the upper surface of insulating layer 285. Also, as shown in Fig. 29A, conductive layer 243a may be formed so that its lower portion is embedded in conductive layer 242a. Similarly, conductive layer 243b may be formed so that its lower portion is embedded in conductive layer 242b.

[0453] The insulating layers 241a and 241b may be barrier insulating layers applicable to the insulating layer 275 or the like. For example, silicon nitride may be used for the insulating layers 241a and 241b. The insulating layers 241a and 241b are provided in contact with the insulating layers 285, 283, 282, 275, 271a, and 271b. This can prevent impurities such as water and hydrogen contained in the insulating layer 280 or the like from being mixed into the semiconductor layer 230 through the conductive layers 243a and 243b. Silicon nitride is particularly suitable because it has a high barrier property against hydrogen. Furthermore, oxygen contained in the insulating layer 280 can be prevented from being absorbed by the conductive layers 243a and 243b.

[0454] The insulating layer 241 a and the insulating layer 241 b may have a stacked structure. In this case, a first insulating layer in contact with a sidewall of an opening such as the insulating layer 280 and a second insulating layer on the inner side thereof preferably use a combination of a barrier insulating layer against oxygen and a barrier insulating layer against hydrogen.

[0455] 28B and other figures, insulating layer 250 is in contact with the side surface of insulating layer 280 in opening 289, but the present invention is not limited to this configuration. For example, an insulating layer may be provided between insulating layer 250 and insulating layer 280 in opening 289.

[0456] 32A to 33C will be used to describe modifications of the semiconductor device described with reference to Figs. 28A to 28D. Figs. 32A to 32D are plan views and cross-sectional views of a semiconductor device including a transistor 200H, and correspond to the plan views and cross-sectional views shown in Figs. 28A to 28D, respectively. Figs. 33A to 33C are enlarged cross-sectional views of the transistor 200H in the channel length direction, and correspond to the enlarged cross-sectional view shown in Fig. 29B, respectively.

[0457] 32A to 32D differs from the transistor 200H shown in Figures 28A to 28D mainly in that it has an insulating layer 254. Hereinafter, differences from the above description will be mainly described, and overlapping portions will be referred to and may not be described again.

[0458] 32A to 32D, the conductive layers 242a and 242b are each shown as a two-layer structure. The conductive layer 242a has a laminated structure of a conductive layer 242a1 and a conductive layer 242a2 on the conductive layer 242a1. The conductive layer 242b has a laminated structure of a conductive layer 242b1 and a conductive layer 242b2 on the conductive layer 242b1. The conductive layers 242a1 and 242b1 correspond to the lower layers of the above-mentioned conductive layers 242a and 242b, respectively, and the conductive layers 242a2 and 242b2 correspond to the upper layers of the above-mentioned conductive layers 242a and 242b, respectively.

[0459] 32B and 32C , insulating layer 254 is disposed inside opening 289 and contacts the side surfaces of insulating layer 280, the side surfaces of conductive layer 242a2, the side surfaces of conductive layer 242b2, the top surfaces of conductive layer 242a1, the top surfaces of conductive layer 242b1, and the top surface of insulating layer 222 in opening 289. In other words, insulating layer 254 can also be said to be formed in the shape of a sidewall in contact with the side wall of opening 289. Here, the side wall of opening 289 corresponds to, for example, the side surface of insulating layer 280, etc. in opening 289.

[0460] The insulating layer 254 preferably has a barrier property against oxygen. The insulating layer 254 having a barrier property against oxygen can prevent the side surfaces of the conductive layers 242a and 242b from being oxidized and oxide films from being formed on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200H. An oxygen barrier insulating layer can be used as the insulating layer 254. For example, silicon nitride can be used as the insulating layer 254.

[0461] The opening 289 overlaps the region between the conductive layer 242a2 and the conductive layer 242b2. In a plan view, the side surfaces of the insulating layer 280 in the opening 289 coincide or substantially coincide with the side surfaces of the conductive layer 242a2 and the conductive layer 242b2. Furthermore, portions of the conductive layers 242a1 and 242b1 are formed to protrude into the opening 289. In other words, the portion of the conductive layer 242a1 on which the insulating layer 254 is formed (hereinafter, sometimes referred to as the protruding portion of the conductive layer 242a1) protrudes toward the conductive layer 260 more than the conductive layer 242a2. Similarly, the portion of the conductive layer 242b1 on which the insulating layer 254 is formed (hereinafter, sometimes referred to as the protruding portion of the conductive layer 242b1) protrudes toward the conductive layer 260 more than the conductive layer 242b2.

[0462] Here, a part of the top surface of the conductive layer 242a1 is in contact with the conductive layer 242a2, and a part of the top surface of the conductive layer 242b1 is in contact with the conductive layer 242b2. Therefore, the insulating layer 254 is in contact with another part of the top surface of the conductive layer 242a1, another part of the top surface of the conductive layer 242b1, a side surface of the conductive layer 242a2, and a side surface of the conductive layer 242b2 inside the opening 289. Furthermore, the insulating layer 250 is in contact with the top surface of the semiconductor layer 230, the side surface of the conductive layer 242a1, the side surface of the conductive layer 242b1, and the side surface of the insulating layer 254.

[0463] The insulating layer 254 is formed by anisotropic etching to have a sidewall shape in contact with the side wall of the opening 289. The insulating layer 254 is formed in contact with the side surface of the conductive layer 242a2 and the side surface of the conductive layer 242b2 and has a function of protecting the conductive layer 242a2 and the conductive layer 242b2.

[0464] 33A , in a cross-sectional view of the transistor 200H, the side edges of the insulating layer 254 coincide or substantially coincide with the side edges of the conductive layer 242a1 and the conductive layer 242b1.

[0465] Note that after the separation into the conductive layer 242a1 and the conductive layer 242b1, heat treatment is preferably performed in an atmosphere containing oxygen before the formation of the insulating layer 250. At this time, by forming the insulating layer 254 in contact with the side surfaces of the conductive layer 242a2 and the conductive layer 242b2, excessive oxidation of the conductive layer 242a2 and the conductive layer 242b2 can be prevented. Furthermore, even when microwave plasma treatment is performed after the separation into the conductive layer 242a1 and the conductive layer 242b1, formation of an oxide film on the side surfaces of the conductive layer 242a and the conductive layer 242b can be suppressed.

[0466] The insulating layer 254, the insulating layer 250, and the conductive layer 260 are provided to reflect the shape of the opening 289. Therefore, the insulating layer 254 is provided so as to cover the sidewall of the opening 289, the insulating layer 250 is provided so as to cover the bottom of the opening 289 and the insulating layer 254, and the conductive layer 260 is provided so as to fill the recess of the insulating layer 250.

[0467] As described above, the insulating layer 250 may have a stacked structure. For example, as shown in FIG. 33A , the insulating layer 250 may have a three-layer structure of insulating layers 250_1 to 250_3. Alternatively, for example, as shown in FIG. 33B , the insulating layer 250 may have a four-layer structure of insulating layers 250_1 to 250_4.

[0468] The thickness of the insulating layer 254 is preferably 0.5 nm to 20 nm, more preferably 0.5 nm to 10 nm, and still more preferably 0.5 nm to 3 nm. By setting the insulating layer 254 to the above thickness, excessive oxidation of the conductive layer 242a2 and the conductive layer 242b2 can be suppressed. Note that the insulating layer 254 only needs to have a region with the above thickness in at least a portion. Furthermore, since the insulating layer 254 is provided in contact with the sidewall of the opening 289, it is preferable to deposit the insulating layer 254 by an ALD method or the like, which has good coverage. If the insulating layer 254 is too thick, the deposition time of the insulating layer 254 by the ALD method increases, resulting in reduced productivity. Therefore, the thickness of the insulating layer 254 is preferably within the above range. The insulating layer 254 preferably has a thickness that does not excessively hinder the diffusion of excess oxygen from the insulating layer 280 to the insulating layer 250_2 and from the insulating layer 250_2 to the semiconductor layer 230.

[0469] As shown in FIG. 33A , in a cross-sectional view of the transistor 200H in the channel length direction, the distance L1 between the conductive layers 242a1 and 242b1 is smaller than the distance L2 between the conductive layers 242a2 and 242b2. Here, distance L1 refers to the shortest distance between the conductive layers 242a1 and 242b1, and distance L2 refers to the shortest distance between the conductive layers 242a2 and 242b2. This configuration allows for a shorter source-drain distance and a correspondingly shorter channel length. This improves the frequency characteristics of the transistor 200H. By miniaturizing the semiconductor device in this way, a semiconductor device with improved operating speed can be provided.

[0470] 33A , the difference between distance L2 and distance L1 is equal to twice the film thickness of insulating layer 254. In other words, distance L2 is equal to or approximately equal to distance L1 obtained by adding twice the film thickness of insulating layer 254. Here, the film thickness of insulating layer 254 refers to the width of at least a portion of insulating layer 254 in the A1-A2 direction.

[0471] The insulating layer 254 may also have a stacked structure of two or more layers. In this case, at least one layer can be the inorganic insulating layer that is resistant to oxidation. For example, the inorganic insulating layer that is resistant to oxidation may be used as the first insulating layer of the insulating layer 254, and an insulating material (e.g., silicon oxide) applicable to the insulating layer 250_2 may be used as the second insulating layer on the first insulating layer of the insulating layer 254. The second insulating layer of the insulating layer 254 preferably has a lower dielectric constant than the first insulating layer of the insulating layer 254. By increasing the thickness of the insulating layer 254 by forming the insulating layer 254 into a two-layer structure, the distance between the conductive layer 260 and the conductive layer 242a or 242b can be increased, thereby reducing parasitic capacitance.

[0472] Although the above describes an example in which the insulating layer 254 is formed in a sidewall shape by anisotropic etching, the present invention is not limited to this. As shown in Fig. 33C, the insulating layer 254 may have an opening inside the opening 289. In this case, the opening in the insulating layer 254 can be formed by removing a part of the insulating film that will become the insulating layer 254 by lithography. The opening in the insulating layer 254 preferably overlaps with the region between the conductive layer 242a1 and the conductive layer 242b1.

[0473] 33C, in a cross-sectional view, a protrusion is formed at the lower part of the insulating layer 254. The protrusion of the insulating layer 254 overlaps with the protrusion of the conductive layer 242a1 and the protrusion of the conductive layer 242b1.

[0474] In the first modification, the insulating layer 254 is provided in contact with the sidewall of the opening 289. However, the present invention is not limited to this configuration. For example, the insulating layer 254 may not be provided in the opening 289.

[0475] 34A to 35 will be used to describe a modification of the semiconductor device described in Modification 1. Figures 34A to 34D are plan views and cross-sectional views of a semiconductor device including a transistor 200H, and correspond to the plan views and cross-sectional views shown in Figures 32A to 32D, respectively. Also, Figure 35 is an enlarged cross-sectional view of the transistor 200H in the channel length direction, and corresponds to the enlarged cross-sectional view shown in Figure 33C.

[0476] 34A to 34D differs from the transistor 200H shown in Figures 32A to 32D mainly in that it does not have an insulating layer 254. Hereinafter, differences from the above description will be mainly described, and overlapping portions will be referred to and may not be described again.

[0477] 35 , in a configuration in which the insulating layer 254 is not provided, a portion of the insulating layer 250 is disposed so as to overlap the protruding portions of the conductive layer 242a1 and the conductive layer 242b1. Also, a portion of the conductive layer 260 may be disposed so as to overlap the protruding portions of the conductive layer 242a1 and the conductive layer 242b1. Here, the protruding portions of the conductive layer 242a1 and the conductive layer 242b1 contact the insulating layer 250. Furthermore, the side surface of the insulating layer 250 contacts the side surfaces of the insulating layer 280, the insulating layer 275, the insulating layer 271a, the insulating layer 271b, the conductive layer 242a2, and the conductive layer 242b2.

[0478] The insulating layer 250 is formed to reflect the shape of the opening 289. Therefore, the insulating layer 250 is formed to reflect the shapes of the conductive layers 242a1 and 242b1 protruding into the opening 289.

[0479] 35, in a cross-sectional view of the transistor 200H in the channel length direction, the distance L1 between the conductive layer 242a1 and the conductive layer 242b1 is smaller than the distance L2 between the conductive layer 242a2 and the conductive layer 242b2. This configuration allows the distance between the source and the drain to be shortened, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200H. By miniaturizing the semiconductor device in this way, a semiconductor device with improved operating speed can be provided.

[0480] 35, the width of the upper portion of the conductive layer 260 can be made larger than the distance L1, thereby reducing the wiring resistance of the conductive layer 260. As a result, the power consumption of the semiconductor device can be reduced.

[0481] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer that constitutes the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0482] [Oxide Semiconductor Layer] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor according to one embodiment of the present invention, the description in <Structure of Semiconductor Device> can be referred to.

[0483] The carrier concentration in the channel formation region is 1×10 １９ cm −３ Less than 1 x 10 １８ cm −３ Less than 5 x 10 １７ cm −３ Less than 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −７ cm −３ It can be said that:

[0484] As described above, in an OS transistor, oxygen vacancies (V Ｏ The presence of impurities may cause fluctuations in electrical characteristics and reduce reliability. Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of an OS transistor. To reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, carbon, and nitrogen.

[0485] When nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to be normally on. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0486] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to be normally on. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Note that the lower limit of the hydrogen concentration in the channel formation region of the oxide semiconductor is not particularly limited, but is, for example, less than 1×10 １６ atoms / cm ３ It can be more than that.

[0487] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0488] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0489] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 212, insulating layer 214, insulating layer 221, insulating layer 222, insulating layer 224, insulating layer 225, insulating layer 241a, insulating layer 241b, insulating layer 250, insulating layer 254, insulating layer 275, insulating layer 280, insulating layer 281, insulating layer 282, insulating layer 283, insulating layer 284, insulating layer 285, etc.) included in the semiconductor device. Examples of the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of the oxide insulating film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of nitride oxide insulating films include silicon nitride oxide films and aluminum nitride oxide films. An organic insulating film may also be used for an insulating layer included in a semiconductor device.

[0490] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-k material for the gate insulating layer allows for lower voltage during transistor operation while maintaining the physical film thickness. It also allows for thinner EOT of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0491] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0492] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0493] Furthermore, a material capable of exhibiting ferroelectricity may be used for an insulating layer of a semiconductor device. As the material capable of exhibiting ferroelectricity, an oxide containing one or both of hafnium and zirconium is preferably used. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Furthermore, as the material capable of exhibiting ferroelectricity, a material obtained by adding an element J1 (here, the element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to a metal oxide containing one of hafnium and zirconium may be used.

[0494] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0495] Furthermore, examples of materials that can have ferroelectricity include metal nitrides containing at least one of element M1 and element M2 and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Furthermore, examples of materials that can have ferroelectricity include materials in which element M3 is added to the above metal nitrides. Note that element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.

[0496] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Furthermore, examples of materials that can have ferroelectricity include lead titanate (PbTiOＸ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0497] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0498] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer 130 described in the second embodiment can have a layered structure made of a plurality of materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0499] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0500] The ferroelectric layer preferably contains crystals having an orthorhombic crystal structure, since this allows ferroelectricity to be exhibited. The crystal structure of the crystals contained in the ferroelectric layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The ferroelectric layer may also have an amorphous structure. In this case, the ferroelectric layer may have a composite structure having an amorphous structure and a crystalline structure.

[0501] A metal oxide containing one or both of hafnium and zirconium is also an insulating material that has the function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing one or both of hafnium and zirconium for at least a part of a gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor having the gate insulating layer can function as a ferroelectric field effect transistor (FeFET).

[0502] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0503] Specifically, examples of materials for the insulating layer that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Examples of nitrides include aluminum nitride, aluminum titanium nitride, and silicon nitride. Examples of nitride oxides include silicon nitride oxide. Examples of materials for the insulating layer that have the function of suppressing the permeation of oxygen include gallium oxide.

[0504] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer preferably has a region containing excess oxygen. For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. For an insulating layer in which a region containing excess oxygen is easily formed, the description in <Structure of Semiconductor Device> can be referred to.

[0505] An insulating layer provided in contact with or near an oxide semiconductor layer is preferably a barrier insulating layer against hydrogen. When the insulating layer has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer can be suppressed. The barrier insulating layer against hydrogen can also be said to have a function of suppressing diffusion of hydrogen.

[0506] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), hafnium silicate, etc. These metal oxides may further contain zirconium, and examples thereof include oxides containing hafnium and zirconium.

[0507] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced.

[0508] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0509] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0510] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are also referred to as a property that makes it difficult for a corresponding substance to diffuse (a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, and NO ２The term "oxygen" when used in reference to a corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0511] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), silicon nitride, and silicon nitride oxide.

[0512] The inorganic insulating layers cited as insulating layers having the function of capturing or fixing hydrogen and insulating layers having the function of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for oxygen barrier insulating layers include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0513] [Conductive Layer] For the conductive layers (conductive layer 205, conductive layer 220, conductive layer 240, conductive layer 242a, conductive layer 242b, conductive layer 243a, conductive layer 243b, conductive layer 246, conductive layer 255, conductive layer 260, conductive layer 265, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements, etc. As the alloy containing any of the above metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0514] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In—Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0515] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0516] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0517] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, or a memory element.

[0518] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0519] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0520] 36A to 42. The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.

[0521] <Configuration Example 1 of Memory Device> The configuration of a memory device having memory cells will be described using Figures 36A to 36C. Figure 36A is a plan view of a memory device having memory cells 150. Figure 36B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Figure 36A. Figure 36C is a cross-sectional view taken along dashed dotted line A3-A4 shown in Figure 36A.

[0522] 36A to 36C includes an insulating layer 140 over a substrate (not shown), a conductive layer 110 over the insulating layer 140, a memory cell 150 over the conductive layer 110, an insulating layer 180 over the conductive layer 110, and an insulating layer 280. The insulating layer 140 and the insulating layer 180 function as interlayer films. The conductive layer 110 functions as wiring.

[0523] The memory cell 150 includes a capacitor 100 over a conductive layer 110 and a transistor 200 over the capacitor 100 .

[0524] The capacitor 100 includes a conductive layer 115 over the conductive layer 110, an insulating layer 130 over the conductive layer 115, and a conductive layer 220_1 over the insulating layer 130. The conductive layer 220_1 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric. That is, the capacitor 100 forms a metal-insulator-metal (MIM) capacitor. Note that the conductive layer 220_2 provided over the conductive layer 220_1 can also be considered as part of the upper electrode of the capacitor 100.

[0525] As shown in FIGS. 36B and 36C , an opening 190 reaching the conductive layer 110 is provided in the insulating layer 180. At least a portion of the conductive layer 115 is disposed in the opening 190. Note that the conductive layer 115 has a region in contact with the top surface of the conductive layer 110 in the opening 190, a region in contact with the side surface of the insulating layer 180 in the opening 190, and a region in contact with at least a portion of the top surface of the insulating layer 180. At least a portion of the insulating layer 130 is disposed so as to be located in the opening 190. At least a portion of the conductive layer 220_1 is disposed so as to be located in the opening 190. Note that, as shown in FIGS. 36B and 36C , the conductive layer 220_1 is preferably provided so as to fill the opening 190. Note that the films provided inside the openings 190 are preferably formed using an ALD method. This improves the coverage of the films. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 220_1 are preferably formed by an ALD method.

[0526] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric sandwiched between them on the side surfaces as well as the bottom surface within the opening 190, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can stabilize the read operation of the memory device. Furthermore, this can promote miniaturization or high integration of memory devices.

[0527] 36B and 36C show an example in which the sidewall of opening 190 is perpendicular to the top surface of conductive layer 110 and opening 190 is circular in plan view. With such a configuration, miniaturization or high integration of the memory device can be achieved.

[0528] A conductive layer 115 and an insulating layer 130 are stacked along the sidewall of the opening 190 and the top surface of the conductive layer 110. In addition, a conductive layer 220_1 is provided on the insulating layer 130 so as to fill the opening 190. The capacitor 100 having such a configuration may be called a trench capacitor.

[0529] The conductive layer 110 functions as wiring CAL, which will be described later, and can be provided, for example, in a strip shape. Note that the strip shape refers to a shape having an area extending in a certain direction (for example, the X direction, the Y direction, or the Z direction).

[0530] The conductive layer 110 can be formed as a single layer or a stacked layer using the conductive material described in [Conductive Layer] in Embodiment 1. For example, a conductive material with high conductivity, such as tungsten, can be used for the conductive layer 110. By using a conductive material with high conductivity, the conductivity of the conductive layer 110 can be improved, and the conductive layer 110 can function sufficiently as a wiring CAL.

[0531] The conductive layer 115 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion, and is used in a single layer or a stacked layer. For example, titanium nitride or ITSO may be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride and a second titanium nitride is stacked on the tungsten may be used. With such a structure, when an oxide is used for the insulating layer 130, the insulating layer 130 can suppress oxidation of the conductive layer 115. Furthermore, when an oxide is used for the insulating layer 180, the insulating layer 180 can suppress oxidation of the conductive layer 115.

[0532] The insulating layer 130 is provided so as to be in contact with the top surface and side surfaces of the conductive layer 115. That is, the insulating layer 130 preferably has a structure that covers the side end portions of the conductive layer 110. This can prevent a short circuit between the conductive layer 115 and the conductive layer 220_1.

[0533] Furthermore, a structure may be adopted in which the side edges of the insulating layer 130 and the conductive layer 115 coincide or substantially coincide with each other. With such a structure, the insulating layer 130 and the conductive layer 115 can be formed using the same mask, which can simplify the manufacturing process of the memory device.

[0534] It is preferable to use a high-k material for the insulating layer 130. By using a high-k material for the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitor 100 can be sufficiently ensured.

[0535] The insulating layer 130 is preferably formed by stacking insulating layers made of a high-k material, and preferably by stacking a high-k material and a material having a higher dielectric strength than the high-k material. For example, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By stacking insulating layers with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0536] Furthermore, a material that can have ferroelectricity may be used as the insulating layer 130. For details of the material that can have ferroelectricity, the description in the first embodiment can also be referred to.

[0537] Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even when they are as thin as a few nanometers, and are therefore preferred as the insulating layer 130. The film thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). Furthermore, for example, the film thickness is preferably 8 nm to 12 nm. By using a ferroelectric layer that can be thinned, the capacitor element 100 can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device.

[0538] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 130. For example, when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２ Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ or less than 1000 nm ２ Even if the thickness is less than 100 Å, the ferroelectric layer may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor element 100 can be reduced.

[0539] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitor element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitor element 100, the memory device described in this embodiment functions as a ferroelectric memory.

[0540] The conductive layer 220_1 is provided in contact with a part of the upper surface of the insulating layer 130. The side end of the conductive layer 220_1 is preferably located inside the side end of the conductive layer 115 in both the X direction and the Y direction. Note that in a structure in which the insulating layer 130 covers the side end of the conductive layer 115, the side end of the conductive layer 220_1 may be located outside the side end of the conductive layer 115.

[0541] Since the insulating layer 180 functions as an interlayer film, it is preferable that the insulating layer 180 has a low relative dielectric constant. By using a material with a low relative dielectric constant as the interlayer film, the parasitic capacitance occurring between wirings can be reduced.

[0542] 36B and 36C, the insulating layer 180 is shown as a single layer, but the present invention is not limited to this. The insulating layer 180 may have a laminated structure of two or more layers.

[0543] FIG. 37A shows an example in which the conductive layer 115 has a region 101 with rounded corners within a recess in the conductive layer 110. This allows for more suppression of electric field concentration in the insulating layer 130 near the region 101 than when the region 101 has a corner (right angle or acute angle) in a cross-sectional view. Furthermore, the end 103 of the conductive layer 115 is located at a lower height from the reference plane than the top surface of the insulating layer 180. This allows for more suppression of electric field concentration in the insulating layer 130 near the end 103 than when the end 103 is located on the insulating layer 180. As described above, suppressing electric field concentration in the insulating layer 130 prevents dielectric breakdown of the insulating layer 130, providing a highly reliable memory device. The reference plane can be the top surface of the substrate, the top surface of the insulating layer 140, or the like.

[0544] 37B is a diagram showing an example in which end 103 shown in FIG. 37A is located on insulating layer 180. In the example shown in FIG. 37B, insulating layer 180 has a curved region 102 extending from the top surface to the side surface of opening 190. Also, in the example shown in FIG. 37B, end 103 has a tapered shape. By having region 102 have a curved portion and end 103 have a tapered shape, even when end 103 is located on insulating layer 180, electric field concentration in insulating layer 130 near region 102 and near end 103 can be suppressed. This suppresses dielectric breakdown of insulating layer 130, making it possible to provide a highly reliable memory device.

[0545] 37C is a d...

Claims

an oxide semiconductor layer, a first insulating layer, a conductive layer having a portion overlapping with the oxide semiconductor layer with the first insulating layer sandwiched therebetween, and a second insulating layer having a portion overlapping with the first insulating layer with the oxide semiconductor layer sandwiched therebetween; the oxide semiconductor layer contains indium, The semiconductor device, wherein the second insulating layer has a thermal expansion coefficient smaller than that of the oxide semiconductor layer. 　 In claim 1, the first insulating layer has a function of capturing oxygen and hydrogen, The second insulating layer has a region containing excess oxygen. 　 In claim 1, the first insulating layer includes a hafnium oxide film; The semiconductor device, wherein the second insulating layer includes a silicon oxide film. 　 an oxide semiconductor layer; an oxide layer in contact with the oxide semiconductor layer; an insulating layer having a portion overlapping with the oxide layer with the oxide semiconductor layer sandwiched therebetween; and a conductive layer having a portion overlapping with the oxide semiconductor layer with the insulating layer sandwiched therebetween; the oxide semiconductor layer contains indium, the oxide semiconductor layer has first crystal grains, the oxide layer has at least one element capable of becoming a trivalent cation, the oxide layer has second crystal grains; the first crystal grains and the second crystal grains each have a cubic crystal structure; A semiconductor device, wherein the crystal orientation of the first crystal grains and the crystal orientation of the second crystal grains are the same or approximately the same. 　 In claim 4, The semiconductor device, wherein the oxide layer contains yttrium and zirconium. 　 In claim 5, The semiconductor device, wherein the oxide layer has a yttrium content of 2 atomic % or more and 15 atomic % or less. 　 an oxide semiconductor layer; an oxide layer in contact with the oxide semiconductor layer; an insulating layer having a portion overlapping with the oxide layer with the oxide semiconductor layer sandwiched therebetween; and a conductive layer having a portion overlapping with the oxide semiconductor layer with the insulating layer sandwiched therebetween; the oxide semiconductor layer contains indium, the oxide semiconductor layer has first crystal grains, the oxide layer comprises indium, gallium, and zinc; the oxide layer has second crystal grains; the first crystal grains have a cubic crystal structure; the second crystal grains have a hexagonal or trigonal crystal structure; the c-axis of the second crystal grain is perpendicular or approximately perpendicular to the surface or the surface on which the oxide layer is formed; The semiconductor device, wherein the crystal orientation of the first crystal grains with respect to a surface of the oxide semiconductor layer or a surface on which the oxide semiconductor layer is formed is <111>. 　 In claim 7, The oxide layer has a composition of In:Ga:Zn=1:1:1 (atomic ratio) or a composition thereabout, or a composition of In:Ga:Zn=1:3:2 (atomic ratio) or a composition thereabout. 　 In any one of claims 4 to 8, The insulating layer has a layered structure in which a hafnium oxide film, a silicon oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer side. 　 an oxide semiconductor layer; an oxide layer in contact with the oxide semiconductor layer; an insulating layer having a portion overlapping with the oxide layer with the oxide semiconductor layer sandwiched therebetween; a first conductive layer having a portion overlapping with the oxide semiconductor layer with the insulating layer sandwiched therebetween; and a second conductive layer in contact with the oxide layer; the oxide semiconductor layer contains indium, the oxide semiconductor layer has first crystal grains, the oxide layer comprises zirconium; the second conductive layer comprises indium, tin, and oxygen; the second conductive layer has second crystal grains; The semiconductor device, wherein the first crystal grains and the second crystal grains each have a cubic crystal structure. 　 In claim 10, A semiconductor device, wherein the crystal orientation of the first crystal grains and the crystal orientation of the second crystal grains are the same or approximately the same.

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