Semiconductor device

Abstract

Provided is a novel semiconductor device. According to the present invention, a first terminal of a first transistor is connected to a first terminal of a second transistor, a first terminal of a fourth transistor, and a first terminal of a first capacitive element. A gate of the second transistor is connected to a first terminal of a third transistor and a second terminal of the first capacitive element. The first transistor has a function for controlling a current amount supplied to a light-emitting element in response to an image signal, and the second transistor has a function for controlling the emission or non-emission of light of the light-emitting element.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. More specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, projection devices, electro-optical devices, light-receiving devices, detection devices, power supply devices, communication devices, information processing devices, arithmetic units, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, electronic devices, systems including these devices, and driving methods or manufacturing methods thereof.

[0003] Display devices are used in a variety of applications. Examples of applications for large display devices include home television devices and PIDs (Public Information Displays) for digital signage. Examples of applications for small display devices include mobile information terminals such as smartphones and tablet devices, and wearable devices such as devices for VR (Virtual Reality) and AR (Augmented Reality). Furthermore, by providing display devices with functions other than display, the display devices are being made more highly functional and have higher added value. For example, display devices with touch panel functions have been developed.

[0004] Furthermore, pixels of a display device use light-emitting elements such as light-emitting diodes, and various pixel circuits (circuits that control the light-emitting intensity of the light-emitting elements) have been proposed to improve the performance of the display device. For example, Patent Document 1 discloses a pixel circuit that can correct variations in the threshold voltage of a drive transistor (a transistor that controls the amount of current supplied to the light-emitting element in response to an image signal).

[0005] JP 2012-14136 A

[0006] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0007] An object of one embodiment of the present invention is to provide a highly reliable semiconductor device or a display device including the semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device capable of increasing emission luminance or a display device including the semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device capable of stabilizing emission luminance or a display device including the semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device capable of reducing power consumption or a display device including the semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device capable of increasing resolution or a display device including the semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device capable of increasing operation speed or a display device including the semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device capable of improving display quality or a display device including the semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device capable of improving performance of a display device or a display device including the semiconductor device. Another object of one embodiment of the present invention is to provide a novel semiconductor device or a display device including the semiconductor device.

[0008] The above-mentioned problem does not preclude the existence of other problems. A person skilled in the art can naturally derive other problems from the description in this specification, drawings, claims, etc., and can extract other problems from the description in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily solve all of these problems (the above-mentioned problem and other problems).

[0009] (1) One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a light-emitting element, in which a first terminal of the first transistor is electrically connected to a first terminal of the second transistor, a first terminal of the fourth transistor, and a first terminal of the first capacitor, and a gate of the second transistor is electrically connected to a first terminal of the third transistor and a second terminal of the first capacitor, in which the first transistor has a function of controlling an amount of current supplied to the light-emitting element in response to an image signal, and the second transistor has a function of controlling whether the light-emitting element emits light or not.

[0010] (2) In the above (1), the channel length of each of the second to fourth transistors may be smaller than the channel length of the first transistor.

[0011] (3) In the above (1), the area where the first electrode having a region that functions as the first terminal of the first capacitance element and the second electrode having a region that functions as the second terminal of the first capacitance element overlap may be larger than the area of ​​the channel formation region of the second transistor.

[0012] (4) In any one of (1) to (3), a first circuit may be provided, and the first circuit may have a function of applying a potential corresponding to an image signal to a gate of the first transistor.

[0013] (5) In any one of (1) to (3), the semiconductor device further includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a second capacitance element, wherein the gate of the first transistor is electrically connected to a first terminal of the seventh transistor, a first terminal of the eighth transistor, and a first terminal of the second capacitance element, the first terminal of the first transistor is electrically connected to a second terminal of the seventh transistor, the second terminal of the first transistor is electrically connected to a first terminal of the fifth transistor and a first terminal of the sixth transistor, the second terminal of the second transistor is electrically connected to a first terminal of the light-emitting element, the second terminal of the sixth transistor is electrically connected to a first wiring, and the second terminal of the second capacitance element is electrically connected to the first wiring. , the second terminal of the third transistor is electrically connected to the second wiring, the gate of the third transistor is electrically connected to the third wiring, the second terminal of the fourth transistor is electrically connected to the fourth wiring, the gate of the fourth transistor is electrically connected to the fifth wiring, the second terminal of the light-emitting element is electrically connected to the sixth wiring, the second terminal of the fifth transistor is electrically connected to a seventh wiring to which an image signal is applied, the gate of the fifth transistor is electrically connected to the eighth wiring, the gate of the sixth transistor is electrically connected to the ninth wiring, the gate of the seventh transistor is electrically connected to the tenth wiring, the second terminal of the eighth transistor is electrically connected to the eleventh wiring, and the gate of the eighth transistor is electrically connected to the twelfth wiring.

[0014] (6) In the above (5), each of the first to eighth transistors may be a p-channel transistor.

[0015] (7) In the above (5), each of the first to sixth transistors may be a p-channel transistor, and each of the seventh and eighth transistors may be an n-channel transistor.

[0016] (8) In the above (5), each of the first to sixth transistors may include silicon in a channel formation region, and each of the seventh and eighth transistors may include an oxide semiconductor in a channel formation region.

[0017] (9) In the above (8), the oxide semiconductor may contain indium oxide.

[0018] (10) In the above (5), the light-emitting element may be a light-emitting diode, the first terminal of the light-emitting element may be an anode of the light-emitting diode, and the second terminal of the light-emitting element may be a cathode of the light-emitting diode.

[0019] (11) In any one of (1) to (3), the semiconductor device further includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a second capacitance element, wherein the gate of the first transistor is electrically connected to a first terminal of the seventh transistor and a first terminal of the second capacitance element, the first terminal of the first transistor is electrically connected to a second terminal of the seventh transistor, the second terminal of the first transistor is electrically connected to a first terminal of the fifth transistor and a first terminal of the sixth transistor, the second terminal of the sixth transistor is electrically connected to a first terminal of the light-emitting element, a second terminal of the second capacitance element, and a first terminal of the eighth transistor, the second terminal of the second transistor is electrically connected to a first wiring, and the third transistor a second terminal of the third transistor electrically connected to the third wiring, a second terminal of the fourth transistor electrically connected to the fourth wiring, a gate of the fourth transistor electrically connected to the fifth wiring, a second terminal of the light-emitting element electrically connected to the sixth wiring, a second terminal of the fifth transistor electrically connected to a seventh wiring to which an image signal is applied, a gate of the fifth transistor electrically connected to an eighth wiring, a gate of the sixth transistor electrically connected to a ninth wiring, a gate of the seventh transistor electrically connected to a tenth wiring, a second terminal of the eighth transistor electrically connected to an eleventh wiring, and a gate of the eighth transistor electrically connected to a twelfth wiring.

[0020] (12) In the above (11), each of the first to eighth transistors may be an n-channel transistor.

[0021] (13) In the above (11), the seventh transistor may include an oxide semiconductor in a channel formation region.

[0022] (14) In the above (13), the oxide semiconductor may contain indium oxide.

[0023] (15) In the above (11), the first transistor may include an oxide semiconductor in a channel formation region.

[0024] (16) In the above (15), the oxide semiconductor may contain indium oxide.

[0025] (17) In the above (11), the light-emitting element may be a light-emitting diode, the first terminal of the light-emitting element may be an anode of the light-emitting diode, and the second terminal of the light-emitting element may be a cathode of the light-emitting diode.

[0026] (18) One aspect of the present invention includes a first pixel circuit, a second pixel circuit, a first light-emitting element, a second light-emitting element, and a first transistor. The first pixel circuit includes a second transistor, a third transistor, and a first capacitance element. The second pixel circuit includes a fourth transistor, a fifth transistor, and a second capacitance element. A first terminal of the second transistor is electrically connected to a first terminal of the third transistor and a first terminal of the first capacitance element. A first terminal of the fourth transistor is electrically connected to a first terminal of the fifth transistor and a first terminal of the second capacitance element. a gate of the fifth transistor electrically connected to a gate of the fifth transistor, a first terminal of the first transistor, a second terminal of the first capacitance element, and a second terminal of the second capacitance element; the second transistor has a function of controlling the amount of current supplied to the first light-emitting element in response to a first image signal; the third transistor has a function of controlling whether the first light-emitting element emits light; the fourth transistor has a function of controlling the amount of current supplied to the second light-emitting element in response to a second image signal; and the fifth transistor has a function of controlling whether the second light-emitting element emits light.

[0027] (19) In the above (18), the first pixel circuit may include a sixth transistor, the second pixel circuit may include a seventh transistor, and a first terminal of the sixth transistor may be electrically connected to a first terminal of the third transistor.

[0028] (20) In the above (18) or (19), the first transistor may include an oxide semiconductor in a channel formation region.

[0029] (21) In the above (20), the oxide semiconductor may contain indium oxide.

[0030] According to one embodiment of the present invention, a highly reliable semiconductor device or a display device including the semiconductor device can be provided. According to another embodiment of the present invention, a semiconductor device capable of increasing emission luminance or a display device including the semiconductor device can be provided. According to another embodiment of the present invention, a semiconductor device capable of stabilizing emission luminance or a display device including the semiconductor device can be provided. According to another embodiment of the present invention, a semiconductor device capable of reducing power consumption or a display device including the semiconductor device can be provided. According to another embodiment of the present invention, a semiconductor device capable of increasing resolution or a display device including the semiconductor device can be provided. According to another embodiment of the present invention, a semiconductor device capable of increasing operation speed or a display device including the semiconductor device can be provided. According to another embodiment of the present invention, a semiconductor device capable of improving display quality or a display device including the semiconductor device can be provided. According to another embodiment of the present invention, a semiconductor device capable of improving performance of a display device or a display device including the semiconductor device can be provided. According to another embodiment of the present invention, a novel semiconductor device or a display device including the semiconductor device can be provided.

[0031] Note that the above effects do not preclude the existence of other effects. A person skilled in the art can naturally derive other effects from the description in this specification, drawings, claims, etc., and can extract other effects from the description in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily have all of these effects (the above effects and other effects).

[0032] FIGS. 1A and 1B are circuit diagrams illustrating an example of the configuration of a semiconductor device. FIGS. 2A and 2B are circuit diagrams illustrating an example of the configuration of a semiconductor device. FIGS. 3A and 3B are circuit diagrams illustrating an example of the configuration of a semiconductor device. FIG. 4 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 5 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 6 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 7 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 8 is a timing chart illustrating an example of the operation of a semiconductor device. FIG. 9 is a circuit diagram illustrating an example of the operation of a semiconductor device. FIG. 10 is a circuit diagram illustrating an example of the operation of a semiconductor device. FIG. 11 is a circuit diagram illustrating an example of the operation of a semiconductor device. FIG. 12 is a circuit diagram illustrating an example of the operation of a semiconductor device. FIG. 13 is a circuit diagram illustrating an example of the operation of a semiconductor device. FIG. 14 is a circuit diagram illustrating an example of the operation of a semiconductor device. FIG. 15 is a circuit diagram illustrating an example of the operation of a semiconductor device. FIG. 16 is a circuit diagram illustrating an example of the operation of a semiconductor device. FIG. 17 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 18 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 19 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 20 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 21 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 22 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 23 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 24 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 25 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 26 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 27 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 28 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 29 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 30 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 31 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 32 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 33 is a circuit diagram illustrating a configuration example of a semiconductor device. FIGS. 34A and 34B are block diagrams illustrating configuration examples of a display device. FIGS. 35A to 35C and 35E are circuit diagrams illustrating configuration examples of semiconductor devices.FIG. 35D is a timing chart illustrating an example of operation of the semiconductor device. FIGS. 36A to 36E are circuit diagrams illustrating an example of the configuration of the semiconductor device. FIGS. 37A and 37B are circuit diagrams illustrating an example of the configuration of the semiconductor device. FIGS. 38A and 38B are circuit diagrams illustrating an example of the configuration of the semiconductor device. FIGS. 39A and 39B are circuit diagrams illustrating an example of the configuration of the semiconductor device. FIG. 40 is a circuit diagram illustrating an example of the configuration of the semiconductor device. FIG. 41 is a circuit diagram illustrating an example of the configuration of the semiconductor device. FIG. 42 is a timing chart illustrating an example of operation of the semiconductor device. FIG. 43 is a circuit diagram illustrating an example of operation of the semiconductor device. FIG. 44 is a circuit diagram illustrating an example of operation of the semiconductor device. FIG. 45 is a circuit diagram illustrating an example of operation of the semiconductor device. FIG. 46 is a circuit diagram illustrating an example of operation of the semiconductor device. FIG. 47 is a circuit diagram illustrating an example of operation of the semiconductor device. FIG. 48 is a circuit diagram illustrating an example of operation of the semiconductor device. FIG. 49 is a circuit diagram illustrating an example of operation of the semiconductor device. FIG. 50 is a circuit diagram illustrating an example of operation of the semiconductor device. FIG. 51 is a circuit diagram illustrating an example of the configuration of the semiconductor device. FIG. 52 is a circuit diagram illustrating an example of the configuration of the semiconductor device. FIG. 53 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 54 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 55 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 56 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 57 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 58 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 59 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 60 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 61 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 62 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 63 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 64 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 65 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 66 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 67 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 68 is a circuit diagram illustrating an example of the configuration of a semiconductor device. FIG. 69 is a circuit diagram illustrating an example of the configuration of a semiconductor device.FIG. 70A is a top view illustrating a structural example of a transistor. FIGS. 70B and 70C are cross-sectional views illustrating a structural example of a transistor. FIG. 71A is a top view illustrating a structural example of a transistor. FIGS. 71B and 71C are cross-sectional views illustrating a structural example of a transistor. FIG. 72A is a top view illustrating a structural example of a transistor. FIG. 72B is a cross-sectional view illustrating a structural example of a transistor. FIG. 73A is a top view illustrating a structural example of a transistor. FIGS. 73B and 73C are cross-sectional views illustrating a structural example of a transistor. FIG. 74A is a top view illustrating a structural example of a transistor. FIGS. 74B and 74C are cross-sectional views illustrating a structural example of a transistor. FIGS. 75A to 75D are cross-sectional views illustrating an example of a method for forming a metal oxide film. FIGS. 76A to 76D are cross-sectional views illustrating an example of a method for forming a metal oxide film. FIG. 77 is a top view illustrating a structural example of a semiconductor device. FIGS. 78A and 78B are cross-sectional views illustrating a structural example of a semiconductor device. FIGS. 79A to 79C are top views illustrating a structural example of a semiconductor device. 80A to 80C are top views illustrating an example of the configuration of a semiconductor device. FIG. 81A is a perspective view illustrating an example of the configuration of a display device. FIGS. 81B to 81F are top views illustrating an example of a pixel arrangement. FIG. 82 is a cross-sectional view illustrating an example of the configuration of a display device. FIGS. 83A and 83B are cross-sectional views illustrating an example of the configuration of a display device. FIGS. 84A and 84B are cross-sectional views illustrating an example of the configuration of a display device. FIG. 85 is a perspective view illustrating an example of the configuration of a display device. FIG. 86 is a cross-sectional view illustrating an example of the configuration of a display device. FIGS. 87A to 87D are views illustrating an example of an electronic device. FIGS. 88A to 88F are views illustrating an example of an electronic device. FIGS. 89A to 89G are views illustrating an example of an electronic device. FIGS. 90A1 to 90A7 and 90B1 to 90B6 are views illustrating electrical connections. FIGS. 91A and 91B are views illustrating the carrier concentration dependence of Hall mobility. FIG. 91C is a cross-sectional view illustrating an indium oxide film.

[0033] In this specification, a semiconductor device refers to a device that utilizes semiconductor characteristics, such as a circuit including a semiconductor element (e.g., a transistor or a diode), or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor characteristics. Examples of semiconductor devices include electronic circuits including semiconductor elements, chips equipped with electronic circuits, electronic components with chips housed in packages, and electronic devices equipped with electronic components. Furthermore, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, projection devices, electro-optical devices, light-receiving devices, detection devices, power supply devices, communication devices, information processing devices, arithmetic units, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, and electronic devices may themselves be semiconductor devices and may also include semiconductor devices.

[0034] The following description of the embodiments will be given with reference to the drawings. However, the embodiments can be implemented in many different forms. Therefore, it will be readily understood by those skilled in the art that various changes can be made to the embodiments and their details without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0035] In this specification and the like, the configuration shown in each embodiment can be appropriately combined with the configuration shown in another embodiment to form one aspect of the present invention. Furthermore, when multiple configurations are shown in one embodiment, these configurations can be appropriately combined to form one aspect of the present invention.

[0036] In addition, in the drawings illustrating the embodiments, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions in the configuration of the invention, thereby omitting repeated description thereof. Furthermore, when the drawings indicate similar functions, for example, the same hatching patterns may be used and no particular reference numerals may be used. Furthermore, in the drawings, for example, in perspective views or top views (also called "plan views"), the illustration of some components may be omitted for ease of understanding. Furthermore, in the drawings, for example, the illustration of some hidden lines may be omitted. Furthermore, in the drawings, for example, the illustration of hatching patterns may be omitted.

[0037] In addition, in the drawings, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not limited to, for example, their size or aspect ratio. The drawings are schematic illustrations to facilitate understanding of the present invention and are not limited to, for example, the shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, layers or resist masks may be unintentionally thinned by processes such as etching. However, these may not be reflected in the drawings to facilitate understanding. Furthermore, for example, in actual circuit operation, variations in voltage or current may occur due to noise or timing errors. However, these may not be reflected in the drawings to facilitate understanding.

[0038] Furthermore, in this specification and drawings, components may be classified by function and shown as independent elements. However, it may be difficult to separate components by function, and one element may be involved in multiple functions, or one function may be involved across multiple elements. Therefore, the elements shown in this specification and drawings may not be limited to the descriptions therein, and may be rephrased appropriately.

[0039] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "A", "b", "_1", "[n]", or "[m, n]". Furthermore, when explaining matters common to multiple elements accompanied by identifying symbols, or when it is not necessary to distinguish between them, the elements may be described without the identifying symbol.

[0040] In this specification and the like, the "conductive state" or "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor are considered to be electrically short-circuited, or a state in which a current can flow between the source and drain (also referred to as a state in which a current can flow). For example, a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage, may be referred to as the "conductive state" or "on state." In addition, the "non-conductive state," "cutoff state," or "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically cut off. For example, a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage, may be referred to as the "non-conductive state," "cutoff state," or "off state."

[0041] In this specification and the like, the voltage between the gate and the source (gate-source) (based on the source potential unless otherwise specified) may be referred to as the "gate voltage," the voltage between the drain and the source (drain-source) (based on the source potential unless otherwise specified) may be referred to as the "drain voltage," and the voltage between the backgate and the source (backgate-source) (based on the source potential unless otherwise specified) may be referred to as the "backgate voltage." Furthermore, the current flowing between the drain and the source (positive in the direction from the drain to the source unless otherwise specified) may be referred to as the "drain current." Note that, in an n-channel transistor, terms such as "high gate voltage," "high drain voltage," and "high backgate voltage" can be interchangeable with terms such as "low gate voltage," "low drain voltage," and "low backgate voltage" in a p-channel transistor, as appropriate. Furthermore, in an n-channel transistor, descriptions such as a low gate voltage, a low drain voltage, and a low back gate voltage can be interchanged with descriptions such as a high gate voltage, a high drain voltage, and a high back gate voltage in a p-channel transistor, as appropriate.

[0042] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification and the like, the off-state current and the current flowing between the gate and the source and drain (also referred to as gate leakage current) may be collectively referred to as leakage current.

[0043] In this specification and the like, one of the source or drain (also referred to as two input / output terminals) of a transistor may be referred to as a first terminal, and the other of the source or drain of the transistor may be referred to as a second terminal. That is, a transistor has at least a gate (also referred to as a gate terminal), a first terminal, and a second terminal. One terminal of a capacitor (also referred to as one of a pair of terminals) may be referred to as a first terminal, and the other terminal of the capacitor (also referred to as the other of the pair of terminals) may be referred to as a second terminal. One terminal of a display element may be referred to as a first terminal, and the other terminal of the display element may be referred to as a second terminal. One terminal of a liquid crystal element may be referred to as a first terminal, and the other terminal of the liquid crystal element may be referred to as a second terminal. One terminal of a light-emitting element may be referred to as a first terminal, and the other terminal of the light-emitting element may be referred to as a second terminal. One terminal of a light-receiving element may be referred to as a first terminal, and the other terminal of the light-receiving element may be referred to as a second terminal. In addition, one of the anode or cathode of the diode (also referred to as one of a pair of terminals) may be referred to as a first terminal, and the other of the anode or cathode of the diode (also referred to as the other of the pair of terminals) may be referred to as a second terminal.

[0044] Embodiment 1 A semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. At least part of the semiconductor device according to one embodiment of the present invention can be used for a display device or the like.

[0045] <Structural Example 1 of Semiconductor Device> Each of FIGS. 1A, 1B, 2A, and 2B is a circuit diagram illustrating a semiconductor device 100 of one embodiment of the present invention.

[0046] 1A and 1B, the semiconductor device 100 includes a pixel circuit 101 and a light-emitting element LD. The pixel circuit 101 includes at least a transistor M11 and a light-emitting control unit 110. The light-emitting control unit 110 includes a transistor M12, a transistor M13, and a transistor M14. The light-emitting control unit 110 may further include a capacitive element C11. The semiconductor device 100 can also be referred to as a pixel.

[0047] One of the source or drain of the transistor M11 is connected to one of the source or drain of the transistor M12, one of the source or drain of the transistor M14, and one terminal of the capacitor C11. The gate of the transistor M12 is connected to one of the source or drain of the transistor M13 and the other terminal of the capacitor C11. The other of the source or drain of the transistor M13 is connected to a wiring EM. The gate of the transistor M13 is connected to a wiring VL1. The other of the source or drain of the transistor M14 is connected to a wiring VL2. The gate of the transistor M14 is connected to a wiring GP. Note that the capacitor C11 may be a parasitic capacitance between the gate of the transistor M12 and one of the source or drain.

[0048] A wiring connected to the gate of transistor M11 or the like may be referred to as node ND1. A wiring connected to one of the source or drain of transistor M11 and one of the source or drain of transistor M12 may be referred to as node ND2. A wiring connected to the other of the source or drain of transistor M11 may be referred to as node ND3. A wiring connected to the gate of transistor M12 or the like may be referred to as node ND4. A wiring connected to the other of the source or drain of transistor M12 may be referred to as node ND5. Note that the terms "node" and "wiring" may be interchangeable.

[0049] The light-emitting element LD, the transistor M11, and the transistor M12 are provided in a current path between the wiring ANO and the wiring CATH. That is, the current flowing through the light-emitting element LD also flows through the channel formation region of the transistor M11 and the channel formation region of the transistor M12. Note that, in addition to the transistor M11 and the transistor M12, another transistor may be provided in the current path.

[0050] The wirings EM and GP each function as a signal line. The wirings EM and GP each function as a signal line. For example, the wirings EM and GP each function as a signal line. The wirings ANO, CATH, VL1, and VL2 each function as a power supply line. For example, the wirings ANO, CATH, VL1, and VL2 each function as a power supply line. At least one of the wirings ANO, CATH, VL1, and VL2 may also function as a signal line.

[0051] The light-emitting element LD emits light with an intensity corresponding to the amount of current flowing through the light-emitting element LD. The light-emitting element LD can be, for example, a self-luminous electroluminescent element (particularly, an injection-type electroluminescent element) such as a light-emitting diode (LED). The LED can be, for example, an LED using an inorganic material as a light-emitting substance, or an LED using an organic material as a light-emitting substance (also called an OLED (organic LED)). The LED using an inorganic material as a light-emitting substance can be, for example, a mini LED, a micro LED, or a QLED (quantum-dot LED).

[0052] The transistor M11 has a function of controlling the amount of current supplied to the light-emitting element LD in response to an image signal provided from a circuit (e.g., a drive circuit such as a source driver) external to the semiconductor device 100. A potential corresponding to the image signal is applied to the gate of the transistor M11. Therefore, a gate voltage corresponding to the image signal is applied to the transistor M11, and a drain current based on the gate voltage flows, and the drain current flows to the light-emitting element LD. In this specification and the like, a transistor having a function similar to that of the transistor M11 may be referred to as a drive transistor. Although not shown, the gate of the transistor M11 may be connected to one terminal of a capacitance element having a function of holding the gate voltage of the transistor M11.

[0053] The transistor M12 functions as a switch that controls whether or not to cut off the current flowing through the light-emitting element LD. In other words, it can be said that the transistor M12 has a function of controlling whether or not the light-emitting element LD emits light. In this specification and the like, a transistor having a function similar to that of the transistor M12 may be referred to as a light-emission control transistor.

[0054] In the light-emission control unit 110, a circuit formed by the transistor M12, the transistor M13, and the capacitance element C11 functions as a bootstrap circuit. The transistor M13 functions as a switch that controls whether or not a potential is supplied to the gate of the transistor M12, and the capacitance element C11 functions to hold the gate voltage of the transistor M12. In other words, it can be said that the transistor M13 functions to control the gate potential of the transistor M12. In this specification, a transistor that functions like the transistor M13 is sometimes referred to as a bootstrap transistor, and a capacitance element that functions like the capacitance element C11 is sometimes referred to as a bootstrap capacitance.

[0055] In the light-emission control unit 110, a circuit formed by the transistors M12 and M14 functions as a precharge circuit. The transistor M14 functions as a switch that controls whether a potential is supplied from the wiring VL2 to one of the source and drain of the transistor M12. In other words, the transistor M14 can be said to have a function of controlling the potential of one of the source and drain of the transistor M12. In this specification and the like, a transistor having a function similar to that of the transistor M14 may be referred to as a precharge transistor.

[0056] 1A, for example, the other of the source or drain of transistor M11 (corresponding to node ND3) is connected to wiring ANO without passing through the source and drain of another transistor (this also means that the other of the source or drain of transistor M11 is directly connected to wiring ANO), or is connected to wiring ANO via the source and drain of another transistor (this also means that the other of the source or drain of transistor M11 is indirectly connected to wiring ANO). The other of the source or drain of transistor M12 (corresponding to node ND5) is connected to one terminal of light-emitting element LD (e.g., the anode of a light-emitting diode). The other terminal of light-emitting element LD (e.g., the cathode of a light-emitting diode) is connected to wiring CATH.

[0057] 1B , for example, the other of the source or drain of transistor M11 (corresponding to node ND3) is connected to the other terminal of light-emitting element LD (e.g., the cathode of a light-emitting diode) without passing through the source and drain of another transistor (this also means that the other of the source or drain of transistor M11 is directly connected to the other terminal of light-emitting element LD), or is connected to the other terminal of light-emitting element LD via the source and drain of another transistor (this also means that the other of the source or drain of transistor M11 is indirectly connected to the other terminal of light-emitting element LD). One terminal of light-emitting element LD (e.g., the anode of a light-emitting diode) is connected to wiring ANO. The other of the source or drain of transistor M12 (corresponding to node ND5) is connected to wiring CATH.

[0058] In the semiconductor device 100 shown in each of FIGS. 1A and 1B, p-channel transistors can be used for each of the transistors (such as the transistors M11 to M14).

[0059] 1A and 1B, an n-channel transistor may be used for at least one of the transistors. In this case, in the description of the semiconductor device 100, the descriptions regarding one terminal (e.g., the anode of the light-emitting diode) and the other terminal (e.g., the cathode of the light-emitting diode) of the light-emitting element LD may be interchanged as appropriate. Furthermore, descriptions regarding the positive / negative relationship of voltage and the magnitude relationship of potential may be interchanged as appropriate. For example, "high potential" may be interchanged as "low potential" and "low potential" as "high potential". Furthermore, for example, "increase potential" may be interchanged as "decrease potential" and "decrease potential" as "increase potential".

[0060] In the semiconductor device 100, the transistor M11 functions as a drive transistor that controls the amount of current flowing through the light-emitting element LD, and therefore preferably has high saturation (small change in drain current relative to drain voltage in the transistor's saturation region). To increase the saturation of the transistor M11, for example, it is preferable to increase the channel length of the transistor M11. Increasing the saturation of the transistor M11 allows a stable current to flow through the light-emitting element LD, thereby stabilizing the light-emitting intensity.

[0061] Furthermore, since the transistor M12 is provided in a current path including the light-emitting element LD, it is preferable that the transistor M12 has a large on-state current (also referred to as a small on-state resistance). In order to increase the on-state current of the transistor M12, for example, it is preferable to reduce the channel length of the transistor M12.

[0062] Since each of the transistors M12, M13, and M14 functions as a switch, it is preferable that the gate capacitance be small in order to improve the operating speed of the display device, and it is preferable that the area of ​​the channel formation region (corresponding to the multiplication of the channel length and the channel width) be small in order to improve the definition of the display device.

[0063] Based on these technical concepts, for example, the channel length of each of transistors M12, M13, and M14 may be smaller than the channel length of transistor M11. Furthermore, for example, the channel width of each of transistors M12, M13, and M14 may be smaller than the channel width of transistor M11. Furthermore, for example, the area of ​​the channel formation region of each of transistors M12, M13, and M14 may be smaller than the area of ​​the channel formation region of transistor M11. Note that the channel length of each of transistors M12, M13, and M14 may be the minimum channel length determined by the minimum processing dimension in the manufacturing process. Furthermore, the channel width of each of transistors M12, M13, and M14 may be the minimum channel width determined by the minimum processing dimension in the manufacturing process.

[0064] In the semiconductor device 100, the capacitance element C11 has a function of holding the gate voltage of the transistor M12, and therefore, for example, the capacitance of the capacitance element C11 may be larger than the gate capacitance of the transistor M12. For example, the area where a pair of electrodes (corresponding to a conductive layer functioning as one terminal and a conductive layer functioning as the other terminal) of the capacitance element C11 overlap each other may be larger than the area of ​​the channel formation region of the transistor M12.

[0065] 2A and 2B, the semiconductor device 100 can further include a write control unit 102 in the pixel circuit 101. The write control unit 102 is connected to at least the wiring SL, the gate of the transistor M11 (corresponding to the node ND1), and the other of the source and the drain of the transistor M11 (corresponding to the node ND3).

[0066] The write control unit 102 has a function of applying a potential corresponding to an image signal provided from the line SL to the gate of the transistor M11. As a result, a gate voltage corresponding to the image signal is applied to the transistor M11. The line SL functions as a signal line. The line SL has a function of transmitting an image signal provided from, for example, a circuit (e.g., a driving circuit such as a source driver) provided outside the semiconductor device 100.

[0067] The pixel circuit 101 may have a function of correcting variations in the threshold voltage of the transistor M11 by including the write control unit 102. The pixel circuit 101 may also have a function of suppressing the influence of hysteresis of the transistor M11. This can improve the display quality of the display device.

[0068] In one aspect of the present invention, the semiconductor device 100 operates by first turning off the transistor M12 and applying a potential to the gate of the transistor M11 according to an image signal. This causes a gate voltage according to the image signal to be applied to the transistor M11. At this time, the write control unit 102 may perform an operation to correct variations in the threshold voltage of the transistor M11 and an operation to suppress the influence of hysteresis. Then, by turning on the transistor M12, a current based on the gate voltage of the transistor M11 flows through the light-emitting element LD, causing the light-emitting element LD to emit light with an intensity according to the current.

[0069] Here, just before the transistor M12 is switched from the off state to the on state, the potential of the node ND2 is the same as or close to the potential of the gate of the transistor M11. That is, the potential of the node ND2 is a potential corresponding to the image signal. At this time, by turning on the transistor M14, a predetermined potential can be applied to the node ND2 from the wiring VL2. This allows a stable gate voltage to be applied to the transistor M12 when the transistor M12 is turned on.

[0070] After that, by turning off the transistor M14, a current based on the gate voltage of the transistor M11 flows through the light-emitting element LD. At this time, the potential of the node ND2 changes depending on the voltage-current characteristics of the light-emitting element LD. At this time, by providing the transistor M13 and the capacitor C11, the potential of the node ND4 also changes in accordance with the change in the potential of the node ND2 due to the capacitive coupling of the capacitor C11. As a result, the gate voltage of the transistor M12 can be maintained after the transistor M12 is turned on.

[0071] This action makes it possible to stabilize the light emission intensity of the light emitting element LD during operation of the semiconductor device 100. This makes it possible to stabilize the light emission brightness of the display device.

[0072] Here, the potential applied to the node ND2 from the wiring VL2 via the transistor M14 is preferably higher than the potential of the node ND2 immediately before the transistor M12 is switched from the off state to the on state. That is, the potential applied to the node ND2 from the wiring VL2 is preferably higher than the potential corresponding to an image signal, for example, and may be the potential of the wiring ANO. This allows the gate voltage applied to the transistor M12 to be increased. In other words, even if the amplitude of the signal applied from the wiring EM (a signal that controls the on / off state of the transistor M12) is reduced, a sufficient gate voltage can be applied to turn on the transistor M12.

[0073] Therefore, even if the channel width of the transistor is reduced, a sufficient gate voltage can be applied to the transistor, thereby obtaining a sufficient on-state current. This reduces the area occupied by the transistor and improves the resolution of the display device. Furthermore, for example, by reducing the amplitude of a signal applied from the wiring EM, the voltage applied between the terminals of the transistor can be reduced. This prevents breakdown and degradation of the transistor and improves the reliability of the display device. In this case, for example, by reducing the voltage applied between the terminals of the transistor, short-channel effects such as drain-induced barrier lowering (DIBL) can be suppressed, thereby reducing the channel length of the transistor. This reduces the area occupied by the transistor and improves the resolution of the display device. Furthermore, for example, by reducing the amplitude of the signal applied from the wiring EM, the breakdown voltage required of the transistor can be reduced, which may eliminate the need for technology with high process costs. This reduces the manufacturing cost of the display device. In this case, for example, using a transistor with a high breakdown voltage may increase the area occupied by the transistor. However, by lowering the breakdown voltage required of the transistor, the increase in the area occupied by the transistor can be suppressed. Therefore, the resolution of the display device can be improved. Furthermore, for example, by reducing the amplitude of a signal provided from the wiring EM, the operating voltage of a circuit (e.g., a driver circuit such as a gate driver) provided outside the semiconductor device 100 can be reduced. Therefore, the power consumption of the display device can be reduced.

[0074] The semiconductor device 100 of one embodiment of the present invention can be used, for example, in a display device with high emission luminance. In the semiconductor device 100, for example, when an OLED is used as the light-emitting element LD, increasing the emission luminance of the display device increases the voltage applied to the OLED. Furthermore, in terms of improving the reliability of the OLED, for example, it is preferable to use a tandem OLED, which further increases the voltage applied to the OLED. In this case, for example, if the semiconductor device 100 does not include the transistor M13, the capacitor C11, and the transistor M14, the amplitude of the signal applied from the wiring EM needs to be increased to apply a sufficient gate voltage to the transistor M12. On the other hand, in the semiconductor device 100, by including the transistor M13, the capacitor C11, and the transistor M14, a sufficient gate voltage can be applied to the transistor M12 and the gate voltage can be maintained even if the amplitude of the signal applied from the wiring EM is reduced.

[0075] Therefore, it can be said that the semiconductor device 100 is particularly preferable for use in a display device with high luminance. ２ Above, 3,000cd / m ２ Above, 5,000cd / m ２ Above, 10,000cd / m ２ or more than 15,000 cd / m ２ It is possible to emit light with the above luminance.

[0076] Here, display devices with high emission brightness are used, for example, in VR devices and AR devices. In VR devices and AR devices, for example, an optical system is used to enlarge the display of the display device, which may result in attenuation of light intensity due to the optical system. Furthermore, for example, black insertion driving (also known as duty driving or time-division driving) may be employed to suppress afterimages. Because this reduces the effective emission brightness, it is necessary to increase the emission brightness of the display device to obtain the desired emission brightness. Therefore, for example, the semiconductor device 100 is preferably used in a display device included in a device using an optical system. Furthermore, for example, the semiconductor device 100 is preferably used in a display device employing black insertion driving.

[0077] Therefore, a display device using semiconductor device 100, for example, employs black insertion driving, so that the non-emission period within one frame period is, for example, 5% to 20%, 20% to 40%, 40% to 60%, 60% to 80%, or 80% to 95%.

[0078] A specific configuration example and an operation example of the semiconductor device 100 will be described later, along with a specific configuration example of the pixel circuit 101. A configuration example of a display device using the semiconductor device 100 will also be described later.

[0079] In one embodiment of the present invention, a transistor including a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor in a channel formation region can be used as a transistor included in the semiconductor device 100. The semiconductor is not limited to a simple semiconductor whose main component is a single element (such as silicon or germanium), but can also be, for example, a compound semiconductor (such as silicon germanium or gallium arsenide), an oxide semiconductor, or the like.

[0080] For example, as a transistor constituting the semiconductor device 100, a transistor containing silicon in a channel formation region (Si transistor) may be used, a transistor containing an oxide semiconductor in a channel formation region (OS transistor) may be used, or both a Si transistor and an OS transistor may be used.

[0081] Furthermore, various types of transistors can be used as the transistors that constitute the semiconductor device 100. For example, MOS field effect transistors, junction field effect transistors, bipolar transistors, or the like can be used.

[0082] Transistors of various structures can be used as transistors constituting the semiconductor device 100. For example, transistors of various structures can be used, such as top-gate transistors (e.g., planar transistors and staggered transistors), bottom-gate transistors (e.g., inverted planar transistors and inverted staggered transistors), dual-gate transistors (structures in which gates are arranged on both sides (e.g., above and below) of a channel formation region), FIN transistors, TRI-GATE transistors, and GAA transistors (gate-all-around transistors). Furthermore, for example, vertical transistors (transistors whose channel length direction is vertical (also referred to as the height direction or the direction perpendicular to the formation surface)) can be used.

[0083] A structural example of a transistor that can be applied to the semiconductor device 100 will be described later in Embodiment 3. A structural example of a light-emitting element that can be applied to the semiconductor device 100 will be described later in Embodiment 6.

[0084] In one embodiment of the present invention, a transistor functioning as a switch has a function of controlling conduction or non-conduction between a connection destination of its source and a connection destination of its drain. For example, the transistor M12 has a function of controlling conduction or non-conduction between the node ND2 and one terminal of the light-emitting element LD or a function of controlling conduction or non-conduction between the node ND2 and a wiring CATH. For example, the transistor M13 has a function of controlling conduction or non-conduction between the wiring EM and a node ND4. For example, the transistor M14 has a function of controlling conduction or non-conduction between the wiring VL2 and the node ND2.

[0085] In one embodiment of the present invention, the on or off state of a transistor functioning as a switch is controlled by the potential of a node to which the gate is connected. For example, the on or off state of the transistor M12 is controlled by the potential of the node ND4. For example, the on or off state of the transistor M13 is controlled by the potential of the wiring VL1. For example, the on or off state of the transistor M14 is controlled by the potential of the wiring GP.

[0086] In one embodiment of the present invention, a transistor having a function as a switch supplies the potential of one of the terminals connected to the source or drain to the other terminal of the source or drain, or supplies the potential of the other terminal of the source or drain to the other terminal of the source or drain. In other words, the potential of the terminal connected to the one of the source or drain of the transistor is supplied to the other terminal of the source or drain of the transistor through a channel formation region of the transistor. Alternatively, the potential of the terminal connected to the other of the source or drain of the transistor is supplied to the other terminal of the source or drain of the transistor through a channel formation region of the transistor. For example, the transistor M12 supplies the potential of one terminal of the light-emitting element LD to the node ND2 or the potential of the wiring CATH to the node ND2. For example, the transistor M13 supplies the potential of the wiring EM to the node ND4. For example, the transistor M14 supplies the potential of the wiring VL2 to the node ND2. In this case, the supplied potentials may differ by the threshold voltage of the transistor.

[0087] [Another Configuration Example 1] Figure 3A is a circuit diagram illustrating a modified example of the semiconductor device 100 shown in Figure 2A. Figure 2A shows a configuration example of the semiconductor device 100 in which one of the source or drain of the transistor M14 is connected to one of the source or drain of the transistor M12 (corresponding to node ND2), but this is not limiting. For example, Figure 3A shows a configuration example of the semiconductor device 100 in which one of the source or drain of the transistor M14 is connected to the other of the source or drain of the transistor M11 (corresponding to node ND3). In the semiconductor device 100 shown in Figure 3A, a predetermined potential can be applied from the wiring VL2 to the node ND2 via the transistors M14 and M11.

[0088] [Another Configuration Example 2] FIG. 3B is a circuit diagram illustrating a modified example of the semiconductor device 100 shown in FIG. 2B . FIG. 2B illustrates a configuration example of the semiconductor device 100 in which the light-emitting control unit 110 is provided between the transistor M11 and the wiring CATH in a current path including the light-emitting element LD, but the present invention is not limited to this. For example, FIG. 3B illustrates a configuration example of the semiconductor device 100 in which the light-emitting control unit 110 is provided between the light-emitting element LD and the transistor M11 in a current path including the light-emitting element LD. In the semiconductor device 100 shown in FIG. 3B , one terminal of the light-emitting element LD (e.g., the anode of the light-emitting diode) is connected to the wiring ANO. The other terminal of the light-emitting element LD (e.g., the cathode of the light-emitting diode) is connected to one of the source or drain of the transistor M12. The other of the source or drain of the transistor M11 is connected to the other of the source or drain of the transistor M12. One of the source or drain of the transistor M11 is connected to the wiring CATH without going through the source and drain of another transistor (also referred to as one of the source or drain of the transistor M11 being directly connected to the wiring CATH), or is connected to the wiring CATH through the source and drain of another transistor (also referred to as one of the source or drain of the transistor M11 being indirectly connected to the wiring CATH).

[0089] <Specific Example of Semiconductor Device> Next, a specific example of the configuration of the semiconductor device 100 will be described.

[0090] The specific examples and modifications of the semiconductor device 100 described below can be applied to the semiconductor device 100 described above with or without illustrations.

[0091] [Specific Example 1] FIG. 4 is a circuit diagram illustrating a specific example of the configuration of the semiconductor device 100 shown in FIGS. 1A and 2A.

[0092] As shown in Fig. 4, the semiconductor device 100A further includes a write control unit 102A in addition to the components of the semiconductor device 100 shown in Fig. 1A. The write control unit 102A includes transistors M21, M22, M23, M24, and a capacitance element C21. In Fig. 4, the pixel circuit 101A corresponds to the pixel circuit 101. The write control unit 102A corresponds to the write control unit 102 in the semiconductor device 100 shown in Fig. 2A. Therefore, the above description can be referred to as appropriate, and the description may be omitted here.

[0093] The gate of transistor M11 (corresponding to node ND1) is connected to one of the source or drain of transistor M23, one of the source or drain of transistor M24, and one terminal of capacitor C21. One of the source or drain of transistor M11 (corresponding to node ND2) is further connected to the other of the source or drain of transistor M23. The other of the source or drain of transistor M11 (corresponding to node ND3) is connected to one of the source or drain of transistor M21 and one of the source or drain of transistor M22. The other of the source or drain of transistor M21 is connected to wiring SL. The gate of transistor M21 is connected to wiring GW. The other of the source or drain of transistor M22 is connected to wiring ANO. The other terminal of capacitor C21 is connected to wiring ANO. The gate of transistor M22 is connected to wiring EM2. The gate of transistor M23 is connected to wiring GC. The other of the source and the drain of the transistor M24 is connected to the wiring VL3, and the gate of the transistor M24 is connected to the wiring GI.

[0094] The wiring SL functions as a signal line. The wiring SL has a function of transmitting an image signal provided from, for example, a circuit (e.g., a driver circuit such as a source driver) provided outside the semiconductor device 100A. The wirings EM, EM2, GW, GI, GC, and GP each have a function of transmitting a signal provided from, for example, a circuit (e.g., a driver circuit such as a gate driver) provided outside the semiconductor device 100A. The wirings ANO, CATH, VL1, VL2, and VL3 each have a function of power supply lines. The wirings ANO, CATH, VL1, VL2, and VL3 each have a function of transmitting a potential provided from, for example, a circuit (e.g., a power supply circuit) provided outside the semiconductor device 100A. Note that at least one of the wiring ANO, the wiring CATH, the wiring VL1, the wiring VL2, and the wiring VL3 may function as a signal line.

[0095] Two or more of the wirings that function as signal lines may be connected to each other as needed. Also, two or more of the wirings that function as power supply lines may be connected to each other as needed. Also, one or more of the wirings that function as power supply lines may be connected to one or more of the wirings that function as signal lines as needed. This allows some of the wirings to be shared, thereby reducing the layout area. Therefore, the resolution of the display device can be improved.

[0096] The transistor M21 functions as a switch that controls whether a potential is supplied from the wiring SL to the other of the source and the drain of the transistor M11.

[0097] The transistor M22 functions as a switch that controls whether or not to cut off the current flowing through the light-emitting element LD, i.e., it can be said to have a function of controlling whether or not the light-emitting element LD emits light.

[0098] The transistor M23 functions as a switch that controls whether a potential is supplied from the source or the drain of the transistor M11 to the gate of the transistor M11.

[0099] The transistor M24 functions as a switch that controls whether or not a potential is supplied from the wiring VL3 to the gate of the transistor M11.

[0100] The capacitance element C21 has a function of holding the gate voltage of the transistor M11.

[0101] In the semiconductor device 100A, a potential corresponding to an image signal supplied from the wiring SL can be applied to the gate of the transistor M11. At this time, a potential in which variations in the threshold voltage of the transistor M11 are corrected can be applied.

[0102] In the semiconductor device 100A, the same configuration as that of the light-emission control unit 110 including the transistor M12 can also be applied to the transistor M22. However, since the other of the source or drain of the transistor M22 is connected to the wiring ANO, a stable gate voltage can be applied to the transistor M22. Therefore, the same configuration as that of the light-emission control unit 110 does not need to be applied to the transistor M22.

[0103] In the semiconductor device 100A shown in FIG. 4, p-channel transistors can be used for the transistors M11 to M14 and the transistors M21 to M24.

[0104] In the semiconductor device 100A, at least one of the transistors may be an n-channel transistor.

[0105] [Specific Example 2] Fig. 5 is a circuit diagram illustrating a semiconductor device 100B, which is a modified example of the semiconductor device 100A shown in Fig. 4. In Fig. 5, the pixel circuit 101B corresponds to the pixel circuit 101A, and the write control unit 102B corresponds to the write control unit 102A. As in the semiconductor device 100B shown in Fig. 5, n-channel transistors can be used for the transistors M23 and M24.

[0106] In this case, it is preferable to use a transistor with low off-state current as each of the transistors M23 and M24. For example, an OS transistor may be used as the transistor with extremely low off-state current. By using a transistor with extremely low off-state current as each of the transistors M23 and M24, the potential of the gate of the transistor M11 (corresponding to the node ND1) can be held for a long period of time.

[0107] As a result, in a display device using the semiconductor device 100B, for example, when displaying a still image, the frequency of writing image data can be reduced, thereby reducing the power consumption of the display device.

[0108] In the semiconductor device 100B, for example, the transistors M23 and M24 may each be an OS transistor, and the transistors M11 to M14, M21, and M22 may each be a Si transistor.

[0109] 6 is a modified example of the semiconductor device 100A shown in FIG. 4, and further includes a transistor M25. In the semiconductor device 100A shown in FIG. 6, one of the source and the drain of the transistor M25 is connected to one terminal of the light-emitting element LD. The other of the source and the drain of the transistor M25 is connected to a wiring VL4. The gate of the transistor M25 is connected to a wiring GI. A p-channel transistor can be used as the transistor M25.

[0110] The transistor M25 functions as a switch that controls whether a potential is supplied from the wiring VL4 to one terminal of the light-emitting element LD. By including the transistor M25, the semiconductor device 100A can apply a potential from the wiring VL4 to one terminal of the light-emitting element LD so that the light-emitting element LD does not emit light when, for example, the transistor M12 is turned off. This can stabilize the operation of the display device.

[0111] Furthermore, for example, in a circuit provided outside the semiconductor device 100A, a current flowing from the wiring VL4 to the wiring CATH via the transistor M25 and the light-emitting element LD may be measured, and the variation in the voltage-current characteristics of the light-emitting element LD for each of the plurality of pixels may be corrected, thereby improving the display quality of the display device.

[0112] 6, the gate of the transistor M22 is connected to the wiring EM instead of the wiring EM2. The gate of the transistor M23 is connected to the wiring GW instead of the wiring GC. In this way, by sharing some of the wiring connected to the semiconductor device 100A, the layout area can be reduced. Therefore, the resolution of the display device can be improved.

[0113] 7 is a modified example of the semiconductor device 100B shown in FIG. 5, and further includes a transistor M25. In the semiconductor device 100B shown in FIG. 7, one of the source and the drain of the transistor M25 is connected to one terminal of the light-emitting element LD. The other of the source and the drain of the transistor M25 is connected to a wiring VL4. The gate of the transistor M25 is connected to a wiring GB. A p-channel transistor can be used as the transistor M25.

[0114] The transistor M25 functions as a switch that controls whether a potential is supplied from the wiring VL4 to one terminal of the light-emitting element LD. By including the transistor M25, the semiconductor device 100B can apply a potential from the wiring VL4 to one terminal of the light-emitting element LD so that the light-emitting element LD does not emit light, for example, when the transistor M12 is turned off. This allows the operation of the display device to be stabilized.

[0115] 7, the gate of the transistor M22 is connected to the wiring EM instead of the wiring EM2. In this way, by sharing part of the wiring connected to the semiconductor device 100B, the layout area can be reduced, and the resolution of the display device can be improved.

[0116] Note that an n-channel transistor may be used as the transistor M25. In this case, the gate of the transistor M25 may be connected to the wiring GI. This allows a portion of the wiring connected to the semiconductor device 100B to be shared, thereby reducing the layout area. This allows for improved definition of the display device.

[0117] In one embodiment of the present invention, a transistor functioning as a switch has a function of controlling conduction or non-conduction between a connection destination of its source and a connection destination of its drain. For example, the transistor M21 has a function of controlling conduction or non-conduction between the wiring SL and the node ND3. For example, the transistor M22 has a function of controlling conduction or non-conduction between the wiring ANO and the node ND3. For example, the transistor M23 has a function of controlling conduction or non-conduction between the node ND2 and the node ND1. For example, the transistor M24 has a function of controlling conduction or non-conduction between the wiring VL3 and the node ND1. For example, the transistor M25 has a function of controlling conduction or non-conduction between the wiring VL4 and one terminal of the light-emitting element LD.

[0118] In one embodiment of the present invention, the on or off state of a transistor functioning as a switch is controlled by the potential of a connection destination of its gate. For example, the on or off state of the transistor M21 is controlled by the potential of the wiring GW. For example, the on or off state of the transistor M22 is controlled by the potential of the wiring EM or the wiring EM2. For example, the on or off state of the transistor M23 is controlled by the potential of the wiring GW or the wiring GC. For example, the on or off state of the transistor M24 is controlled by the potential of the wiring GI. For example, the on or off state of the transistor M25 is controlled by the potential of the wiring GI or the wiring GB.

[0119] In one embodiment of the present invention, a transistor having a function as a switch supplies the potential of one of the nodes connected to the source or drain to the other node connected to the source or drain, or supplies the potential of the other node connected to the source or drain to the other node connected to the source or drain. In other words, the potential of the node connected to the one of the nodes connected to the source or drain is supplied to the other node connected to the source or drain through a channel formation region of the transistor. Alternatively, the potential of the node connected to the other node connected to the source or drain is supplied to the other node connected to the source or drain through a channel formation region of the transistor. For example, the transistor M21 supplies the potential of the wiring SL to the node ND3. For example, the transistor M22 supplies the potential of the wiring ANO to the node ND3. For example, the transistor M23 supplies the potential of the node ND2 to the node ND1. For example, the transistor M24 supplies the potential of the wiring VL3 to the node ND1. For example, the transistor M25 has a function of supplying the potential of the wiring VL4 to one terminal of the light-emitting element LD. In this case, the supplied potential may differ by the threshold voltage of the transistor.

[0120] In addition, at least a portion of the semiconductor device 100A and the semiconductor device 100B, which are specific examples of the semiconductor device 100 described above as illustrated or not illustrated, can be applied to the semiconductor device 100 shown in Figures 1B, 2B, 3A, and 3B.

[0121] The specific structure of the semiconductor device 100 is not limited to the above example. One embodiment of the present invention is a semiconductor device including at least a part of the semiconductor device 100 illustrated in each of FIGS.

[0122] <Example of Operation of Semiconductor Device> Next, a description will be given of an example of operation of the semiconductor device 100. Here, as an example, an example of operation of the semiconductor device 100B shown in FIG.

[0123] Fig. 8 is a timing chart illustrating an example of the operation of the semiconductor device 100B shown in Fig. 7. Figs. 9 to 16 are circuit diagrams illustrating an example of the operation of the semiconductor device 100B shown in Fig. 7.

[0124] In the semiconductor device 100B, the wirings EM, GW, GC, GI, GB, and GP each function as a signal line. The potential of a signal applied to each of the wirings EM, GW, GC, GI, GB, and GP is either a potential L (sometimes simply referred to as "L") or a potential H (sometimes simply referred to as "H") that is higher than the potential L. In this case, the difference between the potential H and the potential L is higher than the threshold voltage of the transistor. Note that the potential L or the potential H may be, for example, a ground potential.

[0125] The wirings ANO, CATH, VL1, VL2, VL3, and VL4 each function as a power supply line. Here, a potential H is applied to the wirings ANO and VL2, and a potential L is applied to the wirings CATH, VL1, VL3, and VL4.

[0126] Note that a signal may be supplied to at least one of the wiring VL1, the wiring VL2, the wiring VL3, and the wiring VL4. That is, at least one of the wiring VL1, the wiring VL2, the wiring VL3, and the wiring VL4 can also function as a signal line.

[0127] The wiring SL also functions as a signal line. A potential based on an image signal is applied to the wiring SL. The potential based on the image signal is a potential between the potential H and the potential L.

[0128] For ease of understanding, the potential applied to each wiring other than the wiring VL1 is the potential L or the potential H. However, different potentials may be applied to each wiring. For example, a potential different from the potential H may be applied to the wiring ANO. Furthermore, for example, a potential different from the potential L may be applied to the wiring CATH.

[0129] In the description of the operation, when the potential changes, a rise time and a fall time may occur due to, for example, a load (parasitic capacitance and parasitic resistance) such as a wiring. Also, even if two different operations are shown to have the same timing, this does not necessarily mean that they are exactly the same timing. For example, even if there is a slight time difference due to signal delay in the wiring, they may be considered to have the same timing.

[0130] Furthermore, in the timing chart, even if each period is shown to have the same length in the drawing for ease of explanation, the time length of each period may be different.

[0131] 8 shows potentials applied to each wiring during each period of operation, and also shows changes in potential at each node.

[0132] 9 to 16 show the state of the circuit (potential of each wiring and each node, state of each transistor, current flowing through each wiring and each node, etc.) at each point in time of operation. A symbol indicating a potential such as "H" or "L" (also called a potential symbol) may be written with a boxed character adjacent to each wiring and each node. In particular, when a potential change occurs, the boxed line may be thickened, and when a floating state occurs, the boxed line may be dotted. An "x" symbol may be written over a transistor in an off state. The direction of current flow (which may also be said to be the direction of movement of positive charge) or the state in which a potential is supplied along each wiring and each node may be shown with a dashed arrow.

[0133] In addition, the threshold voltage of transistor M11 may be denoted as Vt11, the threshold voltage of transistor M12 as Vt12, the threshold voltage of transistor M13 as Vt13, the threshold voltage of transistor M14 as Vt14, the threshold voltage of transistor M21 as Vt21, the threshold voltage of transistor M22 as Vt22, the threshold voltage of transistor M23 as Vt23, the threshold voltage of transistor M24 as Vt24, the threshold voltage of transistor M25 as Vt25, and the forward voltage of light-emitting element LD as Vf.

[0134] In this case, the threshold voltages of the n-channel transistors (corresponding to Vt23 and Vt24, respectively) are greater than 0 V, and the threshold voltages of the p-channel transistors (corresponding to Vt11, Vt12, Vt13, Vt14, Vt21, Vt22, and Vt25, respectively) are less than 0 V.

[0135] For ease of understanding, the following description may be given without taking into consideration the influence of parasitic capacitance when a potential changes due to capacitive coupling.

[0136] Immediately before the period T11, a potential L is applied to the wiring EM, the wiring GC, and the wiring GI, and a potential H is applied to the wiring GW, the wiring GB, and the wiring GP. Therefore, the transistors M14, M21, M23, M24, and M25 are each in an off state, and the transistors M12 and M22 are each in an on state. As a result, the node ND1 is floating. At this time, the potential of the node ND4 is assumed to be smaller than "potential L-Vt13." Therefore, the transistor M13 is in an off state. As a result, the node ND4 is floating. Also, the potential of the node ND3 is assumed to be potential H, and the potential of the node ND1 is assumed to be "potential Vd0+Vt11." As a result, "potential Vd0+Vt11-potential H" is applied as the gate voltage of the transistor M11, and a current based on this gate voltage is supplied to the light-emitting element LD, causing the light-emitting element LD to emit light. At this time, the potentials of the nodes ND2 and ND5 are "potential L+Vf." The state of the circuit at this time is shown in Figure 9. In the following description, unless otherwise specified, it is assumed that the immediately preceding state is maintained.

[0137] In period T11, a potential H is applied to the wiring GI, and a potential L is applied to the wiring GB. This turns on the transistors M24 and M25. Then, the potential of the wiring VL3 is supplied to the node ND1 via the transistor M24, and the potential of the node ND1 becomes the potential L. Furthermore, a current flows from the wiring ANO to the wiring VL4 via the transistors M22, M11, M12, and M25, and the light-emitting element LD does not emit light. At this time, the potentials of the nodes ND3, ND2, and ND5 exceed the "potential L-Vt25." Furthermore, as the potentials of the nodes ND2 and ND5 decrease slightly, the potential of the node ND4 also decreases slightly due to the capacitive coupling of the capacitor C11. The circuit state at this time is shown in FIG. 10.

[0138] During the period T11, a current flows from the wiring ANO to the wiring VL4 via the transistors M22, M11, M12, and M25, resulting in power consumption. Therefore, to reduce this effect, it is preferable to shorten the length of the period T11. For example, the length of the period T11 is preferably equal to or shorter than the length of a period T12 (described later), preferably equal to or shorter than the length of a period T13, preferably equal to or shorter than the length of a period T14, and preferably equal to or shorter than the length of a period T16.

[0139] In the period T12, a potential H is applied to the wiring EM. The potential of the wiring EM is supplied to the node ND4 through the transistor M13, and the potential of the node ND4 becomes the potential H. As a result, the transistors M12 and M22 are turned off. Then, the nodes ND2 and ND3 are each floating, and the potential of the node ND5 becomes the "potential L-Vt25." At this time, the potentials of the nodes ND2 and ND3 may increase due to the capacitive coupling of the capacitor C11. The state of the circuit at this time is shown in FIG. 11.

[0140] In the period T12, the potential of the anode of the light-emitting element LD is set to "potential L-Vt25," thereby initializing the voltage applied to the light-emitting element LD (also referred to as anode voltage initialization or anode reset). This makes it possible to suppress the influence of past display history and improve the display quality of the display device.

[0141] In addition, in the period T12, a predetermined potential may be supplied to the other of the source and drain of the transistor M11 (corresponding to the node ND3) to apply a gate voltage (also referred to as application of an on-bias voltage) that turns on the transistor M11. For example, by applying a potential L to the wiring GW, the potential of the wiring SL (i.e., a potential corresponding to an image signal) may be supplied to the node ND3, and an on-bias voltage of “potential L minus a potential corresponding to an image signal” may be applied to the transistor M11. For example, by connecting the gate of the transistor M22 to a wiring different from the wiring EM and applying a potential L to the different wiring, the potential of the wiring ANO (here, potential H) may be supplied to the node ND3, and an on-bias voltage of “potential L minus potential H” may be applied to the transistor M11. For example, by providing an additional transistor and connecting one of the source and drain of the transistor to the node ND3, a predetermined potential may be supplied from the other of the source and drain of the transistor to the node ND3, and an on-bias voltage of “potential L minus a predetermined potential” may be applied to the transistor M11. In this way, by applying an on-bias voltage to the transistor M11, the influence of hysteresis of the transistor M11 can be suppressed, and the display quality of the display device can be improved.

[0142] In the period T13, first, a potential L is applied to the wiring GI, and a potential H is applied to the wiring GB. As a result, the transistors M24 and M25 are turned off. Next, a potential L is applied to the wiring GW, and a potential H is applied to the wiring GC. As a result, the transistors M21 and M23 are turned on. At this time, a potential Vd1 corresponding to an image signal is applied to the wiring SL. Then, a current flows from the wiring SL to the node ND1 via the transistors M21, M11, and M23, and the potential of the node ND1 increases. The circuit state at this time is shown in FIG. 12.

[0143] Here, "the potential of node ND1 - potential Vd1" is applied as the gate voltage of transistor M11. Therefore, when the potential of node ND1 rises to "potential Vd1 + Vt11", transistor M11 is turned off. Then, nodes ND1 and ND2 are each floated, and the potential difference between node ND1 and wiring ANO, "potential Vd1 + Vt11 - potential H", is held in capacitor C21. The state of the circuit at this time is shown in FIG. 13.

[0144] Thereafter, a potential H is applied to the wiring GW, and a potential L is applied to the wiring GC, thereby turning off the transistors M21 and M23.

[0145] In a period T14, a potential L is applied to the wiring GP. This turns on the transistor M14. Then, the potential of the wiring VL2 is supplied to the nodes ND2 and ND3 through the transistor M14, and the potentials of the nodes ND2 and ND3 become potential H. The state of the circuit at this time is shown in FIG.

[0146] In the period T14, it is preferable to reduce the parasitic capacitance between the nodes ND1 and ND2 and the parasitic capacitance between the nodes ND1 and ND3 so that the potential of the node ND1 does not change in accordance with changes in the potentials of the nodes ND2 and ND3. For example, it is preferable to make the capacitance of the capacitive element C21 larger than the parasitic capacitance.

[0147] In period T15, potential L is applied to the wiring EM. The potential of the wiring EM is supplied to node ND4 via transistor M13, and the potential of node ND4 becomes "potential L-Vt13." This causes transistors M12 and M22 to be turned on. Then, a current flows from wiring VL2 to wiring CATH via transistors M14, M12, and light-emitting element LD. At this time, the potential of node ND5 is "potential L+Vf." The potential of wiring ANO is supplied to node ND3 via transistor M22, and the potential of node ND3 becomes potential H. This causes "potential Vd1+Vt11-potential H" to be applied as the gate voltage of transistor M11. Since the potential of node ND2 is potential H, no drain current flows through transistor M11. The circuit state at this time is shown in FIG. 15.

[0148] In addition, during the period T15, a current flows through the light-emitting element LD, causing the light-emitting element LD to emit light. Therefore, in order to reduce this effect, it is preferable to shorten the length of the period T15. For example, the length of the period T15 is preferably equal to or shorter than the length of the period T12, preferably equal to or shorter than the length of the period T13, preferably equal to or shorter than the length of the period T14, and preferably equal to or shorter than the length of the period T16 described below.

[0149] In period T16, a potential H is applied to the wiring GP. This turns off the transistor M14. Then, the potential of the node ND2 drops to "potential L + Vf." Therefore, a drain current based on the gate voltage of the transistor M11 flows, and this current is supplied to the light-emitting element LD, causing the light-emitting element LD to emit light. At this time, "(potential Vd1 + Vt11) - potential H" is applied as the gate voltage of the transistor M11, and therefore a current proportional to "the gate voltage of the transistor M11 - Vt11," that is, a current proportional to "potential Vd1 - potential H," flows as the drain current of the transistor M11. Therefore, a current independent of the threshold voltage of the transistor M11 can flow as the drain current of the transistor M11. As a result, even if the threshold voltage of the transistor M11 varies among multiple pixels, a drain current that is not affected by the variation in threshold voltage can flow. In this way, the variation in the threshold voltage of the transistor M11 can be corrected.

[0150] Here, when the potential of node ND2 drops, the potential of node ND4 also drops due to the capacitive coupling of capacitive element C11, and the potential of node ND4 becomes smaller than "potential L-Vt13". At this time, transistor M13 is turned off, and the gate voltage of transistor M12 is maintained. The state of the circuit at this time is shown in FIG. 16. Also, in FIG. 8, the change in the potential of node ND2 is shown as Va (here, "Va = (potential L + Vf) - potential H"), and the change in the potential of node ND4 is shown as Vb (here, "Va < Vb < 0 V"). In other words, the potential of node ND4 becomes "potential L-Vt13 + Vb".

[0151] Note that during the period T16, due to the influence of the parasitic capacitance of the node ND4, the change in the potential of the node ND4 accompanying the change in the potential of the node ND2 may become smaller (the absolute value of Vb may become smaller than the absolute value of Va). Therefore, in order to increase the change in the potential of the node ND4 accompanying the change in the potential of the node ND2, it is preferable to reduce the parasitic capacitance of the node ND4. For example, it is preferable to reduce the parasitic capacitance between the node ND4 and the node ND5, the parasitic capacitance between the node ND4 and the wiring VL1, and the parasitic capacitance between the node ND4 and the wiring EM, each smaller than the capacitance of the capacitive element C11.

[0152] In the semiconductor device 100B of one embodiment of the present invention, for example, the potential of the wiring VL2 can be supplied to the node ND2 (corresponding to one of the source and drain of the transistor M12) in the period T14. As a result, a stable gate voltage can be applied to the transistor M12 in the period T15. Furthermore, the gate voltage of the transistor M12 can be maintained in the period T16. Therefore, the light-emitting luminance of the display device can be stabilized.

[0153] For example, in the period T14, the potential supplied from the wiring VL2 to the node ND2 can be made higher than the potential corresponding to the image signal. For example, a potential H higher than the potential Vd1 can be supplied to the node ND2. As a result, the gate voltage applied to the transistor M12 can be increased in the periods T15 and T16.

[0154] In other words, even if the amplitude of the signal provided from the wiring EM is reduced, a sufficient gate voltage can be applied to the transistor M12. Therefore, for example, a sufficient on-state current can be obtained even if the channel width of the transistor M12 is reduced, thereby improving the resolution of the display device. Furthermore, for example, by reducing the amplitude of the signal provided from the wiring EM, the voltage applied between the terminals of the transistor can be reduced, thereby suppressing breakdown and degradation of the transistor and improving the reliability of the display device. For example, by reducing the amplitude of the signal provided from the wiring EM, the withstand voltage required of the transistor can be reduced, eliminating the need for technology with high process costs, thereby reducing the manufacturing cost of the display device. For example, by reducing the amplitude of the signal provided from the wiring EM, the operating voltage of a circuit (e.g., a driver circuit such as a gate driver) provided outside the semiconductor device 100B can be reduced, thereby reducing the power consumption of the display device.

[0155] In addition, in the period T13, a transistor with a large on-state current is preferably used as the transistor M23 in order to shorten the time until the transistor M11 is turned off, thereby improving the operating speed.

[0156] Here, in the semiconductor device 100B, for example, an operation to suppress the influence of hysteresis of the transistor M11 may be performed. In particular, when a Si transistor is used for the transistor M11, it is preferable to perform an operation to suppress the influence of hysteresis of the transistor M11. To suppress the influence of hysteresis of the transistor M11, for example, an operation to initialize the gate potential of the transistor M11 (an operation corresponding to the period T13) may be performed multiple times. Therefore, particularly in such a case, it is preferable to use a transistor with a large on-state current for the transistor M23 in order to improve the operating speed.

[0157] In addition, in the period T16, in order to maintain the gate voltage of the transistor M11, it is preferable to use transistors with low off-state current as the transistors M23 and M24, which can stabilize the light-emission intensity.

[0158] Therefore, for example, a transistor with a small off-state current and a large on-state current is preferably used for each of the transistors M23 and M24.

[0159] In one embodiment of the present invention, an OS transistor can be used as each of the transistors M23 and M24, for example, as a transistor with extremely low off-state current. Various oxide semiconductors can be used for the OS transistor. In particular, it is preferable to use an oxide semiconductor that exhibits low off-state current and high on-state current. Examples of oxide semiconductors that exhibit low off-state current and high on-state current include indium oxide. Details of oxide semiconductors that can be used for OS transistors will be described in Embodiment 4 below. Indium oxide, which is one of oxide semiconductors, will also be described in detail in Embodiment 9.

[0160] In the above-described operation example, the potential H is applied to each of the wirings ANO and VL2. However, this is not limiting. Different potentials may be applied to each of the wirings ANO and VL2. Furthermore, although the potential L is applied to each of the wirings CATH, VL1, VL3, and VL4, this is not limiting. Different potentials may be applied to each of the wirings CATH, VL1, VL3, and VL4. For example, when the same potential is applied to each of the wirings ANO and VL2, the wirings ANO and VL2 may be connected to each other. For example, when the same potential is applied to two or more of the wirings CATH, VL1, VL3, and VL4, two or more of the wirings CATH, VL1, VL3, and VL4 may be connected to each other. This allows some of the wirings connected to the semiconductor device 100B to be shared, thereby reducing the layout area. Therefore, the resolution of the display device can be improved.

[0161] In the above-described operation example, for example, the wiring VL1 needs to be supplied with a potential (e.g., potential L) that turns on the transistor M13 at the timing when the potential applied to the wiring EM changes from potential L to potential H (corresponding to the start of period T12) and the timing when the potential changes from potential H to potential L (corresponding to the start of period T15). A potential (e.g., potential H) higher than the potential L may be supplied at other times. Thus, the wiring VL1 may function as a signal line. In this case, for example, the wiring VL1 may be connected to any one of the wiring GW, the wiring GC, the wiring GI, the wiring GB, and the wiring GP. In this way, by sharing some of the wirings connected to the semiconductor device 100B, the layout area can be reduced. Therefore, the resolution of the display device can be improved.

[0162] Furthermore, for example, the wiring GP needs to be supplied with a potential (e.g., potential L) that turns on the transistor M14 when the potential applied to the wiring EM changes from potential H to potential L, and the wiring VL2 needs to be supplied with potential H when the transistor M14 is on (corresponding to periods T14 and T15). Furthermore, when the transistor M14 is off, a potential (e.g., potential L) lower than the potential H may be supplied. Thus, the wiring VL2 may function as a signal line. In this case, for example, the wiring VL2 may be connected to any one of the wiring EM, the wiring GW, the wiring GC, the wiring GI, the wiring GB, and the wiring GP. In this way, by sharing some of the wirings connected to the semiconductor device 100B, the layout area can be reduced. Therefore, the resolution of the display device can be improved.

[0163] In addition, when some of the wiring connected to the semiconductor device 100B is shared, for example, two or more wirings may be connected to each other inside the semiconductor device 100B or may be connected to each other outside the semiconductor device 100B. Furthermore, for example, the respective wirings of two or more semiconductor devices 100B provided in different rows may be connected to each other. For example, in the above-described operation example, a signal applied to the wiring GP of the semiconductor device 100B provided in one row may be the same signal as a signal applied to the wiring GB or wiring GW of the semiconductor device 100B provided in another row. In this case, the wiring GP of the semiconductor device 100B provided in one row and the wiring GB or wiring GW of the semiconductor device 100B provided in another row may be connected to each other.

[0164] At least a part of the above-described operation example can be applied to the semiconductor device 100B shown in Fig. 5. Also, at least a part of the above-described operation example of the semiconductor device 100B can be applied to the semiconductor device 100A shown in Figs. 4 and 6.

[0165] <Modifications of Semiconductor Device> The semiconductor device of one embodiment of the present invention is not limited to the above structure. The semiconductor device of one embodiment of the present invention can have various structures.

[0166] [Variation 1] Figure 17 is a circuit diagram illustrating a variation of the semiconductor device 100B shown in Figure 5. The semiconductor device 100B shown in Figure 17 differs from the semiconductor device 100B shown in Figure 5 in that it includes transistors M13a and M13b instead of the transistor M13. In this case, one of the source or drain of the transistor M13b is connected to the gate of the transistor M12 and the other terminal of the capacitance element C11. The other of the source or drain of the transistor M13b is connected to one of the source or drain of the transistor M13a. The other of the source or drain of the transistor M13a is connected to a wiring EM. The gates of the transistors M13a and M13b are each connected to a wiring VL1.

[0167] With this configuration, for example, in the period T16, charge is less likely to leak from the node ND4 to the wiring EM, making it easier to maintain the gate voltage of the transistor M12. Thus, the operation of the display device can be stabilized.

[0168] [Variation 2] Fig. 18 is a circuit diagram illustrating a variation of the semiconductor device 100B shown in Fig. 5. The semiconductor device 100B shown in Fig. 18 differs from the semiconductor device 100B shown in Fig. 5 in that an n-channel transistor is used as the transistor M14 and in connection of the transistor M14. Here, the other of the source and the drain of the transistor M14 is connected to the gate of the transistor M14 (corresponding to the wiring GP).

[0169] 19 is a circuit diagram illustrating a modified example of the semiconductor device 100B shown in FIG. The semiconductor device 100B shown in FIG. 19 differs from the semiconductor device 100B shown in FIG. 5 in terms of the connection of the transistor M14. Here, the other of the source and the drain of the transistor M14 is connected to a wiring GP. The gate of the transistor M14 is connected to one of the source and the drain of the transistor M14.

[0170] At this time, for example, a signal obtained by inverting the logical value of the signal supplied to the wiring GP in the above-described operation example is supplied to the wiring GP. As a result, for example, in the period T14, a potential H is supplied to the wiring GP, and the transistor M14 is turned on. Then, the potential of the wiring GP is supplied to each of the nodes ND2 and ND3, and the potentials of the nodes ND2 and ND3 become "potential H+Vt14."

[0171] With this configuration, there is no need to provide the wiring VL2, and therefore the layout area can be reduced. Therefore, the resolution of the display device can be improved. Furthermore, there is no need to generate the potential applied to the wiring VL2 in a circuit (e.g., a power supply circuit) provided outside the semiconductor device 100B, and therefore at least one of miniaturization and low power consumption of the display device can be achieved.

[0172] Fig. 20 is a circuit diagram illustrating a modified example of the semiconductor device 100B shown in Fig. 19. The semiconductor device 100B shown in Fig. 20 differs from the semiconductor device 100B shown in Fig. 19 in terms of the connection of the transistor M13. Here, the gate of the transistor M13 is connected to the wiring GP.

[0173] At this time, a signal is applied to the wiring GP, for example, which has a potential H in the period T14 and a potential L in the other periods. As a result, for example, in the period T14, the potential H is applied to the wiring GP, and the transistor M14 is turned on. Then, the potential of the wiring GP is supplied to each of the nodes ND2 and ND3, and the potentials of the nodes ND2 and ND3 become "potential H+Vt14." Also, for example, in the period T14, the potential H is applied to the gate of the transistor M13, and the transistor M13 is turned off. Then, the node ND4 is made floating, and the potential of the node ND4 remains at potential H. In the other periods, the potential L is applied to the gate of the transistor M13, which is the same as the above-described operation example.

[0174] With this configuration, there is no need to provide the wiring VL1, and therefore the layout area can be reduced. Therefore, the resolution of the display device can be improved. Furthermore, there is no need to generate the potential applied to the wiring VL1 in a circuit (e.g., a power supply circuit) provided outside the semiconductor device 100B, and therefore at least one of miniaturization and low power consumption of the display device can be achieved.

[0175] [Variation 3] Figure 21 is a circuit diagram illustrating a variation of the semiconductor device 100B shown in Figure 5. The semiconductor device 100B shown in Figure 21 differs from the semiconductor device 100B shown in Figure 5 in that it includes a p-channel transistor M15 instead of the capacitive element C11. In this case, the gate of the transistor M15 is connected to the gate of the transistor M12 (corresponding to node ND4). One of the source or drain of the transistor M15 and the other of the source or drain of the transistor M15 are each connected to one of the source or drain of the transistor M12 (corresponding to node ND2).

[0176] With this configuration, for example, during periods T15 and T16, a channel is formed in the channel formation region of transistor M15, allowing the gate capacitance of transistor M15 to function as a capacitive element instead of capacitive element C11. Here, in order to increase the change in the potential of node ND4 accompanying the change in the potential of node ND2 during period T16, it is preferable for the capacitance of capacitive element C11 to be large. To increase the capacitance of capacitive element C11, for example, the layout area of ​​capacitive element C11 can be increased. Alternatively, to increase the capacitance while suppressing an increase in the layout area of ​​capacitive element C11, for example, adding a conductive layer, reducing the film thickness of the dielectric, or using a dielectric with a high dielectric constant can be used. However, these methods increase process costs. Therefore, by using the gate capacitance of transistor M15 as a capacitive element instead of capacitive element C11, the gate insulating film is used as a dielectric, making it easier to increase the capacitance per unit area. Therefore, compared to the configuration shown in FIG. 5, the layout area can be reduced, thereby improving the resolution of the display device.

[0177] Furthermore, for example, in the periods T12 to T14, a potential H is applied to the gate of the transistor M15. Then, the transistor M15 is turned off, and no channel is formed in the channel formation region of the transistor M15. Since no channel is formed in the channel formation region of the transistor M15, the gate capacitance of the transistor M15 is reduced. By reducing the gate capacitance of the transistor M15 in this manner, for example, in the period T13, the current required for charging and discharging the nodes ND1 and ND2 can be reduced, or the time required for charging and discharging (the time required for the potential of the node ND1 to reach "potential Vd1+Vt11") can be shortened. Therefore, at least one of a reduction in power consumption and an improvement in operating speed of the display device can be achieved.

[0178] Although not shown, the semiconductor device 100B may include an n-channel transistor M15 instead of the capacitive element C11. In this case, the gate of the transistor M15 is connected to one of the source or drain of the transistor M12 (corresponding to node ND2). One of the source or drain of the transistor M15 and the other of the source or drain of the transistor M15 are each connected to the gate of the transistor M12 (corresponding to node ND4).

[0179] [Variation 4] Fig. 22 is a circuit diagram illustrating a variation of the semiconductor device 100B shown in Fig. 5. The semiconductor device 100B shown in Fig. 22 differs from the semiconductor device 100B shown in Fig. 5 in terms of the connection of the transistor M13. Here, the gate of the transistor M13 is connected to the other of the source and drain of the transistor M24 (corresponding to the wiring VL3).

[0180] With this configuration, there is no need to provide the wiring VL1, and therefore the layout area can be reduced. Therefore, the resolution of the display device can be improved. Furthermore, there is no need to generate the potential applied to the wiring VL1 in a circuit (e.g., a power supply circuit) provided outside the semiconductor device 100B, and therefore at least one of miniaturization and low power consumption of the display device can be achieved.

[0181] [Variation 5] Fig. 23 is a circuit diagram illustrating a variation of the semiconductor device 100B shown in Fig. 5. The semiconductor device 100B shown in Fig. 23 differs from the semiconductor device 100B shown in Fig. 5 in terms of the connection of the transistor M14. Here, the other of the source or the drain of the transistor M14 is connected to the other of the source or the drain of the transistor M22 (corresponding to the wiring ANO).

[0182] With this configuration, there is no need to provide the wiring VL2, and therefore the layout area can be reduced. Therefore, the resolution of the display device can be improved. Furthermore, there is no need to generate the potential applied to the wiring VL2 in a circuit (e.g., a power supply circuit) provided outside the semiconductor device 100B, and therefore at least one of miniaturization and low power consumption of the display device can be achieved.

[0183] [Variation 6] Fig. 24 is a circuit diagram illustrating a variation of the semiconductor device 100B shown in Fig. 5. The semiconductor device 100B shown in Fig. 24 differs from the semiconductor device 100B shown in Fig. 5 in terms of the connection of the transistor M22. Here, the gate of the transistor M22 is connected to the gate of the transistor M12 (corresponding to the node ND4).

[0184] With this configuration, for example, a region that functions as the gate of the transistor M12 and a region that functions as the gate of the transistor M22 can be provided in one conductive layer. Therefore, compared to the configuration shown in Figure 5, the number of vias can be reduced, and the layout area can be made smaller. Therefore, the resolution of the display device can be improved.

[0185] [Variation 7] Fig. 25 is a circuit diagram illustrating a variation of the semiconductor device 100B shown in Fig. 5. The semiconductor device 100B shown in Fig. 25 differs from the semiconductor device 100B shown in Fig. 5 in terms of the connection of the transistor M14. Here, the other of the source or the drain of the transistor M14 is connected to the gate (corresponding to the wiring GW) of the transistor M21.

[0186] At this time, for example, in the periods T14 and T15, the potential of the wiring GW is supplied to each of the nodes ND2 and ND3, and the potentials of the nodes ND2 and ND3 become the H potential.

[0187] With this configuration, there is no need to provide the wiring VL2, and therefore the layout area can be reduced. Therefore, the resolution of the display device can be improved. Furthermore, there is no need to generate the potential applied to the wiring VL2 in a circuit (e.g., a power supply circuit) provided outside the semiconductor device 100B, and therefore at least one of miniaturization and low power consumption of the display device can be achieved. Furthermore, when the transistor M14 is in an off state, a period can be provided in which the voltage applied between the drain and source of the transistor M14 is low. Therefore, breakdown and degradation of the transistor can be suppressed, and the reliability of the display device can be improved.

[0188] [Variation 8] Fig. 26 is a circuit diagram illustrating a variation of the semiconductor device 100B shown in Fig. 5. The semiconductor device 100B shown in Fig. 26 differs from the semiconductor device 100B shown in Fig. 5 in terms of the connection of the transistor M13. Here, the gate of the transistor M13 is connected to the gate of the transistor M23 (corresponding to the wiring GC).

[0189] At this time, for example, in the periods T11 and T12, the potential L is applied to the gate of the transistor M13, which is the same as the above-described operation example. In the period T13, the potential H is applied to the gate of the transistor M13, which turns off the transistor M13. Then, the node ND4 becomes floating, and the potential of the node ND4 remains at the potential H. In the periods T14 to T16, the potential L is applied to the gate of the transistor M13, which is the same as the above-described operation example.

[0190] Fig. 27 is a circuit diagram illustrating a modified example of the semiconductor device 100B shown in Fig. 5. The semiconductor device 100B shown in Fig. 27 differs from the semiconductor device 100B shown in Fig. 5 in terms of the connection of the transistor M13. Here, the gate of the transistor M13 is connected to the gate of the transistor M24 (corresponding to the wiring GI).

[0191] At this time, a signal that has a potential H in the period T11 and a potential L in the periods T12 to T16 is applied to the wiring GI. As a result, for example, in the period T11, the potential H is applied to the gate of the transistor M13, and the transistor M13 is turned off. This is the same as in the above-described operation example. In the periods T12 to T16, the potential L is applied to the gate of the transistor M13, which is the same as in the above-described operation example.

[0192] With this configuration, there is no need to provide the wiring VL1, and therefore the layout area can be reduced. Therefore, the resolution of the display device can be improved. Furthermore, there is no need to generate the potential applied to the wiring VL1 in a circuit (e.g., a power supply circuit) provided outside the semiconductor device 100B, and therefore at least one of miniaturization and low power consumption of the display device can be achieved.

[0193] [Variation 9] Fig. 28 is a circuit diagram illustrating a variation of the semiconductor device 100B shown in Fig. 5. The semiconductor device 100B shown in Fig. 28 differs from the semiconductor device 100B shown in Fig. 5 in terms of the connection of the transistor M14. Here, one of the source or the drain of the transistor M14 is connected to the other of the source or the drain of the transistor M11 (corresponding to the node ND3).

[0194] At this time, for example, in the periods T14 and T15, a predetermined potential can be applied from the wiring VL2 to one of the source and the drain of the transistor M12 (corresponding to the node ND2) through the transistor M14 and the transistor M11.

[0195] For example, in the period T12, a potential L may be applied to the wiring GP. This turns on the transistor M14, allowing a predetermined potential to be applied from the wiring VL2 to the other of the source and drain of the transistor M11 (corresponding to the node ND3) via the transistor M14. In other words, an on-bias voltage may be applied to the transistor M11. By applying an on-bias voltage to the transistor M11 in this manner, the influence of hysteresis of the transistor M11 can be suppressed, thereby improving the display quality of the display device.

[0196] [Variation 10] Fig. 29 is a circuit diagram illustrating a variation of the semiconductor device 100B shown in Fig. 5. At least one of the transistors included in the semiconductor device 100B may have a back gate. Fig. 29 shows an example in which the transistor M11, the transistor M23, and the transistor M24 each have a back gate.

[0197] The back gate of the transistor M23 is connected to, for example, the gate of the transistor M23. In this case, for example, the gate and back gate of the transistor M23 may be connected to each other outside the semiconductor device 100B or the pixel circuit 101B, or may be connected to each other inside the semiconductor device 100B or the pixel circuit 101B. The transistor M23, which functions as a switch, preferably has a large on-state current. Therefore, by connecting the gate and back gate of the transistor M23 to each other, the on-state current can be increased. This can improve the operating speed of the semiconductor device 100B. Furthermore, for example, even if the channel width of the transistor M23 is reduced, a sufficient on-state current can be easily obtained, thereby reducing the layout area. This can improve the resolution of the display device. Furthermore, reducing the channel width of the transistor M23 can sometimes increase the aperture ratio of the pixel. This can achieve at least one of higher brightness and higher reliability of the display device. Note that the back gate of the transistor M23 may be connected to, for example, a wiring to which a predetermined potential is applied.

[0198] The back gate of transistor M24 is the same as that of transistor M23. Although not shown, transistors M12, M13, M14, M21, and M22 may each have a back gate. In this case, the back gate of each transistor is the same as that of transistor M23.

[0199] The back gate of the transistor M11 is connected to, for example, a wiring ANO. Connecting the back gate of the transistor M11 to the wiring ANO fixes the potential of the back gate side of the channel formation region, thereby stabilizing the electrical characteristics (for example, increasing saturation and suppressing a shift in the threshold voltage). Furthermore, the channel formation region is less susceptible to an electric field generated outside the transistor, thereby stabilizing the electrical characteristics. The channel formation region is less susceptible to light irradiation from outside the transistor, thereby stabilizing the electrical characteristics. The back gate of the transistor M11 may be connected to, for example, the other of the source and drain of the transistor M11 (corresponding to the node ND3), a wiring VL2, or a wiring to which a predetermined potential is applied. For example, the back gate of the transistor M11 and the wiring connected to the back gate may be connected to each other outside the semiconductor device 100B or the pixel circuit 101B or may be connected to each other inside the semiconductor device 100B or the pixel circuit 101B.

[0200] As an example, Figure 29 illustrates a state in which the back gate of transistor M11 and wiring ANO are connected to each other inside pixel circuit 101B, and the back gates and gates of transistors M23 and M24 are connected to each other outside pixel circuit 101B.

[0201] [Variation 11] Fig. 30 is a circuit diagram illustrating a variation of the semiconductor device 100B shown in Fig. 7. The semiconductor device 100B shown in Fig. 30 differs from the semiconductor device 100B shown in Fig. 7 in that it has a switch S14 instead of the transistor M14, a switch S21 instead of the transistor M21, a switch S22 instead of the transistor M22, a switch S23 instead of the transistor M23, a switch S24 instead of the transistor M24, and a switch S25 instead of the transistor M25.

[0202] As described above, one embodiment of the present invention may have a structure in which at least some of the transistors included in the semiconductor device 100B are replaced with other elements that function as switches.

[0203] It should be noted that two or more of the modifications described above, whether illustrated or not, can be applied to the semiconductor device 100B shown in FIGS.

[0204] Furthermore, at least some of the modifications of the semiconductor device 100B described above, whether illustrated or not, can be applied to the semiconductor device 100A shown in FIGS.

[0205] Furthermore, the semiconductor device 100, the semiconductor device 100A, and the semiconductor device 100B described above, whether illustrated or not, can solve at least the problem of providing a new semiconductor device by their circuit configuration alone.

[0206] One embodiment of the present invention also includes a structure in which at least one of a gate, a source, and a drain of one or more transistors is not connected to anything or is connected to any wiring. Another embodiment of the present invention also includes a structure in which nothing is input to one or more wirings or a signal or potential is input to one or more wirings.

[0207] <Structure Example 2 of Semiconductor Device> FIG. 31 is a circuit diagram illustrating a semiconductor device 100X2 of one embodiment of the present invention.

[0208] 31 , the semiconductor device 100X2 includes a pixel circuit 101L, a pixel circuit 101R, a light-emitting element LDL, a light-emitting element LDR, and a transistor M13. The pixel circuit 101L and the pixel circuit 101R each include a transistor M11, a transistor M12, and a capacitance element C11. The semiconductor device 100X2 can also be considered to be two pixels adjacent to each other in the row direction.

[0209] In each of the pixel circuits 101L and 101R, one of the source or drain of the transistor M11 is connected to one of the source or drain of the transistor M12 and one terminal of the capacitor C11. One of the source or drain of the transistor M13 is connected to the gate of the transistor M12 and the other terminal of the capacitor C11 in the pixel circuit 101L, and is also connected to the gate of the transistor M12 and the other terminal of the capacitor C11 in the pixel circuit 101R. The other of the source or drain of the transistor M13 is connected to a wiring EM. The gate of the transistor M13 is connected to a wiring VL1.

[0210] The light-emitting element LDL and the transistors M11 and M12 included in the pixel circuit 101L are provided in the current path between the wiring ANO and the wiring CATH. The light-emitting element LDR and the transistors M11 and M12 included in the pixel circuit 101R are also provided in the current path between the wiring ANO and the wiring CATH.

[0211] The transistor M11 included in the pixel circuit 101L has a function of controlling the amount of current supplied to the light-emitting element LDL in response to an image signal provided from a circuit (e.g., a drive circuit such as a source driver) provided outside the semiconductor device 100X2. The transistor M12 included in the pixel circuit 101L has a function as a switch that controls whether or not to cut off the current flowing through the light-emitting element LDL. The transistor M11 included in the pixel circuit 101R has a function of controlling the amount of current supplied to the light-emitting element LDR in response to an image signal provided from a circuit (e.g., a drive circuit such as a source driver) provided outside the semiconductor device 100X2. The transistor M12 included in the pixel circuit 101R has a function as a switch that controls whether or not to cut off the current flowing through the light-emitting element LDR.

[0212] A circuit including the transistor M13, the transistor M12 in the pixel circuit 101L, and the capacitor C11 functions as a bootstrap circuit. A circuit including the transistor M13, the transistor M12 in the pixel circuit 101R, and the capacitor C11 functions as a bootstrap circuit. Therefore, in each of the pixel circuits 101L and 101R, the capacitor C11 holds the gate voltage of the transistor M12. The transistor M13 controls the gate potential of the transistor M12 in the pixel circuit 101L and the gate potential of the transistor M12 in the pixel circuit 101R.

[0213] The semiconductor device 100X2 of one embodiment of the present invention can be said to have a structure in which one transistor M13 functioning as a bootstrap transistor is shared by two adjacent pixels in the row direction. Note that, for example, one transistor M13 functioning as a bootstrap transistor may be shared by three or more pixels arranged in the row direction. In this case, for example, the transistor M13 may be provided outside the pixel (e.g., in a driver circuit such as a gate driver). In this way, by sharing one bootstrap transistor among multiple pixels, the number of transistors per pixel can be reduced. Therefore, the area occupied by the transistors can be reduced, and the resolution of the display device can be improved.

[0214] 31, the configuration corresponding to one pixel can be said to be equivalent to the configuration of the semiconductor device 100 shown in Fig. 1A described above, without the transistor M14. Therefore, the above description can be referred to as appropriate, and detailed description will be omitted here.

[0215] FIG. 32 is a circuit diagram illustrating an example in which a configuration is applied in which two adjacent pixels in the row direction each correspond to the semiconductor device 100 shown in FIG. 1A described above, and the two pixels share a bootstrap transistor (corresponding to transistor M13).

[0216] In the semiconductor device 100X2 shown in FIG. 32, each of the pixel circuit 101L and the pixel circuit 101R includes a transistor M11, a transistor M12, a transistor M14, a capacitive element C11, and a write control unit 102.

[0217] In this case, the light-emission control unit 110X2 is composed of the transistor M13, the transistor M12, the transistor M14, and the capacitor C11 of the pixel circuit 101L, and the transistor M12, the transistor M14, and the capacitor C11 of the pixel circuit 101R. Therefore, the light-emission control unit 110X2 can be said to be configured such that one transistor M13 is shared between the transistor M13 in the light-emission control unit 110 of the pixel circuit 101L and the transistor M13 in the light-emission control unit 110 of the pixel circuit 101R. In this way, by sharing one bootstrap transistor between two pixels, the number of transistors per pixel can be reduced. This reduces the area occupied by the transistors, thereby improving the resolution of the display device.

[0218] 32, the configuration corresponding to one pixel can be said to correspond to the semiconductor device 100 shown in Fig. 1A described above. Therefore, the above description can be referred to as appropriate, and detailed description will be omitted here.

[0219] FIG. 33 is a circuit diagram illustrating an example in which a configuration is applied in which a bootstrap transistor (corresponding to transistor M13) is shared when n pixels (n is an integer equal to or greater than 2) arranged in the row direction each correspond to the semiconductor device 100 shown in FIG. 1A described above.

[0220] 33 includes pixel circuits 101[1] to 101[n], light-emitting elements LD[1] to LD[n], and a transistor M13. Each of the pixel circuits 101[1] to 101[n] includes a transistor M11, a transistor M12, a transistor M14, a capacitor C11, and a write control unit 102.

[0221] In this case, the light-emitting control unit 110XN is configured with the transistor M13, and the transistors M12, M14, and C11 included in each of the pixel circuits 101[1] to 101[n]. Therefore, the light-emitting control unit 110XN can be said to have a configuration in which the transistor M13 in each of the light-emitting control units 110 of the pixel circuits 101[1] to 101[n] is shared. In this way, by sharing one bootstrap transistor among n pixels, the number of transistors per pixel can be reduced. This reduces the area occupied by the transistors, thereby improving the resolution of the display device.

[0222] 33, the configuration corresponding to one pixel can be said to correspond to the semiconductor device 100 shown in Fig. 1A described above. Therefore, the above description can be referred to as appropriate, and detailed description will be omitted here.

[0223] Here, the transistor M13 included in the light-emission control unit 110XN may be provided outside the semiconductor device 100XN. In FIG. 33, an example in which the transistor M13 included in the light-emission control unit 110XN is provided in the drive circuit 120 is shown.

[0224] As shown in FIG. 33 , the driver circuit 120 includes a buffer BUF and a transistor M13. One of the source and the drain of the transistor M13 is connected to the semiconductor device 100XN. For example, one of the source and the drain of the transistor M13 is connected to the gate of the transistor M12 and the other terminal of the capacitor C11 in each of the pixel circuits 101[1] to 101[n]. The other of the source and the drain of the transistor M13 is connected to a wiring EM. The gate of the transistor M13 is connected to a wiring VL1. The output of the buffer BUF is connected to the wiring EM. The buffer BUF has a function of supplying a signal to the wiring EM.

[0225] The buffer BUF can be configured using, for example, p-channel transistors. Alternatively, it may be configured using both p-channel transistors and n-channel transistors. Alternatively, it may be configured using, for example, a CMOS circuit.

[0226] The drive circuit 120 is provided in, for example, a gate driver section 163 included in a display device 160 shown in FIG. 34A or the like, which will be described later.

[0227] <Structure Example of Display Device> Next, a display device according to one embodiment of the present invention will be described with reference to the drawings. At least a part of the semiconductor device according to one embodiment of the present invention can be used in the display device.

[0228] FIG. 34A is a block diagram illustrating a structural example of a display device of one embodiment of the present invention.

[0229] 34A , display device 160 includes pixel section 162, gate driver section 163, and source driver section 164. Pixel section 162 includes a plurality of pixels 161 arranged in a matrix of m rows and n columns (m is an integer of 2 or more, and n is an integer of 2 or more), for example.

[0230] The pixel 161 may include a functional element. Here, for example, if the functional element is a display element such as a liquid crystal element or a light-emitting element, the display device 160 functions as a display device (sometimes referred to as an output device). Furthermore, for example, if the functional element is a light-receiving element, the display device 160 functions as an imaging device (sometimes referred to as an input device). Note that the pixel 161 may include both a display element and a light-receiving element. In this case, the display device 160 functions as both a display device and an imaging device (sometimes referred to as an input / output device).

[0231] 34A, the pixel 161 arranged in the first row and first column is indicated as pixel 161[1,1], the pixel 161 arranged in the first row and nth column is indicated as pixel 161[1,n], the pixel 161 arranged in the mth row and first column is indicated as pixel 161[m,1], and the pixel 161 arranged in the mth row and nth column is indicated as pixel 161[m,n]. Note that the pixel 161 arranged in the uth row and vth column (u is an integer of 1 to m, and v is an integer of 1 to n) may be indicated as pixel 161[u,v]. Note that when describing matters common to each of a plurality of pixels 161, they may be described without the use of identifying symbols such as "[u,v]".

[0232] The display device 160 also has m gate lines 165 arranged in parallel, and the potential of each gate line 165 is controlled by a circuit included in a gate driver unit 163. The potential of each gate line 165 is applied to n pixels 161 arranged in the row direction. Note that a configuration may be adopted in which each gate line 165 includes multiple wirings in accordance with the configuration of the pixel 161.

[0233] The display device 160 also has n source lines 166 that are arranged in parallel and whose potentials are controlled by a circuit included in a source driver unit 164. The potential of one source line 166 is applied to m pixels 161 arranged in the column direction. Note that a configuration may be adopted in which one source line 166 includes multiple wirings in accordance with the configuration of the pixels 161.

[0234] The circuit included in the gate driver unit 163 functions as, for example, a scanning line driving circuit (sometimes called a gate line driving circuit, gate driver, scan driver, or row driver).

[0235] The circuit included in the source driver unit 164 functions as, for example, a signal line driver circuit (sometimes called a source line driver circuit, a source driver, a data driver, or a column driver).

[0236] FIG. 34B is a block diagram illustrating a modified example of the display device 160. The display device 160 shown in FIG. 34B differs from the display device 160 shown in FIG. 34A in that it has two gate driver units 163 arranged to face each other across the pixel unit 162. In the configuration shown in FIG. 34B, the potentials of m gate lines 165 are controlled by the two gate driver units 163. By using such a configuration, for example, the substantial wiring load (parasitic capacitance and parasitic resistance) can be reduced to one-fourth of the wiring load in the display device 160 shown in FIG. 34A. Therefore, the display device 160 can achieve at least one of higher speed, higher definition, higher resolution, a narrower frame, and a larger screen.

[0237] Note that in one embodiment of the present invention, various transistors can be used as transistors included in the display device 160. For example, Si transistors, OS transistors, or both Si transistors and OS transistors may be used.

[0238] OS transistors can be easily integrated because they can be freely arranged on, for example, a silicon substrate on which Si transistors are provided. Furthermore, OS transistors can be manufactured at low cost because they can be manufactured using the same manufacturing equipment as Si transistors.

[0239] Therefore, in the display device 160, for example, Si transistors including part of a silicon substrate may be used as transistors forming the source driver portion 164, and OS transistors provided over a silicon substrate may be used as transistors forming each of the gate driver portion 163 and the pixel portion 162. Note that at least some of the transistors forming the source driver portion 164 may be OS transistors, or at least some of the transistors forming each of the gate driver portion 163 and the pixel portion 162 may be Si transistors.

[0240] Furthermore, various circuits (which may include an arithmetic circuit, a memory circuit, and the like) that control the operation of the display device 160 may be provided using Si transistors that include part of the silicon substrate. Thus, one embodiment of the present invention can have a structure in which, for example, an OS transistor is provided over a silicon substrate on which a Si transistor is provided, and a display element or a light-receiving element is provided over the layer on which the OS transistor is provided.

[0241] In one embodiment of the present invention, at least a part of the above-described semiconductor devices 100, 100A, 100B, 100X2, 100XN, and the like can be used for the pixel 161. Furthermore, at least a part of the above-described semiconductor devices 100, 100C, 100D, 100X2, 100XN, and the like described in Embodiment 2 can be used for the pixel 161.

[0242] [Configuration Example of Driver Circuit] Next, a configuration example of each element circuit that can be used in the peripheral driver circuit of the display device 160 will be described.

[0243] In this specification and the like, the circuits included in the gate driver unit 163 and the circuits included in the source driver unit 164 of the display device 160 may be collectively referred to as "peripheral driver circuits."

[0244] The peripheral driver circuit can be configured using various element circuits. Examples of such element circuits include a shift register circuit, a flip-flop circuit, a latch circuit, a buffer circuit, an inverter circuit, and a level shifter circuit. Other examples include a multiplexer circuit, a demultiplexer circuit, a source follower circuit, a source-grounded amplifier circuit, a sample-and-hold circuit, and a switch circuit (e.g., a transmission gate and an analog switch). Other examples include a current-voltage converter circuit, an analog-to-digital converter circuit, a digital-to-analog converter circuit, an operational amplifier circuit, a comparator circuit, a pass-transistor logic circuit, an encoder circuit, a decoder circuit, and a gate circuit (e.g., an AND circuit, an OR circuit, and a NOT circuit). Other examples include a combination of these circuits. These element circuits can be configured using, for example, transistors and capacitors.

[0245] In one embodiment of the present invention, various transistors can be used as transistors included in a peripheral driver circuit. For example, Si transistors can be used as some or all of the transistors included in the peripheral driver circuit. Alternatively, for example, OS transistors can be used. Alternatively, for example, both OS transistors and Si transistors can be used.

[0246] OS transistors have the characteristic of having an extremely small off-state current. Furthermore, they have the characteristic that the off-state current hardly increases even in a high-temperature environment, and the on-state current is not easily reduced. Si transistors have a higher operating speed than OS transistors. Furthermore, for example, by connecting the gate of an n-channel transistor and the gate of a p-channel transistor, a CMOS circuit (e.g., a circuit that operates complementarily, a CMOS logic gate, or a CMOS logic circuit) can be configured.

[0247] Therefore, as transistors included in the peripheral driver circuits, OS transistors and Si transistors can be used as appropriate.

[0248] 35A to 35E are circuit diagrams illustrating configuration examples of a semiconductor device that can be used in a peripheral driver circuit. The semiconductor device can be used, for example, as part of a scanning line driver circuit (such as a circuit included in the gate driver unit 163). It can also be used, for example, as part of a shift register.

[0249] A semiconductor device 180 shown in FIG. 35A includes m register units 181 and m buffer units 182. The semiconductor device 180 is connected to m wirings GLa and m wirings GLb. The m register units 181 are connected to each other via m wirings SR. FIG. 35A excerpts a portion of the semiconductor device 180, illustrating register units 181_u to 181_u+2, buffer units 182_u to 182_u+2, wirings SR_u-1 to SR_u+4, wirings GLa_u to GLa_u+2, and wirings GLb_u to GLb_u+2. Note that m is an integer equal to or greater than 2. Also, u is an integer equal to or greater than 1 and equal to or less than m.

[0250] FIG. 35B is a circuit diagram illustrating an example of the configuration of the register unit 181 and the buffer unit 182. FIG. 35C is a circuit block corresponding to the register unit 181 and the buffer unit 182. The register unit 181 can be applied to each of the register units 181_1 to 181_m. The buffer unit 182 can be applied to each of the buffer units 182_1 to 182_m. That is, for example, in the register unit 181_u, the wiring IN81 is connected to the wiring SR_u-1, the wiring IN82 is connected to the wiring SR_u+2, and the wiring OUT81 is connected to the wiring SR_u. Furthermore, for example, in the buffer unit 182_u, the wiring OUT8A is connected to the wiring GLa_u, and the wiring OUT8B is connected to the wiring GLb_u. Note that the wirings IN81, IN8A, IN8B, VLD, and VLS are not shown in FIGS. 35A and 35C . The same applies to the register units 181_1 to 181_u-1 and the register units 181_u+1 to 181_m, and the same applies to the buffer units 182_1 to 182_u-1 and the buffer units 182_u+1 to 182_m.

[0251] That is, in the semiconductor device 180, the wiring OUT81 in the register portion 181_u-1 is connected to the wiring IN81 in the register portion 181_u through the wiring SR_u-1, and the wiring OUT81 in the register portion 181_u is connected to the wiring IN81 in the register portion 181_u+1 through the wiring SR_u. With this configuration, the register portions 181_1 to 181_m are sequentially selected, and desired potentials can be applied to the wirings GLa_u and GLb_u in the buffer portion 182_u connected to the selected register portion 181_u. Note that in the semiconductor device 180, the potential of the wiring VLS is applied to the wirings GLa_u and GLb_u in the buffer portion 182_u connected to the unselected register portion 181_u.

[0252] The register unit 181 shown in FIG. 35B includes transistors M81, M82, M83, M84, M85, and M86. The transistor M81 brings the wiring VLD and the wiring NL81 into a conductive state or a non-conductive state depending on the potential of the wiring IN81. The transistor M82 brings the wiring VLD and the wiring NL82 into a conductive state or a non-conductive state depending on the potential of the wiring IN82. The transistor M83 brings the wiring VLS and the wiring NL81 into a conductive state or a non-conductive state depending on the potential of the wiring NL82. The transistor M84 brings the wiring VLS and the wiring NL82 into a conductive state or a non-conductive state depending on the potential of the wiring IN81. The transistor M85 has a function of bringing the wiring IN83 and the wiring OUT81 into a conductive state or a non-conductive state depending on the potential of the wiring NL81. The transistor M86 has a function of bringing the wiring VLS and the wiring OUT81 into a conductive state or a non-conductive state depending on the potential of the wiring NL82.

[0253] 35B includes a transistor M8A, a transistor M8B, a transistor M8C, and a transistor M8D. The transistor M8A brings the wiring IN8A and the wiring OUT8A into a conductive state or a non-conductive state depending on the potential of the wiring NL81. The transistor M8B brings the wiring IN8B and the wiring OUT8B into a conductive state or a non-conductive state depending on the potential of the wiring NL81. The transistor M8C brings the wiring VLS and the wiring OUT8A into a conductive state or a non-conductive state depending on the potential of the wiring NL82. The transistor M8D brings the wiring VLS and the wiring OUT8B into a conductive state or a non-conductive state depending on the potential of the wiring NL82.

[0254] FIG. 35D is a timing chart illustrating an example of the operation of the register unit 181 and the buffer unit 182 shown in FIG. 35B.

[0255] In the following description of the operation, it is assumed that a potential H is applied to the wiring VLD and a potential L is applied to the wiring VLS. It is also assumed that either the potential H or the potential L is applied to each of the wirings IN81, IN82, IN83, IN8A, and IN8B. Note that the potential H is assumed to be larger than the potential L. For example, it is assumed that the difference between the potential H and the potential L is larger than the threshold voltage of the transistor.

[0256] 35D shows potentials (potential H or potential L) applied to the wirings IN81, IN82, IN83, IN8A, and IN8B in each period (periods T81 to T83) of the operation. The timing chart also shows changes in the potentials of the wirings NL81, NL82, OUT81, OUT8A, and OUT8B.

[0257] In the period T81, a potential L is applied to the wirings IN81 and IN82. The potential of the wiring NL82 is also assumed to be a potential H. Therefore, the potential L is applied to the wiring NL81. At this time, the transistors M85, M8A, and M8B are each in an off state (non-conductive state), and the transistors M86, M8C, and M8D are each in an on state (conductive state). Therefore, the potential L is applied to the wirings OUT81, OUT8A, and OUT8B, regardless of the potentials (potential H or potential L) of the wirings IN83, IN8A, and IN8B. In the following description of the operation, unless otherwise specified, the potential of each wiring is assumed to be maintained at the potential of the previous period.

[0258] In the period T82, a potential H is applied to the wiring IN81, so that the potential of the wiring NL82 becomes a potential L and the potential of the wiring NL81 becomes a potential H. Then, the transistors M85, M8A, and M8B are turned on, and the transistors M86, M8C, and M8D are turned off. Therefore, the potentials (potential H or potential L) of the wirings IN83, IN8A, and IN8B are applied to the wirings OUT81, OUT8A, and OUT8B, respectively, via the transistors M85, M8A, and M8B. Note that even if the potential L is applied to the wiring IN81 after that, the potentials of the wirings NL82 and NL81 are maintained.

[0259] In the period T83, a potential H is applied to the wiring IN82, so that the potential of the wiring NL82 becomes the potential H and the potential of the wiring NL81 becomes the potential L. Then, the transistors M85, M8A, and M8B are turned off, and the transistors M86, M8C, and M8D are turned on. Therefore, the potential L is applied to the wirings OUT81, OUT8A, and OUT8B regardless of the potentials (potential H or potential L) of the wirings IN83, IN8A, and IN8B. Note that even if the potential L is applied to the wiring IN82 after that, the potentials of the wirings NL82 and NL81 are maintained.

[0260] 35E is a circuit diagram illustrating a modified example of the register unit 181 and the buffer unit 182. The register unit 181a and the buffer unit 182a shown in FIG. 35E differ from the register unit 181 and the buffer unit 182 in that they include a bootstrap circuit. That is, the register unit 181a includes a transistor M87 and a capacitance element C81 in addition to the register unit 181, and the buffer unit 182a includes a transistor M8E, a transistor M8F, a capacitance element C8A, and a capacitance element C8B in addition to the buffer unit 182. Note that the capacitance elements C81, C8A, and C8B are sometimes referred to as bootstrap capacitances.

[0261] The gate of the transistor M87 is connected to the wiring VLD. The gate of the transistor M85 is connected to the wiring NL81 via the source and drain of the transistor M87. The gate of the transistor M85 is connected to the wiring OUT81 via the capacitor C81.

[0262] The gate of the transistor M8E is connected to the wiring VLD. The gate of the transistor M8A is connected to the wiring NL81 via the source and drain of the transistor M8E. The gate of the transistor M8A is connected to the wiring OUT8A via the capacitor C8A.

[0263] The gate of the transistor M8F is connected to the wiring VLD. The gate of the transistor M8B is connected to the wiring NL81 via the source and drain of the transistor M8F. The gate of the transistor M8B is connected to the wiring OUT8B via the capacitor C8B.

[0264] In the register unit 181, when the transistor M85 transfers the potential H from the wiring IN83 to the wiring OUT81, a potential drop occurs due to a threshold voltage. Therefore, by employing a bootstrap circuit as in the register unit 181a, the transistor M85 can be maintained in an on state by capacitive coupling due to the bootstrap capacitance. Therefore, the potential H can be transferred to the wiring OUT81 without a potential drop due to the threshold voltage.

[0265] Similarly, in the buffer portion 182, when the transistor M8A transfers the potential H from the wiring IN8A to the wiring OUT8A, a potential drop occurs due to the threshold voltage. Also, when the transistor M8B transfers the potential H from the wiring IN8B to the wiring OUT8B, a potential drop occurs due to the threshold voltage. Therefore, by employing a bootstrap circuit as in the buffer portion 182a, the transistors M8A and M8B can be maintained in an on state by capacitive coupling due to bootstrap capacitance. Therefore, the potential H can be transferred to the wiring OUT8A and the wiring OUT8B without a potential drop due to the threshold voltage.

[0266] In one embodiment of the present invention, at least a part of the semiconductor device 180 can be applied to one or both of the gate driver portion 163 and the source driver portion 164 included in the display device 160. For example, at least a part of the semiconductor device 180 can be applied to the gate driver portion 163. In this case, the wirings OUT8A and OUT8B may be connected to the pixel 161. For example, when any of the various semiconductor devices 100 described above or any of the various semiconductor devices 100 described in Embodiment 2 to be described later is used as the pixel 161, the wirings OUT8A and OUT8B may be connected to the wirings GP and EM, respectively. Note that the gate driver portion 163 may be provided with a circuit that has a function of inverting the logic of a signal output from the semiconductor device 180. The gate driver portion 163 may also be provided with at least a part of the driver circuit 120 described in FIG. 33 or the driver circuit 120 described in FIG. 69 of Embodiment 2 to be described later.

[0267] [Configuration Example of Protection Circuit] Next, a configuration example of an electrostatic discharge (ESD) protection circuit that can be used in the display device 160 will be described.

[0268] 36A is a circuit diagram illustrating an application example of an ESD protection circuit according to one embodiment of the present invention, in which the semiconductor device 100 and the protection circuit 130 shown in FIG. 37A of Embodiment 2, which will be described later, are illustrated as an example.

[0269] The protection circuit 130 is provided, for example, in the gate driver unit 163 of the display device 160 shown in Fig. 34A etc. The protection circuit 130 is provided, for example, in the gate line 165 between the pixel unit 162 and the gate driver unit 163 in the display device 160 shown in Fig. 34A etc.

[0270] 36A is just an example, and at least a part of the various semiconductor devices 100, 100A, 100B, 100X2, 100XN, etc. described above can be applied instead of the semiconductor device 100 shown in Fig. 36A. Also, at least a part of the various semiconductor devices 100, 100A, 100B, 100X2, 100XN, etc. described in a second embodiment, which will be described later, can be applied instead of the semiconductor device 100 shown in Fig. 36A.

[0271] The protection circuit 130 includes a transistor M31 and a transistor M32. One of the source and the drain of the transistor M31 is connected to a wiring VLD. The other of the source and the drain of the transistor M31 is connected to a wiring SIG. The gate of the transistor M31 is connected to a wiring SIG. One of the source and the drain of the transistor M32 is connected to a wiring SIG. The other of the source and the drain of the transistor M32 is connected to a wiring VLS. The gate of the transistor M32 is connected to a wiring VLS. The wiring VLD and the wiring VLS each function as a power supply line. The wiring SIG functions as a signal line.

[0272] The transistors M31 and M32 are, for example, n-channel transistors. In this case, for example, a high potential of a signal supplied to the wiring SIG is applied to the wiring VLD, and a low potential of a signal supplied to the wiring SIG is applied to the wiring VLS. Note that the transistor M31 may be a p-channel transistor. In this case, the gate of the transistor M31 is connected to the wiring VLD. The transistor M32 may be a p-channel transistor. In this case, the gate of the transistor M32 is connected to the wiring SIG.

[0273] In the protection circuit 130, a surge (for example, one or both of a transient overvoltage and an overcurrent) generated in the wiring SIG due to ESD or the like can be released to at least one of the wiring VLD and the wiring VLS. This makes it possible to protect another circuit connected to the wiring SIG from the surge. The configuration including the protection circuit 130 can, for example, prevent a transistor included in another circuit connected to the wiring SIG from being destroyed. Therefore, reliability can be improved.

[0274] 36A , when the wiring SIG of the protection circuit 130 is connected to the wiring GP of the semiconductor device 100, the transistor M14 connected to the wiring GP can be prevented from being destroyed by a surge generated by ESD or the like, thereby improving reliability.

[0275] Note that Figure 36A illustrates an example in which the protection circuit 130 is connected to the wiring GP of the semiconductor device 100, but the protection circuit 130 may also be connected to each of the other wirings (wiring EM, wiring EM2, wiring GW, wiring GC, wiring GI, and wiring GB, etc.) of the semiconductor device 100.

[0276] 36B is a modified example of the protection circuit 130 shown in FIG. 36A , further including a resistor element R31 and a resistor element R32. The other of the source or drain of the transistor M31 is connected to one terminal (also referred to as one of a pair of terminals, or sometimes referred to as a first terminal) of the resistor element R31. The gate of the transistor M31 is connected to one terminal of the resistor element R31. The other terminal (also referred to as the other of the pair of terminals, or sometimes referred to as a second terminal) of the resistor element R31 is connected to the wiring SIG. One terminal of the resistor element R32 is connected to the wiring SIG. The other of the source or drain of the transistor M32 is connected to the other terminal of the resistor element R32.

[0277] 36C is a modified example of the protection circuit 130 shown in FIG. 36A, and further includes a resistor R31 and a resistor R32. One terminal of the resistor R31 is connected to the wiring VLD. One of the source or drain of the transistor M31 is connected to the other terminal of the resistor R31. The other of the source or drain of the transistor M32 is connected to one terminal of the resistor R32. The gate of the transistor M32 is connected to one terminal of the resistor R32. The other terminal of the resistor R32 is connected to the wiring VLS.

[0278] 36D is a modified example of the protection circuit 130 shown in FIG. 36A, further including a resistor R31 and a resistor R32. The other of the source or drain of the transistor M31 is connected to one terminal of the resistor R31. The gate of the transistor M31 is connected to the wiring SIG. The other terminal of the resistor R31 is connected to the wiring SIG. The other of the source or drain of the transistor M32 is connected to one terminal of the resistor R32. The gate of the transistor M32 is connected to the wiring VLS. The other terminal of the resistor R32 is connected to the wiring VLS.

[0279] 36B to 36D , when a surge generated in the wiring SIG due to ESD or the like is released to at least one of the wiring VLD and the wiring VLS, power can be consumed by at least one of the resistor elements R31 and R32. This enhances the effect of protecting another circuit connected to the wiring SIG from a surge, thereby improving reliability.

[0280] 36E is a modification of the protection circuit 130 shown in FIG. 36A, and further includes a resistor R33. The other of the source and the drain of the transistor M31 is connected to the wiring SIG_E. The gate of the transistor M31 is connected to the wiring SIG_E. One of the source and the drain of the transistor M32 is connected to the wiring SIG_E. One terminal of the resistor R33 is connected to the wiring SIG_E. The other terminal of the resistor R33 is connected to the wiring SIG_I.

[0281] 36E, when a surge generated in the wiring SIG_E due to ESD or the like is transmitted to the wiring SIG_I, the power can be consumed by the resistance element R33. Therefore, it is possible to enhance the effect of protecting another circuit connected to the wiring SIG_I from the surge, and improve reliability.

[0282] Here, by using a transistor with a small off-state current for each of the transistors M31 and M32, it is possible to prevent current from flowing from the wiring SIG to at least one of the wirings VLD and VLS when a signal is applied to the wiring SIG. Furthermore, by using a transistor with a large on-state current for each of the transistors M31 and M32, it is possible to effectively allow a surge generated in the wiring SIG due to ESD or the like to escape to at least one of the wirings VLD and VLS. Therefore, it is preferable to use a transistor with a small off-state current and a large on-state current for each of the transistors M31 and M32.

[0283] In one embodiment of the present invention, an OS transistor can be used as each of the transistors M31 and M32, for example, as a transistor with extremely low off-state current. Various oxide semiconductors can be used for the OS transistor. In particular, it is preferable to use an oxide semiconductor that exhibits low off-state current and high on-state current. Examples of oxide semiconductors that exhibit low off-state current and high on-state current include indium oxide. Details of oxide semiconductors that can be used for OS transistors will be described in Embodiment 4 below. Indium oxide, which is one of oxide semiconductors, will also be described in detail in Embodiment 9.

[0284] Furthermore, various resistance elements can be used as each of the resistance elements R31, R32, and R33. For example, a resistance element having silicon (such as a diffused resistor or a polysilicon resistor) can be used as the resistance element. For example, a resistance element having a conductive material (such as a wiring resistor) can be used as the resistance element. For example, a resistance element having a metal oxide can be used as the resistance element. The metal oxide may include, for example, indium oxide.

[0285] Note that one embodiment of the present invention is not limited to the configuration examples, operation examples, and the like described in this embodiment. The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments, etc.

[0286] This embodiment will describe a configuration example in which n-channel transistors are used as the transistors in the semiconductor device 100 or the like described in the above-described Embodiment 1. Note that the description of the above-described Embodiment 1 can be referred to as appropriate, and therefore the description may be omitted.

[0287] <Structure Example 1 of Semiconductor Device> Each of FIGS. 37A, 37B, 38A, and 38B is a circuit diagram illustrating a semiconductor device 100 of one embodiment of the present invention.

[0288] 37A and 37B, the semiconductor device 100 includes a pixel circuit 101 and a light-emitting element LD. The pixel circuit 101 includes at least a transistor M11 and a light-emitting control unit 110. The light-emitting control unit 110 includes a transistor M12, a transistor M13, and a transistor M14. The light-emitting control unit 110 may further include a capacitive element C11. The semiconductor device 100 can also be referred to as a pixel.

[0289] One of the source or drain of the transistor M11 is connected to one of the source or drain of the transistor M12, one of the source or drain of the transistor M14, and one terminal of the capacitor C11. The gate of the transistor M12 is connected to one of the source or drain of the transistor M13 and the other terminal of the capacitor C11. The other of the source or drain of the transistor M13 is connected to a wiring EM. The gate of the transistor M13 is connected to a wiring VL1. The other of the source or drain of the transistor M14 is connected to a wiring VL2. The gate of the transistor M14 is connected to a wiring GP. Note that the capacitor C11 may be a parasitic capacitance between the gate of the transistor M12 and one of the source or drain.

[0290] A wiring connected to the gate of transistor M11 or the like may be referred to as node ND1. A wiring connected to one of the source or drain of transistor M11 and one of the source or drain of transistor M12 may be referred to as node ND2. A wiring connected to the other of the source or drain of transistor M11 may be referred to as node ND3. A wiring connected to the gate of transistor M12 or the like may be referred to as node ND4. A wiring connected to the other of the source or drain of transistor M12 may be referred to as node ND5. Note that the terms "node" and "wiring" may be interchangeable.

[0291] The light-emitting element LD, the transistor M11, and the transistor M12 are provided in a current path between the wiring ANO and the wiring CATH. That is, the current flowing through the light-emitting element LD also flows through the channel formation region of the transistor M11 and the channel formation region of the transistor M12. Note that, in addition to the transistor M11 and the transistor M12, another transistor may be provided in the current path.

[0292] The semiconductor device 100, the light-emitting element LD included in the semiconductor device 100, the pixel circuit 101, the transistor M11 included in the pixel circuit 101, the light-emission control unit 110, and the transistors M12, M13, M14, and the capacitor C11 included in the light-emission control unit 110 shown in this embodiment can refer to the description of the first embodiment as appropriate. In addition, the wiring EM, the wiring GP, the wiring ANO, the wiring CATH, the wiring VL1, the wiring VL2, and the like can refer to the description of the first embodiment as appropriate.

[0293] 37A , for example, the other of the source or drain of transistor M11 (corresponding to node ND3) is connected to one terminal of light-emitting element LD (e.g., the anode of a light-emitting diode) without passing through the source and drain of another transistor (this also means that the other of the source or drain of transistor M11 is directly connected to one terminal of light-emitting element LD), or is connected to one terminal of light-emitting element LD via the source and drain of another transistor (this also means that the other of the source or drain of transistor M11 is indirectly connected to one terminal of light-emitting element LD). The other terminal of light-emitting element LD (e.g., the cathode of a light-emitting diode) is connected to wiring CATH. The other of the source or drain of transistor M12 (corresponding to node ND5) is connected to wiring ANO.

[0294] 37B , for example, the other of the source and drain of transistor M11 (corresponding to node ND3) is connected to wiring CATH without passing through the source and drain of another transistor (this also means that the other of the source and drain of transistor M11 is directly connected to wiring CATH), or is connected to wiring CATH via the source and drain of another transistor (this also means that the other of the source and drain of transistor M11 is indirectly connected to wiring CATH). The other of the source and drain of transistor M12 (corresponding to node ND5) is connected to the other terminal of light-emitting element LD (e.g., the cathode of a light-emitting diode). One terminal of light-emitting element LD (e.g., the anode of a light-emitting diode) is connected to wiring ANO.

[0295] In the semiconductor device 100 illustrated in each of FIGS. 37A and 37B, n-channel transistors can be used for the transistors (such as the transistors M11 to M14).

[0296] 37A and 37B, at least one of the transistors may be a p-channel transistor. In this case, in the description of the semiconductor device 100, the descriptions regarding one terminal (e.g., the anode of the light-emitting diode) and the other terminal (e.g., the cathode of the light-emitting diode) of the light-emitting element LD may be appropriately interchanged. Furthermore, descriptions regarding the positive / negative relationship of voltage and the magnitude relationship of potential may be appropriately interchanged. For example, "high potential" may be appropriately interchanged as "low potential" and "low potential" may be appropriately interchanged as "high potential". Furthermore, for example, "increase potential" may be appropriately interchanged as "decrease potential" and "decrease potential" may be appropriately interchanged as "increase potential".

[0297] In the semiconductor device 100, the transistor M11 preferably has high saturation because it functions as a drive transistor that controls the amount of current flowing through the light-emitting element LD. To increase the saturation of the transistor M11, for example, it is preferable to increase the channel length of the transistor M11. Increasing the saturation of the transistor M11 allows a stable current to flow through the light-emitting element LD, thereby stabilizing the light emission intensity.

[0298] Furthermore, since the transistor M12 is provided in a current path including the light emitting element LD, it is preferable that the on-state current of the transistor M12 is large. In order to increase the on-state current of the transistor M12, for example, it is preferable to reduce the channel length of the transistor M12.

[0299] Since each of the transistors M12, M13, and M14 functions as a switch, it is preferable that the gate capacitance be small in order to improve the operating speed of the display device, and it is preferable that the area of ​​the channel formation region (corresponding to the multiplication of the channel length and the channel width) be small in order to improve the definition of the display device.

[0300] Based on these technical concepts, for example, the channel length of each of transistors M12, M13, and M14 may be smaller than the channel length of transistor M11. Furthermore, for example, the channel width of each of transistors M12, M13, and M14 may be smaller than the channel width of transistor M11. Furthermore, for example, the area of ​​the channel formation region of each of transistors M12, M13, and M14 may be smaller than the area of ​​the channel formation region of transistor M11. Note that the channel length of each of transistors M12, M13, and M14 may be the minimum channel length determined by the minimum processing dimension in the manufacturing process. Furthermore, the channel width of each of transistors M12, M13, and M14 may be the minimum channel width determined by the minimum processing dimension in the manufacturing process.

[0301] In the semiconductor device 100, the capacitance element C11 has a function of holding the gate voltage of the transistor M12, and therefore, for example, the capacitance of the capacitance element C11 may be larger than the gate capacitance of the transistor M12. For example, the area where a pair of electrodes (corresponding to a conductive layer functioning as one terminal and a conductive layer functioning as the other terminal) of the capacitance element C11 overlap each other may be larger than the area of ​​the channel formation region of the transistor M12.

[0302] 38A and 38B , the semiconductor device 100 can further include a write control unit 102 in the pixel circuit 101. The write control unit 102 is connected to at least the wiring SL, the gate of the transistor M11 (corresponding to the node ND1), and the other of the source and the drain of the transistor M11 (corresponding to the node ND3).

[0303] For the write control unit 102 included in the semiconductor device 100 shown in this embodiment, the pixel circuit 101 including the write control unit 102, and the like, the description of the above-mentioned first embodiment can be referred to as appropriate.

[0304] In addition, the operation of the semiconductor device 100 described in this embodiment mode can also be referred to as appropriate in the description of the first embodiment mode.

[0305] That is, when the transistor M12 is switched from an off state to an on state, a predetermined potential can be applied from the wiring VL2 to the node ND2 by turning on the transistor M14, thereby allowing a stable gate voltage to be applied to the transistor M12 when the transistor M12 is turned on.

[0306] After that, by turning off the transistor M14, a current based on the gate voltage of the transistor M11 flows through the light-emitting element LD. At this time, the potential of the node ND2 changes depending on the voltage-current characteristics of the light-emitting element LD. At this time, by providing the transistor M13 and the capacitor C11, the potential of the node ND4 also changes in accordance with the change in the potential of the node ND2 due to the capacitive coupling of the capacitor C11. As a result, the gate voltage of the transistor M12 can be maintained after the transistor M12 is turned on.

[0307] This action makes it possible to stabilize the light emission intensity of the light emitting element LD during operation of the semiconductor device 100. This makes it possible to stabilize the light emission brightness of the display device.

[0308] Here, the potential applied to the node ND2 from the wiring VL2 via the transistor M14 is preferably lower than the potential of the node ND2 immediately before the transistor M12 is switched from the off state to the on state. That is, the potential applied to the node ND2 from the wiring VL2 is preferably lower than the potential corresponding to the image signal, for example, and may be the potential of the wiring CATH. This allows the gate voltage applied to the transistor M12 to be increased. In other words, even if the amplitude of the signal applied from the wiring EM (a signal that controls the on / off state of the transistor M12) is reduced, a sufficient gate voltage can be applied to turn on the transistor M12.

[0309] Here, for the effects obtained by the semiconductor device 100 shown in this embodiment, the description of the first embodiment can be referred to as appropriate.

[0310] For a transistor that can be used in the semiconductor device 100 described in this embodiment, the description in Embodiment 1 can be referred to as appropriate.

[0311] [Another Configuration Example 1] Figure 39A is a circuit diagram illustrating a modified example of the semiconductor device 100 shown in Figure 38A. Figure 38A shows a configuration example of the semiconductor device 100 in which one of the source or drain of the transistor M14 is connected to one of the source or drain of the transistor M12 (corresponding to node ND2), but this is not limiting. For example, Figure 39A shows a configuration example of the semiconductor device 100 in which one of the source or drain of the transistor M14 is connected to the other of the source or drain of the transistor M11 (corresponding to node ND3). In the semiconductor device 100 shown in Figure 39A, a predetermined potential can be applied from the wiring VL2 to the node ND2 via the transistors M14 and M11.

[0312] [Another Configuration Example 2] FIG. 39B is a circuit diagram illustrating a modified example of the semiconductor device 100 shown in FIG. 38A . FIG. 38A illustrates a configuration example of the semiconductor device 100 in which the light-emitting control unit 110 is provided between the wiring ANO and the transistor M11 in a current path including the light-emitting element LD, but this is not limiting. For example, FIG. 39B illustrates a configuration example of the semiconductor device 100 in which the light-emitting control unit 110 is provided between the transistor M11 and the light-emitting element LD in a current path including the light-emitting element LD. In the semiconductor device 100 shown in FIG. 39B , one of the source or drain of the transistor M11 is connected to the wiring ANO without passing through the source and drain of another transistor (this may also be referred to as one of the source or drain of the transistor M11 being directly connected to the wiring ANO), or is connected to the wiring ANO via the source and drain of another transistor (this may also be referred to as one of the source or drain of the transistor M11 being indirectly connected to the wiring ANO). The other of the source or drain of the transistor M11 is connected to the other of the source or drain of the transistor M12. One of the source and drain of the transistor M12 is connected to one terminal (for example, the anode of the light-emitting diode) of the light-emitting element LD, and the other terminal (for example, the cathode of the light-emitting diode) of the light-emitting element LD is connected to the wiring ANO.

[0313] <Specific Example of Semiconductor Device> Next, a specific example of the configuration of the semiconductor device 100 will be described.

[0314] The specific examples and modifications of the semiconductor device 100 described below can be applied to the semiconductor device 100 described above with or without illustrations.

[0315] [Specific Example 1] FIG. 40 is a circuit diagram illustrating a specific example of the configuration of the semiconductor device 100 shown in FIGS. 37A and 38A.

[0316] As shown in Fig. 40, the semiconductor device 100C further includes a write control unit 102C in addition to the semiconductor device 100 shown in Fig. 37A. The write control unit 102C includes transistors M21, M22, M23, M24, and a capacitance element C21. In Fig. 40, the pixel circuit 101C corresponds to the pixel circuit 101. The write control unit 102C corresponds to the write control unit 102 in the semiconductor device 100 shown in Fig. 38A. Therefore, the above description can be referred to as appropriate, and the description may be omitted here.

[0317] The gate of the transistor M11 (corresponding to node ND1) is connected to one of the source or drain of the transistor M23 and one terminal of the capacitance element C21. The one of the source or drain of the transistor M11 (corresponding to node ND2) is further connected to the other of the source or drain of the transistor M23. The other of the source or drain of the transistor M11 (corresponding to node ND3) is connected to one of the source or drain of the transistor M21 and one of the source or drain of the transistor M22. The other of the source or drain of the transistor M22 is connected to one terminal of the light-emitting element LD, the other terminal of the capacitance element C21, and one of the source or drain of the transistor M24. The other of the source or drain of the transistor M21 is connected to the wiring SL. The gate of the transistor M21 is connected to the wiring GW. The gate of the transistor M22 is connected to the wiring EM2. The gate of the transistor M23 is connected to the wiring GC. The other of the source and the drain of the transistor M24 is connected to the wiring VL3, and the gate of the transistor M24 is connected to the wiring GI.

[0318] A wiring connected to one terminal of the light emitting element LD may be referred to as a node ND6. Note that the terms "node" and "wiring" may be interchangeable.

[0319] The transistors M21, M22, M23, M24, and the capacitor C21 included in the semiconductor device 100C can be referred to as appropriate for each of them in the above-described embodiment 1. The wirings SL, EM, EM2, GW, GI, GC, GP, ANO, CATH, VL1, VL2, and VL3 can be referred to as appropriate for each of them in the above-described embodiment 1.

[0320] In the semiconductor device 100C, a potential corresponding to an image signal supplied from the wiring SL can be applied to the gate of the transistor M11. At this time, a potential obtained by correcting variations in the threshold voltage of the transistor M11 can be applied.

[0321] In the semiconductor device 100C shown in FIG. 40, n-channel transistors can be used for the transistors M11 to M14 and the transistors M21 to M24.

[0322] In the semiconductor device 100C, at least one of the transistors may be a p-channel transistor.

[0323] In the semiconductor device 100C, a transistor with low off-state current can be used for at least one of the transistors. In this case, for example, a transistor with low off-state current is preferably used for each of the transistors M13 and M23. An OS transistor, for example, may be used as the transistor with extremely low off-state current. By using a transistor with extremely low off-state current as the transistor M13, the potential of the gate of the transistor M12 (corresponding to the node ND4) can be held for a long period of time. By using a transistor with extremely low off-state current as the transistor M23, the potential of the gate of the transistor M11 (corresponding to the node ND1) can be held for a long period of time.

[0324] As a result, in a display device using the semiconductor device 100C, for example, when displaying a still image, the frequency of writing image data can be reduced, thereby reducing the power consumption of the display device.

[0325] In the semiconductor device 100C, the transistor M11 functioning as a drive transistor preferably has high saturation and small hysteresis.

[0326] In one embodiment of the present invention, an OS transistor, for example, can be used as the transistor M11, which has high saturation property and small hysteresis.

[0327] Here, a transistor with a large on-state current may be used as the transistor M11. This allows, for example, a sufficient on-state current to be obtained even when the channel width of the transistor M11 is reduced, thereby reducing the layout area. This can improve the resolution of the display device. Furthermore, reducing the channel width of the transistor M11 can sometimes increase the aperture ratio of the pixel. This can achieve at least one of higher brightness and higher reliability of the display device.

[0328] Various oxide semiconductors can be used for the OS transistor. Examples of oxide semiconductors that can have a large on-state current include indium oxide. Details of oxide semiconductors that can be used for OS transistors will be described later in Embodiment 4. Indium oxide, which is one of oxide semiconductors, will also be described in detail in Embodiment 9.

[0329] In the semiconductor device 100C, for example, an OS transistor may be used for the transistor M23, and Si transistors may be used for the transistors M11 to M14, the transistor M21, the transistor M22, and the transistor M24. Alternatively, for example, OS transistors may be used for the transistors M11 to M14 and the transistors M21 to M24. Alternatively, Si transistors may be used for the transistors M11 to M14 and the transistors M21 to M24. Alternatively, for example, an OS transistor may be used for at least one of the transistors M11 to M14 and the transistors M21 to M24, and Si transistors may be used for the rest.

[0330] [Specific Example 2] FIG. 41 is a circuit diagram illustrating a specific example of the configuration of the semiconductor device 100 shown in FIG. 39B.

[0331] As shown in Fig. 41 , the semiconductor device 100D has a write control unit 102D as the write control unit 102 of the semiconductor device 100 shown in Fig. 39B . Furthermore, in the semiconductor device 100D, the transistor M11 has a back gate. The write control unit 102D has transistors M21, M22, M23, M24, and capacitive elements C21 and C22. In Fig. 41 , the pixel circuit 101D corresponds to the pixel circuit 101. Therefore, the above description can be referred to as appropriate, and the description may be omitted here.

[0332] The gate of the transistor M11 (corresponding to node ND1) is connected to one of the source or drain of the transistor M21, one of the source or drain of the transistor M23, and one terminal of the capacitor C21. The back gate of the transistor M11 is connected to one of the source or drain of the transistor M24 and one terminal of the capacitor C22. The other of the source or drain of the transistor M11 is further connected to one of the source or drain of the transistor M22, the other of the source or drain of the transistor M23, the other terminal of the capacitor C21, and the other terminal of the capacitor C22. The one of the source or drain of the transistor M11 is connected to a wiring ANO. The other of the source or drain of the transistor M21 is connected to a wiring SL. The gates of the transistors M21 and M22 are each connected to a wiring GW. The other of the source or drain of the transistor M22 is connected to a wiring VL3. The gate of the transistor M23 and the gate of the transistor M24 are connected to the wiring GC. The other of the source and the drain of the transistor M24 is connected to the wiring VL4.

[0333] The transistors M21, M22, M23, and M24 each function as a switch. The capacitor C21 holds a voltage between the gate and the other of the source or drain of the transistor M11 (also referred to as a gate voltage). The capacitor C22 holds a voltage between the backgate and the other of the source or drain of the transistor M11 (also referred to as a backgate voltage). The wirings GW and GC each function as a signal line. The wirings VL3 and VL4 each function as a power supply line.

[0334] The threshold voltage of the transistor M11 can be changed depending on the potential applied to the back gate. At this time, a back gate voltage that corrects the threshold voltage of the transistor M11 to 0 V is held in the capacitance element C22 by a signal applied to the wiring GC. This allows a current that is not dependent on the threshold voltage of the transistor M11 to flow through the light-emitting element LD.

[0335] In the semiconductor device 100D, a transistor with a low off-state current can be used for at least one of the transistors. An OS transistor, for example, may be used as a transistor with an extremely low off-state current. For example, by using a transistor with an extremely low off-state current as the transistor M24, the potential of the back gate of the transistor M11 can be maintained for a long period of time. This allows the threshold voltage of the transistor M11 to be corrected to 0 V for a long period of time. Therefore, for example, the frequency of correcting the threshold voltage variation can be reduced. This allows the power consumption of the display device to be reduced.

[0336] Although not shown, the gate of the transistor M21 and the gate of the transistor M22 may be connected to separate wirings, and although not shown, the gate of the transistor M23 and the gate of the transistor M24 may be connected to separate wirings.

[0337] At least a part of semiconductor device 100C, which is a specific example of semiconductor device 100 described above (whether illustrated or not shown), can be applied to semiconductor device 100 shown in Figures 37B, 38B, 39A, and 39B. Also, at least a part of semiconductor device 100D, which is a specific example of semiconductor device 100 described above (whether illustrated or not shown), can be applied to semiconductor device 100 shown in Figures 37A, 37B, 38A, 38B, and 39A.

[0338] The specific structure of the semiconductor device 100 is not limited to the above example. One embodiment of the present invention is a semiconductor device including at least a part of the semiconductor device 100 shown in each of FIGS.

[0339] <Operation Example of Semiconductor Device> Next, an operation example of the semiconductor device 100 will be described. Here, as an example, an operation example of the semiconductor device 100C shown in Fig. 40 will be described. Note that the description of the first embodiment above can be referred to as appropriate.

[0340] Fig. 42 is a timing chart illustrating an example of operation of the semiconductor device 100C shown in Fig. 40. Figs. 43 to 50 are circuit diagrams illustrating an example of operation of the semiconductor device 100C shown in Fig. 40.

[0341] In the semiconductor device 100C, the wirings EM, EM2, GW, GC, GI, and GP each function as a signal line. The potential of a signal applied to each of the wirings EM, EM2, GW, GC, GI, and GP is either a potential L (sometimes simply referred to as "L") or a potential H (sometimes simply referred to as "H") that is higher than the potential L. In this case, the difference between the potential H and the potential L is higher than the threshold voltage of the transistor. Note that the potential L or the potential H may be, for example, a ground potential.

[0342] The wirings ANO, CATH, VL1, VL2, and VL3 each function as a power supply line. Here, a potential H is applied to the wirings ANO and VL1, and a potential L is applied to the wirings CATH, VL2, and VL3.

[0343] Note that a signal may be supplied to at least one of the wiring VL1, the wiring VL2, the wiring VL3, and the wiring VL4. That is, at least one of the wiring VL1, the wiring VL2, the wiring VL3, and the wiring VL4 can also function as a signal line.

[0344] The wiring SL also functions as a signal line. A potential based on an image signal is applied to the wiring SL. The potential based on the image signal is a potential between the potential H and the potential L.

[0345] For ease of understanding, the potential applied to each wiring other than the wiring VL1 is the potential L or the potential H. However, different potentials may be applied to each wiring. For example, a potential different from the potential H may be applied to the wiring ANO. Furthermore, for example, a potential different from the potential L may be applied to the wiring CATH.

[0346] 42 shows potentials applied to each wiring during each period of operation, and also shows changes in potential at each node.

[0347] 43 to 50 also show the potential of each wiring and each node at each point in time of operation. In this case, a symbol indicating the potential, such as "H" or "L" (also called a potential symbol), may be written adjacent to each wiring as a character enclosed with a line. In particular, when a potential change occurs, the line may be thickened, and when the potential becomes floating, the line may be dotted. An "x" symbol may be written over a transistor in an off state. Also, a dashed arrow may be written along each wiring to indicate the direction of current flow (which may also be said to be the direction of positive charge movement).

[0348] In addition, the threshold voltage of transistor M11 may be written as Vt11, the threshold voltage of transistor M12 as Vt12, the threshold voltage of transistor M13 as Vt13, the threshold voltage of transistor M14 as Vt14, the threshold voltage of transistor M21 as Vt21, the threshold voltage of transistor M22 as Vt22, the threshold voltage of transistor M23 as Vt23, the threshold voltage of transistor M24 as Vt24, and the forward voltage of light-emitting element LD as Vf.

[0349] At this time, the threshold voltage of each transistor is assumed to be greater than 0V.

[0350] For ease of understanding, the following description may be given without taking into consideration the influence of parasitic capacitance when a potential changes due to capacitive coupling.

[0351] Immediately before the period T21, a potential H is applied to the wirings EM and EM2, and a potential L is applied to the wirings GW, GC, GI, and GP. Therefore, the transistors M14, M21, M23, and M24 are each in an off state, and the transistors M12 and M22 are each in an on state. As a result, the node ND1 is floating. At this time, the potential of the node ND4 is assumed to be greater than "potential H-Vt13." Therefore, the transistor M13 is in an off state. As a result, the node ND4 is floating. Also, the potential of the node ND3 is assumed to be "potential L+Vf," and the potential of the node ND1 is assumed to be "potential Vd0+Vt11+Vf." As a result, "potential Vd0+Vt11-potential L" is applied as the gate voltage of the transistor M11, and a current based on this gate voltage is supplied to the light-emitting element LD, causing the light-emitting element LD to emit light. At this time, the potential of node ND2 is potential H, and the potential of node ND6 is "potential L+Vf." The state of the circuit at this time is shown in Figure 43. In the following description, unless otherwise specified, it is assumed that the immediately preceding state is maintained.

[0352] In period T21, a potential L is applied to the wiring EM, and a potential H is applied to the wiring GI. This turns off the transistor M22, and turns on the transistor M24. As a result, the light-emitting element LD does not emit light. Furthermore, the potential of the wiring VL3 is supplied to the node ND6 via the transistor M24, and the potential of the node ND6 becomes the potential L. Next, a potential H is applied to the wiring GC. This turns on the transistor M23. Then, the potential of the wiring ANO is supplied to the node ND1 via the transistors M12 and M23, and the potential of the node ND1 becomes the "potential H-Vt23". The state of the circuit at this time is shown in Figure 44.

[0353] In the period T21, the voltage applied to the light-emitting element LD can be initialized (also referred to as anode voltage initialization or anode reset) by setting the potential of the anode of the light-emitting element LD to potential L. This can suppress the influence of the past display history and improve the display quality of the display device.

[0354] Thereafter, the potential L is applied to the wiring GC, which turns off the transistor M23.

[0355] In a period T22, a potential L is applied to the wiring EM. The potential of the wiring EM is supplied to the node ND4 through the transistor M13, and the potential of the node ND4 becomes the potential L. This turns off the transistor M12. Then, the nodes ND2 and ND3 are each floating. The state of the circuit at this time is shown in FIG. 45.

[0356] Note that in the period T22, a predetermined potential may be supplied to the other of the source and drain of the transistor M11 (corresponding to the node ND3) to apply a gate voltage (also referred to as application of an on-bias voltage) that turns on the transistor M11. For example, by applying a potential H to the wiring GW, the potential of the wiring SL (i.e., a potential corresponding to an image signal) may be supplied to the node ND3, and an on-bias voltage of “potential H-Vt23-potential corresponding to the image signal” may be applied to the transistor M11. Alternatively, by applying a potential H to the wiring EM2, the potential of the wiring VL3 (here, potential L) may be supplied to the node ND3, and an on-bias voltage of “potential H-Vt23-potential L” may be applied to the transistor M11. Alternatively, for example, an additional transistor may be provided, and one of the source and drain of the transistor may be connected to the node ND3 to supply a predetermined potential from the other of the source and drain of the transistor to the node ND3, and an on-bias voltage of “potential H-Vt23-predetermined potential” may be applied to the transistor M11. In this way, by applying an on-bias voltage to the transistor M11, the influence of hysteresis of the transistor M11 can be suppressed, and the display quality of the display device can be improved.

[0357] In the period T23, a potential H is applied to the wiring GW and the wiring GC. This turns on the transistors M21 and M23. At this time, a potential Vd1 corresponding to an image signal is applied to the wiring SL. Then, a current flows from the node ND1 to the wiring SL through the transistors M23, M11, and M21, and the potential of the node ND1 decreases. The circuit state at this time is shown in FIG. 46.

[0358] Here, "the potential of node ND1 - potential Vd1" is applied as the gate voltage of transistor M11. Therefore, when the potential of node ND1 drops to "potential Vd1 + Vt11", transistor M11 is turned off. Then, nodes ND1 and ND2 each become floating, and the potential difference between node ND1 and node ND6, "potential Vd1 + Vt11 - potential L", is held in capacitance element C21. The state of the circuit at this time is shown in FIG. 47.

[0359] After that, the potential L is applied to the wiring GW and the wiring GC, which turns off the transistor M21 and the transistor M23.

[0360] In a period T24, a potential L is applied to the wiring GI. This turns off the transistor M24. Furthermore, a potential H is applied to the wiring GP. This turns on the transistor M14. Then, the potential of the wiring VL2 is supplied to the nodes ND2 and ND3 via the transistor M14, and the potentials of the nodes ND2 and ND3 become the potential L. The state of the circuit at this time is shown in FIG. 48.

[0361] In the period T24, it is preferable to reduce the parasitic capacitance between the nodes ND1 and ND2 and the parasitic capacitance between the nodes ND1 and ND3 so that the potential of the node ND1 does not change in accordance with changes in the potentials of the nodes ND2 and ND3. For example, it is preferable to make the capacitance of the capacitive element C21 larger than the parasitic capacitance.

[0362] In period T25, a potential H is applied to the wiring EM. The potential of the wiring EM is also supplied to the node ND4 via the transistor M13, and the potential of the node ND4 becomes "potential H-Vt13." This turns on the transistor M12. Then, a current flows from the wiring ANO to the wiring VL2 via the transistors M12 and M14. The state of the circuit at this time is shown in FIG. 49.

[0363] Note that during the period T25, a current flows from the wiring ANO to the wiring VL2 via the transistors M12 and M14, resulting in power consumption. Therefore, to reduce this effect, it is preferable to shorten the length of the period T25. For example, the length of the period T25 is preferably equal to or shorter than the length of the period T21, preferably equal to or shorter than the length of the period T22, preferably equal to or shorter than the length of the period T23, preferably equal to or shorter than the length of the period T24, and preferably equal to or shorter than the length of the period T26 (described later).

[0364] In period T26, potential L is applied to the wiring GP, and potential H is applied to the wiring EM2. This turns off the transistor M14 and turns on the transistor M22. Then, the potential of the node ND2 rises to potential H. Therefore, a drain current based on the gate voltage of the transistor M11 flows, and this current is supplied to the light-emitting element LD, causing the light-emitting element LD to emit light. At this time, the potentials of the nodes ND3 and ND6 rise to "potential L + Vf." Furthermore, due to the capacitive coupling of the capacitive element C21, the potential of the node ND1 rises to "potential Vd1 + Vt11 + Vf." Then, "(potential Vd1 + Vt11 + Vf) - (potential L + Vf)" is applied as the gate voltage of the transistor M11, and therefore, a current proportional to "the gate voltage of the transistor M11 - Vt11," that is, a current proportional to "potential Vd1 - potential L," flows as the drain current of the transistor M11. Therefore, a current that does not depend on the threshold voltage of the transistor M11 can flow as the drain current of the transistor M11. As a result, even if the threshold voltage of the transistor M11 varies among multiple pixels, a drain current that is not affected by the variation in threshold voltage can flow. In this way, the variation in the threshold voltage of the transistor M11 can be corrected.

[0365] Here, when the potential of node ND2 rises, the potential of node ND4 also rises due to the capacitive coupling of capacitive element C11, and the potential of node ND4 becomes a value greater than "potential H - Vt13". At this time, transistor M13 is turned off, and the gate voltage of transistor M12 is maintained. The state of the circuit at this time is shown in FIG. 50. Also, in FIG. 42, the change in the potential of node ND2 is shown as Va (here, "Va = potential H - potential L"), and the change in the potential of node ND4 is shown as Vb (here, "0 < Vb < Va"). In other words, the potential of node ND4 becomes "potential H - Vt13 + Vb".

[0366] Note that during the period T26, due to the influence of the parasitic capacitance of the node ND4, the change in the potential of the node ND4 accompanying the change in the potential of the node ND2 may become smaller (the absolute value of Vb may become smaller than the absolute value of Va). Therefore, in order to increase the change in the potential of the node ND4 accompanying the change in the potential of the node ND2, it is preferable to reduce the parasitic capacitance of the node ND4. For example, it is preferable to reduce the parasitic capacitance between the node ND4 and the wiring ANO, the parasitic capacitance between the node ND4 and the wiring VL1, and the parasitic capacitance between the node ND4 and the wiring EM to be smaller than the capacitance of the capacitive element C11.

[0367] In the semiconductor device 100C of one embodiment of the present invention, for example, the potential of the wiring VL2 can be supplied to the node ND2 (corresponding to one of the source and drain of the transistor M12) during the period T24. As a result, a stable gate voltage can be applied to the transistor M12 during the period T25. Furthermore, the gate voltage of the transistor M12 can be maintained during the period T26. Therefore, the light-emitting luminance of the display device can be stabilized.

[0368] For example, in the period T24, the potential supplied from the wiring VL2 to the node ND2 can be set lower than the potential corresponding to the image signal. For example, a potential L lower than the potential Vd1 can be supplied to the node ND2. As a result, the gate voltage applied to the transistor M12 can be increased in the periods T25 and T26.

[0369] In other words, even if the amplitude of the signal provided from the wiring EM is reduced, a sufficient gate voltage can be applied to the transistor M12. Therefore, for example, even if the channel width of the transistor M12 is reduced, a sufficient on-state current can be obtained, thereby improving the resolution of the display device. Furthermore, for example, by reducing the amplitude of the signal provided from the wiring EM, the voltage applied between the terminals of the transistor can be reduced, thereby suppressing breakdown and degradation of the transistor and improving the reliability of the display device. For example, by reducing the amplitude of the signal provided from the wiring EM, the withstand voltage required of the transistor can be reduced, eliminating the need for technology with high process costs, thereby reducing the manufacturing cost of the display device. For example, by reducing the amplitude of the signal provided from the wiring EM, the operating voltage of a circuit (e.g., a driver circuit such as a gate driver) provided outside the semiconductor device 100C can be reduced, thereby reducing the power consumption of the display device.

[0370] In addition, in the period T23, a transistor with a large on-state current is preferably used as the transistor M23 in order to shorten the time until the transistor M11 is turned off, thereby improving the operating speed.

[0371] Here, in the semiconductor device 100C, for example, an operation to suppress the influence of hysteresis of the transistor M11 may be performed. In particular, when a Si transistor is used as the transistor M11, it is preferable to perform an operation to suppress the influence of hysteresis of the transistor M11. To suppress the influence of hysteresis of the transistor M11, for example, an operation to initialize the gate potential of the transistor M11 (an operation corresponding to the period T23) may be performed multiple times. Therefore, particularly in such a case, it is preferable to use a transistor with a large on-state current as the transistor M23 in order to improve the operating speed.

[0372] In the period T26, a transistor with low off-state current is preferably used as the transistor M23 to maintain the gate voltage of the transistor M11. In addition, a transistor with low off-state current is preferably used as the transistor M13 to maintain the gate voltage of the transistor M12. This can stabilize the light-emission intensity.

[0373] Therefore, for example, a transistor with a small off-state current and a large on-state current is preferably used as each of the transistor M23 and the transistor M13.

[0374] In one embodiment of the present invention, an OS transistor can be used as each of the transistors M23 and M13, for example, as a transistor with extremely low off-state current. Various oxide semiconductors can be used for the OS transistor. In particular, it is preferable to use an oxide semiconductor that exhibits low off-state current and high on-state current. Examples of oxide semiconductors that exhibit low off-state current and high on-state current include indium oxide. Details of oxide semiconductors that can be used for OS transistors will be described in Embodiment 4 below. Indium oxide, which is one of oxide semiconductors, will also be described in detail in Embodiment 9.

[0375] In the above-described operation example, the potential H is applied to each of the wirings ANO and VL1. However, this is not limiting. Different potentials may be applied to each of the wirings ANO and VL1. Furthermore, the potential L is applied to each of the wirings CATH, VL2, and VL3. However, this is not limiting. Different potentials may be applied to each of the wirings CATH, VL2, and VL3. For example, when the same potential is applied to each of the wirings ANO and VL1, the wirings ANO and VL1 may be connected to each other. For example, when the same potential is applied to two or more of the wirings CATH, VL2, and VL3, two or more of the wirings CATH, VL2, and VL3 may be connected to each other. This allows some of the wirings connected to the semiconductor device 100C to be shared, thereby reducing the layout area. Therefore, the resolution of the display device can be improved.

[0376] In the above-described operation example, for example, the wiring VL1 needs to be supplied with a potential (e.g., potential H) that turns on the transistor M13 at the timing when the potential applied to the wiring EM changes from potential H to potential L (corresponding to the start of period T22) and the timing when the potential changes from potential L to potential H (corresponding to the start of period T25). A potential (e.g., potential L) lower than potential H may be supplied at other times. Thus, the wiring VL1 may function as a signal line. In this case, for example, the wiring VL1 may be connected to any one of the wiring EM2, the wiring GW, the wiring GC, the wiring GI, and the wiring GP. In this way, by sharing some of the wirings connected to the semiconductor device 100C, the layout area can be reduced. Therefore, the resolution of the display device can be improved.

[0377] Furthermore, for example, the wiring GP needs to be supplied with a potential (e.g., a potential H) that turns on the transistor M14 when the potential applied to the wiring EM changes from a potential L to a potential H, and the wiring VL2 needs to be supplied with the potential L when the transistor M14 is on (corresponding to the periods T24 and T25). Furthermore, a potential (e.g., a potential H) higher than the potential L may be supplied when the transistor M14 is off. Thus, the wiring VL2 may function as a signal line. In this case, for example, the wiring VL2 may be connected to any one of the wiring EM, the wiring EM2, the wiring GW, the wiring GC, the wiring GI, and the wiring GP. In this way, by sharing some of the wirings connected to the semiconductor device 100C, the layout area can be reduced. Therefore, the resolution of the display device can be improved.

[0378] In addition, when some of the wiring connected to the semiconductor device 100C is shared, for example, two or more wirings may be connected to each other inside the semiconductor device 100C or may be connected to each other outside the semiconductor device 100C. Furthermore, for example, the respective wirings of two or more semiconductor devices 100C provided in different rows may be connected to each other. For example, in the above-described operation example, a signal applied to the wiring GP of a semiconductor device 100C provided in a certain row may be the same signal as a signal applied to the wiring GI or wiring GW of a semiconductor device 100C provided in another row. In this case, the wiring GP of a semiconductor device 100C provided in a certain row and the wiring GI or wiring GW of a semiconductor device 100C provided in another row may be connected to each other.

[0379] <Modifications of Semiconductor Device> The semiconductor device of one embodiment of the present invention is not limited to the above structure. The semiconductor device of one embodiment of the present invention can have various structures.

[0380] [Variation 1] Figure 51 is a circuit diagram illustrating a variation of the semiconductor device 100C shown in Figure 40. The semiconductor device 100C shown in Figure 51 differs from the semiconductor device 100C shown in Figure 40 in that it includes transistors M13a and M13b instead of the transistor M13. In this case, one of the source or drain of the transistor M13b is connected to the gate of the transistor M12 and the other terminal of the capacitance element C11. The other of the source or drain of the transistor M13b is connected to one of the source or drain of the transistor M13a. The other of the source or drain of the transistor M13a is connected to a wiring EM. The gates of the transistors M13a and M13b are each connected to a wiring VL1.

[0381] With this configuration, for example, during the period T26, charge is less likely to leak from the node ND4 to the wiring EM, making it easier to maintain the gate voltage of the transistor M12. As a result, the operation of the display device can be stabilized.

[0382] [Variation 2] Fig. 52 is a circuit diagram illustrating a variation of the semiconductor device 100C shown in Fig. 40. The semiconductor device 100C shown in Fig. 52 differs from the semiconductor device 100C shown in Fig. 40 in terms of the connection of the transistor M14. Here, the other of the source and the drain of the transistor M14 is connected to a wiring GP. The gate of the transistor M14 is connected to one of the source and the drain of the transistor M14.

[0383] At this time, for example, a signal obtained by inverting the logical value of the signal supplied to the wiring GP in the above-described operation example is supplied to the wiring GP. As a result, for example, in the period T24, a potential L is supplied to the wiring GP, and the transistor M14 is turned on. Then, the potential of the wiring GP is supplied to each of the nodes ND2 and ND3, and the potentials of the nodes ND2 and ND3 become "potential L+Vt14."

[0384] With this configuration, there is no need to provide the wiring VL2, and therefore the layout area can be reduced. Therefore, the resolution of the display device can be improved. Furthermore, there is no need to generate the potential applied to the wiring VL2 in a circuit (e.g., a power supply circuit) provided outside the semiconductor device 100C, and therefore at least one of miniaturization and low power consumption of the display device can be achieved.

[0385] Moreover, Fig. 53 is a circuit diagram illustrating a modification of the semiconductor device 100C shown in Fig. 52. The semiconductor device 100C shown in Fig. 53 differs from the semiconductor device 100C shown in Fig. 52 in terms of the connection of the transistor M13. Here, the gate of the transistor M13 is connected to the wiring GP.

[0386] At this time, a signal is applied to the wiring GP, for example, which has a potential L in the period T24 and a potential H in the other periods. As a result, for example, in the period T24, the potential L is applied to the wiring GP, and the transistor M14 is turned on. Then, the potential of the wiring GP is supplied to each of the nodes ND2 and ND3, and the potentials of the nodes ND2 and ND3 become "potential L+Vt14." Also, for example, in the period T24, the potential L is applied to the gate of the transistor M13, and the transistor M13 is turned off. Then, the node ND4 is floating, and the potential of the node ND4 remains at potential L. In the other periods, the potential H is applied to the gate of the transistor M13, which is the same as the above-described operation example.

[0387] With this configuration, there is no need to provide the wiring VL1, and therefore the layout area can be reduced. Therefore, the resolution of the display device can be improved. Furthermore, there is no need to generate a potential applied to the wiring VL1 in a circuit (e.g., a power supply circuit) provided outside the semiconductor device 100C, and therefore at least one of miniaturization and low power consumption of the display device can be achieved.

[0388] [Variation 3] Figure 54 is a circuit diagram illustrating a variation of the semiconductor device 100C shown in Figure 40. The semiconductor device 100C shown in Figure 54 differs from the semiconductor device 100C shown in Figure 40 in that it has an n-channel transistor M15 instead of the capacitive element C11. In this case, the gate of the transistor M15 is connected to the gate of the transistor M12 (corresponding to node ND4). One of the source or drain of the transistor M15 and the other of the source or drain of the transistor M15 are each connected to one of the source or drain of the transistor M12 (corresponding to node ND2).

[0389] With this configuration, for example, during periods T25 and T26, a channel is formed in the channel formation region of the transistor M15, allowing the gate capacitance of the transistor M15 to function as a capacitive element instead of the capacitive element C11. Here, in order to increase the change in the potential of the node ND4 accompanying the change in the potential of the node ND2 during period T26, it is preferable for the capacitance of the capacitive element C11 to be large. To increase the capacitance of the capacitive element C11, for example, the layout area of ​​the capacitive element C11 can be increased. Alternatively, to increase the capacitance while suppressing an increase in the layout area of ​​the capacitive element C11, for example, adding a conductive layer, reducing the film thickness of the dielectric, or using a dielectric with a high dielectric constant can be used. However, these methods increase process costs. Therefore, by using the gate capacitance of the transistor M15 as a capacitive element instead of the capacitive element C11, the gate insulating film is used as the dielectric, making it easier to increase the capacitance per unit area. Therefore, compared to the configuration shown in FIG. 40 , the layout area can be reduced, thereby improving the resolution of the display device.

[0390] Furthermore, for example, in the periods T22 to T24, a potential L is applied to the gate of the transistor M15. Then, the transistor M15 is turned off, and no channel is formed in the channel formation region of the transistor M15. Since no channel is formed in the channel formation region of the transistor M15, the gate capacitance of the transistor M15 is reduced. By reducing the gate capacitance of the transistor M15 in this manner, for example, in the period T23, the current required for charging and discharging the nodes ND1 and ND2 can be reduced, or the time required for charging and discharging (the time required for the potential of the node ND1 to reach "potential Vd1+Vt11") can be shortened. Therefore, at least one of a reduction in power consumption and an improvement in operating speed of the display device can be achieved.

[0391] Although not shown, the semiconductor device 100C may include a p-channel transistor M15 instead of the capacitor C11. In this case, the gate of the transistor M15 is connected to one of the source or drain of the transistor M12 (corresponding to node ND2). One of the source or drain of the transistor M15 and the other of the source or drain of the transistor M15 are each connected to the gate of the transistor M12 (corresponding to node ND4).

[0392] [Variation 4] Fig. 55 is a circuit diagram illustrating a variation of the semiconductor device 100C shown in Fig. 40. The semiconductor device 100C shown in Fig. 55 differs from the semiconductor device 100C shown in Fig. 40 in terms of the connection of the transistor M13. Here, the gate of the transistor M13 is connected to the other of the source and drain of the transistor M12 (corresponding to the wiring ANO).

[0393] With this configuration, there is no need to provide the wiring VL1, and therefore the layout area can be reduced. Therefore, the resolution of the display device can be improved. Furthermore, there is no need to generate a potential applied to the wiring VL1 in a circuit (e.g., a power supply circuit) provided outside the semiconductor device 100C, and therefore at least one of miniaturization and low power consumption of the display device can be achieved.

[0394] [Variation 5] Fig. 56 is a circuit diagram illustrating a variation of the semiconductor device 100C shown in Fig. 40. The semiconductor device 100C shown in Fig. 56 differs from the semiconductor device 100C shown in Fig. 40 in terms of the connection of the transistor M14. Here, the other of the source or the drain of the transistor M14 is connected to the other of the source or the drain of the transistor M24 (corresponding to the wiring VL3).

[0395] With this configuration, there is no need to provide the wiring VL2, and therefore the layout area can be reduced. Therefore, the resolution of the display device can be improved. Furthermore, there is no need to generate the potential applied to the wiring VL2 in a circuit (e.g., a power supply circuit) provided outside the semiconductor device 100C, and therefore at least one of miniaturization and low power consumption of the display device can be achieved.

[0396] [Variation 6] Fig. 57 is a circuit diagram illustrating a variation of the semiconductor device 100C shown in Fig. 40. The semiconductor device 100C shown in Fig. 57 differs from the semiconductor device 100C shown in Fig. 40 in terms of the connection of the transistor M22. Here, the gate of the transistor M22 is connected to the gate of the transistor M12 (corresponding to the node ND4).

[0397] With this configuration, for example, a region that functions as the gate of the transistor M12 and a region that functions as the gate of the transistor M22 can be provided in one conductive layer. Therefore, compared to the configuration shown in Figure 40, the number of vias can be reduced, and the layout area can be made smaller. As a result, the resolution of the display device can be improved.

[0398] [Variation 7] Fig. 58 is a circuit diagram illustrating a variation of the semiconductor device 100C shown in Fig. 40. The semiconductor device 100C shown in Fig. 58 differs from the semiconductor device 100C shown in Fig. 40 in terms of the connection of the transistor M14. Here, the other of the source or the drain of the transistor M14 is connected to the gate of the transistor M21 (corresponding to the wiring GW).

[0399] At this time, for example, in the periods T24 and T25, the potential of the wiring GW is supplied to each of the nodes ND2 and ND3, and the potentials of the nodes ND2 and ND3 become the potential L.

[0400] Moreover, Fig. 59 is a circuit diagram illustrating a modification of the semiconductor device 100C shown in Fig. 40. The semiconductor device 100C shown in Fig. 59 differs from the semiconductor device 100C shown in Fig. 40 in terms of the connection of the transistor M14. Here, the other of the source or the drain of the transistor M14 is connected to the gate (corresponding to the wiring GC) of the transistor M23.

[0401] At this time, for example, in the periods T24 and T25, the potential of the wiring GC is supplied to each of the nodes ND2 and ND3, and the potentials of the nodes ND2 and ND3 become the potential L.

[0402] Fig. 60 is a circuit diagram illustrating a modified example of the semiconductor device 100C shown in Fig. 40. The semiconductor device 100C shown in Fig. 60 differs from the semiconductor device 100C shown in Fig. 40 in terms of the connection of the transistor M14. Here, the other of the source or the drain of the transistor M14 is connected to the gate (corresponding to the wiring GI) of the transistor M24.

[0403] At this time, for example, in the periods T24 and T25, the potential of the wiring GI is supplied to each of the nodes ND2 and ND3, and the potentials of the nodes ND2 and ND3 become the potential L.

[0404] 61 is a circuit diagram illustrating a modified example of the semiconductor device 100C shown in Fig. 40. The semiconductor device 100C shown in Fig. 61 differs from the semiconductor device 100C shown in Fig. 40 in terms of the connection of the transistor M14. Here, the other of the source and the drain of the transistor M14 is connected to the gate of the transistor M22 (corresponding to the wiring EM2).

[0405] At this time, for example, in the periods T24 and T25, the potential of the wiring EM2 is supplied to each of the nodes ND2 and ND3, and the potentials of the nodes ND2 and ND3 become the potential L.

[0406] With this configuration, there is no need to provide the wiring VL2, and therefore the layout area can be reduced. Therefore, the resolution of the display device can be improved. Furthermore, there is no need to generate the potential applied to the wiring VL2 in a circuit (e.g., a power supply circuit) provided outside the semiconductor device 100C, and therefore at least one of miniaturization and low power consumption of the display device can be achieved. Furthermore, when the transistor M14 is in an off state, a period can be provided in which the voltage applied between the drain and source of the transistor M14 is low. Therefore, breakdown and degradation of the transistor can be suppressed, and the reliability of the display device can be improved.

[0407] [Variation 8] Fig. 62 is a circuit diagram illustrating a variation of the semiconductor device 100C shown in Fig. 40. The semiconductor device 100C shown in Fig. 62 differs from the semiconductor device 100C shown in Fig. 40 in terms of the connection of the transistor M13. Here, the gate of the transistor M13 is connected to the gate of the transistor M24 (corresponding to the wiring GI).

[0408] At this time, a signal is applied to the wiring GI, which has a potential H from the period T21 to the period T25 and a potential L from the period T26. As a result, for example, a potential H is applied to the gate of the transistor M24 from the period T21 to the period T23, and a potential L is applied to the gate of the transistor M24 from the period T26, which is the same as the above-described operation example. For example, a potential H is applied to the gate of the transistor M24 from the period T24 to the period T25, and the transistor M24 is turned on. Then, the potential of the wiring VL3 is supplied to the node ND6 through the transistor M24, and the potential of the node ND6 becomes a potential L. Furthermore, for example, a potential H is applied to the gate of the transistor M13 from the period T21 to the period T25, which is the same as the above-described operation example. For example, a potential L is applied to the gate of the transistor M13 from the period T26, and the transistor M13 is turned off. Then, the gate voltage of the transistor M12 is maintained.

[0409] With this configuration, there is no need to provide the wiring VL1, and therefore the layout area can be reduced. Therefore, the resolution of the display device can be improved. Furthermore, there is no need to generate a potential applied to the wiring VL1 in a circuit (e.g., a power supply circuit) provided outside the semiconductor device 100C, and therefore at least one of miniaturization and low power consumption of the display device can be achieved.

[0410] [Modification 9] Fig. 63 is a circuit diagram illustrating a modification of the semiconductor device 100C shown in Fig. 40. The semiconductor device 100C shown in Fig. 63 differs from the semiconductor device 100C shown in Fig. 40 in terms of the connection of the transistor M14. Here, one of the source or the drain of the transistor M14 is connected to the other of the source or the drain of the transistor M11 (corresponding to the node ND3).

[0411] At this time, for example, in the periods T24 and T25, a predetermined potential can be applied from the wiring VL2 to one of the source and the drain of the transistor M12 (corresponding to the node ND2) through the transistor M14 and the transistor M11.

[0412] For example, in the period T22, a potential H may be applied to the wiring GP. This turns on the transistor M14, allowing a predetermined potential to be applied from the wiring VL2 to the other of the source and drain of the transistor M11 (corresponding to the node ND3) via the transistor M14. In other words, an on-bias voltage may be applied to the transistor M11. By applying an on-bias voltage to the transistor M11 in this manner, the influence of hysteresis of the transistor M11 can be suppressed, thereby improving the display quality of the display device.

[0413] [Modification 10] Fig. 64 is a circuit diagram illustrating a modification of the semiconductor device 100C shown in Fig. 40. At least one of the transistors included in the semiconductor device 100C may have a back gate. Fig. 64 shows an example in which the transistors M11 to M14 and the transistors M21 to M24 each have a back gate.

[0414] The back gate of the transistor M12 is connected to, for example, the gate of the transistor M12. The transistor M12, which functions as a switch, preferably has a large on-state current. Therefore, by connecting the gate and back gate of the transistor M12 to each other, the on-state current can be increased. This can improve the operating speed of the semiconductor device 100C. Furthermore, for example, even if the channel width of the transistor M12 is reduced, a sufficient on-state current can be easily obtained, thereby reducing the layout area. This can improve the definition of the display device. Furthermore, reducing the channel width of the transistor M12 can sometimes increase the aperture ratio of the pixel. This can achieve at least one of higher brightness and higher reliability of the display device. Note that the back gate of the transistor M12 may be connected to, for example, a wiring to which a predetermined potential is applied.

[0415] Note that the back gates of the transistors M13, M14, and M21 to M24 are similar to the back gate of the transistor M12 described above. In this case, for example, the gates and back gates of the transistors may be connected to each other outside the semiconductor device 100C or the pixel circuit 101C, or may be connected to each other inside the semiconductor device 100C or the pixel circuit 101C.

[0416] The back gate of the transistor M11 is connected to, for example, the other of the source and drain of the transistor M11 (corresponding to node ND3). Connecting the back gate of the transistor M11 to the other of the source and drain of the transistor M11 fixes the potential of the back gate side of the channel formation region, thereby stabilizing the electrical characteristics (for example, increasing saturation and suppressing a shift in the threshold voltage). Furthermore, the channel formation region is less susceptible to an electric field generated outside the transistor, thereby stabilizing the electrical characteristics. Furthermore, the channel formation region is less susceptible to light irradiation from outside the transistor, thereby stabilizing the electrical characteristics. The back gate of the transistor M11 may be connected to, for example, the wiring VL2, the wiring VL3, the wiring CATH, or a wiring to which a predetermined potential is applied. For example, the back gate of the transistor M11 and the wiring connected to the back gate may be connected to each other outside the semiconductor device 100C or the pixel circuit 101C or may be connected to each other inside the semiconductor device 100C or the pixel circuit 101C.

[0417] As an example, Figure 64 illustrates a state in which the back gate and the other of the source or drain (corresponding to node ND3) of transistor M11 are connected to each other inside pixel circuit 101C, the back gate and gate of transistor M12 are connected to each other inside pixel circuit 101C, and the back gates and gates of transistors M13, M14, and M21 to M24 are connected to each other outside pixel circuit 101C.

[0418] [Variation 11] Fig. 65 is a circuit diagram illustrating a variation of the semiconductor device 100C shown in Fig. 40. The semiconductor device 100C shown in Fig. 65 differs from the semiconductor device 100C shown in Fig. 40 in that the configuration of the light-emission control unit 110 is also applied to the transistor M22 (i.e., the semiconductor device 100C has a light-emission control unit 110_2). Therefore, the semiconductor device 100C shown in Fig. 65 further has a transistor M13_2 and a capacitive element C11_2.

[0419] The gate of the transistor M22 is connected to one of the source and drain of the transistor M13_2 and one terminal of the capacitor C11_2. The other terminal of the capacitor C11_2 is connected to the other of the source and drain of the transistor M22. The other of the source and drain of the transistor M13_2 is connected to a wiring EM. The gate of the transistor M13_2 is connected to a wiring VL4.

[0420] In the light-emitting control unit 110_2, the transistor M22 corresponds to the transistor M12 in the light-emitting control unit 110, the transistor M22 corresponds to the transistor M12 in the light-emitting control unit 110, the transistor M13_2 corresponds to the transistor M13 in the light-emitting control unit 110, the transistor M24 corresponds to the transistor M14 in the light-emitting control unit 110, and the capacitive element C11_2 corresponds to the capacitive element C11 in the light-emitting control unit 110. Furthermore, the wiring VL4 may be connected to, for example, the wiring VL1 or the wiring ANO.

[0421] With this configuration, a stable gate voltage can be applied to the transistor M22 when the transistor M22 is turned on. Furthermore, the gate voltage of the transistor M22 can be maintained after the transistor M22 is turned on. Therefore, the light emission brightness of the display device can be stabilized.

[0422] [Variation 12] Fig. 66 is a circuit diagram illustrating a variation of the semiconductor device 100C shown in Fig. 40. The semiconductor device 100C shown in Fig. 66 differs from the semiconductor device 100C shown in Fig. 40 in that it has a switch S14 instead of the transistor M14, a switch S21 instead of the transistor M21, a switch S22 instead of the transistor M22, a switch S23 instead of the transistor M23, and a switch S24 instead of the transistor M24.

[0423] As described above, one embodiment of the present invention may have a structure in which at least some of the transistors included in the semiconductor device 100C are replaced with other elements that function as switches.

[0424] It should be noted that two or more of the modifications described above, whether illustrated or not, can be applied to the semiconductor device 100C shown in FIG.

[0425] Furthermore, at least a part of the modifications of the semiconductor device 100C described above, whether illustrated or not, can be applied to a semiconductor device 100D shown in FIG.

[0426] Furthermore, the semiconductor device 100, the semiconductor device 100C, and the semiconductor device 100D described above, whether illustrated or not, can at least solve the problem of providing a novel semiconductor device by their circuit configuration alone.

[0427] One embodiment of the present invention also includes a structure in which at least one of a gate, a source, and a drain of one or more transistors is not connected to anything or is connected to any wiring. Another embodiment of the present invention also includes a structure in which nothing is input to one or more wirings or a signal or potential is input to one or more wirings.

[0428] <Structure Example 2 of Semiconductor Device> FIG. 67 is a circuit diagram illustrating a semiconductor device 100X2 of one embodiment of the present invention.

[0429] 67, the semiconductor device 100X2 includes a pixel circuit 101L, a pixel circuit 101R, a light-emitting element LDL, a light-emitting element LDR, and a transistor M13. The pixel circuit 101L and the pixel circuit 101R each include a transistor M11, a transistor M12, and a capacitance element C11. The semiconductor device 100X2 can also be considered to be two pixels adjacent to each other in the row direction.

[0430] The description of the above-mentioned embodiment 1 can be referred to as appropriate for the semiconductor device 100X2 shown in this embodiment, and the pixel circuit 101L, the pixel circuit 101R, the light-emitting element LDL, the light-emitting element LDR, the transistor M13, and the like included in the semiconductor device 100X2.

[0431] In each of the pixel circuits 101L and 101R, one of the source or drain of the transistor M11 is connected to one of the source or drain of the transistor M12 and one terminal of the capacitor C11. One of the source or drain of the transistor M13 is connected to the gate of the transistor M12 and the other terminal of the capacitor C11 in the pixel circuit 101L, and is also connected to the gate of the transistor M12 and the other terminal of the capacitor C11 in the pixel circuit 101R. The other of the source or drain of the transistor M13 is connected to a wiring EM. The gate of the transistor M13 is connected to a wiring VL1.

[0432] The light-emitting element LDL and the transistors M11 and M12 included in the pixel circuit 101L are provided in the current path between the wiring ANO and the wiring CATH. The light-emitting element LDR and the transistors M11 and M12 included in the pixel circuit 101R are also provided in the current path between the wiring ANO and the wiring CATH.

[0433] The semiconductor device 100X2 of one embodiment of the present invention can be said to have a structure in which one transistor M13 functioning as a bootstrap transistor is shared by two adjacent pixels in the row direction. Note that, for example, one transistor M13 functioning as a bootstrap transistor may be shared by three or more pixels arranged in the row direction. In this case, for example, the transistor M13 may be provided outside the pixel (e.g., in a driver circuit such as a gate driver). In this way, by sharing one bootstrap transistor among multiple pixels, the number of transistors per pixel can be reduced. Therefore, the area occupied by the transistors can be reduced, and the resolution of the display device can be improved.

[0434] 67, the configuration corresponding to one pixel can be said to correspond to the configuration of the semiconductor device 100 shown in Fig. 37A described above without the transistor M14. Therefore, the above description can be referred to as appropriate, and detailed description will be omitted here.

[0435] FIG. 68 is a circuit diagram illustrating an example in which a configuration is applied in which two adjacent pixels in the row direction each correspond to the semiconductor device 100 shown in FIG. 37A described above, and a bootstrap transistor (corresponding to transistor M13) is shared.

[0436] In the semiconductor device 100X2 shown in FIG. 68, each of the pixel circuit 101L and the pixel circuit 101R includes a transistor M11, a transistor M12, a transistor M14, a capacitive element C11, and a write control unit 102.

[0437] In this case, the light-emission control unit 110X2 is composed of the transistor M13, the transistor M12, the transistor M14, and the capacitor C11 of the pixel circuit 101L, and the transistor M12, the transistor M14, and the capacitor C11 of the pixel circuit 101R. Therefore, the light-emission control unit 110X2 can be said to be configured such that one transistor M13 is shared between the transistor M13 in the light-emission control unit 110 of the pixel circuit 101L and the transistor M13 in the light-emission control unit 110 of the pixel circuit 101R. In this way, by sharing one bootstrap transistor between two pixels, the number of transistors per pixel can be reduced. This reduces the area occupied by the transistors, thereby improving the resolution of the display device.

[0438] 68, the configuration corresponding to one pixel can be said to correspond to the semiconductor device 100 shown in Fig. 37A described above. Therefore, the above description can be referred to as appropriate, and detailed description will be omitted here.

[0439] FIG. 69 is a circuit diagram illustrating an example in which a configuration is applied in which a bootstrap transistor (corresponding to transistor M13) is shared when n pixels (n is an integer equal to or greater than 2) arranged in the row direction each correspond to the semiconductor device 100 shown in FIG. 37A described above.

[0440] 69 includes pixel circuits 101[1] to 101[n], light-emitting elements LD[1] to LD[n], and a transistor M13. Each of the pixel circuits 101[1] to 101[n] includes a transistor M11, a transistor M12, a transistor M14, a capacitor C11, and a write control unit 102.

[0441] The description of the above-mentioned embodiment 1 can be referred to as appropriate for the semiconductor device 100XN shown in this embodiment, and the pixel circuits 101[1] to 101[n], light-emitting elements LD[1] to LD[n], and transistor M13 included in the semiconductor device 100XN.

[0442] In this case, the light-emitting control unit 110XN is configured with the transistor M13, and the transistors M12, M14, and C11 included in each of the pixel circuits 101[1] to 101[n]. Therefore, the light-emitting control unit 110XN can be said to have a configuration in which the transistor M13 in each of the light-emitting control units 110 of the pixel circuits 101[1] to 101[n] is shared. In this way, by sharing one bootstrap transistor among n pixels, the number of transistors per pixel can be reduced. This reduces the area occupied by the transistors, thereby improving the resolution of the display device.

[0443] 69, the configuration corresponding to one pixel can be said to correspond to the semiconductor device 100 shown in Fig. 37A described above. Therefore, the above description can be referred to as appropriate, and detailed description will be omitted here.

[0444] Here, the transistor M13 included in the light-emission control unit 110XN may be provided outside the semiconductor device 100XN. In FIG. 69, an example in which the transistor M13 included in the light-emission control unit 110XN is provided in the drive circuit 120 is shown.

[0445] As shown in FIG. 69 , the driver circuit 120 includes a buffer BUF and a transistor M13. One of the source and the drain of the transistor M13 is connected to the semiconductor device 100XN. For example, one of the source and the drain of the transistor M13 is connected to the gate of the transistor M12 and the other terminal of the capacitor C11 in each of the pixel circuits 101[1] to 101[n]. The other of the source and the drain of the transistor M13 is connected to a wiring EM. The gate of the transistor M13 is connected to a wiring VL1. The output of the buffer BUF is connected to the wiring EM. The buffer BUF has a function of supplying a signal to the wiring EM.

[0446] The buffer BUF can be configured using, for example, n-channel transistors. Alternatively, it may be configured using both n-channel and p-channel transistors. Alternatively, it may be configured using, for example, a CMOS circuit.

[0447] The driving circuit 120 is provided in, for example, the gate driver unit 163 included in the display device 160 shown in FIG. 34A and the like in the first embodiment described above.

[0448] Note that one embodiment of the present invention is not limited to the configuration examples, operation examples, and the like described in this embodiment. The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments, etc.

[0449] In this embodiment, a transistor according to one embodiment of the present invention will be described. At least part of the transistor described in this embodiment can be applied to the semiconductor device and display device described in Embodiment 1, the semiconductor device described in Embodiment 2, or the like.

[0450] <Transistor Configuration Example 1> Fig. 70A is a top view of a transistor 200A. Fig. 70B is a cross-sectional view taken along the line A1-A2 indicated by the dashed-dotted line in Fig. 70A. Fig. 70C is a cross-sectional view taken along the line A3-A4 indicated by the dashed-dotted line in Fig. 70A. Note that some elements are omitted from the top view in Fig. 70A for clarity. Some elements may also be omitted from other top views.

[0451] The transistor 200A has an insulating layer 202 over a substrate 201 and a semiconductor layer 203 over the insulating layer 202. The transistor 200A also has an insulating layer 204 over the insulating layer 202 and the semiconductor layer 203. The transistor 200A also has a conductive layer 205 over the insulating layer 204. The semiconductor layer 203 and the conductive layer 205 have regions that overlap with each other with the insulating layer 204 interposed therebetween.

[0452] The semiconductor layer 203 has a region 203a that functions as one of the source region and the drain region of the transistor 200A, a channel formation region 203b, and a region 203c that functions as the other of the source region and the drain region. In the semiconductor layer 203, a region that overlaps with the conductive layer 205 functions as the channel formation region 203b. Therefore, the conductive layer 205 functions as the gate electrode of the transistor 200A. The insulating layer 204 functions as a gate insulating film of the transistor 200A.

[0453] In the semiconductor layer 203, the length of the channel formation region 203b in the X direction (corresponding to the distance between the region 203a and the region 203c in the channel formation region 203b) is the channel length Lch of the transistor 200A (see FIGS. 70A and 70B ). In the semiconductor layer 203, the length of the channel formation region 203b in the Y direction (corresponding to the length of the portion where the region 203a and the region 203c face each other in the channel formation region 203b) is the channel width Wch of the transistor 200A (see FIGS. 70A and 70C ).

[0454] An insulating layer 206 is provided over the insulating layer 204 and the conductive layer 205. An opening 207a is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with the region 203a of the semiconductor layer 203. An opening 207b is provided in the insulating layer 204 and the insulating layer 206 in a region overlapping with the region 203c of the semiconductor layer 203.

[0455] A conductive layer 208a is provided over the insulating layer 206 and in the opening 207a, and a conductive layer 208b is provided over the insulating layer 206 and in the opening 207b. The conductive layer 208a is in contact with the region 203a of the semiconductor layer 203 at the bottom of the opening 207a. The conductive layer 208b is in contact with the region 203c of the semiconductor layer 203 at the bottom of the opening 207b. Thus, the conductive layer 208a functions as one of the source and drain electrodes of the transistor 200A, and the conductive layer 208b functions as the other of the source and drain electrodes of the transistor 200A.

[0456] In addition, an insulating layer 209 is provided over the insulating layer 206 and the conductive layer 208 (the conductive layer 208a and the conductive layer 208b).

[0457] 71A is a top view of a transistor 200B. The transistor 200B is a variation of the transistor 200A. To reduce repetition of description, differences between the transistor 200B and the transistor 200A will be mainly described.

[0458] Fig. 71B is a cross-sectional view taken along the dashed line A1-A2 in Fig. 71A. Fig. 71C is a cross-sectional view taken along the dashed line A3-A4 in Fig. 71A.

[0459] The transistor 200B differs from the transistor 200A in that a conductive layer 219 is provided between the substrate 201 and the insulating layer 202. The conductive layer 219 overlaps with the channel formation region 203b through the insulating layer 202. Thus, the insulating layer 202 functions as a back-gate insulating film of the transistor 200B, and the conductive layer 219 functions as a back-gate electrode of the transistor 200B. Note that the insulating layer 202 may have a different thickness between a region overlapping with the conductive layer 219 and a region not overlapping with the conductive layer 219, or may have a uniform thickness. The conductive layer 219 may extend beyond the end of the channel formation region 203b. Note that, although not shown, an insulating layer may be provided between the substrate 201 and the conductive layer 219.

[0460] In a transistor having a back gate, the gate and the back gate of the transistor are arranged to sandwich a channel formation region of the semiconductor layer. The back gate can function in the same manner as the gate. When the gate is used to control the on / off state of the transistor, the potential of the back gate can be the same as that of the gate. Alternatively, the back gate can be set to any potential.

[0461] For example, when a transistor is turned on, supplying a potential that turns the transistor on to both the gate and the back gate can increase the on-state current compared to supplying a potential to only one of them. For example, by connecting the gate and the back gate, the gate and the back gate can always be at the same potential. Furthermore, by controlling the back gate potential independently of the gate potential, the threshold voltage of the transistor can be adjusted.

[0462] A constant potential such as a ground potential may be supplied to the back gate. Since the gate and the back gate are formed of a conductive layer or the like, sandwiching the channel formation region of the semiconductor layer between the gate and the back gate makes it difficult for an electric field generated outside the transistor to act on the channel formation region (also referred to as an "electric field shielding effect"). Therefore, providing a back gate in a transistor stabilizes the operation of the transistor. Furthermore, providing a back gate in a transistor reduces variations in characteristics among multiple transistors. Providing a back gate in a transistor can improve the reliability of the transistor. Therefore, the reliability of a semiconductor device including the transistor can be improved. Note that the electric field shielding effect can be obtained even when one or both of the gate and the back gate are electrically floating (also referred to as a "floating state"), but the effect can be enhanced by supplying a potential to the gate and the back gate.

[0463] 72A is a top view of a transistor 200C. FIG. 72B is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in FIG. 72A.

[0464] The transistor 200C includes an insulating layer 202 over a substrate 201 and a conductive layer 255 over the insulating layer 202. The transistor 200C also includes an insulating layer 257 over the conductive layer 255, an insulating layer 258 over the insulating layer 257, and an insulating layer 259 over the insulating layer 258. Note that in this specification and the like, the insulating layer 257, the insulating layer 258, and the insulating layer 259 may be collectively referred to as an insulating layer 256 or a spacer layer. The transistor 200C also includes a conductive layer 261 over the insulating layer 259.

[0465] In addition, an opening 262 is provided in the conductive layer 261, the insulating layer 259, the insulating layer 258, and the insulating layer 257 in a region overlapping with part of the conductive layer 255. In addition, a semiconductor layer 263 is provided in contact with an inner wall of the opening 262.

[0466] The semiconductor layer 263 has a region overlapping with the bottom of the opening 262 and a region overlapping with the inner wall of the opening 262. That is, the semiconductor layer 263 has a region in contact with the insulating layer 256 in the opening 262. The semiconductor layer 263 also has a region in contact with the conductive layer 255 and a region in contact with the conductive layer 261 in the opening 262.

[0467] An insulating layer 264 is provided over the insulating layer 259, the conductive layer 261, and the semiconductor layer 263. A conductive layer 265 is provided over the insulating layer 264. The conductive layer 265 has a region overlapping with the semiconductor layer 263. The conductive layer 265 has a region overlapping with the semiconductor layer 263 with the insulating layer 264 interposed therebetween.

[0468] The insulating layer 264 and the conductive layer 265 each have a region overlapping with the opening 262. In the opening 262, the semiconductor layer 263 has a region overlapping with the conductive layer 265 with the insulating layer 264 interposed therebetween and a region overlapping with an inner wall of the opening 262 (a side surface of the insulating layer 256).

[0469] Furthermore, an insulating layer 266 is provided on the insulating layer 264. Note that the upper surface of the insulating layer 266 is preferably flat. Alternatively, the heights (positions in the Z direction) of the upper surfaces of the insulating layer 266 and the conductive layer 265 may be the same. For example, the flatness of the upper surface of the insulating layer 266 can be improved by performing chemical mechanical polishing (CMP) processing or the like. Furthermore, the heights of the upper surfaces of the insulating layer 266 and the conductive layer 265 can be made the same by performing CMP processing. By performing CMP processing, unevenness on the sample surface can be reduced, and the coverage of the insulating layer and conductive layer to be formed subsequently can be improved.

[0470] When an oxide semiconductor is used for the semiconductor layer 263, the conductive layer 255 in contact with the semiconductor layer 263 and the conductive layer 261 in contact with the semiconductor layer 263 are preferably formed using a conductive material that makes the oxide semiconductor n-type. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. Alternatively, another conductive material may be provided over the conductive material containing nitrogen.

[0471] When an oxide semiconductor is used for the semiconductor layer 263, it is preferable to use a material containing oxygen and having reduced hydrogen for the insulating layer 258. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide or silicon oxynitride may be used. Since hydrogen is an impurity element in an oxide semiconductor, contact between the semiconductor layer 263, which is an oxide semiconductor, and the insulating layer 258 in which hydrogen is reduced makes it difficult for the semiconductor layer 263 to become n-type. Furthermore, contact between the semiconductor layer 263, which is an oxide semiconductor, and the insulating layer 258 containing oxygen reduces oxygen vacancies in the semiconductor layer 263, thereby stabilizing the characteristics of the transistor and improving its reliability.

[0472] In the case where an oxide semiconductor is used for the semiconductor layer 263, the insulating layer 258 may contain excess oxygen. In this specification and the like, the term "excess oxygen" refers to oxygen that is released by heating. A material that releases oxygen by heating is a material that releases oxygen in an amount of 1.0×10 converted into oxygen atoms in a thermal desorption spectroscopy (TDS) analysis. １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３ More preferably, 2.0 × 10 １９ atoms / cm ３ or more or 3.0 x 10 ２０ atoms / cm ３ The surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C or 100°C to 400°C.

[0473] When a material containing excess oxygen is used for the insulating layer 258, it is preferable to use a material that is impermeable to oxygen for the insulating layers 257 and 259. Examples of the material that is impermeable to oxygen include an oxide containing one or both of aluminum and hafnium, and a nitride of silicon. By using a material that is impermeable to oxygen for the insulating layers 257 and 259, the excess oxygen contained in the insulating layer 258 is less likely to be released into the lower or upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, a structure may be used in which an insulating layer (insulating layer 258) containing silicon and oxygen is provided between two insulating layers (insulating layer 257 and insulating layer 259) containing silicon and nitrogen.

[0474] When an oxide semiconductor is used for the semiconductor layer 263, a material containing hydrogen may be used for the insulating layers 257 and 259. As a result, hydrogen is supplied to a region of the semiconductor layer 263 in contact with the insulating layer 257 and a region of the semiconductor layer 263 in contact with the insulating layer 259, and each region of the semiconductor layer 263 becomes n-type. Therefore, the region of the semiconductor layer 263 in contact with the conductive layer 261 and the region of the semiconductor layer 263 in contact with the insulating layer 259 function as one of the source region and the drain region. The region of the semiconductor layer 263 in contact with the conductive layer 255 and the region of the semiconductor layer 263 in contact with the insulating layer 257 function as the other of the source region and the drain region.

[0475] The conductive layer 261 functions as one of the source electrode and the drain electrode of the transistor 200C. The conductive layer 255 functions as the other of the source electrode and the drain electrode of the transistor 200C. The transistor 200C is a transistor in which the source electrode and the drain electrode are arranged in the Z direction. That is, the source electrode and the drain electrode of the transistor 200C are arranged at different heights. In other words, the source electrode and the drain electrode of the transistor 200C are arranged at different positions in the Z direction. Such a transistor is also called a "vertical channel transistor," "vertical channel transistor," "vertical transistor," or "VFET (Vertical Field Effect Transistor)."

[0476] In the above configuration, in the transistor 200C, which is a VFET, the length of the side surface of the insulating layer 258 as viewed in the X direction or the Y direction is the channel length Lch (here, the channel length L1) of the transistor 200C (see FIG. 72B ). Therefore, the channel length Lch of the transistor 200C is determined according to the thickness t1 of the insulating layer 258.

[0477] Alternatively, the insulating layers 257 and 259 may be formed using a material that does not contain hydrogen or contains very little hydrogen. For example, silicon nitride or silicon nitride oxide containing very little hydrogen may be used. In this case, the region of the semiconductor layer 263 in contact with the insulating layer 257 and the region of the semiconductor layer 263 in contact with the insulating layer 259 are not made n-type. Therefore, the region of the semiconductor layer 263 in contact with the conductive layer 261 functions as one of the source region and the drain region. The region of the semiconductor layer 263 in contact with the conductive layer 255 functions as the other of the source region and the drain region. The region of the semiconductor layer 263 in contact with the insulating layer 258 functions as a channel formation region.

[0478] In this case, the sum of the lengths of the side surfaces of the insulating layers 257, 258, and 259 as viewed from the X direction or the Y direction is the channel length Lch (here, the channel length L2) of the transistor 200C. Therefore, the channel length Lch of the transistor 200C is determined according to the total thickness t2 of the insulating layers 257, 258, and 259. In this way, the transistor 200C has a channel formation region that extends along the side surface of the insulating layer 256.

[0479] Furthermore, because the semiconductor layer 263 is provided in the opening 262, the perimeter of the opening 262 as viewed from the Z direction is the channel width Wch of the transistor 200C (see FIG. 72A ). The perimeter can be determined, for example, at a position halfway between the thickness t1 or the thickness t2 of the insulating layer 258. Note that, if necessary, the perimeter of any position on the opening 262 may be used as the channel width Wch. For example, the perimeter of the bottom of the opening 262 may be used as the channel width Wch, or the perimeter of the top of the opening 262 may be used as the channel width Wch. Although FIG. 72A shows the outline (planar shape) of the opening 262 as viewed from the Z direction as a circle, this is not limiting. For example, the outline of the opening 262 as viewed from the Z direction may be an ellipse or a rectangle.

[0480] The channel length Lch of the transistor 200C is preferably at least smaller than the channel width Wch of the transistor 200C. For example, the channel length Lch can be set to 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width Wch.

[0481] In order to improve the coverage of the semiconductor layer 263, the insulating layer 264, and the conductive layer 265 formed inside the opening 262, the taper angle θ of the inner wall of the opening 262, i.e., the taper angle θ of each of the side surfaces of the insulating layer 257, the insulating layer 258, and the insulating layer 259, may be set to 45° or more and 90° or less, preferably 50° or more and 75° or less. Note that the taper angle θ of the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle between the bottom surface and the side surface of the layer (see FIG. 72B ).

[0482] A vertical transistor can occupy a smaller area than a transistor (also called a "horizontal transistor") in which a channel formation region, a source region, and a drain region are separately provided on the XY plane. Therefore, by using a vertical transistor in a semiconductor device, the area occupied by the semiconductor device can be reduced. Furthermore, by using a vertical transistor in a semiconductor device, high integration of the semiconductor device can be achieved.

[0483] Furthermore, in a lateral transistor, the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult. On the other hand, in a vertical transistor, the channel length can be set by the film thickness of the insulating layer 256 or 258. Therefore, the channel length of the transistor can be made into an extremely fine structure (e.g., 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more or 5 nm or more) that is equal to or less than the exposure limit of photolithography. This increases the on-state current of the transistor 200C, thereby improving frequency characteristics. By using a vertical transistor, a semiconductor device with high operating speed can be provided.

[0484] <Transistor Configuration Example 4> Fig. 73A is a top view of a transistor 200D. Fig. 73B is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in Fig. 73A. Fig. 73C is a cross-sectional view taken along the line A3-A4 indicated by the dashed dotted line in Fig. 73A. Note that Fig. 73B is a cross-sectional view of the transistor 200D in the channel length direction, and Fig. 73C is a cross-sectional view of the transistor 200D in the channel width direction.

[0485] As shown in Figures 73A to 73C, the transistor 200D has a semiconductor layer 520a arranged on a substrate 201, a semiconductor layer 520b arranged on the semiconductor layer 520a, conductive layers 542a and 542b arranged spaced apart from each other on the semiconductor layer 520b, an insulating layer 580 arranged on the conductive layers 542a and 542b and having an opening formed between the conductive layers 542a and 542b, a conductive layer 560 arranged in the opening, an insulating layer 550 arranged among the semiconductor layer 520b, the conductive layers 542a, 542b, and the insulating layer 580, and the conductive layer 560, and a semiconductor layer 520c arranged among the semiconductor layer 520b, the conductive layers 542a, 542b, the insulating layer 580, and the insulating layer 550. 73B and 73C , the height of the top surface of the conductive layer 560 is the same as the height of the top surfaces of the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580. Note that hereinafter, the semiconductor layers 520a, 520b, and 520c may be collectively referred to as the semiconductor layer 520. The conductive layers 542a and 542b may be collectively referred to as the conductive layer 542.

[0486] 73A to 73C , an insulating layer 554 is disposed between the insulating layer 524, the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542a, the conductive layer 542b, and the insulating layer 580. The insulating layer 554 is in contact with the top surface and side surfaces of the conductive layer 542a, the top surface and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524.

[0487] The conductive layer 542a functions as one of the source electrode and the drain electrode of the transistor 200D. The conductive layer 542b functions as the other of the source electrode and the drain electrode of the transistor 200D. In the semiconductor layer 520, a region overlapping with the conductive layer 560 functions as a channel formation region of the transistor 200D. Therefore, the conductive layer 560 functions as a gate electrode of the transistor 200D. The insulating layer 550 functions as a gate insulating film of the transistor 200D.

[0488] The channel formation region of the transistor 200D is formed between a region that functions as one of the source region and the drain region and a region that functions as the other of the source region and the drain region in the semiconductor layer 520. Therefore, the distance between the conductive layer 542a and the conductive layer 542b can be defined as the channel length Lch of the transistor 200D (see FIGS. 73A and 73B ). The length of the portion where the conductive layer 542a and the conductive layer 542b face each other can be defined as the channel width Wch of the transistor 200D (see FIGS. 73A and 73C ).

[0489] Although the transistor 200D has a three-layer structure including the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c in the channel formation region and its vicinity, the present invention is not limited to this. For example, a two-layer structure including the semiconductor layer 520b and the semiconductor layer 520c or a stacked structure of four or more layers may be provided. Furthermore, each of the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c may have a stacked structure of two or more layers.

[0490] For example, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer 520, and the semiconductor layer 520c has a stacked structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, the first metal oxide may have a composition similar to that of the semiconductor layer 520b, and the second metal oxide may have a composition similar to that of the semiconductor layer 520a.

[0491] The conductive layer 560 is formed so as to fill the opening formed in the insulating layer 580 and the region sandwiched between the conductive layers 542a and 542b. The conductive layers 560, 542a, and 542b are arranged in a self-aligned manner with respect to the opening formed in the insulating layer 580. That is, in the transistor 200D, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductive layer 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 200D. This reduces the area occupied by the semiconductor device. Furthermore, the integration density of the semiconductor device can be increased.

[0492] 73A to 73C , the conductive layer 560 includes a conductive layer 560a provided over the insulating layer 550 and a conductive layer 560b provided over the conductive layer 560a, both of which are located inside an opening formed in the insulating layer 580. The insulating layer 550 and the conductive layer 560 are provided so as to fill the opening formed in the insulating layer 580. Note that although the conductive layer 560 in the transistor 200D has a two-layer stacked structure, this is not limiting. For example, the conductive layer 560 may have a single-layer structure or a three- or more-layer stacked structure.

[0493] The transistor 200D includes an insulating layer 202 disposed on the substrate 201, an insulating layer 514 disposed on the insulating layer 202, an insulating layer 516 disposed on the insulating layer 514, a conductive layer 505 disposed so as to be embedded in the insulating layer 516, an insulating layer 522 disposed on the insulating layer 516 and the conductive layer 505, and an insulating layer 524 disposed on the insulating layer 522. In addition, a semiconductor layer 520a is disposed on the insulating layer 524.

[0494] Further, insulating layers 574 and 581 functioning as interlayer films are provided over the transistor 200D. The insulating layer 574 is provided in contact with top surfaces of the conductive layer 560, the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580.

[0495] When an oxide semiconductor is used for the semiconductor layer 520, the insulating layers 522, 554, and 574 may be insulating layers having a function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, and the like). For example, the insulating layers 522, 554, and 574 may be insulating layers having lower hydrogen permeability than the insulating layers 524, 550, and 580. Alternatively, the insulating layers 522 and 554 may be insulating layers having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like). For example, the insulating layers 522 and 554 may be insulating layers having lower oxygen permeability than the insulating layers 524, 550, and 580. For example, the insulating layers 522, 554, and 574 may be made of silicon nitride, silicon nitride oxide, or the like.

[0496] Here, the insulating layer 524, the semiconductor layer 520, and the insulating layer 550 are separated from the layers above the insulating layer 574 and below the insulating layer 522 by the insulating layer 522 and the insulating layer 574. Therefore, impurities such as hydrogen and excess oxygen contained in the layers above the insulating layer 574 and below the insulating layer 522 can be prevented from being mixed into the insulating layer 524, the semiconductor layer 520, and the insulating layer 550.

[0497] 73B shows an example in which a conductive layer 545 (conductive layer 545a and conductive layer 545b) connected to the transistor 200D and functioning as a plug is provided. Note that an example in which an insulating layer 541 (insulating layer 541a and insulating layer 541b) is provided in contact with the side surface of the conductive layer 545 functioning as a plug is shown. That is, the insulating layer 541a and the insulating layer 541b are provided in contact with the inner walls of two openings formed in the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581, respectively. In addition, in FIG. 73B, a first conductive layer of the conductive layer 545 is provided in contact with the side surface of the insulating layer 541, and a second conductive layer of the conductive layer 545 is provided further inside.

[0498] Here, the height of the top surface of the conductive layer 545 can be made approximately the same as the height of the top surface of the insulating layer 581. Note that although the transistor 200D has a structure in which the first conductive layer of the conductive layer 545 and the second conductive layer of the conductive layer 545 are stacked, the present invention is not limited to this. For example, the conductive layer 545 may have a single layer structure or a stacked structure of three or more layers.

[0499] In addition, the thickness of a region of the semiconductor layer 520b that does not overlap with the conductive layer 542 may be thinner than the thickness of a region that overlaps with the conductive layer 542. This is achieved by removing part of the top surface of the semiconductor layer 520b when forming the conductive layers 542a and 542b. When a conductive film that will become the conductive layer 542 is formed on the top surface of the semiconductor layer 520b, a low-resistance region may be formed near the interface with the conductive film. In this case, removing the low-resistance region located between the conductive layers 542a and 542b in the semiconductor layer 520b can prevent a channel from being formed in the region.

[0500] Next, the detailed configuration of the transistor 200D will be described.

[0501] The conductive layer 505 is arranged to have a region overlapping with the conductive layer 560 with the semiconductor layer 520 interposed therebetween. By providing the conductive layer 505 so as to be embedded in the insulating layer 516, unevenness on the top surfaces of the conductive layer 505 and the insulating layer 516 can be reduced, and coverage with layers formed in later steps can be improved.

[0502] The conductive layer 505 includes a conductive layer 505a, a conductive layer 505b, and a conductive layer 505c. The conductive layer 505a is provided in contact with the bottom and inner wall of an opening provided in the insulating layer 516. The conductive layer 505b is provided so as to fill a recess formed in the conductive layer 505a. The height of the top surface of the conductive layer 505b is lower than the height of the top surface of the conductive layer 505a and the height of the top surface of the insulating layer 516. The conductive layer 505c is provided in contact with the top surface of the conductive layer 505b and the side surface of the conductive layer 505a. The height of the top surface of the conductive layer 505c is the same as the height of the top surface of the conductive layer 505a and the height of the top surface of the insulating layer 516. In other words, the conductive layer 505b is surrounded by the conductive layers 505a and 505c.

[0503] In the case where an oxide semiconductor is used for the semiconductor layer 520, the conductive layer 505a and the conductive layer 505c can be formed of a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (N ２ O, NO, NO ２ Alternatively, a conductive material having a function of suppressing the diffusion of impurities such as copper atoms, etc., or a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) may be used.

[0504] By using a conductive material that can reduce hydrogen diffusion for the conductive layers 505a and 505c, impurities such as hydrogen contained in the conductive layer 505b can be prevented from diffusing into the semiconductor layer 520 through the insulating layer 524 or the like. Furthermore, by using a conductive material that can reduce oxygen diffusion for the conductive layers 505a and 505c, it is possible to prevent the conductive layer 505b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can reduce oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductive layer 505a can be formed as a single layer or a stack of the above conductive materials. For example, the conductive layer 505a can be formed as titanium nitride.

[0505] Alternatively, the conductive layer 505b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0506] When the conductive layer 560 is used as a gate electrode, the conductive layer 505 functions as a back gate electrode. The insulating layers 522 and 524 function as back gate insulating films.

[0507] Note that the conductive layer 505 may be used as a gate electrode. In this case, the conductive layer 560 functions as a back gate electrode. The insulating layers 522 and 524 function as gate insulating films, and the insulating layer 550 functions as a back gate insulating film.

[0508] The conductive layer 505 may be provided to be larger than the channel formation region in the semiconductor layer 520. In particular, as shown in Fig. 73C, the conductive layer 505 may extend to a region outside the end portion intersecting with the channel width direction of the semiconductor layer 520. In other words, the conductive layer 505 and the conductive layer 560 may overlap with each other with an insulating layer interposed therebetween on the outside of the side surface of the semiconductor layer 520 in the channel width direction.

[0509] With the above structure, the channel formation region of the semiconductor layer 520 can be surrounded by the electric field of the conductive layer 560 functioning as a gate electrode and the electric field of the conductive layer 505 functioning as a back gate electrode.

[0510] The conductive layer 505 may be used as a wiring by extending it beyond the end of the semiconductor layer 520. However, the present invention is not limited to this, and a conductive layer that functions as a wiring may be provided under the conductive layer 505.

[0511] The insulating layer 514 may be formed using an insulating material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200D from the substrate side. Therefore, the insulating layer 514 may be formed using an insulating material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200D from the substrate side. ２ O, NO, NO ２ Alternatively, an insulating material having a function of suppressing the diffusion of impurities such as copper atoms (i.e., impurities are less likely to permeate) may be used. Alternatively, an insulating material having a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., oxygen is less likely to permeate) may be used.

[0512] For example, aluminum oxide, silicon nitride, or the like can be used for the insulating layer 514. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulating layer 514 to the transistor 200D. Alternatively, it can prevent oxygen contained in the insulating layer 524 or the like from diffusing toward the substrate side of the insulating layer 514.

[0513] The insulating layer 516, the insulating layer 580, and the insulating layer 581, which function as interlayer films, may be formed using an insulating material having a lower dielectric constant than the insulating layer 514. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, the insulating layer 516, the insulating layer 580, and the insulating layer 581 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like.

[0514] Here, the insulating layer 524 in contact with the semiconductor layer 520 may contain excess oxygen. For example, silicon oxide, silicon oxynitride, or the like can be used for the insulating layer 524. By providing an insulating layer containing oxygen in contact with the semiconductor layer 520, oxygen vacancies in the semiconductor layer 520 are reduced, and the reliability of the transistor 200D is improved.

[0515] 73C , the thickness of the insulating layer 524 in a region that does not overlap with the insulating layer 554 and the semiconductor layer 520b may be thinner than the thickness of the other region. It is preferable that the thickness of the insulating layer 524 in a region that does not overlap with the insulating layer 554 and the semiconductor layer 520b is set to a thickness that allows sufficient diffusion of the oxygen.

[0516] The insulating layer 522 may be formed using a material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200D from the substrate side, similar to the insulating layer 514. For example, the insulating layer 522 may be formed using a material that has lower hydrogen permeability than the insulating layer 524. By surrounding the insulating layer 524, the semiconductor layer 520, the insulating layer 550, and the like with the insulating layer 522, the insulating layer 554, and the insulating layer 574, impurities such as water or hydrogen can be prevented from entering the transistor 200D from the outside.

[0517] Furthermore, the insulating layer 522 may be made of a material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) (i.e., is less permeable to oxygen). For example, the insulating layer 522 may be made of a material that has lower oxygen permeability than the insulating layer 524. The insulating layer 522 has a function of suppressing the diffusion of oxygen, which can reduce oxygen diffusing from the semiconductor layer 520 toward the substrate. Furthermore, the conductive layer 505 can be prevented from reacting with oxygen contained in the insulating layer 524 or the semiconductor layer 520.

[0518] The insulating layer 522 may contain an oxide of one or both of insulating materials, such as aluminum and hafnium. Examples of the insulating layer containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxide containing aluminum and hafnium (hafnium aluminate). When the insulating layer 522 is formed using such a material, the insulating layer 522 functions as a layer that suppresses oxygen release from the semiconductor layer 520 and the intrusion of impurities such as hydrogen into the semiconductor layer 520 from the periphery of the transistor 200D.

[0519] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulating layers. Alternatively, these insulating layers may be nitrided. Furthermore, a stacked structure of the above insulating layer and silicon oxide, silicon oxynitride, or silicon nitride may be used. For example, the insulating layer 522 may have a three-layer structure in which silicon nitride, silicon oxide, and aluminum oxide are stacked in this order.

[0520] The insulating layer 522 may be made of a material having a high relative dielectric constant (high-k) (aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ) or (Ba,Sr)TiO ３ An insulating layer containing a material such as BST may be used as a single layer or a laminate. As transistors become smaller and more highly integrated, problems such as gate leakage current may occur due to thinner gate insulating films. By using a material with a high dielectric constant for the insulating layer that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0521] Note that each of the insulating layer 522 and the insulating layer 574 may have a stacked structure of two or more layers. In this case, the insulating layer 522 and the insulating layer 574 are not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0522] The semiconductor layer 520 includes a semiconductor layer 520a, a semiconductor layer 520b on the semiconductor layer 520a, and a semiconductor layer 520c on the semiconductor layer 520b. By providing the semiconductor layer 520a below the semiconductor layer 520b, it is possible to suppress the diffusion of impurities from structures formed below the semiconductor layer 520a to the semiconductor layer 520b. Furthermore, by providing the semiconductor layer 520c on the semiconductor layer 520b, it is possible to suppress the diffusion of impurities from structures formed above the semiconductor layer 520c to the semiconductor layer 520b.

[0523] When an oxide semiconductor is used for the semiconductor layer 520, the semiconductor layer 520 may have a stacked structure of multiple oxide layers with different atomic ratios of metal atoms. For example, when the semiconductor layer 520 includes at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the semiconductor layer 520a to the number of atoms of all elements constituting the semiconductor layer 520a may be higher than the ratio of the number of atoms of the element M contained in the semiconductor layer 520b to the number of atoms of all elements constituting the semiconductor layer 520b. Furthermore, the atomic ratio of the element M contained in the semiconductor layer 520a to In may be higher than the atomic ratio of the element M contained in the semiconductor layer 520b to In. Here, the semiconductor layer 520c may use a metal oxide that can be used for the semiconductor layer 520a or the semiconductor layer 520b.

[0524] The energy levels of the conduction band minimums of the semiconductor layers 520a and 520c may be higher than the energy level of the conduction band minimum of the semiconductor layer 520b. In other words, the electron affinity of the semiconductor layers 520a and 520c may be lower than the electron affinity of the semiconductor layer 520b. In this case, the semiconductor layer 520c may be made of a metal oxide that can be used for the semiconductor layer 520a. Specifically, the ratio of the number of atoms of the element M contained in the semiconductor layer 520c to the number of atoms of all elements constituting the semiconductor layer 520c may be higher than the ratio of the number of atoms of the element M contained in the semiconductor layer 520b to the number of atoms of all elements constituting the semiconductor layer 520b. Furthermore, the atomic ratio of the element M contained in the semiconductor layer 520c to In may be higher than the atomic ratio of the element M contained in the semiconductor layer 520b to In.

[0525] Here, the energy level of the conduction band minimum changes gradually at the junction between the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c. In other words, the energy level of the conduction band minimum at the junction between the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c changes continuously or can be said to be a continuous junction. To achieve this, the defect level density of the mixed layer formed at the interface between the semiconductor layer 520a and the semiconductor layer 520b and the interface between the semiconductor layer 520b and the semiconductor layer 520c may be reduced.

[0526] Specifically, the semiconductor layers 520a and 520b, and the semiconductor layers 520b and 520c, may have a common element other than oxygen to form a mixed layer with a low defect level density. For example, when the semiconductor layer 520b is indium gallium zinc oxide (In—Ga—Zn oxide), the semiconductor layers 520a and 520c may be made of In—Ga—Zn oxide, gallium zinc oxide (Ga—Zn oxide), gallium oxide, or the like. The semiconductor layer 520c may also have a stacked structure. For example, a stacked structure of In—Ga—Zn oxide and Ga—Zn oxide on the In—Ga—Zn oxide, or a stacked structure of In—Ga—Zn oxide and gallium oxide on the In—Ga—Zn oxide, may be used. In other words, a stacked structure of In—Ga—Zn oxide and an oxide not containing In may be used as the semiconductor layer 520c.

[0527] Specifically, the semiconductor layer 520a may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of 1:1:0.5 or thereabouts. The semiconductor layer 520b may be made of a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of 3:1:2 or thereabouts, or an atomic ratio of 1:1:1 or thereabouts. The semiconductor layer 520c may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of Ga:Zn=2:1 or thereabouts, or an atomic ratio of Ga:Zn=2:5 or thereabouts. Specific examples of the semiconductor layer 520c having a stacked structure include a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or a ratio thereof near it and Ga:Zn=2:1 [atomic ratio] or a ratio thereof near it, a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or a ratio thereof near it and Ga:Zn=2:5 [atomic ratio] or a ratio thereof near it, and a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or a ratio thereof near it and gallium oxide.

[0528] In this case, the main carrier path is the semiconductor layer 520b. By configuring the semiconductor layers 520a and 520c as described above, the defect state density at the interface between the semiconductor layers 520a and 520b and the interface between the semiconductor layers 520b and 520c can be reduced. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 200D to achieve a large on-state current and high frequency characteristics. Note that when the semiconductor layer 520c has a stacked structure, in addition to the effect of reducing the defect state density at the interface between the semiconductor layers 520b and 520c, the diffusion of constituent elements of the semiconductor layer 520c toward the insulating layer 550 can be suppressed. More specifically, the semiconductor layer 520c has a stacked structure, and an oxide not containing In is positioned above the stacked structure, thereby suppressing In diffusion toward the insulating layer 550. The insulating layer 550 functions as a gate insulating film, and diffusion of In can result in poor transistor characteristics. Therefore, by forming the semiconductor layer 520c into a stacked structure, a highly reliable semiconductor device can be provided.

[0529] A conductive layer 542 (a conductive layer 542a and a conductive layer 542b) functioning as a source electrode and a drain electrode is provided over the semiconductor layer 520b. When an oxide semiconductor is used for the semiconductor layer 520b, the conductive layer 542 may be formed using a conductive material that is not easily oxidized or a conductive material that maintains its conductivity even when it absorbs oxygen.

[0530] A region of the semiconductor layer 520 in contact with the conductive layer 542 functions as a source region or a drain region of the transistor 200D. Here, the region between the conductive layer 542a and the conductive layer 542b is formed to overlap with an opening formed in the insulating layer 580. This allows the conductive layer 560 to be disposed in a self-aligned manner between the conductive layer 542a and the conductive layer 542b.

[0531] The insulating layer 550 functions as a gate insulating film. The insulating layer 550 is disposed in contact with the top surface of the semiconductor layer 520c. The insulating layer 550 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. For example, the insulating layer 550 can be formed using silicon oxide or silicon oxynitride.

[0532] The insulating layer 550 may be formed using an insulating material with a reduced concentration of impurities such as water or hydrogen, similar to the insulating layer 524. The thickness of the insulating layer 550 may be greater than or equal to 1 nm and less than or equal to 20 nm.

[0533] A metal oxide may be provided between the insulating layer 550 and the conductive layer 560. The metal oxide suppresses oxygen diffusion from the insulating layer 550 to the conductive layer 560. This can suppress oxidation of the conductive layer 560 due to oxygen contained in the insulating layer 550.

[0534] Although the conductive layer 560 is shown as having a two-layer structure in FIGS. 73A to 73C, it may have a single-layer structure or a stacked structure of three or more layers.

[0535] The conductive layer 560a is made of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ Alternatively, a conductive material having a function of suppressing the diffusion of impurities such as copper atoms, etc., or a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) may be used.

[0536] The conductive layer 560a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductive layer 560b caused by oxygen contained in the insulating layer 550. Examples of conductive materials that can suppress oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0537] The conductive layer 560b may be made of a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductive layer 560 also functions as a wiring, a conductive layer with high conductivity may be used. Furthermore, the conductive layer 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0538] 73B and 73C , in a region of the semiconductor layer 520b that does not overlap with the conductive layer 542, in other words, in the channel formation region of the semiconductor layer 520, the side surface of the semiconductor layer 520 is arranged to be covered with the conductive layer 560. This makes it easier for the electric field of the conductive layer 560, which functions as the gate electrode of the transistor 200D, to act on the side surface of the semiconductor layer 520. This increases the on-state current of the transistor 200D and improves its frequency characteristics.

[0539] The insulating layer 554 may be formed using an insulating material that prevents impurities such as water or hydrogen from entering the transistor 200D, similar to the insulating layer 514. For example, the insulating layer 554 may be formed using an insulating material that has lower hydrogen permeability than the insulating layer 524. Furthermore, as shown in FIGS. 73B and 73C , the insulating layer 554 is provided in contact with the side surfaces of the semiconductor layer 520c, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524. This structure can prevent hydrogen contained in the insulating layer 580 from entering the semiconductor layer 520.

[0540] Furthermore, an insulating material that has a function of suppressing diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) (i.e., oxygen is less permeable) may be used as the insulating layer 554. For example, an insulating material that has lower oxygen permeability than the insulating layer 580 or the insulating layer 524 may be used as the insulating layer 554.

[0541] When an oxide semiconductor is used for the semiconductor layer 520, the insulating layer 554 may be formed by a sputtering method. By forming the insulating layer 554 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulating layer 524 in the vicinity of a region in contact with the insulating layer 554. This allows oxygen to be supplied from this region into the semiconductor layer 520 through the insulating layer 524. Here, the insulating layer 554 has a function of suppressing upward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 to the insulating layer 580. Furthermore, the insulating layer 522 has a function of suppressing downward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 toward the substrate. In this manner, oxygen is supplied to the channel formation region of the semiconductor layer 520. This reduces oxygen vacancies in the semiconductor layer 520, and suppresses the transistor from becoming normally on.

[0542] For example, an insulating layer containing an oxide of one or both of aluminum and hafnium may be formed as the insulating layer 554. Note that as the insulating layer containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like can be used.

[0543] The insulating layer 580 is provided over the insulating layer 524, the semiconductor layer 520, and the conductive layer 542 with the insulating layer 554 interposed therebetween. For example, the insulating layer 580 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly suitable because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly suitable because they can easily form a region containing oxygen that is released by heating.

[0544] The insulating layer 574 may be formed using an insulating material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the insulating layer 580 from above, similar to the insulating layer 514. The insulating layer 574 may be formed using an insulating material that can be used for the insulating layer 514, the insulating layer 554, and the like, for example.

[0545] 73A to 73C show an example in which an insulating layer 581 functioning as an interlayer film is provided over the insulating layer 574. As the insulating layer 581, an insulating material in which the concentration of impurities such as water or hydrogen is reduced may be used, similar to the insulating layer 524.

[0546] A conductive layer 545a and a conductive layer 545b are disposed in each of two openings formed in the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554. The conductive layer 545a and the conductive layer 545b are provided opposite each other with the conductive layer 560 interposed therebetween. Note that the height of the top surfaces of the conductive layer 545a and the conductive layer 545b may be the same as the height of the top surface of the insulating layer 581.

[0547] Note that an insulating layer 541a is provided in contact with one of the inner walls of two openings formed in the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545a is formed in contact with the side surface of the insulating layer 541a. A conductive layer 542a is located in at least a part of the bottom of the opening, and the conductive layer 545a is in contact with the conductive layer 542a. Similarly, an insulating layer 541b is provided in contact with the inner wall of the other of the two openings formed in the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545b is formed in contact with the side surface of the insulating layer 541b. A conductive layer 542b is located in at least a part of the bottom of the opening, and the conductive layer 545b is in contact with the conductive layer 542b.

[0548] The conductive layers 545a and 545b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Each of the conductive layers 545a and 545b may have a stacked structure of two or more layers.

[0549] When the conductive layer 545 has a stacked-layer structure, a conductive layer having a function of suppressing diffusion of impurities such as water or hydrogen may be used as a conductive layer in contact with the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542, the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide can be used. By using such a conductive material, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b. Furthermore, impurities such as water or hydrogen from above the insulating layer 581 can be prevented from entering the semiconductor layer 520 through the conductive layers 545a and 545b.

[0550] The insulating layer 541a and the insulating layer 541b may be, for example, an insulating layer that can be used for the insulating layer 554. The insulating layer 541a and the insulating layer 541b are provided in contact with the insulating layer 554, and therefore can prevent impurities such as water or hydrogen from the insulating layer 580 or the like from entering the semiconductor layer 520 through the conductive layers 545a and 545b. Furthermore, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b.

[0551] <Transistor Configuration Example 5> Modifications of the transistor 200D shown in FIGS. 73A to 73C are shown in FIGS. 74A to 74C. FIG. 74A is a top view of a transistor 200E which is a modification of the transistor 200D. FIG. 74B is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in FIG. 74A. FIG. 74C is a cross-sectional view taken along the line A3-A4 indicated by the dashed dotted line in FIG. 74A. Because the transistor 200E is a modification of the transistor 200D, differences between the transistor 200E and the transistor 200D will be mainly described.

[0552] The transistor 200E has a structure in which the semiconductor layer 520c and the conductive layer 505c are omitted from the structure of the transistor 200D. Reducing the number of components of the transistor reduces production costs. Furthermore, reducing the number of components of the transistor shortens the manufacturing process, improving manufacturin...

Claims

a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance element, and a light emitting element; a first terminal of the first transistor is electrically connected to a first terminal of the second transistor, a first terminal of the fourth transistor, and a first terminal of the first capacitive element; a gate of the second transistor is electrically connected to a first terminal of the third transistor and a second terminal of the first capacitive element; the first transistor has a function of controlling an amount of current supplied to the light-emitting element in response to an image signal; the second transistor has a function of controlling whether the light-emitting element emits light or not; Semiconductor device. 　 In claim 1, a channel length of each of the second transistor to the fourth transistor is shorter than a channel length of the first transistor; Semiconductor device. 　 In claim 1, an area where a first electrode having a region that functions as a first terminal of the first capacitance element and a second electrode having a region that functions as a second terminal of the first capacitance element overlap with each other is larger than an area of ​​a channel formation region of the second transistor; Semiconductor device. 　 In any one of claims 1 to 3, a first circuit; the first circuit has a function of applying a potential corresponding to the image signal to a gate of the first transistor; Semiconductor device. 　 In any one of claims 1 to 3, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a second capacitance element; a gate of the first transistor is electrically connected to a first terminal of the seventh transistor, a first terminal of the eighth transistor, and a first terminal of the second capacitive element; a first terminal of the first transistor electrically connected to a second terminal of the seventh transistor; a second terminal of the first transistor is electrically connected to a first terminal of the fifth transistor and a first terminal of the sixth transistor; a second terminal of the second transistor electrically connected to a first terminal of the light-emitting element; a second terminal of the sixth transistor is electrically connected to a first wiring; a second terminal of the second capacitance element electrically connected to the first wiring; a second terminal of the third transistor is electrically connected to a second wiring; a gate of the third transistor electrically connected to a third wiring; a second terminal of the fourth transistor is electrically connected to a fourth wiring; a gate of the fourth transistor is electrically connected to a fifth wiring; a second terminal of the light-emitting element electrically connected to a sixth wiring; a second terminal of the fifth transistor is electrically connected to a seventh wiring to which the image signal is applied; a gate of the fifth transistor is electrically connected to an eighth wiring; a gate of the sixth transistor is electrically connected to a ninth wiring; The gate of the seventh transistor is electrically connected to a tenth wiring, a second terminal of the eighth transistor is electrically connected to an eleventh wiring; The gate of the eighth transistor is electrically connected to a twelfth wiring. Semiconductor device. 　 In claim 5, each of the first to eighth transistors is a p-channel transistor; Semiconductor device. 　 In claim 5, each of the first transistor to the sixth transistor is a p-channel transistor, each of the seventh transistor and the eighth transistor is an n-channel transistor; Semiconductor device. 　 In claim 5, each of the first to sixth transistors includes silicon in a channel formation region; each of the seventh transistor and the eighth transistor includes an oxide semiconductor in a channel formation region; Semiconductor device. 　 In claim 8, the oxide semiconductor contains indium oxide; Semiconductor device. 　 In claim 5, the light-emitting element is a light-emitting diode, the first terminal of the light-emitting element is the anode of the light-emitting diode; the second terminal of the light-emitting element is the cathode of the light-emitting diode; Semiconductor device. 　 In any one of claims 1 to 3, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a second capacitance element; a gate of the first transistor is electrically connected to a first terminal of the seventh transistor and a first terminal of the second capacitive element; a first terminal of the first transistor electrically connected to a second terminal of the seventh transistor; a second terminal of the first transistor is electrically connected to a first terminal of the fifth transistor and a first terminal of the sixth transistor; a second terminal of the sixth transistor is electrically connected to a first terminal of the light-emitting element, a second terminal of the second capacitive element, and a first terminal of the eighth transistor; a second terminal of the second transistor electrically connected to a first wiring; a second terminal of the third transistor is electrically connected to a second wiring; a gate of the third transistor electrically connected to a third wiring; a second terminal of the fourth transistor is electrically connected to a fourth wiring; a gate of the fourth transistor is electrically connected to a fifth wiring; a second terminal of the light-emitting element electrically connected to a sixth wiring; a second terminal of the fifth transistor is electrically connected to a seventh wiring to which the image signal is applied; a gate of the fifth transistor is electrically connected to an eighth wiring; a gate of the sixth transistor is electrically connected to a ninth wiring; The gate of the seventh transistor is electrically connected to a tenth wiring, a second terminal of the eighth transistor is electrically connected to an eleventh wiring; The gate of the eighth transistor is electrically connected to a twelfth wiring. Semiconductor device. 　 In claim 11, each of the first to eighth transistors is an n-channel transistor; Semiconductor device. 　 In claim 11, the seventh transistor includes an oxide semiconductor in a channel formation region; Semiconductor device. 　 In claim 13, the oxide semiconductor contains indium oxide; Semiconductor device. 　 In claim 11, the first transistor includes an oxide semiconductor in a channel formation region; Semiconductor device. 　 In claim 15, the oxide semiconductor contains indium oxide; Semiconductor device. 　 In claim 11, the light-emitting element is a light-emitting diode, the first terminal of the light-emitting element is the anode of the light-emitting diode; the second terminal of the light-emitting element is the cathode of the light-emitting diode; Semiconductor device. 　 a first pixel circuit, a second pixel circuit, a first light-emitting element, a second light-emitting element, and a first transistor; the first pixel circuit includes a second transistor, a third transistor, and a first capacitance element; the second pixel circuit includes a fourth transistor, a fifth transistor, and a second capacitive element; a first terminal of the second transistor is electrically connected to a first terminal of the third transistor and a first terminal of the first capacitive element; a first terminal of the fourth transistor is electrically connected to a first terminal of the fifth transistor and a first terminal of the second capacitive element; a gate of the third transistor is electrically connected to a gate of the fifth transistor, a first terminal of the first transistor, a second terminal of the first capacitance element, and a second terminal of the second capacitance element; the second transistor has a function of controlling an amount of current supplied to the first light-emitting element in response to a first image signal; the third transistor has a function of controlling whether the first light-emitting element emits light, and the fourth transistor has a function of controlling an amount of current supplied to the second light-emitting element in response to a second image signal; the fifth transistor has a function of controlling whether the second light-emitting element emits light or not; Semiconductor device. 　 In claim 18, the first pixel circuit includes a sixth transistor; the second pixel circuit includes a seventh transistor; a first terminal of the sixth transistor electrically connected to a first terminal of the third transistor; a first terminal of the seventh transistor electrically connected to a first terminal of the fifth transistor; Semiconductor device. 　 In claim 18 or claim 19, the first transistor includes an oxide semiconductor in a channel formation region; Semiconductor device. In claim 20, the oxide semiconductor contains indium oxide; Semiconductor device.

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