Semiconductor temperature test device using peltier element

Abstract

The present invention relates to a semiconductor temperature test device using a Peltier element and, more specifically, to a semiconductor temperature test device using a Peltier element, the semiconductor temperature test device comprising one or more pairs of Peltier element parts formed by stacking Peltier elements, wherein the one or more pairs of Peltier element parts are diagonally arranged to enhance durability while increasing heat generation or heat absorption.

Description

Semiconductor temperature test device using Peltier elements

[0001] The present invention relates to a semiconductor temperature test device using a Peltier element, and more specifically, to a semiconductor temperature test device using a Peltier element, which comprises at least one pair of Peltier element parts formed by stacking Peltier elements, and wherein at least one pair of Peltier element parts is arranged diagonally to increase heat generation or heat absorption while enhancing durability.

[0002] Wafers that have gone through various semiconductor manufacturing processes contain chips with hundreds of thousands of integrated circuits, and each chip is separated after its characteristics are measured and assembled into individual packages.

[0003] Through this process, a single semiconductor package is completed. The completed semiconductor package must be able to function normally in any environment. In other words, it must be able to function properly not only at room temperature but also at low and high temperatures.

[0004] However, some semiconductor packages do not operate or operate abnormally at low or high temperatures, and these semiconductor packages are classified as defective.

[0005] Here, in order to verify the electrical characteristics of the semiconductor package according to temperature conditions, a test process is performed under various temperature conditions.

[0006] To this end, a temperature control device separately installed outside the inspection chamber was used to supply high-temperature air or low-temperature air into the inspection chamber, thereby setting various temperature conditions in the inspection chamber.

[0007] However, the conventional method described above suffers from the problem of requiring a very long time to heat or cool the inspection chamber. Therefore, it inevitably takes a considerable amount of time to establish the desired temperature conditions within the inspection chamber.

[0008] Furthermore, since the temperature of the semiconductor package is indirectly set using air supplied from outside the inspection chamber, the temperature variation within the chamber is significant. Consequently, electrical characteristic testing of the semiconductor package cannot be performed at the exact desired temperature, resulting in very low reliability of the test results.

[0009] To improve this, a method has recently emerged in which a test module using a Peltier element is configured and the test module is brought into contact with the upper surface of the semiconductor package to perform a temperature inspection on the semiconductor package.

[0010] This Peltier element-based test module has the advantage of being able to perform tests while conveniently and quickly controlling the temperature to a desired level, compared to the existing chamber heating method, which is difficult to control, by heating or cooling the contact surface of the semiconductor element using a Peltier element whose one side is heated or cooled depending on the application of current.

[0011] However, as illustrated in Fig. 1, the Peltier elements configured in the existing test module are configured to be horizontally stacked, and these Peltier elements are configured to have a standardized size and heat capacity.

[0012] In addition, a Peltier element with the same size as the area of ​​the semiconductor package has a low heat capacity and is therefore unsuitable for controlling the temperature of the semiconductor package. Therefore, a Peltier element with a heat capacity capable of controlling the temperature of the semiconductor package must be configured to be relatively large, which causes the volume of the test module to become large.

[0013] In addition, since the test module is configured taking such volume into consideration, there is a problem that the thermal capacity of the test module using the Peltier element is limited and there is a problem that the test conditions for the semiconductor package are limited, making it difficult to perform tests on the semiconductor package under various temperature conditions.

[0014] The purpose of the present invention is to provide a device that can support easy and accurate temperature testing of a semiconductor package by having sufficient heat capacity to efficiently perform low-temperature and high-temperature tests on a semiconductor package using a Peltier element while being configured to have a minimal volume, and also has sufficient heat capacity to support temperature testing of a semiconductor package under various temperature conditions.

[0015] A semiconductor temperature test device using a Peltier element according to an embodiment of the present invention may include one or more pairs of Peltier elements configured in a diagonally symmetrical or asymmetrical structure to be heated or cooled according to the application of current, a temperature merging block configured between the one or more pairs of Peltier elements to be heated or cooled by the one or more pairs of Peltier elements, and a temperature conducting block heated or cooled by the temperature merging block to heat or cool a semiconductor element to be tested.

[0016] As an example related to the present invention, each of the pair or more Peltier element parts may be characterized by being composed of one or more Peltier elements or by being composed of a plurality of Peltier elements stacked on top of each other.

[0017] As an example related to the present invention, the semiconductor temperature test device using the Peltier element may be characterized by further including a control unit that applies a forward or reverse current to each of at least one Peltier element configured in each of the at least one pair of Peltier element sections.

[0018] As an example related to the present invention, the semiconductor temperature test device using the Peltier element may further include a main body including the one or more pairs of Peltier elements, and the one or more pairs of Peltier elements may include a first Peltier element portion arranged diagonally within the main body and a second Peltier element portion arranged diagonally within the main body to be symmetrical or asymmetrical with respect to the first Peltier element portion.

[0019] As an example related to the present invention, the temperature merging block unit may be provided between the first Peltier element unit and the second Peltier element unit, configured such that one side is in surface contact with the lower surface of the first Peltier element unit, and the other side is in surface contact with the lower surface of the second Peltier element unit, so as to merge and conduct heat from the first Peltier element unit and the second Peltier element unit, or merge and conduct cold air from the first Peltier element unit and the second Peltier element unit.

[0020] As an example related to the present invention, the semiconductor temperature test device using the Peltier element may be characterized by further including an adjustment knob for adjusting the height of the main body.

[0021] As an example related to the present invention, the semiconductor temperature test device using the Peltier element may further include a first heat exchange unit configured on the upper surface of the first Peltier element unit to perform heat exchange; and a second heat exchange unit configured on the upper surface of the second Peltier element unit to perform heat exchange.

[0022] As an example related to the present invention, the semiconductor temperature test device using the Peltier element may be characterized by further including an insulating block portion configured to be in contact with the upper portion of the temperature merging block portion to block the heat of the temperature merging block portion from being released to the outside.

[0023] As an example related to the present invention, the temperature conducting block part may be characterized by including a single temperature conducting block that is heated or cooled by the temperature merging block part and transmits heat or cold to the semiconductor element to be tested, and a guide temperature conducting block that is configured to be coupled to the outer peripheral surface or a part of the outer peripheral surface of the single temperature conducting block and that is heated or cooled by the single temperature conducting block and controls the temperature around the element to be tested.

[0024] As an example related to the present invention, the temperature conductive block section may be configured to include a conductive block coupled to a lower portion of the temperature merging block section so that a temperature test can be simultaneously performed on a plurality of test target devices mounted in each of the plurality of mounting areas by descending to a plate section having a plurality of mounting areas for mounting a plurality of semiconductor devices to be tested, and heated or cooled by the temperature merging block section; a first extension block configured to extend downwardly from one side of the conductive block and receive heat or cold air transmitted by the conductive block so as to heat or cool the test target device mounted in a first mounting area among the plurality of mounting areas through a surface in contact with the test target device; and a second extension block configured to extend downwardly from the other side of the conductive block and receive heat or cold air transmitted by the conductive block so as to heat or cool another test target device mounted in a second mounting area among the plurality of mounting areas through a surface in contact with the other test target device.

[0025] The semiconductor temperature test device using a Peltier element according to the present invention is configured to have a diagonal arrangement of one or more pairs of Peltier elements, each of which includes one or more Peltier elements, and to combine and transfer heat or cold air provided from each of the one or more pairs of Peltier elements to a semiconductor element to be tested, thereby providing sufficient heat generation or heat absorption to accurately temperature test the operating limit according to temperature change of the semiconductor element through the heat or cold air provided from the one or more pairs of Peltier elements, and by arranging one or more pairs of Peltier elements in a diagonal parallel arrangement, it is possible to obtain a high heat generation or heat absorption by arranging a large number of Peltier elements in a narrow space, and at the same time, transfer of heat or cold air can be performed by utilizing the entire planar area while reducing the planar area of ​​the Peltier elements, thereby greatly improving the heat or cold air transfer efficiency and transfer capability compared to existing equipment in which Peltier elements are stacked in a horizontal structure to reduce the contact area with the semiconductor element to be tested.

[0026] In addition, a semiconductor temperature test device configured to have one or more pairs of Peltier elements having a diagonal arrangement structure according to an embodiment of the present invention can increase durability because the Peltier elements are structured so that they do not directly receive a load, but receive a constant force from a variable repetitive load.

[0027] Figure 1 is a configuration diagram of a test module for semiconductor temperature testing according to the prior art.

[0028] Figure 2 is a configuration diagram of a semiconductor temperature test device using a Peltier element according to an embodiment of the present invention.

[0029] FIG. 3 is an exemplary diagram comparing temperature performance of a semiconductor temperature test device using a Peltier element according to an embodiment of the present invention when the Peltier element portion is formed in a vertical structure and when the Peltier element portion is formed diagonally.

[0030] Figure 4 is a configuration diagram of a semiconductor temperature test device using a Peltier element according to another embodiment of the present invention.

[0031] Hereinafter, detailed embodiments of the present invention will be described with reference to the drawings.

[0032] FIG. 2 is a configuration diagram of a semiconductor temperature test device (hereinafter, “semiconductor temperature test device”) using a Peltier element according to an embodiment of the present invention.

[0033] As illustrated, a semiconductor temperature test device according to an embodiment of the present invention may be configured to contact a semiconductor element (or semiconductor package element or semiconductor device) as a temperature test target mounted on a plate portion to apply heat to the semiconductor element or cool the semiconductor element.

[0034] Hereinafter, the semiconductor element that is the subject of the temperature test is referred to as the test subject element (200).

[0035] At this time, the plate portion (100) may be configured to include a mounting board plate (102) that constitutes the main body of the plate portion (100) and provides a mounting area where the test target element (200) is mounted, and a device guide plate (101) for guiding the mounting area of ​​the test target element (200).

[0036] In addition, the plate portion (100) may be configured so that the upper surface of the test target element (200) mounted on the mounting area of ​​the mounting board plate (102) is exposed to the outside.

[0037] In addition, the mounting board plate (102) may have a plurality of mounting areas, and the plate portion (100) may be configured to include a plurality of device guide plates (101) so as to correspond to each of the plurality of mounting areas.

[0038] Meanwhile, the semiconductor temperature test device may be configured to include a main body (10) (or housing) forming the exterior of the semiconductor temperature test device, one or more pairs of Peltier element parts (20, 30) configured inside the main body (10), a temperature merging block part (40), a temperature conducting block part (50), etc.

[0039] First, the above one or more pairs of Peltier elements (20, 30) may each be configured to include one or more Peltier elements.

[0040] At this time, the Peltier element is an electronic material that utilizes the Peltier effect, and is composed of one or more N-type semiconductors and one or more P-type semiconductors. The N-type semiconductors and P-type semiconductors are arranged alternately so that when current flows, one side absorbs heat (cooling) and the other side releases heat (heating).

[0041] In addition, the above-described pair of Peltier elements (20, 30) may be configured inside the main body (10) in a diagonally symmetrical or asymmetrical structure.

[0042] For example, the pair of Peltier elements (20, 30) may be configured to include a first Peltier element (20) arranged diagonally within the main body (10) and a second Peltier element (30) arranged diagonally within the main body (10) so as to be symmetrical or asymmetrical with respect to the first Peltier element (20).

[0043] At this time, in the pair of Peltier elements (20, 30), the surface that comes into contact with the temperature merging block (40) may be configured as the lower surface, and the distance between the right side (or right side) of the first Peltier element (20) adjacent to the upper part of the temperature merging block (40) based on the lower surface of the first Peltier element (20) and the left side (or left side) of the second Peltier element (30) adjacent to the upper part of the temperature merging block (40) based on the lower surface of the second Peltier element (30) may be configured to be smaller than the distance between the left side (or left side) of the first Peltier element (20) and the right side (right side) of the second Peltier element (30).

[0044] In addition, the first Peltier element part (20) and the second Peltier element part (30) may be configured inside the main body part (10) so that the first Peltier element part (20) and the second Peltier element part (30) are symmetrical or asymmetrical with respect to the central axis of the main body part (10), and the first Peltier element part (20) and the second Peltier element part (30) may be arranged inside the main body part (10) so that a predetermined distance is provided between them.

[0045] Additionally, the first Peltier element unit (20) and the second Peltier element unit (30) may each be configured to include one or more Peltier elements.

[0046] At this time, it is preferable that the first Peltier element (20) and the second Peltier element (30) are each composed of a plurality of Peltier elements so as to secure sufficient heat capacity for a temperature test on the test target element (200).

[0047] As another example, three pairs of Peltier elements may be configured inside the main body (10), and the three pairs of Peltier elements may be configured to be arranged diagonally in a triangular pyramid shape with respect to the temperature merging block (40), and the lower surface of each of the three pairs of Peltier elements may be configured to contact the facing surface of the temperature merging block (40).

[0048] Not limited thereto, a plurality of Peltier elements, such as four pairs or five pairs, may be configured inside the main body (10), and the plurality of Peltier elements may be arranged diagonally in a symmetrical or asymmetrical structure with respect to each other.

[0049] In addition, each of the above pair of Peltier elements (20, 30) (the first Peltier element (20) and the second Peltier element (30)) may be configured in a form in which a plurality of Peltier elements are stacked.

[0050] In addition, when current is applied to each of the plurality of Peltier elements constituting the Peltier element portion, depending on the direction of current application, the upper surface of each of the plurality of Peltier elements constituting the Peltier element portion is heated while the lower surface is cooled, or the upper surface is cooled while the lower surface is heated, and the Peltier element portion can be configured to have a heat generation amount or heat absorption amount for a temperature test of the element to be tested (200) through heating or cooling between the Peltier elements.

[0051] For example, when the first Peltier element (21) located at the lowest position in the first Peltier element section (20) is heated on the lower surface and cooled on the upper surface according to the application of current in the forward direction (or the first direction), the lower surface of the second Peltier element (22) laminated on the upper surface of the first Peltier element (21) and through which current is applied in the same direction as the first Peltier element (21) can heat the upper surface of the first Peltier element (21) to maintain the heating temperature of the first Peltier element (21) and operate to have sufficient heat generation, and when a third Peltier element (23) is bonded (laminated) to the upper surface of the second Peltier element (22), the third Peltier element (23) through which current is applied in the same direction as the second Peltier element (22) can also heat the cooled upper surface of the second Peltier element (22) in the same direction as the second Peltier element (22). By heating the lower surface of the third Peltier element (23), the third Peltier element (23) can be operated so that the temperature of the second Peltier element (22) is maintained while the first Peltier element (21) is heated by the second Peltier element (22), so that the first Peltier element (21) has sufficient heat generation.

[0052] Alternatively, when the first Peltier element (21) located at the bottom of the first Peltier element section (20) is cooled on the lower surface and heated on the upper surface by applying current in the reverse direction (or the second direction), the second Peltier element (22) to which the current is applied in the same direction as the first Peltier element (21) can be operated to cool the upper surface of the first Peltier element (21) with the lower surface of the cooled second Peltier element (22) to maintain the cooling temperature of the first Peltier element (21) and to have sufficient heat absorption, and when the third Peltier element (23) is combined (stacked) on the upper surface of the second Peltier element (22), the third Peltier element (23) to which the current is applied in the same direction as the second Peltier element (22) also heats the heated upper surface of the second Peltier element (22) with the third By cooling the lower surface of the Peltier element (23), the third Peltier element (23) can maintain the temperature of the second Peltier element (22), while the first Peltier element (21) can be cooled by the second Peltier element (22), so that the first Peltier element (21) can have sufficient heat absorption.

[0053] In addition, the fourth Peltier element (31) located at the bottom of the second Peltier element section (30), the fifth Peltier element (32) stacked on the fourth Peltier element (31), and the sixth Peltier element (33) stacked on the fifth Peltier element (32) can also operate in the same manner as the operation of the plurality of Peltier elements (21, 22, 23) configured in the first Peltier element section (20), and when current is applied in the first direction and the first Peltier element (21) is in a state of generating heat (or a heated state), the fourth Peltier element (31) can also be in a state of generating heat (or a heated state) when current is applied in the first direction and the first Peltier element (21) is in a state of absorbing heat (or a cooled state), It may also be in a state where current is applied in the second direction and heat absorption is performed (or a cooled state).

[0054] In the above-described configuration, the semiconductor temperature test device may further include a control unit that applies (supplies) current to each of the plurality of Peltier elements constituting the one or more pairs of Peltier element sections (20, 30).

[0055] At this time, the control unit may include a power supply module that supplies current to each of the plurality of Peltier elements and a control circuit that controls the direction of the current supplied to each of the plurality of Peltier elements according to a target temperature value.

[0056] The above control circuit can change the direction of the current supplied to each of the plurality of Peltier elements by changing the polarity (+, -) of the power supply module.

[0057] At this time, the control unit can apply a current in the same direction to the one or more pairs of Peltier elements (20, 30).

[0058] In addition, the control unit may be configured in the main body (10) or inside the main body (10) or may be configured separately from the main body (10) and outside.

[0059] In addition, in the above-described configuration, the semiconductor temperature test device may further include a plurality of heat exchange parts (61, 62) coupled to the upper surface of the Peltier element parts so as to correspond to the pair or more Peltier element parts (20, 30), respectively.

[0060] For example, the plurality of heat exchange parts (61, 62) are coupled to be in surface contact with the upper surface of the first Peltier element part (20) among the pair of Peltier elements (20, 30) or the upper surface of the Peltier element (for example, the third Peltier element (23)) located at the uppermost part of the first Peltier element part (20) and perform heat exchange with the first Peltier element part (20) or the Peltier element located at the uppermost part of the first Peltier element part (20), and the first heat exchange part (61) is coupled to be in surface contact with the upper surface of the second Peltier element part (30) among the pair of Peltier elements (20, 30) or the upper surface of the Peltier element (for example, the sixth Peltier element (33)) located at the uppermost part of the second Peltier element part (30) and perform heat exchange with the second Peltier element part It may include a second heat exchange unit (62) that performs heat exchange with the Peltier element located at the uppermost part of the element unit (30) or the second Peltier element unit (30).

[0061] At this time, the first heat exchange unit (61) or the second heat exchange unit (62) can cool the heat generated from the upper surface of the Peltier element located at the uppermost position using liquid or heat the cold air generated from the upper surface of the Peltier element located at the uppermost position.

[0062] Additionally, as an example of the above liquid, cooling water or heat exchanger water can be used.

[0063] Through this, each of the plurality of heat exchange parts (61, 62) can maintain the temperature of the Peltier element located at the top of the Peltier element part, thereby maintaining the target temperature of the Peltier element part set to the target temperature through current application, thereby inducing the Peltier element part to have the amount of heat generation or heat absorption required for testing the element to be tested (200).

[0064] At this time, a liquid transport tube for transporting liquid into the first heat exchange unit (61) or the second heat exchange unit (62) may be connected to the first heat exchange unit (61) or the second heat exchange unit (62), and the liquid transport tube may be connected by penetrating the main body unit (10) from the outside of the main body unit (10) to the inside of the main body unit (10).

[0065] Meanwhile, the temperature merging block (40) may be configured between one or more pairs of Peltier elements (20, 30) inside the main body (10), and may be configured to be heated or cooled by the one or more pairs of Peltier elements (20, 30).

[0066] For example, the temperature merging block (40) may be configured between the first Peltier element (20) and the second Peltier element (30), such that one side thereof is configured to be in surface contact with the lower surface of the first Peltier element (20), and the other side thereof is configured to be in surface contact with the lower surface of the second Peltier element (30).

[0067] More specifically, the temperature merging block (40) may be configured (arranged) such that one side (for example, the left side) is in surface contact with the lower surface of a Peltier element (for example, the first Peltier element) located at the lowest (bottom) of the first Peltier element section (20), and the other side (for example, the right side) is configured (arranged) such that the other side is in surface contact with the lower surface of a Peltier element (for example, the fourth Peltier element (31)) located at the lowest surface of the second Peltier element section (30).

[0068] Accordingly, when the lower surface of the Peltier element located at the lowest position among one or more Peltier elements configured in each of one or more pairs of Peltier elements (20, 30) to which current is applied (or to which current is applied in the forward or first direction) is heated, the temperature merging block (40) can be heated by receiving the heat transferred by the one or more pairs of Peltier elements (20, 30) through surface contact with the lower surface of each Peltier element located at the lowest position in each of the one or more pairs of Peltier elements (20, 30).

[0069] Alternatively, when the lower surface of the Peltier element located at the lowest position among one or more Peltier elements configured in each of one or more pairs of Peltier elements (20, 30) to which current is applied (or to which current is applied in the reverse direction or the second direction) is cooled, the temperature merging block (40) can be cooled by receiving cold air transmitted by the one or more pairs of Peltier elements (20, 30) through surface contact with the lower surface of each Peltier element located at the lowest position in each of the one or more pairs of Peltier elements (20, 30).

[0070] That is, the temperature merging block (40) can be heated or cooled by merging the heat or cold provided from the first Peltier element (20) and the heat or cold provided from the second Peltier element (30).

[0071] In addition, the temperature merging block unit (40) can receive and merge heat or cold provided from one or more pairs of Peltier elements (20, 30), and conduct the merged heat or cold to the temperature conducting block unit (50).

[0072] In addition, the temperature conducting block part (50) is configured to be coupled to the lower part of the temperature merging block part (40) inside the main body part (10), and receives heat or cold air provided by the temperature merging block part (40) and is heated or cooled through conduction of the heat or cold air, and can be configured to provide heat or cold air to the test target element (200) mounted in the mounting area of ​​the plate part (100).

[0073] At this time, a part or a lower part of the temperature conducting block part (50) may be configured to be exposed to the outside of the main body part (10), and the exposed part or lower part of the temperature conducting block part (50) may come into contact with the upper surface of the test target element (200) to heat or cool the test target element (200).

[0074] For example, the temperature conducting block (50) can heat or cool the test subject element (200) to reach a target temperature when the lower surface of the lower portion of the temperature conducting block (50) comes into contact with the upper surface of the test subject element (200).

[0075] In addition, the temperature conducting block part (50) may be configured to include a single temperature conducting block (50) that is coupled to the lower part of the temperature merging block part (40) and receives (receives) the heat or cold transmitted (provided) by the temperature merging block part (40) to heat or cool the test target element (200) through heat dissipation (heat generation) or heat absorption when in contact with the test target element (200), and a guide temperature conducting block (50a) that is coupled to the outer peripheral surface or a part of the outer peripheral surface of the single temperature conducting block (50) and is heated or cooled by the single temperature conducting block (50) to control the temperature around the test target element (200).

[0076] In addition, in the above-described configuration, the semiconductor temperature test device may be configured so that the lower surface inside the main body (10) is in surface contact with the upper surface (or upper portion) of the temperature merging block portion (40), and may further include an insulating block portion (70) that blocks the heat of the temperature merging block portion (40) from being released to the outside through the upper portion of the temperature merging block portion (40).

[0077] At this time, the insulating block part (70) may be configured to be combined with or in contact with the upper portion of the temperature merging block part (40) inside the main body part (10).

[0078] In addition, the semiconductor temperature test device may further include an adjustment knob (80) for adjusting the height of the main body (10), and the height of the main body (10) is adjusted according to the driving (operation) of the adjustment knob (80), so that the temperature conduction block (50) (or the lower surface of the temperature conduction block (50)) can come into contact with the test target element (200).

[0079] At this time, the semiconductor temperature test device may further include a driving unit that drives (or raises and lowers) the control knob (80), and the driving unit may be controlled by the control unit (or the control circuit).

[0080] In addition, the control knob (80) may be configured to be included in the driving unit, or the driving unit may be configured in the main body (10) or inside the main body (10).

[0081] As described above, conventional semiconductor test equipment for testing semiconductor devices is configured to have a horizontal structure, and according to this structure, in order to increase the amount of heat generated or absorbed, not only must the number of Peltier elements to be stacked be increased, but also the area of ​​the Peltier elements must be increased, so the volume of the semiconductor test equipment increases significantly. However, since there is a limit to the spacing of DUTs (Device Under Test) on a plane in the semiconductor test equipment, there are many restrictions on increasing the area and volume.

[0082] Therefore, in semiconductor test equipment using existing Peltier elements, there is a problem in that it is difficult to provide sufficient heat generation or heat absorption for testing semiconductor elements.

[0083] In addition, in terms of durability of the Peltier element, the conventional horizontal structure-based semiconductor test equipment has a rapidly reduced durability due to fatigue destruction as the load is repeatedly and fluctuatingly applied to the Peltier element in the process of directly pressing the test target element (200) (for example, when a load of 15 g is applied per ball based on LPDDR5X FBGA 496 Balls, a load of 7.44 kg is applied to the Peltier).

[0084] However, the semiconductor temperature test device according to the embodiment of the present invention, as described above, arranges one or more pairs of Peltier elements each including one or more Peltier elements in a diagonal arrangement (or inclined arrangement) structure, and combines the heat or cold air provided from each of the one or more pairs of Peltier elements and transfers it to the semiconductor element being tested, so that not only can sufficient heat generation or heat absorption be provided to accurately temperature test the operating limit according to the temperature change of the semiconductor element through the heat or cold air provided from the one or more pairs of Peltier elements, but also, by arranging one or more pairs of Peltier elements in parallel diagonally, it is possible to arrange many Peltier elements in a narrow space to obtain a high heat generation or heat absorption, and at the same time, it is possible to transfer heat or cold air by utilizing the entire planar area while reducing the planar area of ​​the Peltier elements, so that the efficiency and transfer capability of heat or cold air can be greatly improved compared to existing equipment in which Peltier elements are stacked in a horizontal structure to reduce the contact area with the semiconductor element being tested.

[0085] In addition, a semiconductor temperature test device configured to have one or more pairs of Peltier elements having a diagonal arrangement structure according to an embodiment of the present invention can increase durability because the Peltier elements are structured so that they do not directly receive a load, but receive a constant force from a variable repetitive load.

[0086] Therefore, the present invention configures the Peltier element in a diagonal structure, thereby significantly improving cooling efficiency, cooling capacity, and durability compared to the existing horizontally structured Peltier element.

[0087] FIG. 3 is an exemplary diagram comparing temperature performance when a pair of Peltier elements (20, 30) of a semiconductor temperature test device according to an embodiment of the present invention are formed in a vertical structure and when a pair of Peltier elements (20, 30) are formed diagonally.

[0088] First, in the structure of the temperature merging block part (40) having a vertical shape by vertically arranging a pair of Peltier elements (20, 30) as illustrated in FIG. 3(a), in order to change the temperature of the temperature conducting block part (50), the temperature transferred to the upper part (A) of the temperature merging block part (40) by the pair of Peltier elements (20, 30) and the temperature transferred to the lower part (B) of the temperature merging block part (40) by the pair of Peltier elements (20, 30) are merged and transferred to the temperature conducting block part (50) (C) through the lower part (B) of the temperature merging block part (40), a bottleneck phenomenon may occur due to the narrow cross-sectional area of ​​the lower part (B) of the temperature merging block part (40), which may deteriorate the temperature performance.

[0089] However, in the structure of the temperature merging block part (40) in which a pair of Peltier elements (20, 30) according to an embodiment of the present invention as illustrated in FIG. 3(b) are arranged diagonally symmetrically so that both sides of the temperature merging block part (40) are inclined, the temperature transferred to the upper part (A) of the temperature merging block part (40) by the pair of Peltier elements (20, 30) and the temperature transferred to the lower part (B) of the temperature merging block part (40) by the pair of Peltier elements (20, 30) are merged and transferred to the temperature conducting block part (50) (C) through the lower part (B) of the temperature merging block part (40), so that the temperature performance can be improved due to the wide cross-sectional area of ​​the lower part (B) of the temperature merging block part (40) that facilitates temperature transfer.

[0090] In addition, in the vertical structure of the Peltier element as shown in Fig. 3(a), the upper area of ​​the temperature merging block (40) is large, so that the amount of heat escaping through the upper part (A) of the temperature merging block (40) is considerable, resulting in low heat conduction efficiency, whereas in the diagonal structure of the Peltier element as shown in Fig. 3(b), the upper area of ​​the temperature merging block (40) is narrow, so that the amount of heat escaping through the upper part (A) of the temperature merging block (40) is small, but heat conduction can be concentrated to the lower part (B) of the temperature merging block (40), resulting in high heat conduction efficiency.

[0091] Meanwhile, the semiconductor temperature test device according to the embodiment of the present invention may be configured to perform temperature tests simultaneously on a plurality of test target elements (200), which will be described in detail with reference to FIG. 4.

[0092] As illustrated, the mounting board plate (102) constituting the plate portion (100) may have a plurality of mounting areas, and the plate portion (100) may be configured to include a plurality of device guide plates (101) so as to correspond to each of the plurality of mounting areas.

[0093] In addition, among the configurations of the semiconductor temperature test device, the temperature conduction block part (50) is lowered to the plate part (100) when the main body part (10) is lowered to the plate part (100) by driving (or adjusting the height) of the control knob (80), and the temperature conduction block part (50) is also lowered to the plate part (100).

[0094] In addition, the temperature conducting block part (50) is configured to be coupled to the lower part of the temperature merging block part (40) so that temperature tests on a plurality of test target devices (200) mounted on each of the plurality of mounting areas can be simultaneously performed as the temperature conducting block part (50) descends to the plate part, and is heated or cooled by the temperature merging block part (40), and a conductive block (51) that extends downwardly (or downwardly of the conductive block (51) from one side of the conductive block (51) so as to be bent so as to be heated or cooled by the temperature merging block part (40) and a first extension block (52) configured to receive heat or cold air transmitted by the conductive block (51) through a surface that contacts the test target device (201) (or the first test target device) mounted on a first mounting area among the plurality of mounting areas, and extends downwardly (or downwardly of the conductive block (51)) from the other side of the conductive block (51) so as to be bent so as to be heated so as to be heated by the conductive block (51). It may be configured to include a second extension block (53) configured to heat or cool another test subject element (202) (second test subject element) mounted in a second mounting area among the plurality of mounting areas by receiving heat or cold air through a surface that comes into contact with the other test subject element (202) (second test subject element).

[0095] Through the above-described configuration, the semiconductor temperature test device according to the embodiment of the present invention can perform temperature tests on multiple test target elements simultaneously, thereby increasing the efficiency of semiconductor temperature tests.

[0096] Those skilled in the art will appreciate that modifications and variations of the above-described content may be made without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed herein are intended to illustrate, rather than limit, the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included within the scope of the present invention.

[0097] Description of the symbol

[0098] 10: Main body 20: First Peltier element

[0099] 30: Second Peltier element section 40: Temperature merging block section

[0100] 50: Temperature conduction block section 61: First heat exchange section

[0101] 62: Second heat exchanger section 70: Insulating block section

[0102] 80: Adjustment knob 100: Plate section

[0103] 101: Device Guide Plate

[0104] 102: Mounting board plate 200: Test target element

Claims

1. One or more pairs of Peltier elements configured in a symmetrical or asymmetrical structure diagonally and heated or cooled according to the application of current; A temperature merging block configured between the one or more pairs of Peltier elements and heated or cooled by the one or more pairs of Peltier elements; and A temperature conduction block section that heats or cools a semiconductor element to be tested by being heated or cooled by the above temperature merging block section. A semiconductor temperature test device using a Peltier element including a .

2. In claim 1, A semiconductor temperature test device using a Peltier element, characterized in that each of the above one or more pairs of Peltier elements is composed of one or more Peltier elements or is composed by stacking a plurality of Peltier elements.

3. In claim 1, A semiconductor temperature test device using a Peltier element, characterized in that it further includes a control unit that applies forward or reverse current to each of one or more Peltier elements configured in each of the above one or more pairs of Peltier elements.

4. In claim 1, Further comprising a main body including one or more pairs of Peltier elements, The above one or more pairs of Peltier elements, A first Peltier element portion arranged diagonally inside the main body portion; and A second Peltier element portion arranged diagonally inside the main body portion so as to be symmetrical or asymmetrical with respect to the first Peltier element portion. A semiconductor temperature test device using a Peltier element characterized by including:

5. In claim 4, The above temperature merging block part is, A semiconductor temperature test device using a Peltier element, characterized in that it is provided between the first Peltier element part and the second Peltier element part, and one side is configured to be in surface contact with the lower surface of the first Peltier element part, and the other side is configured to be in surface contact with the lower surface of the second Peltier element part, and conducts heat of the first Peltier element part and the second Peltier element part by combining it or conducts cold air of the first Peltier element part and the second Peltier element part by combining it.

6. In claim 4, A semiconductor temperature test device using a Peltier element, characterized in that it further includes an adjustment knob for adjusting the height of the main body.

7. In claim 4, A first heat exchanger configured on the upper surface of the first Peltier element to perform heat exchange; and A second heat exchanger configured on the upper surface of the second Peltier element to perform heat exchange A semiconductor temperature test device using a Peltier element, characterized in that it further includes:

8. In claim 1, An insulating block portion configured to contact the upper portion of the above temperature merging block portion and blocking the heat of the above temperature merging block portion from being released to the outside. A semiconductor temperature test device using a Peltier element, characterized in that it further includes:

9. In claim 1, The above temperature conducting block part is, A single temperature conducting block that is heated or cooled by the temperature merging block section and transmits heat or cold to the semiconductor element under test; and A semiconductor temperature test device using a Peltier element, characterized in that it includes a guide temperature conduction block configured to be coupled to the outer surface or a part of the outer surface of the single temperature conduction block and to control the temperature around the test target element by being heated or cooled by the single temperature conduction block.

10. In claim 1, The above temperature conducting block part is, A conductive block that is lowered into a plate section having a plurality of mounting areas for mounting a plurality of semiconductor devices to be tested, and is configured to be coupled to the lower portion of the temperature merging block section so that temperature tests are simultaneously performed on a plurality of test target devices mounted on each of the plurality of mounting areas, and is heated or cooled by the temperature merging block section; A first extension block configured to extend downwardly from one side of the conductive block and receive heat or cold transmitted by the conductive block to heat or cool the test target device mounted in a first mounting area among the plurality of mounting areas through a surface that comes into contact with the test target device; and A semiconductor temperature test device using a Peltier element, characterized in that it comprises a second extension block configured to extend from the other side of the conductive block and bend downward to receive heat or cold transmitted by the conductive block and heat or cool another test target element mounted in a second mounting area among the plurality of mounting areas through a surface that comes into contact with the other test target element.

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