CVD process method and system for improving epitaxial auto-doping of polished wafer substrate

Abstract

The present invention provides a CVD process method and system for improving epitaxial auto-doping of a polished substrate wafer. The method comprises: step 1, separately placing test silicon wafers in different production line CVD workshops, collecting sample wafers, testing the pH content of surfaces of the sample wafers, and selecting, on the basis of the test results, a workshop with a low environmental pH content for processing; step 2, in the workshop with the low environmental pH content, conventionally depositing a POLY film on the back surface of the silicon wafer; step 3, in the workshop with the low environmental pH content, depositing an LTO film on the basis of the POLY film on the back surface of the silicon wafer; and step 4, in the workshop with the low environmental pH content, performing an end face treatment on the backside LTO film by means of a beveling machine, such that the edge removal distance of the LTO film is within a preset range. The present invention enables improvements in the use stability, reliability, and lifespan of a chip, and solves the abnormal problems of edge failure such as not being voltage resistant and a large current leakage caused by the large auto-doping effect of a silicon wafer in automotive-grade chips.

Description

CVD process method and system for improving epitaxial self-doping of substrate polishing wafer TECHNICAL FIELD

[0001] The present application relates to the technical field of CVD process, in particular to a CVD process method and system for improving epitaxial self-doping of substrate polishing wafer. BACKGROUND

[0002] In recent years, with the rapid development of automobile electrification and intelligence, the demand for automotive-grade application chips in China's new energy vehicle industry chain has surged. Automotive-grade chips have higher performance than industrial-grade and consumer-grade chips, so compared with ordinary consumer-grade chips, automotive-grade chips have higher requirements for silicon wafer substrates. Therefore, the silicon wafer substrate products processed by the conventional back sealing process cannot meet the low self-doping level required by automotive-grade chips on the market. Resistivity uniformity (RRG) refers to whether the distribution of resistivity within the material is uniform. In the process of manufacturing electronic devices, ensuring the resistivity uniformity of the material can improve the stability and reliability of the device. If there is a large resistivity difference within the material, it will cause the device to work unstably or fail. Therefore, during the production process of automotive-grade chips, the self-doping phenomenon after epitaxy of the substrate needs to be strictly controlled to ensure that the in-plane resistivity uniformity (RRG) is as small as possible.

[0003] The most common CVD process for processing the back surface of a silicon wafer on the market is: LPCVD+APCVD+end face processing process, wherein the LPCVD process corresponds to a POLY film, the APCVD process corresponds to an LTO film, and the end face processing process corresponds to an LTO film edge distance (EOS). Since the POLY layer is a porous and disordered structure composed of many small silicon crystals, it is easy to adsorb impurity pollutants. If there is impurity pollution (especially Ph element) under the POLY layer during the deposition of the POLY film, the impurities under the POLY layer will slowly diffuse from the inside of the POLY to the edge of the front surface of the silicon wafer during the epitaxial process, resulting in poor uniformity of the resistivity of the edge of the front surface of the silicon wafer. The closer to the edge of the silicon wafer, the more obvious the self-doping phenomenon. It is generally believed that the important factors affecting epitaxial self-doping are the LTO edge distance (EOS) and the Ph content level under the POLY layer of the silicon wafer substrate. There are two main end face processing methods for LTO edge on the market, one is to use the property that Si is difficult to react with HF acid, and SiO2 can be dissolved in HF acid. After the silicon wafer is coated with a protective film (coated with a tape), the LTO film on the chamfer surface is etched away by HF acid to remove the SiO2 film on the end face of the silicon wafer after APCVD film formation. The second method is a tape grinding method. The tape with silicon carbide particles is used to remove the LTO film on the end face of the silicon wafer by setting appropriate parameters on the tape grinding machine, vibrating the tape and rotating the silicon wafer. The edge distance (EOS) of the two LTO film end face processing methods is relatively large. At the same time, the Ph pollution level of the conventional 150mm production line CVD workshop environment is higher than that of the 200mm production line CVD workshop environment. Therefore, during the epitaxial high temperature process, the Ph element under the POLY layer is easy to diffuse from the large edge distance to the polishing surface, resulting in self-doping abnormalities at the edge of the polishing surface.

[0004] Taking the LPCVD+APCVD+end face processing process substrate as an example, if there is a small amount of Ph pollution under the POLY layer, as shown in FIG. 1, during the epitaxial high temperature process, Ph will run from the position under the POLY layer to the edge of the POLY layer, and then diffuse from the LTO film end face processing (EOS) to the edge of the front surface of the silicon wafer, causing the resistivity uniformity RRG of the edge of the silicon wafer to deteriorate, and causing epitaxial self-doping.

[0005] SUMMARY

[0006] In view of the defects in the prior art, the purpose of the present application is to provide a CVD process method and system for improving the epitaxial self-doping of a substrate polishing wafer.

[0007] The CVD process method for improving the epitaxial self-doping of a substrate polishing wafer provided by the present application comprises:

[0008] Step 1: Put the test wafers into different production line CVD workshops respectively, collect the sample wafers and test the surface Ph content of the sample wafers, and select the workshop with low environmental Ph content according to the test results for processing;

[0009] Step 2: In the workshop with low environmental Ph content, a POLY film is deposited on the back surface of the wafer;

[0010] Step 3: In the workshop with low environmental Ph content, an LTO film is deposited on the basis of the POLY film on the back surface of the wafer;

[0011] Step 4: In the workshop with low environmental Ph content, the edge of the LTO film on the back surface is processed by an edge removing machine, so that the edge removing distance of the LTO film is within a preset range.

[0012] Preferably, the POLY film is formed by gas deposition using an LPCVD machine, the film thickness of 5 points on the surface of the wafer is tested by an F50 film thickness tester to calculate the average value, the preliminary range is determined based on the product customer's regulation, and the specific value is determined based on the test results; the POLY film thickness is 7000A-8000A or 8000A-9000A; and the POLY film plays a role of external gettering of the wafer.

[0013] Preferably, the LTO film is formed by gas deposition using an APCVD machine, the film thickness of 5 points on the surface of the wafer is tested by an F50 film thickness tester to calculate the average value, the preliminary range is determined based on the product customer's regulation, and the specific value is determined based on the test results; the LTO film thickness is 5000A-6000A or 6000A-7000A; and the LTO film plays a role of back sealing of the wafer.

[0014] Preferably, after the edge processing, the edge removing distance of the wafer is measured by a microscope at 5 points respectively, and the average value is taken; the preliminary range is determined based on the product customer's regulation, and the specific value is determined based on the test results; the LTO film edge removing distance range is 0-0.3mm, 0-0.5mm, 0-1mm or 0-2mm.

[0015] Preferably, the edge processing process is: the LTO film on the back surface of the wafer is vacuumed by the chuck of the edge removing machine, and the LTO film on the chamfer surface is etched by HF acid, so as to remove the SiO2 film on the chamfer surface of the wafer after APCVD film formation.

[0016] The CVD process system for improving the external epitaxial self-doping of the polished wafer substrate provided by the present application comprises:

[0017] Module M1: Put the test wafers into different production line CVD workshops respectively, collect the sample wafers and test the surface Ph content of the sample wafers, and select the workshop with low environmental Ph content according to the test results for processing;

[0018] Module M2: in a workshop with low environmental Ph content, a POLY film is deposited on the back of the silicon wafer;

[0019] Module M3: in a workshop with low environmental Ph content, an LTO film is deposited on the POLY film on the back of the silicon wafer;

[0020] Module M4: in a workshop with low environmental Ph content, the LTO film on the back is edge-processed by an edge-removing machine, so that the edge-removing distance of the LTO film is within a preset range.

[0021] Preferably, the POLY film is formed by gas phase deposition of an LPCVD machine, and the film thickness of 5 points on the surface of the silicon wafer is tested by an F50 film thickness tester to calculate the average value; a preliminary range is determined based on the product customer's regulation, and a specific value is determined based on the test result; the POLY film thickness is 7000A-8000A or 8000A-9000A; and the POLY film plays a role of external gettering of the silicon wafer.

[0022] Preferably, the LTO film is formed by gas phase deposition of an APCVD machine, and the film thickness of 5 points on the surface of the silicon wafer is tested by an F50 film thickness tester to calculate the average value; a preliminary range is determined based on the product customer's regulation, and a specific value is determined based on the test result; the LTO film thickness is 5000A-6000A or 6000A-7000A; and the LTO film plays a role of back sealing of the silicon wafer.

[0023] Preferably, after the edge processing, the edge-removing distance of the silicon wafer at 5 points is measured by a microscope respectively, and the average value is taken; a preliminary range is determined based on the product customer's regulation, and a specific value is determined based on the test result; the LTO film edge-removing distance range is 0-0.3mm, 0-0.5mm, 0-1mm or 0-2mm.

[0024] Preferably, the edge processing process is: the LTO film on the back of the protective silicon wafer is vacuumed by the chuck of the edge-removing machine, and the LTO film on the chamfer surface is etched by HF acid, so as to remove the SiO2 film on the chamfer surface of the silicon wafer after the APCVD film formation.

[0025] Compared with the prior art, the present application has the following beneficial effects:

[0026] The present application can greatly improve the substrate epitaxial self-doping effect by inventing a new CVD back sealing process. Compared with the conventional product resistivity uniformity (RRG: 3%-5%), the substrate wafer using the back sealing process has a lower resistivity uniformity (RRG: <1%) after epitaxy, improves the chip stability, reliability and service life, solves the edge failure abnormal problems such as chip pressure resistance and large leakage caused by large silicon wafer self-doping effect (poor resistivity uniformity) of the automotive chip, and has great innovation and practicality. BRIEF DESCRIPTION OF DRAWINGS

[0027] Other features, objects, and advantages of the application will become apparent from the following detailed description of non-limiting embodiments, when read in connection with the following accompanying drawings:

[0028] Figure 1 is a schematic diagram of Ph element diffusion under an epitaxial process POLY layer;

[0029] Figure 2 is a schematic diagram of Ph content in a 200mm production line environment;

[0030] Figure 3 is a schematic diagram of Ph content in a 150mm production line environment;

[0031] Figure 4 is a flow chart of a CVD process method for improving epitaxial self-doping of a substrate polishing wafer. DETAILED DESCRIPTION

[0032] The application will be described in greater detail by way of specific embodiments. The following examples will facilitate further understanding of the application for those skilled in the art, but do not limit the application in any form. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the application. These are within the scope of the application.

[0033] Example 1

[0034] As shown in Figure 4, the application provides a CVD process method for improving epitaxial self-doping of a substrate polishing wafer, comprising the following steps:

[0035] Step 1: Place the test dummy wafer in a 150mm production line CVD workshop and a 200mm production line CVD workshop, respectively, collect the sample and outsource SIMS testing of the surface Ph content of the sample; according to the test results, preferentially select the workshop with low environmental Ph content for processing, to reduce the impact of environmental Ph pollution on the substrate;

[0036] Step 2: In the workshop with low environmental Ph content, first deposit a layer of POLY film (LPCVD) on the back of the silicon wafer, with a film thickness of about 7000A-8000A, 8000-9000A; determine the approximate range based on product customer specifications, and determine the specific value based on test results; use the LPECVD machine to deposit the POLY film by vapor deposition, use the F50 film thickness meter to test the surface of the silicon wafer at 5 points to confirm the film thickness, and calculate the average value; the POLY film serves as a gettering effect for the silicon wafer;

[0037] Third step: in the workshop with low Ph content in the environment, on the basis of the POLY film (LPCVD) on the back of the silicon wafer, a layer of LTO film (APCVD) is deposited, the film thickness is about 5000A-6000A, 6000-7000A; based on the product customer regulation to determine the approximate range, based on the test results to determine the specific value; LTO film is formed by using APCVD machine vapor deposition, the film thickness is tested by using F50 film thickness instrument, and the average value is calculated; the LTO film plays the role of back sealing of the silicon wafer.

[0038] Fourth step: in the workshop with low Ph content in the environment, the end face of the back LTO film is treated by using a new edge removing machine, so that the edge removing distance (EOS) of the LTO film is in the range of 0-0.3mm, 0-0.5mm, 0-1mm, 0-2mm. Based on the product customer regulation to determine the approximate range, based on the test results to determine the specific value; after the end face treatment, the edge removing distance of the silicon wafer edge is measured by using a microscope respectively, and the average value is taken.

[0039] End face treatment process: Si and HF acid are difficult to have chemical response, and SiO2 can be dissolved in HF acid, the new edge removing machine suction cup is used to suck the back LTO film of the silicon wafer, the LTO film on the chamfer surface is etched away by using HF acid, and the purpose of removing the SiO2 film on the chamfer surface after APCVD film formation is achieved; acid etching process and cleaning process are adopted.

[0040] Example 2

[0041] Taking 6-inch LP+AP products as an example, by using the control variable method, CVD back sealing process adjustment test is carried out respectively, the best process window is found, the resistivity uniformity of the substrate wafer after epitaxy is less than 1%, and the application requirements of the vehicle regulation level chip are met. It is generally considered that the factors affecting the epitaxial self-doping of the substrate are CVD workshop environmental pollution, CVD film thickness and CVD edge removing distance, and the best process window of low epitaxial self-doping level is found by controlling a single variable respectively and verifying one by one.

[0042] The test wafers are processed in the 150mm production line CVD workshop and the 200mm production line CVD workshop respectively, and the test wafer LPCVD / APCVD / EOS condition parameters are limited to be the same, so as to confirm the influence of the environment on the epitaxial self-doping effect of the product.

[0043] 1), the conventional flow to the polished wafer, and the Ph content under the PLOY layer of the silicon wafer is tested by SIMS. According to the SIMS test results, the environment of the 200mm production line CVD workshop is obviously better than that of the 150mm production line CVD workshop, as shown in Figs. 2 and 3.

[0044] 2), the conventional flow to the epitaxial wafer, and the in-plane resistivity uniformity of the silicon wafer is tested.

[0045] As shown in Table 1 below, the experimental group 2 is obviously superior to the experimental group 1 in the uniformity of the back surface resistivity (RRG) of the CVD product wafer after 200mm workshop processing.

[0046] Table 1

[0047] Experimental conclusion: under the same conditions of LPCVD / APCVD / EOS parameters, it is suggested that the CVD process of the new vehicle standard product be arranged in the 200mm production line CVD workshop for film forming processing, which can effectively reduce the content of Ph element under the POLY layer of the silicon wafer substrate, and the uniformity of the back surface resistivity after epitaxy is good, and the phenomenon of epitaxial self-doping of Ph element is effectively inhibited.

[0048] Taking the 6-inch LP+AP product as an example, different LPCVD and APCVD film thicknesses are deposited, and the test pieces are simultaneously limited to be processed in the 200mm production line CVD workshop, and the EOS condition parameters of the test pieces are the same, so as to confirm the influence of CVD film thickness on the epitaxial self-doping effect of the product.

[0049] 1), the test pieces are conventionally flowed to epitaxial wafers, and the uniformity of the silicon wafer surface resistivity is tested.

[0050] As shown in Table 2 below, the uniformity of the back surface resistivity (RRG) of the test pieces of the result 4 group is basically the same.

[0051] Table 2

[0052] Experimental conclusion: under the same conditions of 200mm CVD workshop film forming and EOS condition parameters, the LPCVD+APCVD back sealing process with different film thicknesses has no obvious improvement on the inhibition of the Ph element self-doping effect of the silicon wafer after epitaxy.

[0053] Taking the 6-inch LP+AP product as an example, the end face of the back LTO film is treated by using a new edge removing machine, so that the LTO film edge removing distance (EOS) is in the range of 0-0.3mm, 0-0.5mm, 0-1mm, 0-2mm, and the test pieces are simultaneously limited to be processed in the 200mm production line CVD workshop, and the LPCVD / APCVD film thickness condition parameters of the test pieces are the same, so as to confirm the influence of the EOS edge removing distance on the epitaxial self-doping effect of the product.

[0054] 1), the test pieces are conventionally flowed to epitaxial wafers, and the uniformity of the silicon wafer surface resistivity is tested.

[0055] As shown in Table 3 below, the uniformity of the resistivity (RRG) after epitaxy: experimental group 1 < experimental group 2 < experimental group 3 < experimental group 4.

[0056] Table 3

[0057] Experimental conclusion: In the case of 200mm CVD workshop film forming and the same LPCVD / APCVD film thickness condition parameters, the resistivity uniformity of epitaxial products is different by using different LTO film edge removal distance (EOS). According to the experimental results, the smaller the edge removal distance EOS, the better the resistivity uniformity after epitaxy, and the better the effect of inhibiting Ph element epitaxial self-doping.

[0058] Those skilled in the art know that, in addition to implementing the system, device and each module thereof provided by the present application in the form of pure computer readable program code, the same program can also be realized in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers and embedded microcontrollers by logically programming the method steps. Therefore, the system, device and each module thereof provided by the present application can be considered as a hardware component, and the modules included therein for implementing various programs can also be considered as structures within the hardware component; the modules for implementing various functions can also be considered as both software programs for implementing methods and structures within the hardware component.

[0059] The specific embodiments of the present application are described above. It needs to be understood that the present application is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essential content of the present application. In the case of no conflict, the embodiments of the present application and the features in the embodiments can be combined with each other at will.

Claims

1. A method for improving epitaxial self-doping of a CVD process for polishing a wafer of a substrate, characterized by, Comprising: Step 1: Put the test wafers into different production line CVD workshops respectively, collect the sample wafers and test the surface Ph content of the sample wafers, and select the workshop with low environmental Ph content for processing according to the test results; Step 2: In the workshop with low environmental Ph content, a layer of POLY film is deposited on the back surface of the wafer; Step 3: In the workshop with low environmental Ph content, a layer of LTO film is deposited on the basis of the POLY film on the back surface of the wafer; Step 4: In the workshop with low environmental Ph content, the edge of the LTO film on the back surface is treated by using an edge removing machine, so that the edge removing distance of the LTO film is within a preset range.

2. The method of claim 1, wherein the CVD process is a process for epitaxial self-doping of a polished wafer of a substrate. POLY film is formed by using LPCVD machine vapor deposition, F50 film thickness tester is used to test the film thickness of 5 points on the surface of the wafer to calculate the average value; based on the preliminary range determined by the product customer regulation, the specific value is determined based on the test results; the thickness of the POLY film is 7000A-8000A, 8000A-9000A; the POLY film plays the role of external gettering of the wafer.

3. The method of claim 1, wherein the CVD process is a process for epitaxial self-doping of a polished wafer of a substrate. LTO film is formed by using APCVD machine vapor deposition, F50 film thickness tester is used to test the film thickness of 5 points on the surface of the wafer to calculate the average value; based on the preliminary range determined by the product customer regulation, the specific value is determined based on the test results; the thickness of the LTO film is 5000A-6000A, 6000A-7000A; the LTO film plays the role of back sealing of the wafer.

4. The method of claim 1, wherein the CVD process is a process for epitaxial self-doping of a wafer for improving polishing of a substrate. After edge treatment, the edge removing distance of the wafer is measured by using a microscope respectively, and the average value is taken; based on the preliminary range determined by the product customer regulation, the specific value is determined based on the test results; the LTO film edge removing distance range is 0-0.3mm, 0-0.5mm, 0-1mm, 0-2mm.

5. The method of claim 1, wherein the CVD process is epitaxial self-doping. The edge treatment process is: the LTO film on the back surface of the wafer is sucked by the vacuum suction disc of the edge removing machine, and the LTO film on the chamfer surface is etched away by HF acid, so as to remove the SiO2 film on the chamfer surface of the wafer after APCVD film formation.

6. A CVD process system for improving epitaxial self-doping of a polished wafer of a substrate, comprising: Comprising: Module M1: Put the test wafers into different production line CVD workshops respectively, collect the sample wafers and test the surface Ph content of the sample wafers, and select the workshop with low environmental Ph content for processing according to the test results; Module M2: In the workshop with low environmental Ph content, a layer of POLY film is deposited on the back surface of the wafer; Module M3: In the workshop with low environmental Ph content, a layer of LTO film is deposited on the basis of the POLY film on the back surface of the wafer; Module M4: In the workshop with low environmental Ph content, the edge of the LTO film on the back surface is treated by using an edge removing machine, so that the edge removing distance of the LTO film is within a preset range. POLY film is formed by using LPCVD machine vapor deposition, F50 film thickness tester is used to test the film thickness of 5 points on the surface of the wafer to calculate the average value; based on the preliminary range determined by the product customer regulation, the specific value is determined based on the test results; the thickness of the POLY film is 7000A-8000A, 8000A-9000A; the POLY film plays the role of external gettering of the wafer.

7. The CVD process system for improving epitaxial self-doping of a substrate polishing wafer of claim 6, wherein, ​ 8. The CVD process system for improving epitaxial self-doping of a substrate polishing wafer of claim 6, wherein, LTO film is formed by using APCVD machine table vapor deposition, F50 film thickness tester is used to test silicon wafer surface 5 point position to confirm film thickness, average value is calculated; based on product customer rules to determine the preliminary range, based on the test results to determine the specific value; LTO film thickness is 5000A-6000A, 6000A-7000A; the LTO film plays a silicon wafer back sealing role.

9. The CVD process system for improving epitaxial self-doping of a substrate polishing wafer of claim 6, wherein, After end face treatment, microscope is used to measure silicon wafer edge 5 point position edge removal distance, average value is taken; based on product customer rules to determine the preliminary range, based on the test results to determine the specific value; LTO film edge removal distance range is 0-0.3mm, 0-0.5mm, 0-1mm, 0-2mm.

10. The CVD process system for improving epitaxial self-doping of a substrate polishing wafer of claim 6, wherein, End face treatment process is: using edge removal machine suction disc vacuum suction to protect silicon wafer back LTO film, using HF acid to corrode LTO film on the chamfer surface, thereby removing SiO2 film on the silicon wafer chamfer surface after APCVD film formation.

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