Semiconductor device and manufacturing method therefor

Abstract

The present invention relates to a semiconductor device and a manufacturing method therefor. The method comprises: forming a gate structure on a substrate of a wafer; forming a photoresist on the wafer, and performing first body region photoetching, to form a first implantation window; performing first ion implantation on the wafer, and forming a first implantation region below the first implantation window; removing the photoresist, and then forming a nitriding layer on the wafer; forming a photoresist covering the nitriding layer on the wafer, and performing second body region photoetching to form a second implantation window; performing second ion implantation on the wafer, the implantation energy being greater than the implantation energy when the first implantation region is formed, and forming a second implantation region below the second implantation window. The device formed by the present invention can obtain Vt having good uniformity.

Description

Semiconductor device and manufacturing method thereof TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] Inter-wafer uniformity refers to the consistency of the difference of the index between different wafers in the same batch. The Vt (threshold voltage) uniformity of an exemplary NLDMOS (N-channel lateral double-diffused metal-oxide-semiconductor field-effect transistor) is poor, i.e., the difference of the device Vt in different wafers is large, thereby affecting the reliability of the device. SUMMARY

[0003] Therefore, it is necessary to provide a semiconductor device with better Vt uniformity and a manufacturing method thereof.

[0004] A manufacturing method of a semiconductor device includes: forming a gate structure on a substrate of a wafer; forming a first photoresist layer on the wafer, and performing first body region lithography to form a first implantation window; performing first ion implantation on the wafer to form a first implantation region below the first implantation window; removing the first photoresist layer, and then forming a nitride layer on the wafer; forming a second photoresist layer on the wafer to cover the nitride layer, and performing second body region lithography to form a second implantation window; and performing second ion implantation on the wafer to form a second implantation region below the second implantation window, the implantation energy being greater than that in the first ion implantation.

[0005] The manufacturing method of the semiconductor device includes two implantations to form the body region. The first implantation uses a lower implantation energy, so that a thinner photoresist layer can be used as an implantation barrier layer to obtain a Vt with better uniformity. The photoresist layer for the second implantation is formed on the nitride layer, and the anti-reflection characteristic of the nitride layer is used to obtain a second implantation window with better edge morphology, which is also conducive to obtaining a Vt with better uniformity.

[0006] In one embodiment, the ions implanted in the first implantation region and the second implantation region have the same conductivity type.

[0007] In one embodiment, before the nitride layer is formed, the method further includes forming a first oxide layer on the wafer, and the nitride layer is formed on the first oxide layer.

[0008] In one embodiment, after forming the second implant region, the method further comprises removing a second photoresist layer covering the nitride layer, then forming a second oxide layer covering the nitride layer, and etching the first oxide layer, the nitride layer and the second oxide layer to form a sidewall on the side of the gate structure.

[0009] In one embodiment, after forming the first implant region and before forming the second photoresist layer covering the nitride layer, the method further comprises activating the impurity ions implanted by the first implant region by a thermal treatment to form channel surface ions.

[0010] In one embodiment, the thermal treatment is rapid thermal annealing, rapid thermal oxidation or other high temperature activation method.

[0011] In one embodiment, the ion implantation energy for forming the first implant region is 15keV to 50keV.

[0012] In one embodiment, the first photoresist layer formed on the wafer has a thickness of to

[0013] In one embodiment, before forming the first photoresist layer on the wafer, the method further comprises forming a drift region having a first conductivity type, the first implant region and the second implant region having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; after forming the second implant region, the method further comprises forming a drain region and a source region, the source region being formed in a body region formed by the first implant region and the second implant region, the drain region and the source region having the first conductivity type, and the drain region and the source region having a higher doping concentration than the drift region.

[0014] In one embodiment, the first body region photoetching and the second body region photoetching use the same mask.

[0015] In one embodiment, the nitride layer is a silicon nitride layer or a silicon oxynitride layer.

[0016] In one embodiment, the semiconductor device is a lateral double diffused metal oxide semiconductor field effect transistor or a vertical double diffused metal oxide semiconductor field effect transistor.

[0017] In one embodiment, the first conductivity type is N type, the second conductivity type is P type, and the semiconductor device is an N-channel lateral double diffused metal oxide semiconductor field effect transistor; or the first conductivity type is P type, the second conductivity type is N type, and the semiconductor device is a P-channel lateral double diffused metal oxide semiconductor field effect transistor.

[0018] A semiconductor device manufactured by the manufacturing method of any one of the preceding embodiments.

[0019] The semiconductor device has a Vt with good uniformity. BRIEF DESCRIPTION OF DRAWINGS

[0020] For a better understanding of the embodiments and / or examples of the inventions disclosed herein, reference can be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and / or examples, and the best mode presently contemplated of these inventions.

[0021] Fig. 1 is a flow chart of a manufacturing method of a semiconductor device in an embodiment of the present application;

[0022] Fig. 2 is a schematic diagram of a cross-sectional structure of a device after a photoresist 292 is coated on a polysilicon layer 244 in an embodiment of the present application;

[0023] Fig. 3 is a schematic diagram of a cross-sectional structure of a device after step S110 is completed in an embodiment of the present application;

[0024] Fig. 4 is a schematic diagram of a cross-sectional structure of a device corresponding to step S130 in an embodiment of the present application;

[0025] Fig. 5 is a schematic diagram of a cross-sectional structure of a device after step S140 is completed in an embodiment of the present application;

[0026] Fig. 6 is a schematic diagram of a cross-sectional structure of a device after step S150 is completed in an embodiment of the present application;

[0027] Fig. 7 is a schematic diagram of a cross-sectional structure of a device after step S160 is completed in an embodiment of the present application;

[0028] Fig. 8 is a schematic diagram of a cross-sectional structure of a device after a second oxide layer 256 is formed in an embodiment of the present application;

[0029] Fig. 9 is a schematic diagram of a cross-sectional structure of a device after a side wall 250 is formed in an embodiment of the present application;

[0030] Fig. 10 is a schematic diagram of a structure of a semiconductor device in an embodiment of the present application. DETAILED DESCRIPTION

[0031] For the purpose of promoting an understanding of the principles of the application, reference will now be made to the embodiments illustrated in the drawings. There is shown in the drawings, preferred embodiments of the application. It should be noted, however, that the application can be practiced in many different forms and should not be considered limited to the embodiments set forth in the following description. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art, and that the application will be fully defined and

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this description, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0034] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0035] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the application.

[0037] The semiconductor field terms used herein are the technical terms commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, simply P+ type represents P-type with heavy doping concentration, P type represents P-type with medium doping concentration, P- type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N type represents N-type with medium doping concentration, N- type represents N-type with light doping concentration.

[0038] The source of the exemplary NLDMOS includes at least one high-energy implantation when performing Pbody (P-type body region) implantation, which can cause the edge profile of the photoresist to be poor, so that the high-energy implantation ions are easy to accumulate on the surface of the conductive channel, and the Vt uniformity of the device is poor.

[0039] The present application proposes a semiconductor device manufacturing method, which adopts an improved body region forming method, and can improve the Vt uniformity of the device, and further improve the reliability of the device.

[0040] FIG. 1 is a flowchart of a semiconductor device manufacturing method in an embodiment of the present application, including the following steps:

[0041] S110, forming a gate structure on a substrate of a wafer.

[0042] The substrate can be a semiconductor substrate, which can be made of undoped monocrystalline silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), etc., and can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors.

[0043] The gate structure includes a gate dielectric layer and a gate layer on the gate dielectric layer. In one embodiment of the present application, the gate dielectric layer can include conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon having a dielectric constant of from about 4 to about 20 (measured in vacuum), or the gate dielectric layer can include a generally higher dielectric constant dielectric material having a dielectric constant of from about 20 to at least about 100. Such higher dielectric constant dielectric materials can include, but are not limited to, hafnium oxide, hafnium silicates, titanium oxide, barium strontium titanate (BSTs) and lead zirconium titanate (PZTs). In one embodiment of the present application, the gate layer is made of polysilicon material, and in other embodiments, a metal, metal nitride, metal silicide or similar compound can also be used as the material of the gate layer.

[0044] In one embodiment of the present application, a gate oxide layer can be formed on the substrate by dry oxygen oxidation, wet oxygen oxidation, high temperature oxidation (HTO) or the like, and then the gate material is deposited on the gate oxide layer, and finally the gate structure is formed by patterning (e.g. photolithography and etching).

[0045] Referring to FIG. 2, in the embodiment shown in FIG. 2, an epitaxial layer 220 of the second conductivity type is first formed on a substrate 210 of the second conductivity type, and then impurity ions of the first conductivity type are implanted by an ion implantation process at a position near the top of the epitaxial layer 220 to form a drift region 232 of the first conductivity type. Then a gate oxide layer 242 is formed on the front side of the wafer by dry oxygen oxidation, wet oxygen oxidation, high temperature oxidation (HTO) or the like. Next, a polysilicon layer 244 is deposited on the gate oxide layer 242, and a layer of photoresist 292 is coated on the polysilicon layer 244.

[0046] Next, the photoresist 292 is exposed using a gate mask, and then developed and the like to remove the photoresist 292 above the polysilicon layer 244 that is not required to be retained, and then the polysilicon layer 244 and the gate oxide layer 242 are etched to obtain the gate structure, as shown in FIG. 3.

[0047] In the embodiment shown in FIG. 2, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type.

[0048] S120, performing first body region lithography to form a first implantation window.

[0049] In one embodiment of the present application, after the photoresist 292 is removed, a layer of photoresist 294 (e.g., a first photoresist layer) is re-coated on the wafer, and then the photoresist 294 is exposed to the first implantation window by using a body region mask for lithography.

[0050] S130, performing ion implantation on the front side of the wafer to form a first implantation region under the first implantation window.

[0051] The arrow in FIG. 4 represents the direction of the ion implantation of the second conductive type impurities in step S130, and the ion implantation step uses a lower implantation energy to form a first implantation region 22 with a shallower implantation position, so the thickness of the photoresist 294 can be thinner to obtain a more uniform Vt.

[0052] For the NLDMOS, the conductive channel is generally P-type doped, but in the low-energy implantation of step S130, an N-type doping can also be formed near the surface of the gate oxide layer 242 to reduce the on-resistance of the entire device.

[0053] S140, forming a nitride layer on the wafer.

[0054] After the photoresist 294 is removed, a layer of nitride layer 254 is deposited on the wafer. In one embodiment of the present application, the nitride layer 254 is subsequently used as part of the side wall of the gate structure. In one embodiment of the present application, the material of the nitride layer 254 is silicon nitride, such as silicon nitride. In another embodiment of the present application, the material of the nitride layer 254 is silicon oxynitride.

[0055] In one embodiment of the present application, before the nitride layer 254 is formed, a step of forming a first oxide layer 252 on the wafer is further included, and the first oxide layer 252 can be formed by deposition. The nitride layer 254 is formed on the first oxide layer 252, as shown in FIG. 5. In one embodiment of the present application, the material of the first oxide layer 252 is silicon oxide, such as silicon dioxide.

[0056] S150, performing second body region lithography to form a second implantation window.

[0057] A layer of photoresist 296 (e.g. a second photoresist layer) is coated on the wafer to cover the nitride layer 254, and then photolithography is performed to expose the second implantation window, as shown in Fig. 6. The anti-reflective property of the nitride layer 254 allows the photoresist 296 to have a better edge profile after exposure and development, so that the second implantation window has a better edge profile. In an embodiment of the present application, the photolithography of step S150 can use the same mask as the photolithography of step S120, so as to avoid the cost increase caused by adding a mask.

[0058] S160, ion implantation is performed on the front side of the wafer to form a second implantation region 24 under the second implantation window.

[0059] The implantation energy of step S160 is greater than the implantation energy of step S130, so as to form the second implantation region 24 of the second conductivity type under the second implantation window (under the first implantation region 22), as shown in Fig. 7. As mentioned above, since the edge profile of the second implantation window is better, the implantation of step S160 can have a better Vt uniformity. After the second implantation region 24 is subjected to a subsequent heat treatment such as annealing, the implanted second conductivity type impurity ions diffuse and form the body region 20 together with the first implantation region 22.

[0060] The manufacturing method of the semiconductor device described above includes two implantations in the process of forming the body region 20. The first implantation uses a lower implantation energy, so that a thinner photoresist 294 can be used as the implantation barrier layer to obtain a more uniform Vt. The photoresist for the second implantation is formed on the nitride layer 254, and the anti-reflective property of the nitride layer 254 allows the second implantation window to have a better edge profile, which is also beneficial to obtaining a uniform Vt, so as to improve the reliability of the device.

[0061] In an embodiment of the present application, the thickness of the photoresist 294 formed in step S120 is to A thinner photoresist 294 is used to obtain a more uniform Vt. In an embodiment of the present application, the ion implantation energy of step S130 is 15 kev to 50 kev.

[0062] In an embodiment of the present application, after step S160, the photoresist 296 is removed, and then a second oxide layer 256 is formed to cover the nitride layer 254, as shown in Fig. 8. The second oxide layer 256 can be formed by deposition. In an embodiment of the present application, the material of the second oxide layer 256 is silicon oxide, such as silicon dioxide.

[0063] Referring to FIG. 9, in one embodiment of the present application, the first oxide layer 252, the nitride layer 254 and the second oxide layer 256 are etched, and the remaining first oxide layer 252, the nitride layer 254 and the second oxide layer 256 after etching are used as the side wall 250 with O-N-O structure located at the side of the gate structure. That is, in the embodiment of the present application, after forming the nitride layer 254, the photoetching of step S150 and the implantation of step S160 are performed first, and the quality of the photoetching of the second implantation window side wall is improved by using the nitride layer in the side wall 250; and then the second oxide layer 256 in the side wall 250 with O-N-O structure is formed.

[0064] In one embodiment of the present application, after step S130 and before step S150, a step of activating the implanted impurity ions in the first implantation region 22 by heat treatment to form channel surface ions is further included. Specifically, the implanted impurity ions can be activated by rapid thermal annealing before step S140. In other embodiments, the implanted impurity ions can also be activated by rapid thermal oxidation or other high-temperature activation methods.

[0065] In one embodiment of the present application, after forming the side wall 250, the drain region 236 and the source region 234 are formed by patterning (e.g. photoetching) and ion implantation. The source region 234 is formed in the body region 20, the drain region 236 and the source region 234 have the first conductivity type, and the doping concentration of the drain region 236 and the source region 234 is greater than the doping concentration of the drift region 232. The gate structure is located above the region between the source region 234 and the drain region 236. In the embodiment shown in FIG. 10, the drain region 236 and the source region 234 are N+ regions. In one embodiment of the present application, the method for manufacturing a semiconductor device further includes a step of leading out the drain, source / bulk and gate electrodes by depositing metal, etching a contact hole, leading out by the contact hole, etc.

[0066] The method for manufacturing a semiconductor device of the present application forms the body region in a manner particularly suitable for LDMOS, such as NLDMOS (or PLDMOS), but also suitable for other types of semiconductor devices, such as VDMOS.

[0067] The present application accordingly provides a semiconductor device formed by the method for manufacturing a semiconductor device according to any one of the preceding embodiments, and the structure of which can be referred to FIG. 10.

[0068] It should be understood that, although the steps in the flowcharts of the present application are shown in a sequence as indicated by arrows, the steps are not necessarily executed in the order as indicated by the arrows. Unless otherwise specified herein, the execution of the steps is not necessarily limited to the order as indicated by the arrows, and the steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the present application can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution of the steps or stages is not necessarily sequential, but can be performed in rotation or alternation with at least some of the other steps or the steps or stages in the other steps.

[0069] In the description of the present application, the description referring to the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0070] The technical features of the above-described embodiments can be combined in any manner. In order to make the description concise, not all possible combinations of the technical features of the above-described embodiments are described, however, as long as the combinations of the technical features do not contradict each other, they should be considered within the scope of the present application.

[0071] The above-described embodiments only express several implementation manners of the present application, and the description is specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises: forming a gate structure on a substrate of a wafer; forming a first photoresist layer on the wafer, and performing first body region photolithography to form a first implantation window; performing first ion implantation on the wafer to form a first implantation region below the first implantation window; removing the first photoresist layer, and then forming a nitride layer on the wafer; forming a second photoresist layer on the wafer to cover the nitride layer, and performing second body region photolithography to form a second implantation window; performing second ion implantation on the wafer to form a second implantation region below the second implantation window, the implantation energy being greater than that of forming the first implantation region.

2. The method of manufacturing a semiconductor device according to claim 1, wherein Before forming the nitride layer, the method further comprises forming a first oxide layer on the wafer, and forming the nitride layer on the first oxide layer. After forming the second implantation region, the method further comprises removing the second photoresist layer covering the nitride layer, then forming a second oxide layer covering the nitride layer, and etching the first oxide layer, the nitride layer, and the second oxide layer to form a side wall on the side of the gate structure.

3. The method of manufacturing a semiconductor device according to claim 1, wherein After forming the first implantation region and before forming the second photoresist layer covering the nitride layer, the method further comprises activating the impurity ions implanted in the first implantation region by heat treatment to form channel surface ions.

4. The method of manufacturing a semiconductor device according to Claim 1, wherein The ion implantation energy used in forming the first implantation region is 15 keV to 50 keV; and / or The thickness of the first photoresist layer formed on the wafer is To 5. The method of manufacturing a semiconductor device according to Claim 1, wherein Before forming the first photoresist layer on the wafer, the method further comprises forming a drift region, the drift region having a first conductivity type, the first implantation region and the second implantation region having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; After forming the second implantation region, the method further comprises forming a drain region and a source region, the source region being formed in a body region formed by the first implantation region and the second implantation region, the drain region and the source region having the first conductivity type, and the doping concentration of the drain region and the source region being greater than the doping concentration of the drift region.

6. The method of manufacturing a semiconductor device according to Claim 1, wherein The first body region photolithography and the second body region photolithography use the same mask.

7. The method of manufacturing a semiconductor device according to Claim 1, wherein The nitride layer is a silicon nitride layer or a silicon oxynitride layer.

8. The method of manufacturing a semiconductor device according to any one of Claims 1-7, wherein The semiconductor device is a lateral double-diffusion metal-oxide-semiconductor field-effect transistor or a vertical double-diffusion metal-oxide-semiconductor field-effect transistor.

9. The method of manufacturing a semiconductor device according to claim 8, wherein The first conductivity type is N type, the second conductivity type is P type, and the semiconductor device is an N-channel lateral double-diffusion metal-oxide-semiconductor field-effect transistor; or The first conductivity type is P type, the second conductivity type is N type, and the semiconductor device is a P-channel lateral double-diffusion metal-oxide-semiconductor field-effect transistor.

10. A semiconductor device, characterized by comprising: The semiconductor device is manufactured according to the manufacturing method of any one of claims 1-9.

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