Chip system, chip system operation method, electronic device, and readable storage medium

Abstract

The present application relates to the technical field of semiconductors, and provides a chip system, a chip system operation method, an electronic device, and a readable storage medium. The chip system comprises a first chip and a second chip. The first chip comprises a first pin, the second chip comprises a second pin, and the first pin and the second pin are coupled by means of an interconnect bus. The first chip comprises a first loading module, and the first loading module is configured to load a first link connection configuration when the first chip boots. The second chip comprises a second loading module, and the second loading module is configured to load a second link connection configuration when the second chip boots. In response to the first link connection configuration and the second link connection configuration having been loaded, the first chip establishes a connection with the second chip. The first link connection configuration and the second link connection configuration comprise transmission rate information of a bitstream between the first pin and the second pin. The embodiments of the present application eliminate the need for the process of transmitting link connection configurations, improving the boot speed of the chip system.

Description

Chip system, chip system operation method, electronic device and readable storage medium

[0001] The present application claims priority to the Chinese patent application No. 202410480371.8, filed on April 19, 2024, and entitled "Chip system, chip system operation method, electronic device and readable storage medium", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application belongs to the technical field of semiconductors, and particularly relates to a chip system, a chip system operation method, an electronic device and a readable storage medium. BACKGROUND

[0003] A system-on-a-chip (SOC) can solve the problem of insufficient user terminal coding and decoding capability by adopting a multi-chip cascading manner. In the system-on-a-chip, usually one chip is selected from multiple chips as a master chip, and the other chips are slave chips. When the system-on-a-chip is started, the master chip needs to send a startup program to the slave chip. In actual application, the startup program contains a large amount of data, and it takes a long time to complete the transmission of the startup program, thereby causing a long time consumption in the startup process of the system-on-a-chip when the multiple chips are cascaded, and the startup of the system-on-a-chip is slow. SUMMARY

[0004] Embodiments of the present application provide a chip system, a chip system operation method, an electronic device and a readable storage medium, which are used to improve the startup speed of the chip system.

[0005] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a chip system is provided. The chip system includes a first chip and a second chip, the first chip includes a first pin, the second chip includes a second pin, and the first pin and the second pin are coupled through an interconnection bus. The first chip stores a first link connection configuration, and the second chip stores a second link connection configuration. The first chip includes a first loading module, the first loading module is configured to load the first link connection configuration when the first chip is started. The second chip includes a second loading module, the second loading module is configured to load the second link connection configuration when the second chip is started. In response to the first link connection configuration and the second link connection configuration being loaded, a connection is established between the first chip and the second chip. The first link connection configuration and the second link connection configuration include transmission rate information of a code stream between the first pin and the second pin.

[0007] In the embodiments of the present application, the first chip and the second chip load the link connection configurations locally. That is, the first chip automatically loads the first link connection configuration from the local, and the second chip automatically loads the second link connection configuration from the local. The process that the first chip and the second chip need to transmit the link connection configuration through the low-speed bus is omitted, and after the first chip and the second chip load the link connection configurations locally, the first chip and the second chip can directly complete the high-speed mode link building through the interconnection bus, thereby improving the startup speed of the chip system.

[0008] In some possible embodiments, when the first chip and the second chip are combined for packaging, the code stream is transmitted between the first pin and the second pin through a single-ended signal; when the first chip and the second chip are packaged separately, the code stream is transmitted between the first pin and the second pin through a differential signal. In different application scenarios, the first chip and the second chip transmit the code stream in different modes. The differential mode has strong anti-interference ability and can effectively suppress electromagnetic interference, but at the same time, it also has the problem of large power consumption. Therefore, in the scene with short transmission distance and small interference, the single-ended mode is more advantageous.

[0009] In some possible embodiments, the first chip stores mode configuration information of the second chip, and the mode configuration information includes configuration information of a plurality of register operating states of the second chip. The first loading module is further configured to load the mode configuration information when the first chip starts. The first chip further includes a driving module, and the driving module is configured to control the register operating state of the second chip according to the mode configuration information. That is, the mode configuration information of the second chip can be mapped to the first chip, so that the control of the second chip is opened to the first chip.

[0010] In some examples, the first chip includes a first address mapping module, and the first address mapping module is configured to map the address space of the second chip to the address space of the first chip. In the embodiments of the present application, the management of the address mapping relationship is completed by the first address mapping module, which is invisible to the driver, thereby realizing the non-perception of the driver to the interface deployment.

[0011] Exemplarily, the driving module is configured to access the register in the first chip through the bus of the first chip, and is configured to access the register in the second chip through the interconnection bus according to the first address mapping module. That is, in the embodiments of the present application, the first chip can control the work of the first chip and the work of the second chip through the driving module and the first address mapping module.

[0012] In some possible embodiments, the second chip includes a second address mapping module, and the second address mapping module is configured to map the address space of the first chip to the address space of the second chip. That is, in the embodiments of the present application, the second chip can access the address space in the first chip through the second address mapping module.

[0013] In a second aspect, a chip system operation method is provided. The operation method is applied to a chip system, the chip system comprising a first chip and a second chip, the first chip comprising a first pin, the second chip comprising a second pin, the first pin being coupled with the second pin through an interconnection bus. The first chip stores a first link connection configuration, and the second chip stores a second link connection configuration. The operation method comprises: loading, by the first chip, the first link connection configuration when starting; loading, by the second chip, the second link connection configuration when starting; and establishing, by the first chip and the second chip, a connection in response to the first link connection configuration and the second link connection configuration being loaded completely. The first link connection configuration and the second link connection configuration comprise transmission rate information of a code stream between the first pin and the second pin.

[0014] In some possible implementation manners, the first chip stores mode configuration information of the second chip, and the mode configuration information comprises configuration information of a plurality of register operating states of the second chip. The operation method further comprises: loading, by the first chip, the mode configuration information when starting; and controlling, by the first chip, the register operating states of the second chip according to the mode configuration information.

[0015] Exemplarily, after the first chip and the second chip establish the connection, the operation method further comprises: accessing, by the first chip, a register in the first chip through a bus of the first chip; and accessing, by the first chip, a register in the second chip through the interconnection bus.

[0016] In some possible implementation manners, after the first chip and the second chip establish the connection, the operation method further comprises: sending, by the first chip, a mirror program to the second chip through the interconnection bus; and loading, by the second chip, and running the mirror program.

[0017] In a third aspect, an electronic device is provided. The electronic device comprises a PCB board and the chip system of any one of the first aspect. The chip system is arranged on the PCB board.

[0018] In a fourth aspect, a readable storage medium is provided. The readable storage medium stores computer executable instructions. The computer executable instructions, when executed, implement the method of any one of the second aspect.

[0019] In a fifth aspect, a chip is provided. The chip comprises a chip interconnection circuit. The chip interconnection circuit comprises an output interface circuit, an input interface circuit, and a test controller. The input interface circuit comprises a first amplifier and a first gate, and the output interface circuit comprises a second amplifier. A first input end of the first gate is coupled with an input end of the second amplifier, a second input end of the first gate is coupled with an output end of the first amplifier, and the test controller is coupled with a gate control end of the first gate.

[0020] The embodiment of the present application can realize internal loopback and external loopback of the test by controlling the first gate through the test controller, and the internal loopback and the external loopback can cover different circuits. In the internal loopback, the transmission code stream input by the second amplifier is looped back to the chip through the first gate, and the first amplifier and the second amplifier are not covered. In the external loopback, the first amplifier receives the transmission code stream output by the second amplifier, and the transmission code stream is looped back to the chip through the first gate, and the first amplifier and the second amplifier are covered. That is, if the internal loopback test passes and the external loopback test fails, it indicates that the fault is located in the first amplifier and the second amplifier; if the internal loopback fails, it indicates that the fault is located in other devices of the chip interconnection circuit. Moreover, in the case that the internal loopback test passes and the external loopback test fails, if there is transmission code stream output from the chip in the external loopback test, the fault is located in the first amplifier; if there is no transmission code stream output from the chip in the external loopback test, the fault is located in the second amplifier (or, the fault is located in the second amplifier and the first amplifier). The embodiment of the present application can better locate the fault position, thereby improving the test efficiency of the chip.

[0021] In some possible embodiments, the test controller is configured to receive a test instruction. According to the test instruction, the output end of the first gate is controlled to be conductive with the first input end, so as to realize the external loopback of the test. Or, the output end of the first gate is controlled to be conductive with the second input end, so as to realize the internal loopback of the test.

[0022] In some possible embodiments, the output interface circuit further comprises a second gate, the first input end of the second gate is coupled with the output end of the first gate, the output end of the second gate is coupled with the input end of the second amplifier, and the first input end of the first gate is coupled; the test controller is coupled with the gate control end of the second gate. The transmission code stream received by the first amplifier can be output from the second amplifier through the first gate and the second gate, and the embodiment of the present application can also determine whether the fault is located in the first amplifier and the second amplifier by comparing the transmission code stream sent to the first amplifier and the transmission code stream output from the second amplifier.

[0023] In some possible embodiments, the chip interconnection circuit further comprises an encoder, and the encoder can encode the test excitation signal into the transmission code stream when the internal loopback test and the external loopback test are performed. The output end of the encoder is coupled with the second input end of the second gate, and if the internal loopback fails, it indicates that the fault can be located in the encoder.

[0024] In some possible implementation manners, the test controller is further configured to receive a test instruction. According to the test instruction, the output end of the second gate is controlled to be conductive with the first input end, and the transmission code stream received by the first amplifier can be output from the second amplifier. Alternatively, the output end of the second gate is controlled to be conductive with the second input end, so that internal loopback testing or external loopback testing can be performed.

[0025] In some possible implementation manners, the chip interconnection circuit further includes a third gate and a signal generator. The first input end of the third gate is coupled with the data sending end of the chip interconnection circuit. The second input end of the third gate is coupled with the output end of the signal generator. The output end of the third gate is coupled with the input end of the encoder. The third gate is further coupled with the test controller. The signal generator can output a test excitation signal. The test controller controls the third gate, so that in a test scenario, the encoder receives the test excitation signal output by the signal generator. In a working scenario, the encoder receives data (or a signal) from the data sending end of the chip interconnection circuit. That is, the test controller controls the third gate, so that the switching between the test scenario and the working scenario can be realized.

[0026] In some possible implementation manners, the test controller is configured to receive a test instruction. According to the test instruction, the output end of the third gate is controlled to be conductive with the first input end, so as to switch to the working scenario. Alternatively, the output end of the third gate is controlled to be conductive with the second input end, so as to switch to the test scenario.

[0027] In some possible implementation manners, the chip interconnection circuit further includes a decoder. The input end of the decoder is coupled with the output end of the first gate. The output end of the decoder is coupled with the data receiving end of the chip interconnection circuit. The decoder can decode the transmission code stream received by the input interface circuit, and send the decoded data (or a signal) to the core circuit (for example, a processing circuit and a storage circuit) of the chip through the data receiving end of the chip interconnection circuit.

[0028] In some possible implementation manners, the chip interconnection circuit further includes a signal verifier. The input end of the signal verifier is coupled with the output end of the decoder. In a test scenario, the signal verifier can verify the test response signal decoded and output by the decoder, so as to determine whether the test is passed.

[0029] In some possible implementation manners, the first amplifier is a differential amplifier with double-ended input, and the second amplifier is a differential amplifier with double-ended output; the chip interconnection circuit further includes a mode controller coupled with the first amplifier and the second amplifier. The mode controller is configured to control output modes of the first amplifier and the second amplifier. The differential mode has strong anti-interference capability and can effectively suppress electromagnetic interference, but also brings the problem of high power consumption; in a scenario with short transmission distance and small interference, the single-ended mode is more advantageous. The mode controller is configured to switch the output modes of the first amplifier and the second amplifier, so that the chip can be applied to different scenarios. In addition, the single-ended mode and the differential mode multiplexing circuit and the interface can also save the area of the chip.

[0030] In a sixth aspect, a chip testing method is provided. The testing method includes: encoding a test excitation signal to obtain a first transmission code stream; receiving a test instruction, the test instruction indicating a test mode of the chip; in response to the test mode indicated by the test instruction being a first test mode, decoding the first transmission code stream to obtain a first test response signal; and checking the first test response signal to obtain a first test result, the first test result indicating whether a coding and decoding function of the chip has a fault.

[0031] In some possible implementation manners, the testing method further includes: sending the first transmission code stream; receiving a second transmission code stream, the second transmission code stream being generated based on the first transmission code stream; in response to the test mode indicated by the test instruction being a second test mode, decoding the second transmission code stream to obtain a second test response signal; and checking the second test response signal to obtain a second test result, the second test result indicating whether a coding, decoding, sending and receiving function of the chip has a fault.

[0032] In some possible implementation manners, the testing method includes: receiving a test instruction, the test instruction indicating a test mode of the chip; receiving a first transmission code stream; in response to the test mode indicated by the test instruction being a third test mode, sending a second transmission code stream, the second transmission code stream being generated based on the first transmission code stream; and the first transmission code stream and the second transmission code stream are used to determine whether a sending and receiving function of the chip has a fault.

[0033] In a seventh aspect, a chip system is provided. The chip system includes a first chip and a second chip, and the first chip and the second chip each include the chip interconnection circuit of the first aspect. An input interface circuit of the first chip is coupled with an output interface circuit of the second chip, and an output interface circuit of the first chip is coupled with an input interface circuit of the second chip.

[0034] In an eighth aspect, a chip system testing method is provided. The method comprises: receiving, by a first node and a second node, a test instruction, the test instruction indicating a test mode of a chip; in response to the test mode indicated by the test instruction being a fourth test mode, encoding, by the first node, a test stimulus signal to obtain a first transmission code stream, and transmitting, by the first node, the first transmission code stream. In response to the test mode indicated by the test instruction being the fourth test mode, receiving, by the second node, the first transmission code stream, and transmitting, by the second node, a second transmission code stream; the second transmission code stream being generated based on the first transmission code stream. Receiving, by the first node, the second transmission code stream, decoding, by the first node, the second transmission code stream to obtain a third test response signal. Checking, by the first node, the third test response signal to obtain a third test result; the third test result indicating whether a coding, decoding, transmitting and receiving function of the first node is faulty; and indicating whether a transmitting and receiving function of the second node is faulty. BRIEF DESCRIPTION OF DRAWINGS

[0035] FIG. 1 is a structural schematic diagram of a first electronic device according to an embodiment of the present application;

[0036] FIG. 2 is a structural schematic diagram of a chip system according to an embodiment of the present application;

[0037] FIG. 3 is a structural schematic diagram of another chip system according to an embodiment of the present application;

[0038] FIG. 4 is a structural schematic diagram of a second electronic device according to an embodiment of the present application;

[0039] FIG. 5 is a structural schematic diagram of a third electronic device according to an embodiment of the present application;

[0040] FIG. 6 is a circuit structural schematic diagram of a chip and a chip interconnection circuit according to an embodiment of the present application;

[0041] FIG. 7 is a circuit structural schematic diagram of one of output modes of a chip interconnection circuit according to an embodiment of the present application;

[0042] FIG. 8 is a circuit structural schematic diagram of another of output modes of a chip interconnection circuit according to an embodiment of the present application;

[0043] FIG. 9 is an internal loopback testing flowchart of one of chip testing methods according to an embodiment of the present application;

[0044] FIG. 10 is a path schematic diagram of internal loopback of chip testing according to an embodiment of the present application;

[0045] FIG. 11 is an external loopback testing flowchart of one of chip testing methods according to an embodiment of the present application;

[0046] FIG. 12 is a path schematic diagram of external loopback of chip testing according to an embodiment of the present application;

[0047] FIG. 13 is a flowchart of another chip testing method according to an embodiment of the present application;

[0048] FIG. 14 is a loopback path diagram of another chip testing method according to an embodiment of the present application;

[0049] FIG. 15 is a flowchart of a chip system testing method according to an embodiment of the present application;

[0050] FIG. 16 is a loopback path diagram of a chip system testing method according to an embodiment of the present application;

[0051] FIG. 17 is a structural diagram of a chip system according to an embodiment of the present application;

[0052] FIG. 18 is a software architecture diagram of a chip system according to an embodiment of the present application;

[0053] FIG. 19 is an address space mapping diagram of a second chip on a first chip according to an embodiment of the present application;

[0054] FIG. 20 is a software call path diagram of an application using a first hardware circuit according to an embodiment of the present application;

[0055] FIG. 21 is a software call path diagram of an application using a second hardware circuit according to an embodiment of the present application;

[0056] FIG. 22 is an address space mapping diagram of a first chip on a second chip according to an embodiment of the present application;

[0057] FIG. 23 is an operation flowchart of a chip system according to an embodiment of the present application.

[0058] Reference signs: 100, electronic device; 110, chip system; 111, first chip; 112, second chip; 200, core circuit; 300, chip interconnection circuit; 310, input interface circuit; 311, first amplifier; 312, first gate; 320, output interface circuit; 321, second amplifier; 322, second gate; 330, encoder; 340, decoder; 350, signal generator; 360, third gate; 370, signal verifier; 380, test controller; 390, mode controller; 410, first pin; 420, processor; 430, first memory; 440, third memory; 450, first address mapping module; 510, second pin; 520, input / output interface; 530, second memory; 540, fourth memory; 550, second address mapping module. DETAILED DESCRIPTION

[0059] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in combination with Figs. 1-23 and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0060] The terms "first", "second", etc. used in the embodiments of the present application are only used for the purpose of distinguishing the same type of features, and should not be understood as indicating relative importance, quantity, order, etc.

[0061] The terms "exemplary" or "for example" used in the embodiments of the present application are used to represent an example, illustration or description. Any embodiment or design solution described as "exemplary" or "for example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design solutions. Rather, the terms "exemplary" or "for example" are used in the sense of presenting a related concept in a specific manner.

[0062] The terms "coupled" and "connected" used in the embodiments of the present application should be interpreted in a broad sense, for example, can refer to a direct physical connection, or can refer to an indirect connection through electronic devices, such as a connection through resistors, inductors, capacitors or other electronic devices.

[0063] Design for testability (DFT) refers to auxiliary design made for the purpose of fault detection by adding certain hardware when designing circuits and systems. In order to improve the controllability and observability of the circuit, thereby reducing the difficulty and complexity of the circuit test, and improving the test efficiency of the circuit.

[0064] The embodiments of the present application provide an electronic device, as shown in Fig. 1, the electronic device 100 includes a circuit board (not shown in the figure) and a chip system 110, the chip system 110 is arranged on the circuit board. The chip system 110 can include a first chip 111 (which can be referred to as a first die) and a second chip 112 (which can be referred to as a second die), the first chip 111 is coupled with the second chip 112. Wherein, the circuit board can be a printed circuit board (PCB), and the circuit board can also be a chip substrate (SUB).

[0065] FIG. 2 shows a structural diagram of a chip system. As shown in FIG. 2, the first chip 111 and the second chip 112 can perform protocol conversion on data content, and send the data content to a root complex port (RC) module in a peripheral component interconnect express (PCIe) protocol packet format. The RC module and a PCIe physical interface can implement interconnection communication between the first chip 111 and the second chip 112 according to a PCIe interface protocol.

[0066] FIG. 3 shows a structural diagram of another chip system. As shown in FIG. 3, the first chip 111 and the second chip 112 can be coupled through a PCIe bus and an inter-integrated circuit (IIC) bus. When the chip system 110 is started, the two chips can first be interconnected through the IIC bus at a low speed, and then be interconnected through the PCIe bus at a high speed. When the two chips are interconnected through the IIC bus at the low speed, the first chip 111 (which can be referred to as a sending end) can first send a link connection configuration to the second chip 112 (which can be referred to as a receiving end) through the IIC bus. When the link connection configuration takes effect and parameters at both ends of the PCIe bus are matched, the first chip 111 and the second chip 112 can be interconnected through the PCIe bus at the high speed. The first chip 111 sends a start-up program to the second chip 112 through the PCIe bus (high-speed bus), which can reduce the transmission time of the start-up program and improve the start-up speed of the chip.

[0067] In some embodiments, the first chip 111 and the second chip 112 can be deployed in an inter-board interconnection manner and be deployed on the same circuit board. That is, the electronic device 100 can be a mobile phone (for example, a mobile phone), a tablet computer, a notebook computer, or the like.

[0068] In some embodiments, the first chip 111 and the second chip 112 can be deployed in a cross-board interconnection manner and be deployed on two circuit boards, respectively, or be deployed on two different electronic devices 100, respectively.

[0069] As shown in FIG. 4, an embodiment of the present application provides an electronic device 100, which includes a circuit board (not shown in the figure) and a first chip 111. The first chip 111 is disposed on the circuit board. In some examples, the electronic device 100 can be a television display terminal in a split television.

[0070] As shown in FIG. 5, the embodiment of the present application provides an electronic device 100, which comprises a circuit board (not shown in the figure) and a second chip 112, and the second chip 112 is arranged on the circuit board. In some examples, the electronic device 100 can be a television main machine in a split television.

[0071] In some embodiments, the electronic device 100 (television display terminal) shown in FIG. 4 is interconnected with the electronic device 100 (television main machine) shown in FIG. 5, and the split television can deploy all complex interfaces on the television main machine, and the television display terminal only has a display function.

[0072] In some other embodiments, the electronic device 100 can also be used independently, for example, the electronic device 100 can be an interface expansion dock, which is connected to a host through a bus, simplifies a master control chip deployed on the expansion dock, and realizes a low-cost high-performance expansion dock scheme.

[0073] As shown in FIG. 6, the first chip 111 and the second chip 112 each include a core circuit 200 and a chip interconnection circuit 300, and the difference between the first chip 111 and the second chip 112 lies in the core circuit 200. That is, different devices can be integrated on the first chip 111 and the second chip 112 to realize different functions. In some embodiments, the core circuit 200 of the first chip 111 can include a processor and a memory, where the processor can be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processing unit (CPU), an application processor (AP), a network processor (NP), a digital signal processor (DSP), a micro controller unit (MCU), a programmable logic device (PLD), a modem, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a baseband processor, and a neural-network processing unit (NPU), etc. A cache can also be provided in the processor to store computer instructions and data. The cache can store computer instructions or data that have just been used or are frequently used by the processor. If the processor needs to use the computer instructions or data again, the computer instructions or data can be directly called from the cache. This avoids repeated access and reduces the waiting time of the processor, which helps to improve the efficiency of the first chip 111.

[0074] In some embodiments, the core circuit 200 of the second chip 112 can include an input / output (I / O) interface. The input / output interface can be a high definition multimedia (HDMI) interface, a display port (DP) interface, a composite video broadcast signal (CVBS) interface, a video graphics array (VGA) interface, a radio frequency (RF) interface, a universal serial bus (USB) interface, or the like.

[0075] The embodiments of the present application do not limit the types of the first chip 111 and the second chip 112. In some examples, one first chip 111 can be interconnected with one or more second chips 112 of different types; for example, one first chip 111 for processing video can be interconnected with a second chip 112 integrating an HDMI interface, a second chip 112 integrating an RF interface, and / or a second chip 112 integrating a USB interface. In other examples, one second chip 112 can also be interconnected with one or more first chips 111 of different types.

[0076] In testing, in order to reduce the dependence on automatic test equipment (ATE), the embodiments of the present application integrate a built-in self test (BIST) circuit in the chip interconnection circuit 300 to realize the function of self-testing. The built-in self test circuit has two working scenarios: one is a test scenario, and the other is a working scenario in which the self-test circuit does not work. As shown in FIG. 7, in some embodiments, the chip interconnection circuit 300 includes an input interface circuit 310, an output interface circuit 320, an encoder 330, a decoder 340, a signal generator 350, a third gate 360, a signal checker 370, and a test controller 380. In this way, after the chip is processed, the chip itself can be tested by using the attached built-in self test circuit.

[0077] The encoder 330 is coupled with the output interface circuit 320, and the encoder 330 encodes the signal (or data) that can be output by the core circuit 200, and sends the transmission code stream obtained by encoding to other chips connected through the output interface circuit 320. The decoder 340 is coupled with the input interface circuit 310, and the input interface circuit 310 can receive the transmission code stream from other chips connected, and outputs to the core circuit 200 after decoding by the decoder 340, and is processed by the core circuit 200.

[0078] In some embodiments, the input interface circuit 310 includes a first amplifier 311 and a first gate 312, and the output interface circuit 320 includes a second amplifier 321 and a second gate 322.

[0079] The first input end of the first gate 312 is coupled with the input end of the second amplifier 321, the second input end of the first gate 312 is coupled with the output end of the first amplifier 311, the output end of the first gate 312 is coupled with the input end of the decoder 340, and the first input end of the second gate 322. The output end of the decoder 340 is coupled with the signal verifier 370, and the output end of the decoder 340 is also coupled with the core circuit 200 through the data receiving end (Rx_Data) of the chip interconnection circuit 300.

[0080] The first input end of the third gate 360 is coupled with the core circuit 200 through the data sending end (Tx_Data) of the chip interconnection circuit 300, the second input end of the third gate 360 is coupled with the output end of the signal generator 350, the output end of the third gate 360 is coupled with the input end of the encoder 330, the output end of the encoder 330 is coupled with the second input end of the second gate 322, the output end of the second gate 322 is coupled with the input end of the second amplifier 321, and the first input end of the first gate 312.

[0081] The test controller 380 is coupled with the control end of the first gate 312, the control end of the second gate 322 and the control end of the third gate 360 respectively, and is used for controlling the first gate 312, the second gate 322 and the third gate 360.

[0082] Further, as shown in FIG. 7 and FIG. 8, in some possible implementation manners, the first amplifier 311 is a differential amplifier with double-ended input, the second amplifier 321 is a differential amplifier with double-ended output, and the chip interconnection circuit 300 further includes a mode controller 390 coupled with the first amplifier 311 and the second amplifier 321. The mode controller 390 is configured to control the output mode of the first amplifier 311 and the second amplifier 321. The differential mode has strong anti-interference ability and can effectively suppress electromagnetic interference, but at the same time, it also brings the problem of high power consumption; in the scene of short transmission distance and small interference, the single-ended mode is more advantageous. The mode controller 390 is configured to switch the output mode of the first amplifier 311 and the second amplifier 321, so that the chip can be applied to different scenes, and the applicability of the chip is stronger. In addition, the single-ended mode and differential mode multiplexing circuit and interface can also save the area of the chip.

[0083] As shown in FIG. 9, the embodiment of the present application provides a chip test method, including steps S110-S140, as follows:

[0084] S110, the encoder encodes the test stimulus signal to obtain a first transmission code stream.

[0085] In some embodiments, the test stimulus signal can be initiated by the signal generator 350; in other embodiments, the test stimulus signal can also be initiated by the automatic test equipment, which is not limited herein.

[0086] S120, the test controller receives a test instruction.

[0087] As shown in FIG. 10, the test controller 380 can be coupled with the automatic test equipment through the test mode end (Test_Mode) of the chip interconnection circuit 300 to receive the test instruction. In some embodiments, the test instruction indicates the test mode of the chip. The test controller 380 is coupled with the first gate 312, the second gate 322 and the third gate 360, so as to control the output end of the first gate 312 to be conductive with the first input end or control the output end of the first gate 312 to be conductive with the second input end according to the test instruction; control the output end of the second gate 322 to be conductive with the first input end or control the output end of the second gate 322 to be conductive with the second input end; and control the output end of the third gate 360 to be conductive with the first input end or control the output end of the third gate 360 to be conductive with the second input end.

[0088] S130, in response to the test mode indicated by the test instruction being the first test mode, the decoder decodes the first transmission code stream to obtain a first test response signal.

[0089] FIG. 10 shows an internal loopback path of the chip test. As shown in FIG. 10 (the core circuit 200 is not shown), in some embodiments, the test controller 380 controls the output end of the second gate 322 to be conductive with the second input end, and controls the output end of the first gate 312 to be conductive with the first input end, in response to the test mode indicated by the test instruction being the first test mode. Thus, the first transmission code stream obtained by the encoder 330 is input to the decoder 340, and the first transmission code stream is decoded by the decoder 340 to obtain the first test response signal, so as to realize the internal loopback test.

[0090] It should be understood that, in the test scenario, the test controller 380 can control the output end of the third gate 360 to be conductive with the second input end, so as to make the encoder 330 receive the test excitation signal output by the signal generator 350. In the working scenario, the test controller 380 can control the output end of the third gate 360 to be conductive with the first input end, so as to make the encoder 330 receive data (or signals) from the data sending end of the chip interconnection circuit 300. That is, the embodiments of the present application can realize the switching between the test scenario and the working scenario by controlling the third gate 360 through the test controller 380.

[0091] S140, the signal verifier verifies the first test response signal to obtain a first test result.

[0092] In some embodiments, the signal verifier 370 can compare the first test response signal with the pre-stored expected response signal to obtain the first test result, and the first test result can indicate whether the encoding and decoding functions of the chip exist faults. In some embodiments, the output end of the signal verifier 370 can also be packaged into the pin of the device, so as to send the first test result indicating whether the encoding and decoding functions of the chip exist faults to the automatic test equipment.

[0093] As shown in FIG. 11, in some embodiments, the test method can further include steps S150-S180, as follows:

[0094] S150, the second amplifier sends the first transmission code stream.

[0095] FIG. 12 shows an external loopback path of the chip test. As shown in FIG. 12 (the core circuit 200 is not shown), in some embodiments, the automatic test equipment can receive the first transmission code stream from the second amplifier 321 through the pin of the device. In other embodiments, other test analysis equipment can also receive the first transmission code stream from the second amplifier 321 through the pin of the device, which is not limited herein.

[0096] S160, the first amplifier receives the second transmission code stream.

[0097] As shown in FIG. 12, in some embodiments, the automatic test equipment can generate a second transmission code stream based on the first transmission code stream, and send the second transmission code stream to the first amplifier 311 through the pins of the device.

[0098] S170, in response to the test mode indicated by the test instruction being the second test mode, the decoder decodes the second transmission code stream to obtain a second test response signal.

[0099] As shown in FIG. 12, in some embodiments, in response to the test mode indicated by the test instruction being the second test mode, the test controller 380 controls the output end of the second gate 322 to be conductive with the second input end, and controls the output end of the first gate 312 to be conductive with the second input end. Thus, the first transmission code stream obtained by the encoder 330 can be sent through the second amplifier 321, and the second transmission code stream (generated based on the first transmission code stream) received by the first amplifier 311 can be decoded by the decoder 340 to obtain a second test response signal, thereby realizing external loopback test.

[0100] S180, the signal verifier verifies the second test response signal to obtain a second test result.

[0101] In some embodiments, the signal verifier 370 can compare the second test response signal with a pre-stored expected response signal to obtain a second test result, and the second test result can indicate whether the encoding, decoding, sending and receiving functions of the chip are faulty.

[0102] The first gate 312 can realize internal loopback and external loopback of the test respectively under the control of the test controller 380 in the embodiment, and the internal loopback and the external loopback can cover different circuits. When the internal loopback, the transmission code stream input by the second amplifier 321 is looped back to the chip through the first gate 312, and the first amplifier 311 and the second amplifier 321 are not covered. When the external loopback, the first amplifier 311 receives the transmission code stream output by the second amplifier 321, and the transmission code stream is looped back to the chip through the first gate 312, and the first amplifier 311 and the second amplifier 321 are covered. That is, if the internal loopback test passes and the external loopback test fails, it indicates that the fault is located in the first amplifier 311 and the second amplifier 321; if the internal loopback test fails, it indicates that the fault is located in other devices of the chip interconnection circuit 300. Moreover, in the case that the internal loopback test passes and the external loopback test fails, if there is transmission code stream output from the chip during the external loopback test, the fault is located in the first amplifier 311; if there is no transmission code stream output from the chip during the external loopback test, the fault is located in the second amplifier 321 (or, the fault is located in the second amplifier 321 and the first amplifier 311). The embodiment can better locate the fault position, thereby improving the test efficiency of the chip.

[0103] As shown in FIG. 13, the embodiment further provides a chip test method, comprising steps S210-S230, as follows:

[0104] S210, the test controller receives a test instruction.

[0105] As shown in FIG. 14 (the core circuit 200 is not shown), the test controller 380 can be coupled with the automatic test equipment through the test mode end of the chip interconnection circuit 300 to receive the test instruction. In some embodiments, the test instruction indicates the test mode of the chip.

[0106] S220, the first amplifier receives a first transmission code stream.

[0107] As shown in FIG. 14, when the chip is tested, the first transmission code stream can be sent to the chip through a device or equipment capable of sending the transmission code stream (such as the automatic test equipment).

[0108] S230, in response to the test mode indicated by the test instruction being the third test mode, the second amplifier sends a second transmission code stream.

[0109] As shown in FIG. 14, in some embodiments, the first amplifier 311 can receive the first transmission code stream. The test controller 380 controls the output end of the second gate 322 to be conductive with the first input end, and controls the output end of the first gate 312 to be conductive with the second input end, in response to the test mode indicated by the test instruction being the third test mode. Thus, the first transmission code stream received by the first amplifier 311 passes through the first amplifier 311, the first gate 312, the second gate 322 and the second amplifier 321 in sequence. At the same time, since the first amplifier 311 and the second amplifier 321 can amplify the first transmission code stream, the second amplifier 321 finally sends the second transmission code stream through the pin of the device. In some embodiments, by comparing the first transmission code stream and the second transmission code stream, it can be determined whether the sending and receiving functions of the chip are faulty.

[0110] As shown in FIG. 15, the embodiment of the present application provides a chip system test method, comprising steps S310-S350, as follows:

[0111] S310, the first node and the second node receive a test instruction.

[0112] As shown in FIG. 16 (the core circuit 200 is not shown), the test mode end of the first node (i.e., the first chip 111) is coupled with the test mode end of the second node (i.e., the second chip 112), and the test mode end of the first node (or the test mode end of the first node) is coupled with the automatic test equipment to receive the test instruction. In some embodiments, the test instruction indicates the test mode of the chip.

[0113] S320, in response to the test mode indicated by the test instruction being the fourth test mode, the first node encodes the test excitation signal to obtain a first transmission code stream, and the first node sends the first transmission code stream.

[0114] As shown in FIG. 16, in some embodiments, the test controller 380 in the first chip 111 controls the output end of the third gate 360 in the first chip 111 to be conductive with the second input end, and controls the output end of the second gate 322 in the first chip 111 to be conductive with the second input end, in response to the test mode indicated by the test instruction being the fourth test mode. Thus, the first transmission code stream obtained by the encoder 330 in the first chip 111 can be sent through the second amplifier 321 in the first chip 111.

[0115] S330, in response to the test mode indicated by the test instruction being the fourth test mode, the second node receives the first transmission code stream and sends a second transmission code stream.

[0116] As shown in FIG. 16, in some embodiments, the test controller 380 in the second chip 112 controls the output end of the second gate 322 in the second chip 112 to be conductive with the first input end, and controls the output end of the first gate 312 in the second chip 112 to be conductive with the second input end, in response to the test mode indicated by the test instruction being the fourth test mode. The first amplifier 311 and the second amplifier 321 in the second chip amplify the first transmission code stream, so that the second chip 112 transmits a second transmission code stream; that is, the second transmission code stream is generated based on the first transmission code stream.

[0117] S340, the first node receives the second transmission code stream, decodes the second transmission code stream, and obtains a third test response signal.

[0118] In some embodiments, the test controller 380 in the first chip 111 also controls the output end of the first gate 312 in the first chip 111 to be conductive with the second input end, in response to the test mode indicated by the test instruction being the fourth test mode, and decodes the second transmission code stream by the decoder 340 in the first chip 111.

[0119] S350, the first node checks the third test response signal, and obtains a third test result.

[0120] In some embodiments, the signal checker 370 in the first chip 111 can compare the third test response signal with a pre-stored expected response signal to obtain the third test result. The first test result can indicate whether the encoding, decoding, transmitting and receiving functions of the first chip 111 have faults, and whether the transmitting and receiving functions of the second chip 112 have faults.

[0121] The chip system test method provided by the embodiments of the present application transmits the transmission code stream to the input interface circuit 310 in the second chip 112 through the output interface circuit 320 in the first chip 111. The transmission code stream is looped back to the output interface circuit 320 inside the second chip 112, is transmitted to the input interface circuit 310 in the first chip 111 through the output interface circuit 320 in the second chip 112, and completes the loopback test of the chip system 110. The loopback path covers the chip interconnection circuit 300 of the first chip 111 and the second chip 112.

[0122] It should be understood that the first chip 111 (may be referred to as a first die) and the second chip 112 (may be referred to as a second die) can have various packaging forms. In some embodiments, the first chip 111 and the second chip 112 can be packaged as two independent devices. As described above, the two independent devices can be deployed to the electronic device 100 in an inter-board interconnection manner, or can be deployed to the electronic device 100 in a cross-board interconnection manner. At this time, the input terminal of the input interface circuit 310 (i.e., the input end of the first amplifier 311) and the output terminal of the output interface circuit 320 (i.e., the output end of the second amplifier 321) in the chip interconnection circuit 300 can be packaged to the pins of the device. In some examples, when the first chip 111 and the second chip 112 are packaged separately, the first chip 111 (or the second chip 112) can be tested by using the method shown in FIG. 9, FIG. 11 or FIG. 13. In other examples, when the first chip 111 and the second chip 112 are packaged separately, the device in which the first chip 111 is located can be coupled with the device in which the second chip 112 is located, and the first chip 111 and the second chip 112 can be tested by using the test method shown in FIG. 15.

[0123] In other embodiments, the first chip 111 and the second chip 112 can be merged and packaged into one device by using a chiplet technology and an advanced packaging (for example, 2.5D packaging, 3D packaging) process, so as to improve the integration of the chips, and optimize the performance and power consumption of the chips. By using the above packaging process, the first chip 111 and the second chip 112 (or even more chips) are integrated into one device. Since the number of device pins is limited, the terminals of the first chip 111 and the second chip 112 cannot be all packaged to the pins of the device, and the test of the chips is greatly improved. In some examples, when the first chip 111 and the second chip 112 are merged and packaged into one device, the first chip 111 and the second chip 112 can be tested by using the test method shown in FIG. 15.

[0124] The application provides a chip, a chip testing method, a chip system and a chip system testing method. When a single chip is packaged alone, internal loopback and external loopback of testing can be respectively realized by controlling a first gate by a testing controller, the internal loopback and the external loopback can cover different circuits, and the position of a fault can be better located, so that the testing efficiency of the chip is improved. When a plurality of chips are packaged together, a transmission code stream is sent to an input interface circuit in a second chip through an output interface circuit in a first chip. The transmission code stream is looped back to the output interface circuit in the second chip, and is sent to an input interface circuit in the first chip through the output interface circuit in the second chip. The loopback path covers the chip interconnection circuit of the first chip and the second chip, so that the chip system can be better tested. That is, the embodiments of the application can better test the chip in the scene of a single chip packaged alone or the scene of a plurality of chips packaged together.

[0125] The application also provides a chip system. As shown in FIG. 17, the chip system 110 includes a first chip 111 and a second chip 112. The first chip 111 includes a first pin 410, and the second chip 112 includes a second pin 510. The first pin 410 and the second pin 510 are coupled through an interconnection bus. In some embodiments, the first chip 111 can include a processor 420, and the second chip 112 can include an input / output interface 520.

[0126] The processor 420 can execute programs and computer instructions stored in a memory. As shown in FIG. 18, in some examples, the programs running on the processor 420 can be layered according to functions, and can include an application layer, a framework layer, an SDK layer and the like. The embodiments of the application add a first boot loader in the SDK layer of the first chip 111 and a second boot loader (boot ROM) in the second chip 112. The first boot loader is used to load a first link connection configuration when the first chip 111 starts, and the second boot loader is used to load a second link connection configuration when the second chip 112 starts. The first link connection configuration and the second link connection configuration both include transmission rate information of a code stream between the first pin 410 and the second pin 510.

[0127] In some embodiments, the first link connection configuration and the second link connection configuration can be determined in a test phase of the chip and burned into the respective memories. That is, the first chip 111 includes a first memory 430 for storing the first link connection configuration. In some examples, the first memory 430 is a read-only memory (ROM). The second chip 112 can include a second memory 530 for storing the second link connection configuration. In some examples, the second memory 530 is a one time programmable (OTP) memory.

[0128] In the embodiments of the present application, the first chip 111 and the second chip 112 correspondingly load the respective link connection configurations, thereby eliminating the process that the first chip 111 and the second chip 112 need to first transmit the link connection configuration through the low-speed bus. After the link connection configuration is loaded, the first chip 111 and the second chip 112 can directly complete the high-speed mode link establishment through the interconnection bus, thereby improving the startup speed of the chip system 110. That is, the embodiments of the present application eliminate the low-speed pins in the first chip 111 and the second chip 112. The first pin 410 and the second pin 510 are high-speed pins; in some examples, the transmission rate of the code stream between the first pin 410 and the second pin 510 is greater than 1 Gbsp.

[0129] In some embodiments, the first memory 430 is further configured to store mode configuration information (sysreg) of the second chip 112. That is, the first chip 111 stores the mode configuration information of the second chip 112, and the mode configuration information includes configuration information of the running states of a plurality of registers of the second chip 112. The first loading module is further configured to load the mode configuration information of the second chip 112 when the first chip 111 starts. That is, the mode configuration information of the second chip 112 can be mapped to the first chip 111, thereby opening the control of the second chip 112 to the first chip 111.

[0130] As shown in FIG. 18, in some embodiments, the first chip 111 further comprises a driving module. The driving module can control the register running state of the first chip 111, so as to drive the first hardware circuit in the first chip 111. The driving module can also control the register running state of the second chip 112, so as to drive the second hardware circuit in the second chip 112. That is, the first chip 111 further comprises a third memory 440, the third memory 440 is used to store the driver of the first hardware circuit, and store the driver of the second hardware circuit. In some examples, the third memory 440 is a random access memory (RAM). In some embodiments, the second chip 112 can comprise a fourth memory 540. In some examples, the fourth memory 540 is a random access memory (RAM). Since the driver of the first hardware circuit and the driver of the second hardware circuit are both stored in the third memory 440, the data storage amount of the fourth memory 540 is less than that of the third memory 440.

[0131] It should be understood that the software development kit area of the first chip 111 can also comprise other modules; for example, an application programming interface (API), a standby wake-up module, a device tree source (DTS) module, etc., which are configured to adaptively expand to match different second chips 112.

[0132] In some possible implementations, the first chip 111 includes a first address mapping module 450, which is configured to map the address space of the second chip 112 to the address space of the first chip 111. That is, in the embodiments of the present application, the first chip 111 reserves the address space in advance, so that the entire address space of the second chip 112 can be mapped to the address space of the first chip 111 according to the requirement. As shown in FIG. 19, in some examples, the address space segment configured by the peripheral A in the second chip 112 is 0xa_0000-0xb_0000, which belongs to the address space range of the second chip 112. The first address mapping module 450 can map 0xa_0000-0xb_0000 to the address space segment 0xf00_0000-0xff0_0000 of the first chip 111. Therefore, if the processor 420 on the first chip 111 needs to access the 0xa_1000 register of the peripheral A, it actually only needs to access the 0xf0a_1000 address. In this way, for the driver of the peripheral A, whether it is deployed on the first chip 111 or the second chip 112, the offset of the register is the same, and the difference is only the base address. The management of the address mapping relationship is completed by the system, which is invisible to the driver, and the driver has no awareness of the interface deployment.

[0133] FIG. 20 shows the software call path of the application when using the hardware circuit (i.e., the first hardware circuit) of the first chip 111. As shown in FIG. 20, when the application uses the hardware circuit of the first chip 111, the driver module can access the register of the first hardware circuit through the bus of the first chip 111. FIG. 21 shows the software call path of the application when using the hardware circuit (i.e., the second hardware circuit) of the second chip 112. As shown in FIG. 21, when the application uses the hardware circuit of the second chip 112, the driver module can access the register of the second hardware circuit through the interconnection bus.

[0134] In some possible implementation manners, the second chip 112 comprises a second address mapping module 550, which is configured to map the address space of the first chip 111 to the address space of the second chip 112. That is, in the implementation manners of the present application, the second chip 112 reserves the address space in advance, so as to map the entire address space of the first chip 111 to the address space of the second chip 112 according to the requirement. As shown in FIG. 22, in some examples, the address space range of the double data rate (DDR) memory in the first chip 111 is 0x000_0000-0xeff_ffff, which is the address directly accessed when the device is on the first chip 111. The second address mapping module 550 can map 0x000_0000-0xeff_ffff to the address space segment 0xf000_0000-0xfeff_ffff of the second chip 112. The peripheral on the second chip 112 can access the double data rate memory on the first chip 111 by accessing the address segment 0xf000_0000-0xfeff_ffff. For example, the peripheral A on the second chip 112 can access the 0x1_0000 address of the double data rate memory by accessing the address 0xf001_0000.

[0135] It should be understood that the above address space mapping relationship is not fixed, and can be flexibly matched based on the actual application, which is not limited in the present application.

[0136] The implementation manners of the present application provide a chip system operation method, as shown in FIG. 23, which comprises the following steps:

[0137] S410, the first chip loads the first link connection configuration, and the second chip loads the mode configuration information.

[0138] S420, the second chip loads the second link connection configuration.

[0139] In some implementation manners, the first chip 111 and the second chip 112 are powered on at the same time, and each loads the local link connection configuration. Therefore, the process that the first chip 111 and the second chip 112 need to transmit the link connection configuration through the low-speed bus is omitted, so as to realize the fast start of the chip system 110.

[0140] S430, the first chip and the second chip establish connection.

[0141] In some embodiments, the connection between the first chip 111 and the second chip 112 is a high-speed bus. After the first chip 111 initializes the double-rate memory, the first chip 111 can initiate a link establishment request to the second chip 112. After the first chip 111 receives a link establishment response from the second chip 112, the first chip 111 and the second chip 112 establish a connection through the interconnection bus, and then initialize the interconnection bus.

[0142] S440, the first chip controls the register running state of the second chip according to the mode configuration information.

[0143] In some embodiments, the mode configuration information includes configuration information of multiple register running states of the second chip 112. That is, the mode configuration information of the second chip 112 can be mapped to the first chip 111, so that the control of the second chip 112 is opened to the first chip 111. As shown in FIG. 21, the first chip 111 can access the register in the second chip 112 through the interconnection bus.

[0144] S450, the first chip sends a mirror program to the second chip through the interconnection bus.

[0145] S460, the second chip loads and runs the mirror program.

[0146] In some embodiments, steps S450-S460 can not be performed. When the second chip 112 needs to implement a more complex function, the first chip 111 can send a mirror program in a flash memory to the second chip 112 through the high-speed bus, so as to save the flash memory.

[0147] The embodiments of the present application provide a chip system, a chip system operation method, an electronic device, and a readable storage medium. The first chip and the second chip load a local link connection configuration respectively. That is, the first chip automatically loads a first link connection configuration from the local, and the second chip automatically loads a second link connection configuration from the local. The process that the first chip and the second chip need to transmit the link connection configuration through a low-speed bus is omitted. After the first chip and the second chip load the local link connection configuration respectively, the first chip and the second chip can complete high-speed mode link establishment directly through the interconnection bus, and the start speed of the chip system is improved.

[0148] It should be understood that, in various embodiments of the present application, the size of the serial number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0149] Those skilled in the art can understand that the modules and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0150] In several embodiments provided in the present application, it should be understood that the disclosed apparatus, method and device can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the modules is only a logical function division, and actual implementation can have another division manner, for example, a plurality of modules or components can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed mutual ones can be indirect coupling or communication connection through some interfaces, devices or modules, and can be electrical, mechanical or other forms.

[0151] The modules described as separate components can or can not be physically separated, and the components shown as modules can or can not be physical modules, that is, they can be located in one device or distributed to multiple devices. Part or all of the modules can be selected according to actual needs to achieve the purpose of the present embodiment.

[0152] In addition, each functional module in each embodiment of the present application can be integrated in one device, or each module can exist physically alone, or two or more modules can be integrated in one device.

[0153] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by using a software program, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer readable storage medium can be any available medium that can be accessed by a computer or data storage device including one or more servers, data centers, etc. integrated with the medium. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0154] The above description is merely a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip system, characterized by The chip system comprises a first chip and a second chip, the first chip comprises first pins, the second chip comprises second pins, and the first pins are coupled with the second pins through an interconnection bus; the first chip stores a first link connection configuration, and the second chip stores a second link connection configuration; wherein, The first chip comprises a first loading module, which is configured to load the first link connection configuration when the first chip is started; The second chip comprises a second loading module, which is configured to load the second link connection configuration when the second chip is started; In response to the first link connection configuration and the second link connection configuration being loaded, a connection is established between the first chip and the second chip; the first link connection configuration and the second link connection configuration comprise transmission rate information of code streams between the first pins and the second pins.

2. The chip system according to claim 1, characterized by When the first chip and the second chip are combined and packaged, code streams are transmitted between the first pins and the second pins through single-ended signals; when the first chip and the second chip are separately packaged, code streams are transmitted between the first pins and the second pins through differential signals.

3. The chip system according to claim 1 or 2, characterized by The first chip stores mode configuration information of the second chip, the mode configuration information comprises configuration information of running states of a plurality of registers of the second chip, and the first loading module is further configured to load the mode configuration information when the first chip is started; The first chip further comprises a driving module, which is configured to control the running states of the registers of the second chip according to the mode configuration information.

4. The chip system according to claim 3, characterized by The first chip further comprises a first address mapping module, which is configured to map an address space of the second chip to an address space of the first chip.

5. The chip system according to claim 4, characterized by The driving module is further configured to access registers in the first chip through a bus of the first chip, and to access registers in the second chip through the interconnection bus according to the first address mapping module.

6. The chip system according to any one of claims 1 to 5, characterized in that The second chip comprises a second address mapping module, which is configured to map an address space of the first chip to an address space of the second chip.

7. A chip system operation method characterized by, The operation method is applied to a chip system, the chip system comprises a first chip and a second chip, the first chip comprises first pins, the second chip comprises second pins, and the first pins are coupled with the second pins through an interconnection bus; The first chip stores a first link connection configuration, and the second chip stores a second link connection configuration, and the operation method comprises: The first chip loads the first link connection configuration when being started; The second chip loads the second link connection configuration when being started; In response to the first link connection configuration and the second link connection configuration being loaded, a connection is established between the first chip and the second chip; the first link connection configuration and the second link connection configuration comprise transmission rate information of code streams between the first pins and the second pins.

8. The method of claim 7, wherein, The first chip stores mode configuration information of the second chip, and the mode configuration information includes configuration information of a plurality of register operating states of the second chip; and the operation method further includes: The first chip loads the mode configuration information when starting; The first chip controls the register operating state of the second chip according to the mode configuration information.

9. The method of claim 8, wherein, After the first chip establishes a connection with the second chip, the operation method further includes: The first chip accesses the register in the first chip through a bus of the first chip, and accesses the register in the second chip through the interconnection bus.

10. The method of operation according to any of claims 7-9, characterized by, After the first chip establishes a connection with the second chip, the operation method further includes: The first chip sends a mirror program to the second chip through the interconnection bus; The second chip loads and runs the mirror program.

11. An electronic device, comprising: The electronic device includes a PCB board and the chip system according to any one of claims 1-6, and the chip system is arranged on the PCB board.

12. A readable storage medium, characterized by, The readable storage medium stores computer executable instructions; and the computer executable instructions, after being executed, can implement the method according to any one of claims 7-10.

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