Optoelectronic package and method for manufacturing an optoelectronic package

Abstract

An optoelectronic package is provided, which comprises a semiconductor chip, a bonding connection and an encapsulation body. The semiconductor chip has a top edge. The semiconductor chip and the bonding connection are covered and laterally surrounded by the encapsulation body. In top view, the bonding connection crosses the top edge of the semiconductor chip. The bonding connection is prevented from being in direct contact with the top edge in virtue of a kink-like shape of the bonding connection and / or in virtue of a structure, wherein the structure is different from the encapsulation body and the structure is located at least in places between the bonding connection and the top edge of the semiconductor chip. Furthermore, a method for manufacturing an optoelectronic package is provided.

Description

[0001] Description

[0002] OPTOELECTRONIC PACKAGE AND METHOD FOR MANUFACTURING AN OPTOELECTRONIC PACKAGE

[0003] An optoelectronic package and a method for manufacturing an optoelectronic package are provided .

[0004] It is an obj ect to provide an ef ficient optoelectronic package . A further obj ect is to provide a method for manufacturing an ef ficient optoelectronic package .

[0005] These obj ects are solved by an optoelectronic package and a method for manufacturing an optoelectronic package according to the independent claims . Further embodiments of the optoelectronic package and the method for manufacturing an optoelectronic package are the subj ect matter of the further claims .

[0006] According to at least one embodiment of the optoelectronic package , the optoelectronic package comprises a semiconductor chip . The semiconductor chip can be an optoelectronic semiconductor chip . This can mean that the semiconductor chip is configured to generate or emit electromagnetic radiation . For instance , the semiconductor chip is or comprises a LED or a laser . Alternatively, the semiconductor chip can be configured to detect electromagnetic radiation . For instance , the semiconductor chip is or comprises a photodiode or a pho to trans is tor .

[0007] The semiconductor chip can comprise a semiconductor layer sequence with an active region configured to generate the electromagnetic radiation . For example , the semiconductor chip comprises an epi-layer . This can mean that semiconductor layers of the semiconductor layer sequence are grown epitaxially .

[0008] The optoelectronic package can comprise a package carrier . The package carrier can be a lead- frame , for example . The package carrier can comprise a main extension plane .

[0009] A lateral direction can be at least approximately parallel to the main extension plane of the package carrier or a main extension plane of the semiconductor chip . A vertical direction means a direction which is at least approximately perpendicular to the lateral direction, e . g . perpendicular to the main extension plane of the semiconductor chip .

[0010] It is also possible , that the semiconductor chip comprises a chip carrier . The chip carrier can be a substrate , for example a growth substrate . The semiconductor layer sequence of the semiconductor chip can be arranged on the chip carrier . For example , the semiconductor chip is arranged on the package carrier . The chip carrier can be arranged between the package carrier and the semiconductor layer sequence .

[0011] The semiconductor chip can comprise a top edge . For example , the top edge is located on the side of the semiconductor chip facing away from the package carrier . The top edge can be comprised by the chip carrier and / or by the semiconductor layer sequence . The top edge of the semiconductor chip can be a part of or can be in direct contact with a top side of the semiconductor chip . The top edge can be a line , for instance a straight line , connecting a lateral surface and a vertical surface , for instance the top side and one side surface , of the semiconductor chip . This line can connect two adj acent corners , for instance two upper adj acent corners , of the semiconductor chip .

[0012] For example , a wire bond pad is arranged on the top side of the semiconductor chip . The wire bond pad can be understood to be comprised by the semiconductor chip . This can mean that the wire bond pad is arranged on the semiconductor layer sequence or on the chip carrier of the semiconductor chip .

[0013] According to at least one embodiment of the optoelectronic package , the optoelectronic package comprises a bonding connection . The bonding connection can be a bonding wire or a ribbon bond . The bonding connection can be arranged in the optoelectronic package as a prefabricated component . In other words , the bonding connection may not be manufactured in the optoelectronic package . It is possible that the optoelectronic package comprises a plurality of bonding connections . The bonding connections can be bonding wires and / or ribbon bonds . In this case , for example , each bonding connection can be arranged in the optoelectronic package as prefabricated component . For instance , the bonding connection is configured or adapted to electrically contact the semiconductor chip . For example , the bonding connection, in particular a first end of the bonding connection is connected to the wire bond pad . A diameter of the bonding connection can be at most 50 pm, for example . It is possible , that the diameter of the bonding connection is within a range from 10 pm to 40 pm, for example between and including 20 pm and 30 pm .

[0014] According to at least one embodiment , the optoelectronic package comprises an encapsulation body . The encapsulation body can encapsulate the semiconductor chip and / or the bonding connection . For instance , the encapsulation body covers and / or surrounds the semiconductor chip and / or the bonding connection at least partially or entirely . The bonding connection and / or the semiconductor chip can be embedded in the encapsulation body .

[0015] The encapsulation body may be made of an electrically insulating molding material , for example of a plastic, a castable polymer such as epoxies or silicones . For example , the housing body is formed by compression molding or by film assisted molding . It is also possible , that the housing body is formed by dispensing . The molding material may contain filler particles .

[0016] According to at least one embodiment , the bonding connection crosses the top edge of the semiconductor chip, in top view . In other words , the top edge of the semiconductor chip and the bonding connection can overlap, in top view . This can mean that the first end of the bonding connection is connected to the wire bond pad on the top side of the semiconductor chip and, that a second end of the bonding connection is connected to the package carrier .

[0017] According to at least one embodiment , the bonding connection is prevented from being in direct contact with the top edge in virtue of a kink-like shape of the bonding connection .

[0018] According to at least one embodiment , the bonding connection is prevented from being in direct contact with the top edge in virtue of a structure di f ferent from the encapsulation body . For instance , the structure is located at least in places between the bonding connection and the top edge of the semiconductor chip . Due to the structure being arranged between the bonding connection and the top edge of the semiconductor chip, the bonding connection is ef ficiently prevented from being pushed towards the top edge of the semiconductor chip, e . g . during film assisted molding ( FAM) , trans fer molding and / or thermal cycling of a medium surrounding the bonding connection or the semiconductor chip . The structure , for example the material of the structure can comprise a small coef ficient of thermal expansion ( GTE ) , for instance a smaller coef ficient of thermal expansion compared to material of the encapsulation body . Such a structure can provide a good stability or resistivity during thermal cycling .

[0019] For example , the structure is applied to the semiconductor chip on wafer level . In other words , the structure can be applied to the semiconductor chip prior to attaching the semiconductor chip to the chip carrier, e . g . the substrate , or to the package .

[0020] According to at least one embodiment of the optoelectronic package , the optoelectronic package comprises a semiconductor chip, a bonding connection and an encapsulation body, wherein the semiconductor chip has a top edge , the semiconductor chip and the bonding connection are covered and laterally surrounded by the encapsulation body, and, in top view, the bonding connection crosses the top edge of the semiconductor chip . It is possible , that the bonding connection is prevented from being in direct contact with the top edge in virtue of a kink-like shape of the bonding connection and / or in virtue of a structure , wherein the structure is di f ferent from the encapsulation body and the structure is located at least in places between the bonding connection and the top edge of the semiconductor chip . Prevented from being in direct contact can also mean that the bonding connection is prevented from trans ferring electrical current to the top edge of the semiconductor chip or in general to the semiconductor chip in regions outside a wire bond pad .

[0021] An idea is to prevent a short circuit by preventing that the bonding connection is in direct contact with the semiconductor chip in a region outside the wire bond pad . Further, this can enable the application of low bonding connection loops , for instance of low bonding wire loops or low ribbon bond loops , e . g . bonding connections which protrude the semiconductor chip at most 80 pm, for instance at most 50 pm . Also , as the bonding connection should be covered and / or laterally surrounded by the encapsulation material , a si ze of the optoelectronic package can be decreased by applying low bonding connection loops .

[0022] According to at least one embodiment of the optoelectronic package , the structure is electrically insulating .

[0023] Due to the application of an insulating material between the bonding connection and the semiconductor chip, the risk for a short circuit can ef ficiently be reduced or eliminated . As the risk for short circuits is reduced or prevented, a low bonding connection loop can be ef ficiently reali zed . Due to the application of a low bonding connection loop, the semiconductor chip and / or the bonding connection can be ef ficiently encapsulated using a FAM process , for example a FAM process with a planar mold tool , or a casting process . Thereby, a small overall height of the optoelectronic package can be obtained . Due to the compatibility with a FAM process using a planar mold tool , no alignment of a structured mold tool is necessary, for example .

[0024] According to at least one embodiment of the optoelectronic package , the structure over-moulds the top edge of the semiconductor chip at least in places or only in places . In this way, the occurrence of a short-circuit between the bonding connection and the semiconductor chip can be reduced or prevented .

[0025] According to at least one embodiment of the optoelectronic package , the structure comprises an insulating thin film coating . For instance , the structure or the insulating thin film coating comprises SiCt or AI2O3. For example , the structure covers the bonding connection at least in places . For instance , the structure covers the side of the semiconductor chip on which the bonding connection is attached and / or the bonding connection .

[0026] According to at least one embodiment of the optoelectronic package , the structure is more rigid than the encapsulation body .

[0027] According to at least one embodiment of the optoelectronic package , the structure is electrically conductive .

[0028] According to at least one embodiment of the optoelectronic package , the bonding connection is in direct contact with the structure . This can enable a particularly thin optoelectronic package . "Thin" can thereby refer to an extension along a direction perpendicular to a main extension plane of the optoelectronic package . According to at least one embodiment , the top edge of the semiconductor chip is at least partially in direct contact with the encapsulation body . This can mean that the top edge is not completely covered by the structure . For instance , the structure covers the top edge only in vicinity of the bonding connection . The structure can be in direct contact with the top edge of the semiconductor chip .

[0029] The structure can cover only one part of the top edge and not the entire top edge . In top view, the part of the top edge covered by structure can overlap with the bonding connection . This covered part can be in direct contact with the structure and thus is not in direct contact with the encapsulation body . The top edge can comprise one or several subregions which are not covered by the structure . This one subregion or these subregions can be in direct contact with the encapsulation body .

[0030] According to at least one embodiment of the optoelectronic package , the kink-like shape is not located between two ends of the bonding connection, in top view .

[0031] According to at least one embodiment , the optoelectronic package comprises a conversion layer . The conversion layer can be arranged on the semiconductor chip, for instance on the top side of the semiconductor chip . For example , the conversion layer is spaced apart from the bonding connection along a lateral direction . The conversion layer is configured to convert electromagnetic radiation generated or emitted by the semiconductor chip .

[0032] The conversion layer can be arranged downstream of the semiconductor chip with respect to the generated or emitted electromagnetic radiation . For example , the conversion layer comprises a top side . For instance , the top side of the conversion layer faces away from the semiconductor chip . It is possible that the top side of the conversion layer forms an outcoupling surface of the optoelectronic package . In particular, electromagnetic radiation generated or emitted by the semiconductor chip can exit the optoelectronic package through the top side of the conversion layer .

[0033] For example , a thickness of the conversion layer is at most 150 pm, for instance at most 100 pm or at most 50 pm . It is possible , that the thickness of the conversion layer is between and including 10 pm and 70 pm, for example between 30 pm and 60 pm or, in particular, between 40 pm and 50 pm . For example , the bonding connection does not protrude the conversion layer along the vertical direction, in particular in a direction along which the conversion layer follows the semiconductor chip .

[0034] It is possible , that the conversion layer is in direct contact with the semiconductor chip, for instance with the semiconductor layer sequence of the semiconductor chip . Alternatively, the conversion layer can be attached to the semiconductor chip by an adhesive layer . In other words , the adhesive layer can be arranged between the semiconductor chip and the conversion layer .

[0035] Alternatively or additionally, layers other than the conversion layer can be arranged on the top side of the semiconductor chip . For example , a glass plate can be arranged on the top side of the semiconductor chip . The total thickness of these layer or layers may correspond to the thickness of the conversion layer described herein . Due to a conversion layer with a thickness of at most 100 pm, in particular of at most 50 pm, an optoelectronic package with improved brightness of the electromagnetic radiation can be obtained . Additionally, particularly thin optoelectronic packages can be manufactured . To ensure a stable electrical contacting of such optoelectronic packages , the bonding connections are preferably formed to not protrude the conversion layer and / or to be covered by the encapsulation body to at least a large extent .

[0036] According to at least one embodiment of the optoelectronic package , the conversion layer protrudes or is flush with a top part of the bonding connection along a vertical direction .

[0037] According to at least one embodiment , the structure is not in direct contact with the conversion layer . This can mean that at least a part of the structure , in particular a transparent fixation structure is not in direct contact with the conversion layer . An advantage of this embodiment is that an outcoupling of the electromagnetic radiation via the transparent conversion structure is reduced or prevented .

[0038] Furthermore , a method for manufacturing an optoelectronic package is provided . The method for manufacturing an optoelectronic package can be used to manufacture the optoelectronic package described herein . This means for instance that all features disclosed for the optoelectronic package are also disclosed for the method for manufacturing an optoelectronic package and vice-versa . According to at least one embodiment of the method for manufacturing an optoelectronic package , the method comprises providing a semiconductor chip with a top edge .

[0039] According to at least one embodiment , the method comprises connecting a bonding connection to the semiconductor chip . For instance , the bonding connection crosses the top edge of the semiconductor chip, in top view . The bonding connection can be configured to electrically contact the semiconductor chip . For instance , the bonding connection is arranged in the optoelectronic package as a prefabricated component . This can mean that the bonding connection is not manufactured in the optoelectronic package , for example .

[0040] According to at least one embodiment , the bonding connection is prevented from being in direct contact with the top edge of the semiconductor chip by applying the bonding connection having a kink-like shape and / or by forming a structure at least in places between the bonding connection and the top edge of the semiconductor chip . For example , the structure is formed to be arranged directly between the bonding connection and the top edge in the optoelectronic package . For instance , the bonding connection and / or the top edge are in direct contact with the structure . It is also possible , that , in the assembled optoelectronic package , the structure is arranged between, for instance directly between, the top edge and the encapsulation body .

[0041] According to at least one embodiment , the method comprises applying an encapsulation body to cover and laterally surround the semiconductor chip and the bonding connection . According to at least one embodiment , the method for manufacturing an optoelectronic package comprises providing a semiconductor chip with a top edge , connecting a bonding connection to the semiconductor chip, wherein the bonding connection crosses the top edge of the semiconductor chip, in top view, preventing the bonding connection from being in direct contact with the top edge of the semiconductor chip by applying the bonding connection having a kink-like shape and / or by forming a structure at least in places between the bonding connection and the top edge of the semiconductor chip, and applying an encapsulation body to cover and laterally surround the semiconductor chip and the bonding connection .

[0042] For example , the steps can be performed in the given order . It is , however, possible to apply the structure or at least a part of the structure prior to connecting the bonding connection to the semiconductor chip .

[0043] According to at least one embodiment , the structure is formed on a top side of the semiconductor chip prior to connecting the bonding connection with the semiconductor chip, in particular with the wire bond pad of the semiconductor chip . An advantage of this embodiment is that the structure can be easily applied . Additionally, the probability of a short circuit can be further reduced as the top edge of the semiconductor chip is already protected by the structure at the time the bonding connection is connected to the semiconductor chip .

[0044] According to at least one embodiment , the structure is applied between the bonding connection and the top edge of the semiconductor chip via thin film coating or via capillary forces .

[0045] According to at least one embodiment , the method comprises compressing the bonding connection, for instance with a mold tool , wherein the bonding connection moves laterally in virtue of the kink-like shape .

[0046] For instance , upon connecting the bonding connection with the semiconductor chip, the bonding connection is arranged to protrude the semiconductor chip or a conversion layer arranged on the semiconductor chip along the vertical direction . For example , the bonding connection protrudes the semiconductor chip or the conversion layer at most 100 pm, for example at most 50 pm or at most 40 pm . For instance , the bonding connection protrudes the semiconductor chip or the conversion layer between 30 pm and 40 pm, inclusive . Subsequently, the bonding connection can be deformed by pushing or pressing the bonding connection for instance with a mold tool such that the bonding connection does not protrude the conversion layer along the vertical direction .

[0047] The method is particularly suitable for manufacturing the optoelectronic package described in this disclosure . Features described in connection with the optoelectronic package may therefore also be used for the method, and vice versa .

[0048] Further advantages and advantageous designs and further implementations of the optoelectronic package and the method for manufacturing an optoelectronic package will become apparent from the following exemplary embodiments , which are described below in association with the figures . Figure 1 shows a top view of an optoelectronic package according to an exemplary embodiment .

[0049] Figures 2 , 3 , 4 , 5 , 6 , 7 , 8 and 9 show schematic views of optoelectronic packages according to exemplary embodiments .

[0050] Figures 10 , 11 , 12 and 13 show schematic side views of steps in a method for manufacturing an optoelectronic package according to an exemplary embodiment and an optoelectronic package according to a further exemplary embodiment .

[0051] Figures 14 , 15 and 16 show schematic views of the principle of the method for manufacturing an optoelectronic package according to the exemplary embodiment shown for instance in Figures 10 to 13 .

[0052] Figures 17 and 18 show schematic side views of optoelectronic packages according to comparative examples .

[0053] Identical , similar, or equivalent elements are marked with the same reference signs in the figures . The figures and the proportions of the elements represented in the figures among each other are not to be considered as true to scale . Rather, individual elements may be oversi zed for better representability and / or comprehensibility . Identical or ef fectively identical components and parts might be described only with respect to the figures where they occur first . Their description is not necessarily repeated in successive figures .

[0054] Figure 1 shows a top view of an optoelectronic package 1 according to an exemplary embodiment . The optoelectronic package 1 comprises a semiconductor chip 2 . The semiconductor chip 2 comprises a top side 23 and a top edge 24 . The optoelectronic package 1 further comprises a bonding connection 4 . The bonding connection 4 crosses the top edge 24 of the semiconductor chip 2 . The optoelectronic package 1 may comprise an encapsulation body 3 , not shown in Figure 1 but for instance in Figures 7 to 9 and 13 . In this case , the semiconductor chip 2 and the bonding connection 4 can be covered and / or laterally surrounded by the encapsulation body 3 .

[0055] For instance , the bonding connection 4 is prevented from being in direct contact with the top edge 24 in virtue of a structure 6 . The structure 6 is di f ferent from the encapsulation body 3 . In particular, this can mean that the material of the structure 6 is di f ferent from the material of the encapsulation body 3 . However, it is also possible , that the material of the structure 6 and the material of the encapsulation body 3 are the same or at least approximately the same . The structure 6 is arranged on the top side 23 of the semiconductor chip 2 . The structure 6 is located at least in places between the bonding connection 4 and the top edge 24 of the semiconductor chip 2 . The structure 6 can comprise or be formed of a spacer 61 . The spacer 61 can be arranged close to the top edge 24 of the semiconductor chip 2 . For example , the spacer 61 is in direct contact with the top edge 24 of the semiconductor chip 2 . It is possible , however, that the structure 6 is spaced apart from the top edge 24 . The structure 6 , for example the spacer 61 , can be electrically insulating .

[0056] For instance , the structure 6 or the spacer 61 comprises a polymer, e . g . thermoplastic material . For example , the spacer 61 is a thermoplastic bead which can be directly attached to the semiconductor chip 2 by pressing the thermoplastic bead onto the semiconductor chip 2, for example onto a hot semiconductor chip 2. A suitable temperature for attaching the spacer can be between and including 100°C and 280°C, for instance, in particular for LEDs, between and including 160°C and 280°C. In case the structure 6 is directly mounted onto the semiconductor chip 2, bleed of an adhesive is prevented. Alternatively or additionally, the structure 6 comprises, for example, a thermosetting polymer, thermoset, or an elastomer. The structure 6 can be hardened with the complete optoelectronic package. It is also possible that the structure 6 is only hardened partially initially. Subsequently, the structure 6 can then be hardened together with the encapsulation body 3, for example at a temperature between and including 100°C and 200°C.

[0057] For example, particularly in the embodiments shown in Figures 1 to 4, in which the structure 6 does not over-mould the top edge 24 of the semiconductor chip 2, the structure 6 can be applied to the semiconductor chip 2 on wafer level, for instance prior or after singulation of the semiconductor chips 2. In this case, the semiconductor chip 2 with the structure 6 can be arranged in the optoelectronic package 1.

[0058] For example, a wire bond pad 25 is arranged on the top side 23 of the semiconductor chip 2. The structure 6 or the spacer 61 can be arranged at least in places between the wire bond pad 25 and the bonding connection 4. For instance, the structure 6 or the spacer 61 is arranged between the bonding connection 4 and the top edge 24 in top view of the optoelectronic package 1. It is possible, that the spacer 61 is in direct contact with the bonding connection 4. However, it is also possible, that the encapsulation body 3 is partially located between the spacer 61 and the bonding connection 4 .

[0059] For instance , shown here , a conversion layer 5 is arranged on the semiconductor chip 2 , in particular on the top side 23 of the semiconductor chip 2 . For example , the conversion layer 5 is arranged spaced apart from the bonding connection 4 along a lateral direction x, y . The conversion layer 5 can comprise a thickness of at most 50 pm . It is possible , that the structure 6 , in particular the spacer 61 , is not in direct contact with the conversion layer 5 .

[0060] Figure 2 shows a schematic side view of the optoelectronic package 1 shown in Figure 1 . In side view, the conversion layer 5 can protrude or can be flush with the bonding connection 4 along a vertical direction z . Only for the sake of clarity, a conversion layer 5 is not shown explicitly in Figure 2 . The optoelectronic package 1 comprises a package carrier 11 . The package carrier 11 can be a lead- frame , for example . For example , the package carrier 11 comprises a further wire bond pad 10 . The further wire bond pad 10 is for instance part of the package carrier 11 . The bonding connection 4 can electrically connect the further bond pad 10 with the wire bond pad 25 .

[0061] As shown in Figure 2 , the carrier 11 comprises two separated subregions which can be assigned to two di f ferent electrical polarities of the optoelectronic package 1 . The semiconductor chip 2 or the optoelectronic package 1 can be electrically connected to an electric source by the two separated subregions of the carrier 11 . Figure 3 shows a schematic side view of an optoelectronic package 1 according to a further exemplary embodiment . The structure 6 , for instance the spacer 61 , is arranged at a side of the wire bond pad 25 close to the top edge 24 of the semiconductor chip 2 . The optoelectronic package 1 shown here di f fers from the optoelectronic package 1 shown in Figure 2 in that the structure 6 , for example the spacer 61 , can be electrically conductive . For instance , the structure 6 is or comprises a wire bump or a nailhead . It is possible , that the structure 6 protrudes the wire bond pad 25 along the lateral direction x, y . In case the structure 6 is electrically conductive , the structure 6 is preferably not in direct contact with a semiconductor layer sequence 21 of the semiconductor chip 2 . The structure 6 is for instance spaced apart from the top edge 24 .

[0062] Figures 4 to 6 show schematic side views of optoelectronic packages 1 according to further exemplary embodiments . The embodiments of the optoelectronic packages 1 di f fer from each other in the shape or application method of the structure 6 , e . g . the spacer 61 . Preferably, the structures 6 shown in Figures 4 to 6 are electrically insulating to prevent a short circuit of the optoelectronic package 1 . For instance , the dashed circle highlights the region of interest in which a short circuit can be prevented . The structure 6 can be in direct contact with the top edge 24 , for instance with one part of the top edge 24 .

[0063] The exemplary embodiment of Figure 4 di f fers from the exemplary embodiment shown in Figure 2 in that the structure

[0064] 6 does not cover the wire bond pad 25 . This can mean that the structure 6 is arranged closer to the top edge 24 of the semiconductor chip 2 than in the exemplary embodiment shown in Figure 2 .

[0065] In the exemplary embodiments shown in Figures 5 and 6 , the structure 6 over-moulds the top edge 24 of the semiconductor chip 2 . The structure 6 shown in Figure 6 may be applied using a laser induced forward trans fer process ( LI FT-process ) or an electrically induced forward trans fer process . For example , the structure 6 is applied onto the semiconductor chip 2 from a side of the semiconductor chip 2 facing away from the package carrier 11 . The structure 6 thereby protrudes the semiconductor chip 2 , for example the top edge 24 along the lateral direction x, y . Subsequently, the part of the structure 6 protruding the semiconductor chip 2 folds over the top edge 24 to over-mould the top edge 24 of the semiconductor chip 2 . Thus , it is possible to over-mould the top edge 24 exactly and particularly small . Particularly small can thereby mean that an extension of the structure 6 in a direction away from the semiconductor chip 2 , in particular on the top side 23 of the semiconductor chip 2 is small , e . g . at most 40 pm, at most 20 pm, at most 10 pm or at mo st 5 pm .

[0066] The structures 6 or spacers 61 shown in Figures 1 to 6 are preferably arranged on the top side 23 of the semiconductor chip 2 , e . g . of the semiconductor layer sequence 21 or of the wire bond pad 25 , prior to attaching the bonding connection 4 to the wire bond pad 25 . In this case , the spacer 61 is applied via direct mounting, molding, gluing, laser printing, 3D printing or via a LI FT-process , for example . Alternatively, in case the structure 6 is applied to the semiconductor chip 2 on wafer level , the spacer 61 can be applied using a lithographic process . Then, the bonding connection 4 can be guided directly or with only a small distance above the structure 6 or spacer 61 during the process of arranging the bonding connection 4 . Preferably, the spacer 61 is arranged outside a heat af fected zone of the bonding connection 4 . This can mean that the spacer 61 is arranged in a ductile region of the bonding connection 4 . As the structure 6 or the spacer 61 is arranged in the ductile region of the bonding connection 4 , it is possible to form the bonding connection 4 to be in direct contact with the structure 6 or spacer 61 also during attaching the bonding connection 4 to the semiconductor chip 2 .

[0067] Here and in the following, the heat af fected zone of the bonding connection 4 can refer to portions of the bonding connection 4 , which are more brittle than remaining portions of the bonding connection 4 . The bonding connection 4 comprises two ends 41 , 42 . For example , the bonding connection 4 is more brittle close to or at the two ends 41 , 42 of the bonding connection 4 due to a soldering process . For instance , the bonding connection 4 is soldered to the wire bond pads 10 , 25 .

[0068] Alternatively or additionally, it is also possible to apply the structure 6 after connecting the bonding connection 4 to the semiconductor chip 2 , in particular to the wire bond pad 25 of the semiconductor chip 2 . For instance , the structure 6 can be or can comprise a coating 62 or a thin film coating 62 , for example an inorganic thin film coating 62 ( see Figure 11 ) . In this case , the structure 6 can be applied by vapour phase deposition, e . g . by plasma-enhanced chemical vapour deposition ( PECVD) or by atomic layer deposition (ALD) . It is also possible to form the coating 62 by sputtering or spraying .

[0069] The structure 6 might be arranged to cover the bonding connection 4 as well as exposed regions of the semiconductor chip 2 and / or the conversion layer 5. For instance, no mask is required if the structure 6 is applied to all exposed regions within the optoelectronic package 1. In this case, preferably, the material of the structure 6 is translucent, transparent and / or insulating. For instance, the structure 6 comprises, is formed of or consists of a thin film coating. For example, the structure 6 or the thin film coating comprises or is made of silicon dioxide (SiCy) . It is also possible, that the structure 6 comprises or consists of AI2O3, HfCy, Ta2Os or any other insulating material.

[0070] Alternatively or additionally, the structure 6 might be applied via local dispensing. This can mean that the material of the structure 6 is applied close to, e.g. in proximity of or in direct contact with, the bonding connection 4 and / or the semiconductor chip 2. The material of the structure 6 may be applied in liquid form. Due to capillary forces, the material of the structure 6 can creep between the bonding connection 4 and the semiconductor chip 2, e.g. the top side

[0071] 23 of the semiconductor chip 2. Afterwards, the material of the structure 6 can be cured or hardened to form the structure 6 between the bonding connection 4 and the top edge

[0072] 24 of the semiconductor chip 2. For example, the material of the structure 6 exhibits a low volume shrinkage during curing. This can prevent the formation of mechanical stress between the semiconductor chip 2 and the bonding connection 4. The structure 6 may be insulating. For instance, the structure 6 comprises a polysiloxane, for example "SolSil". The encapsulation body 3 , not shown, can be applied after applying the structure 6 and / or after attaching the bonding connection 4 to the semiconductor chip 2 .

[0073] Figure 7 shows a schematic side view of an optoelectronic package 1 according to another exemplary embodiment . In the exemplary embodiment shown here , the bonding connection 4 is prevented from being in direct contact with the top edge 24 of the semiconductor chip 2 in virtue of the structure 6 . The structure 6 is di f ferent from an encapsulation body 3 . In other words , the material of the structure 6 is di f ferent from the material of the encapsulation body 3 .

[0074] The optoelectronic package 1 shown here comprises a cavity 12 . For instance , the package carrier 11 comprises side walls I la which laterally confine the cavity 12 . The side walls I la can be formed as integral parts of a housing body . The housing body can laterally surround the package carrier 11 . In lateral directions , di f ferent subregions of the package carrier 11 can be completely surrounded by the housing body and thus are mechanically connected to each other by the housing body .

[0075] The conversion layer 5 is arranged on the top side 23 of the semiconductor chip 2 . The conversion layer 5 can comprise a top side 51 , which may form an out-coupling surface of the optoelectronic package 1 .

[0076] The cavity 12 can be filled with the encapsulation body 3 . This can mean that the encapsulation body 3 covers the semiconductor chip 2 , the bonding connection 4 , the conversion layer 5 , the package carrier 11 , the side walls Ila and / or the structure 6 at least partially. The top side 51 of the conversion layer 5 can be free from the encapsulation body 3.

[0077] The structure 6 comprises or consists of a fixation structure 63. The structure 6, in particular the fixation structure 63, can cover the wire bond pad 25, a wire bump 26 and / or the bonding connection 4 at least in the heat affected zone of the bonding connection 4. For example, shown here, the structure 6 completely covers the bonding connection 4 in a region in which the bonding connection 4 overlaps the semiconductor chip 2 along the vertical direction z. The structure 6 or the fixation structure 63 can be arranged spaced apart from the conversion layer 5.

[0078] The structure 6, for instance the fixation structure 63 comprises or consist of silicone or epoxy, for example of highly filled silicone or highly filled epoxy. The fixation structure 63 is electrically insulating. For instance, the structure 6, e.g. the fixation structure 63, is more rigid than the encapsulation body 3. In this way, the fixation structure 63 can protect the bonding connection 4 at least within the heat affected zone / s from mechanical stress and reduce or prevent an elastoplastic deformation of the bonding connection 4 in the heat affected zone / s.

[0079] The bonding connection 4 comprises two ends 41, 42. The first end 41 of the bonding connection 4 is attached to the semiconductor chip 2 via the wire bond pad 25. The second end 42 of the bonding connection 4 is connected to the package carrier 11 or the further wire bond pad 10. For instance, shown here, a second heat affected zone of the bonding connection 4 is arranged at the second end 42 of the bonding connection 4. A further fixation structure 64 can be applied to the second heat affected zone, e.g. to the second end 42 of the bonding connection 4. The further fixation structure 64 can cover, for instance completely cover, the further wire bump 46. The further fixation structure 64 can comprise the same features as the fixation structure 63. In particular, a material of the further fixation structure 64 and a material of the fixation structure 63 can be the same or differ, for instance lightly differ from each other.

[0080] The exemplary embodiment of the optoelectronic package 1 shown in Figure 8 differs from the exemplary embodiment of the optoelectronic package 1 of Figure 7 in that the structure 6 or fixation structure 63 is in direct contact with the conversion layer 5. Additionally, the structure 6 or fixation structure 63 over-moulds the top edge 24 of the semiconductor chip 2, at least or only in the region of the bonding connection 4.

[0081] For instance, the structure 6 or the fixation structure 63 is at least partially non-transparent. This can mean that the structure 6 or the fixation structure 63 is at least partially opaque. For example, the structure 6 or the fixation structure 63 is reflective, e.g. white reflective. This can prevent or at least reduce that electromagnetic radiation is coupled into the fixation structure 63.

[0082] The fixation structure 63 can enable the usage of thinner bonding connections 4, e.g. bonding connections with a diameter smaller than 30 pm, for example smaller than or equal to 20 pm or 10 pm. Thinner bonding connections are typically less stiff. Thus, without the fixation structure 63 they might be easily deformed. The optoelectronic package 1 according to the exemplary embodiment shown in Figure 9 di f fers from the optoelectronic package 1 shown in Figure 8 in that the fixation structure 63 covers a larger portion of the bonding connection 4 . The bonding connection 4 comprises a more complex shape . In particular, bonding connection 4 is arranged closer to the package carrier 11 than in the exemplary embodiment shown in Figure 8 . In this case , the bonding connection 4 can be fixated by the fixation structure 63 at least partially in the ductile region of the bonding connection 4 , e . g . laterally of the semiconductor chip 2 . The bonding connection 4 can be prevented from being in contact with a side surface of the semiconductor chip 2 , which runs at least approximately perpendicular to the top side 23 of the semiconductor chip 2 . The bonding connection 4 may be partially at least approximately parallel to the side surface of the semiconductor chip 2 .

[0083] Figures 10 , 11 , 12 and 13 show schematic side views of steps in a method for manufacturing an optoelectronic package 1 according to an exemplary embodiment and an optoelectronic package 1 according to another exemplary embodiment .

[0084] Figure 10 shows a first step in a method for manufacturing an optoelectronic package 1 . The optoelectronic package 1 comprises a semiconductor chip 2 with a chip carrier 22 and a semiconductor layer sequence 21 arranged on the chip carrier 22 . The wire bond pad 25 is arranged on the chip carrier 22 laterally to the semiconductor layer sequence 21 . The conversion layer 5 is arranged on the semiconductor chip 2 , in particular on the side of the semiconductor layer sequence 21 facing away from the chip carrier 22 . The conversion layer 5 is directly applied to the semiconductor layer sequence 21 . Alternatively, an adhesive layer, not shown, can be arranged between the conversion layer 5 and the semiconductor layer sequence 21 or the semiconductor chip 2 . For example , the semiconductor layer sequence can be electrically contacted via through-vias , not shown . For instance , the through-vias can extend through the chip carrier and / or the semiconductor layer sequence . In particular, the anode and the cathode of the semiconductor chip 2 are electrically contacted via the wire bond pad 25 and a die bond pad, e . g . comprised by the package carrier 11 .

[0085] In the step shown in Figure 10 , the bonding connection 4 is attached or connected to the semiconductor chip 2 . In other words , the first end 41 of the bonding connection 4 is connected with the wire bond pad 25 . After the wire bump 26 , the bonding connection 4 can initially run obliquely to a main extension plane of the semiconductor chip 2 , for instance of the chip carrier 22 . In other words , the bonding connection 4 can form an angle of less than 90 ° with the top side 23 of the semiconductor chip 2 . Alternatively, not shown, the bonding connection 4 can include an angle of approximately 90 ° with the main extension plane of the semiconductor chip 2 . This can enlarge a gap between the bonding connection 4 and the semiconductor chip 2 in a region in which the bonding connection 4 and the chip carrier 22 overlap, in top view . In this exemplary embodiment , the top edge 24 of the semiconductor chip 2 can be comprised by the chip carrier 22 . The bonding connection 4 is applied in a kink-like shape 43 . The bonding connection 4 is attached to the semiconductor chip 2 such that the bonding connection 4 protrudes the semiconductor chip 2 , in particular the chip carrier 21 and / or the semiconductor layer sequence 21 along the vertical direction z . Additionally, the bonding connection 4 can protrude the conversion layer 5 along the vertical direction z . For instance , the bonding connection 4 protrudes the conversion layer 5 by a height h, which can be between and including 10 pm and 60 pm, for example between and including 30 pm and 40 pm .

[0086] The bonding connection 4 is prevented from being in direct contact with the top edge 24 in virtue of a kink-like shape 43 of the bonding connection 4 . The kink-like shape 43 can be or can resemble a " J"-shape , for instance a 3-dimensional " J"-shape . The bonding connection 4 comprises at least one kink 43 . In top view, the kink 43 of the kink-like shape 43 is not located between the two ends 41 , 42 , namely the first end 41 and the second end 42 of the bonding connection 4 . It is also possible , that the kink 43 or kink-like shape 43 does not overlap with the second end 42 of the bonding connection 4 , in top view . For instance , the kink 43 is arranged on the side of the further wire bond pad 10 opposing the semiconductor chip 2 . However, other shapes of the bonding connection 4 which provide a mechanical flexibility and stability and / or are configured to be laterally moved due to a kink under application of a force , e . g . during film assisted molding, are also possible . For instance , the direction of the movement under force occurs at least partially along a direction perpendicular to the direction of the applied force due to the kink-like shape 43 .

[0087] Figure 11 shows another step in a method for manufacturing an optoelectronic package 1 according to an exemplary embodiment . In this step, a coating 62 is applied to the bonding connection 4 . For instance , the coating 62 completely covers all surfaces of the bonding connection 4 , which are exposed after connecting the bonding connection 4 to the semiconductor chip 2 . The coating 62 is electrically insulating . For instance , the coating 62 is deposited onto the bonding connection 4 , the wire bond pad 25 and / or the chip carrier 22 , e . g . by PECVD . In this case , the conversion layer 5 can be covered by a mask, not shown, during deposition of the coating 62 . Thus , in this case , the structure 6 can be formed by the coating 62 . Alternatively, the coating 62 can cover the conversion layer 5 partially or completely . Then, preferably, the coating 62 is transparent . Due to the large gap between the bonding connection 4 and the semiconductor chip 2 obtained by forming the bonding connection 4 to protrude the semiconductor chip 2 and / or the conversion layer 5 , the coating 62 can be ef ficiently deposited .

[0088] Figure 12 shows a step of the method for manuf cturing an optoelectronic package 1 in which the bonding connection 4 is pressed towards the package carrier 11 during a film assisted molding process ( FAM) , by a mold tool 9 . In other words , the bonding connection 4 is compressed using a mold tool 9 . A mold film 91 can be arranged on the side of the mold tool 9 facing the optoelectronic package 1 . The mold tool 9 can be a flat mold tool 9 . In other words , the side of the mold tool 9 or of the mold film 91 facing the optoelectronic package 1 is planar . During pressing of the bonding connection 4 towards the package carrier 11 , the bonding connection 4 moves laterally in virtue of the kink-like shape 43 .

[0089] In a method step shown in Figure 13 the encapsulation body 3 is applied to cover and laterally surround the semiconductor chip 2 and the bonding connection 4 . For instance , in places no material of the encapsulation body 3 is arranged between the bonding connection 4 and the mold tool 9 or the mold film 91 . This can mean that the bonding connection 4 is partially in direct contact with the mold tool 9 or the mold film 91 . Alternatively, the encapsulation body 3 is arranged between the bonding connection 4 and the mold tool 9 . In this case , a thickness of the encapsulation body 3 between the bonding connection 4 and the mold tool 9 can be at least 0 . 1 pm, for example at least 0 . 3 pm and at most 1 pm or at most 0 . 5 pm .

[0090] Afterwards , not shown, the mold tool 9 and / or the mold film 91 can be removed .

[0091] For instance , the dashed circle in Figure 12 and 13 indicates the region of the top edge 24 , in which a short circuit can be prevented .

[0092] Figures 14 , 15 and 16 show schematic views illustrating some principles of the method for manufacturing an optoelectronic package 1 according to the exemplary embodiment shown in Figures 10 to 13 . Figure 14 shows the application of planar film assisted molding ( FAM) for an optoelectronic package 1 according to a comparative example , e . g . shown in Figure 17 or in Figure 18 . Thereby, the bonding connection 4 does not comprise a kink-like shape and does not move laterally during FAM . In absence of a structure between the bonding connection and the top edge , this can cause a short-circuit . Figure 16 displays the vertical movement of the bonding connection 4 of a bonding connection 4 with a kink-like shape 43 , not shown . In this case , the bonding connection 4 is not brought into direct contact with the top edge 24 of the semiconductor chip 2 . Figure 15 shows a top view of an optoelectronic package 1 in which the bonding connection 4 crosses the top edge of the semiconductor chip 2 . The conversion layer 5 is arranged on the semiconductor chip 2 . The bonding connection 4 does not overlap with or cross the conversion layer 5 , in top view .

[0093] The kink-like shape 43 of the bonding connection 4 can be combined with the exemplary embodiments of the optoelectronic packages 1 shown in Figures 1 to 9 . It is also possible to apply the fixation structure 63 , the spacer 61 , the coating 62 and / or the further fixation structure 64 in the exemplary embodiments in which the respective structure 6 is not explicitly described . In other words , the kink-like shape 43 of the bonding connection 4 and / or the structure 6 including the fixation structure 63 , the spacer 61 , the further fixation structure 64 and / or the coating 62 can be combined with the exemplary embodiments of the optoelectronic packages 1 of Figures 1 to 16 .

[0094] Figure 17 shows a schematic side view of an optoelectronic package 1 according to a comparative example . Here , the bonding connection 4 is not prevented from being in direct contact with the top edge 24 of the semiconductor chip 2 in virtue of a kink-like shape of the bonding connection 4 and / or in virtue of a structure . Thus , disadvantageously, the bonding connection 4 can be in direct contact with the top edge 24 of the semiconductor chip 2 , for example during thermal cycling, during curing of the encapsulation body 3 and / or during the application of forces , for instance during FAM, onto the optoelectronic package 1 , which leads to a short circuit within the optoelectronic package 1 . This is highlighted by the dashed circle shown in Figure 17 .

[0095] Figure 18 shows an optoelectronic package 1 according to a further comparative example . The optoelectronic package 1 shown here is similar to the optoelectronic package shown in Figure 7. However, the bonding connection 4 is not prevented from being in direct contact with the top edge 24 of the semiconductor chip 2 by a kink-like shape of the bonding connection 4 or by a structure arranged between the bonding connection 4 and the top edge 24. Thus, within the region outlined by the dashed circle, the bonding connection 4 can contact, e.g. electrically contact the top edge 24, causing a short circuit.

[0096] This patent application claims the priority of German patent application 102024111028.7, the disclosure of which is hereby incorporated by reference.

[0097] The invention described herein is not limited by the description given with reference to the embodiments. Rather, the invention encompasses any novel feature and any combination of features, including in particular any combination of features in the claims, even if this feature or this combination is not itself explicitly indicated in the claims or embodiments.

[0098] References

[0099] 1 Optoelectronic package

[0100] 11 package carrier

[0101] I la side wall

[0102] 12 cavity

[0103] 2 semiconductor chip

[0104] 21 semiconductor layer sequence

[0105] 22 chip carrier

[0106] 23 top side

[0107] 24 top edge

[0108] 25 wire bond pad

[0109] 26 wire bump

[0110] 3 encapsulation body

[0111] 4 bonding connection

[0112] 41 first end of the bonding connection

[0113] 42 second end of the bonding connection

[0114] 43 kink

[0115] 46 further wire bump

[0116] 5 conversion layer

[0117] 51 top side

[0118] 6 structure

[0119] 61 spacer

[0120] 62 coating

[0121] 63 fixation structure

[0122] 64 further fixation structure

[0123] 9 mold tool

[0124] 91 mold film

[0125] 10 further wire bond pad x, y lateral direction z vertical direction

Claims

Claims1. Optoelectronic package (1) comprising: an optoelectronic semiconductor chip (2) ; a bonding connection (4) ; and an encapsulation body (3) , wherein- the optoelectronic semiconductor chip (2) has a top edge (24) ,- the optoelectronic semiconductor chip (2) and the bonding connection (4) are covered and laterally surrounded by the encapsulation body (3) ,- in top view, the bonding connection (4) crosses the top edge (24) of the optoelectronic semiconductor chip (2) , and- the bonding connection (4) is prevented from being in direct contact with the top edge (24) in virtue of a kinklike shape (43) of the bonding connection (4) and / or in virtue of a structure (6) , wherein the structure (6) is different from the encapsulation body (3) and the structure (6) is located at least in places between the bonding connection (4) and the top edge (24) of the optoelectronic semiconductor chip (2) .

2. The optoelectronic package (1) according to claim 1, wherein the bonding connection (4) is prevented from being in direct contact with the top edge (24) of the optoelectronic semiconductor chip (2) in virtue of the structure (6) , wherein the structure (6) is different from the encapsulation body (3) and the structure (6) is electrically insulating.

3. The optoelectronic package (1) according to one of the previous claims, wherein the structure (6) over-moulds the top edge (24) of the optoelectronic semiconductor chip (2) at least in places.

4. The optoelectronic package (1) according to one of the previous claims, wherein the structure (6) comprises an insulating thin film coating and covers the bonding connection (4) at least in places.

5. The optoelectronic package (1) according to one of the previous claims, wherein the structure (6) is more rigid than the encapsulation body (3) .

6. The optoelectronic package (1) according to claim 1, wherein the structure (6) is electrically conductive.

7. The optoelectronic package (1) according to one of the previous claims, wherein the bonding connection (4) is in direct contact with the structure (6) .

8. The optoelectronic package (1) according to one of the previous claims, wherein the top edge (24) is at least partially in direct contact with the encapsulation body (3) .

9. The optoelectronic package (1) according to one of the previous claims, wherein the bonding connection (4) is prevented from being in direct contact with the top edge (24) in virtue of a kink-like shape (43) of the bonding connection (4) and wherein in top view, the kink-like shape (43) is not located between two ends (41, 42) of the bonding connection (4) .

10. The optoelectronic package (1) according to one of the previous claims, comprising a conversion layer (5) arranged on the optoelectronic semiconductor chip (2) , wherein- the conversion layer (5) is arranged spaced apart from the bonding connection (4) along a lateral direction (x, y) , and- a thickness of the conversion layer (5) is at most 50 pm.

11. The optoelectronic package (1) according to the previous claim, wherein the conversion layer (5) protrudes or is flush with a top part of the bonding connection (4) along a vertical direction (z) .

12. The optoelectronic package (1) according to one of the claims 9 to 11, wherein the structure (6) is not in direct contact with the conversion layer (5) .

13. A method for manufacturing an optoelectronic package (1) , the method comprising:- providing an optoelectronic semiconductor chip (2) with a top edge (24 ) ,- connecting a bonding connection (4) to the optoelectronic semiconductor chip (2) , wherein- the bonding connection (4) crosses the top edge (24) of the optoelectronic semiconductor chip (2) , in top view,- the bonding connection (4) is prevented from being in direct contact with the top edge (24) of the optoelectronic semiconductor chip (2) by applying the bonding connection (4) having a kink-like shape (43) and / or by forming a structure (6) at least in places between the bonding connection (4) and the top edge (24) of the optoelectronic semiconductor chip( 2 ) , and- applying an encapsulation body (3) to cover and laterally surround the optoelectronic semiconductor chip (2) and the bonding connection (4) .

14. The method according to the previous claim, wherein the bonding connection (4) is prevented from being in direct contact with the top edge (24) of the optoelectronicsemiconductor chip (2) by forming the structure (6) at least in places between the bonding connection (4) and the top edge (24) of the optoelectronic semiconductor chip (2) , and the structure (6) is formed on a top side (23) of the optoelectronic semiconductor chip (2) prior to connecting the bonding connection (4) with the optoelectronic semiconductor chip ( 2 ) .

15. The method according to claim 13, wherein the structure (6) is applied between the bonding connection (4) and the top edge (24) of the optoelectronic semiconductor chip (2) via thin film coating or via capillary forces.

16. The method according to one of the claims 13 to 15, wherein the bonding connection (4) is prevented from being in direct contact with the top edge (24) of the optoelectronic semiconductor chip (2) by applying the bonding connection (4) in a kink-like shape (43) , the method further comprising:- compressing the bonding connection (4) , wherein the bonding connection (4) moves laterally in virtue of the kink-like shape ( 43 ) .

Images