Method for producing a nanochannel

Abstract

The invention relates to a method for producing a nanochannel (200), comprising the following steps: a) depositing a nanochannel sacrificial layer (3) on a substrate (1) by means of an ALD process, wherein the nanochannel sacrificial layer defines the later channel height at least at one point; b) depositing a first cover layer (4) on the nanochannel sacrificial layer (3); c) at least partially structuring and / or etching the nanochannel sacrificial layer (3) and the first cover layer (4) such that a first exposed region (10) is formed; d) at least partially etching the now exposed nanochannel sacrificial layer (3) at an etching rate of < 100nm / min, preferably <10nm / min, and particularly preferably <5nm / min and yet more preferably <2nm / min, such that an underetched second exposed region (20) is formed which defines the channel width; e) depositing a second cover layer (5) on the first cover layer (4) and the first exposed region (10) such that the second exposed region (20) is sealed and forms a nanochannel (200).

Description

[0001] Description

[0002] title

[0003] Method for producing a nanochannel

[0004] The present invention relates to a method for producing a nanochannel, a nanochannel and a cartridge comprising a sequencing chip with at least one such according to the preamble of the independent patent claims.

[0005] State of the art

[0006] Nanochannels can be used for DNA sequencing, as can be seen, for example, in US 7670770 B2.

[0007] WO 2017 / 087908 A1 discloses a method for fabricating a nanochannel device. It describes the etching of a sacrificial layer to form the nanochannel.

[0008] Such nanochannels are characterized by a width and height of less than 100 nm. Their length is much greater than their diameter and can range from microns to millimeters. Such channels can be used to guide a DNA strand through them and analyze the DNA strand.

[0009] Disclosure of the invention According to the invention, a method for producing a nanochannel, a nanochannel and a cartridge comprising a sequencing chip with at least one such according to the characterizing features of the independent patent claims are provided.

[0010] The inventive method for producing a nanochannel comprises the following steps: a) Depositing a nanochannel sacrificial layer by means of an atomic layer deposition (ALD) process on a substrate, which defines the later channel height at least at one point. b) Depositing a first cover layer onto the nanochannel sacrificial layer c) At least partially structuring and / or etching the nanochannel sacrificial layer and the first cover layer to create a first exposed region. Structuring is a general term that can create shape-giving structures by adding, modifying, or removing material. The term etching refers to a specific type of structuring in which material that is initially physically or chemically present is removed again.d) At least partially etching the now exposed nanochannel sacrificial layer with an etching rate < 100 nm / min, preferably < 10 nm / min, particularly preferably < 5 nm / min and even more preferably < 2 nm / min, so that an under-etched second exposed region is created which defines the channel width e) Depositing a second cover layer onto the first cover layer and the first exposed region so that the second exposed region is sealed and forms a nanochannel.

[0011] The method according to the invention results in particular in the following advantages. The use of an ALD process for the deposition of the nanochannel sacrificial layer enables precise control of the thickness of the nanochannel sacrificial layer, as this process offers excellent thickness control and homogeneity of the nanochannel sacrificial layer. The thickness of the layer—and thus the height of the nanochannel—is very well controllable using the ALD process, since, in particular, one atomic monolayer is deposited after the other. Another advantage is that the ALD process is cost-effective.

[0012] Furthermore, compared to a thermal SiO2 sacrificial layer, for example, it is possible to deposit the ALD sacrificial layer over all other types of layers, such as metals.

[0013] Another important dimension besides the height of the nanochannel is its width, which is determined by a time-controlled undercutting process. Etching is performed at slow etching rates of <100 nm / min, preferably <10 nm / min, particularly preferably <5 nm / min, and even more preferably <2 nm / min, as this allows the undercutting process to be precisely controlled and reliable etching dimensions in the nanometer range to be achieved. The slow etching rates allow for very targeted and precise undercutting, allowing the width of the nanochannel to be manufactured with great accuracy. The low etching rate also allows for easier removal of etched products.

[0014] Further advantageous embodiments of the present invention are the subject of the subclaims.

[0015] In an advantageous embodiment, the substrate is a wafer.

[0016] In an additional or alternative advantageous embodiment, at least one passivation layer and / or at least one metal layer is applied to the substrate. The nanochannel sacrificial layer deposited by the ALD process can be deposited on all other types of layers, especially metals. This allows the method according to the invention to offer considerable flexibility.

[0017] If at least one metal layer is applied to the substrate, in an advantageous embodiment this is designed as at least one electrode or comprises at least one such electrode. The electrode is made of platinum or titanium nitride, for example. At least one electrode within and / or adjacent to, in particular underneath, the nanochannel is advantageous, for example, to transport a DNA strand through the nanochannel, for example by means of electrophoresis, and / or for the electrical readout and identification of the respective base pairs of the DNA strand. For nanochannel-based DNA sequencing devices, the diameter of the channel and the possibility of directly contacting the liquid in the nanochannel using electrodes, in particular metal electrodes, are crucial. Another advantage is that a passivation layer can be applied directly to the substrate.

[0018] In a further advantageous embodiment, the nanochannel sacrificial layer is formed from aluminum oxide (AlOx), silicon dioxide (SiO2), or silicon nitride (SiN). These materials offer the advantage that they can be deposited using ALD and can be selectively etched.

[0019] The nanochannel sacrificial layer is preferably deposited with a height of 5–100 nm, and especially with a height of 5–20 nm. The height at which the nanochannel sacrificial layer is deposited defines the final height of the nanochannel. The lower the height of the nanochannel sacrificial layer, the more predictable the position of the DNA. The advantage of a final nanochannel height of 5–20 nm is that at this height, the probability of two DNA strands lying on top of each other while being pulled through the nanochannel is greatly reduced.

[0020] Furthermore, in one embodiment, it is advantageous if the first cover layer in step b) is deposited by means of an atomic layer deposition (ALD), a plasma enhanced chemical vapor deposition (PECVD) or sputtering process.

[0021] The first capping layer in step b) is, for example, aluminum oxide (AlOx), silicon dioxide (SiO2), and / or silicon nitride (SiN). The material used depends on the respective material of the nanochannel sacrificial layer and the process used to undercut the nanochannel sacrificial layer.

[0022] In a particularly advantageous embodiment, the first cover layer in step b) comprises a plurality of layers which, in particular, have different voltage gradients. Different voltage gradients can lead to the first cover layer bending downwards in this region, for example, after the underlying nanochannel sacrificial layer has been undercut. For the nanochannel, this means that, on the one hand, in the region in which the first cover layer bends downwards, it has a smaller, in particular continuously decreasing, height. The width-to-height aspect ratio of the nanochannel is therefore increased. A large part of the opening remaining after the undercut is covered by the downwardly bent first cover layer, which in turn minimizes the coverage of this opening with the second cover layer, in particular at the location where, in one embodiment, an electrode is arranged.

[0023] The voltage gradient can also be increased by varying the deposition conditions of the first capping layer during the deposition of a single one of the multiple layers, for example by varying the process parameters such as temperature, pressure or radio frequency (RF) bias.

[0024] In an advantageous embodiment, the first capping layer comprises silicon dioxide (SiCh) and / or silicon nitride (SiN), particularly when the nanochannel sacrificial layer is formed from AlOx. Different voltages of the layers of the first capping layer can also be achieved with the same material by varying the process parameters.

[0025] Furthermore, the at least partial structuring and / or etching in step c) is advantageously carried out using a standard lithography process, in particular using a dry etching technique such as ion beam etching or reactive ion etching. Alternatively, only a portion of the nanochannel sacrificial layer can be structured and / or etched, or alternatively, an adjacent layer, such as the further layer, can also be at least partially structured and / or etched.

[0026] In a particularly advantageous embodiment, an isotropic etchant is used in step d) to undercut the exposed sacrificial nanochannel layer. The isotropic etchant is, for example, diluted tetramethylammonium hydroxide (TMAH), xenon difluoride (XeF2), or hydrogen fluoride (HF).

[0027] In an advantageous embodiment, the etchant in step d) does not attack the first covering layer, so that the etching can be carried out very precisely.

[0028] In an alternative advantageous embodiment, the selectivity between the sacrificial layer and the first cover layer is 10:1 or higher, so that precise and successful etching is also ensured.

[0029] In this way, a second exposed area is created that defines the later nanochannel width.

[0030] The under-etching step is advantageously carried out until the second exposed region has a width of 5-200nm, preferably 5-100nm and particularly preferably 5-50nm.

[0031] Furthermore, the second covering layer is deposited in step e), for example by means of PECVD, sputtering or evaporation.

[0032] In a particularly advantageous embodiment, the nanochannel is manufactured such that the width-to-height ratio of the nanochannel is > factor 2, and preferably > / = factor 2.5. This achieves reliable coverage of the nanochannel by the second cover layer without covering an underlying layer, in particular a metal electrode layer.

[0033] Furthermore, in an advantageous embodiment, the second capping layer is formed from silicon dioxide (SiCh) and / or silicon nitride (SiN) and / or aluminum oxide (AlOx). The material of the second capping layer can be selected more or less freely, but subsequent etching steps and, if applicable, the stress state of the wafer should be taken into account.

[0034] A further advantageous embodiment provides that, in a further step f), access openings are introduced into the nanochannel, in particular by etching through the second cover layer. This can be done, for example, by ion beam etching or reactive ion etching with a carbon-fluorine (CF)- or chlorine (Cl)-based etching chemistry.

[0035] The access openings make it possible to fill the channel with liquid and thus, for example, with DNA. This allows the nanochannel to be used, for example, for DNA sequencing. Furthermore, the present invention relates to a nanochannel produced according to the method of the invention, as well as a cartridge comprising a sequencing chip with at least one nanochannel.

[0036] Short description of the drawing

[0037] Advantageous embodiments of the present invention are illustrated in the drawing and explained in more detail in the following description. It shows:

[0038] Figure 1a: a schematic cross-sectional view of a substrate with a further layer

[0039] Figure 1 b: a schematic cross-sectional view of a first

[0040] Method step according to a first embodiment of the present invention,

[0041] Figure 1 c: a schematic cross-sectional view of a second

[0042] Method step according to a first embodiment of the present invention,

[0043] Figure 1d: a schematic cross-sectional view of a third

[0044] Method step according to a first embodiment of the present invention,

[0045] Figure 1 e: a schematic cross-sectional view of a fourth

[0046] Method step according to a first embodiment of the present invention,

[0047] Figure 1f: a schematic cross-sectional view of a fifth

[0048] Process step according to a first embodiment of the present invention, Figure 2a: a schematic cross-sectional view of a third

[0049] Method step according to a second embodiment of the present invention,

[0050] Figure 2b: a schematic cross-sectional view of a process step in which the cover layers bend downwards according to a second embodiment of the present invention,

[0051] Figure 2c: a schematic cross-sectional view of a fifth

[0052] Method step according to a second embodiment of the present invention, and

[0053] Figure 3: a schematic representation of a flow diagram of a

[0054] Embodiment of the method according to the invention.

[0055] Embodiments of the invention

[0056] Figures 1a - 1f describe, in particular successive, process steps according to a first embodiment of the process according to the invention, wherein a nanochannel with a height of 20 nm and a width of 50 nm is produced.

[0057] Figure 1a shows a cross-sectional view of a substrate 1 with an additional layer 2. The substrate 1 is formed, for example, as a silicon wafer. The additional layer 2 is, for example, a thermal SiO2 layer.

[0058] Figure 1b shows a first process step, in which a nanochannel sacrificial layer 3 made of AlQx, for example, with a thickness of 20 nm, is deposited onto the further layer 2 using an ALD process. The nanochannel sacrificial layer 3 defines the subsequent height of the nanochannel. Figure 1c shows a second process step of the inventive method, in which a first cover layer 4 made of SiCh, for example with a thickness of 70 nm, is deposited onto the nanochannel sacrificial layer 3 using PECVD.

[0059] Figure 1d shows a third method step, namely a subsequent structuring and / or etching of the first cover layer 4 and the nanochannel sacrificial layer 3, so that a first exposed region 10 is created which allows an etchant direct access to the nanochannel sacrificial layer.

[0060] Structuring and / or etching is carried out using a standard lithography process such as a dry etching technique.

[0061] Figure 1 e) shows a fourth method step, wherein an in particular isotropic etchant, for example diluted TMAH, attacks the exposed nanochannel sacrificial layer 3, so that at least a partial under-etching of the nanochannel sacrificial layer 3 occurs. This creates an under-etched second exposed region 20, which defines the channel width. The etchant does not attack the first cover layer 4 or the selectivity between the nanochannel sacrificial layer 3 and the first cover layer is high enough, in particular 10:1 or higher. In order to be able to reliably control the under-etching, it is important that the time-controlled etching takes place very slowly, ie at an etching rate of < 100 nm / min, preferably < 10 nm / min and particularly preferably < 5 nm / min and even more preferably < 2 nm / min.

[0062] The under-etching is carried out until the second exposed region 20 has a width of 50 nm and is then stopped, for example, in time.

[0063] Figure 1f) shows a fifth method step, wherein a second cover layer 5 is deposited onto the first cover layer 4 and the first exposed region 10, so that the second exposed region 20 is sealed and forms a nanochannel 200. The nanochannel here has dimensions of 20 nm high x 50 nm wide. The second cover layer 5 is SiO2 and is deposited, for example, by PECVD, sputtering, or vapor deposition with a thickness of 300 nm. Figures 2a-2c describe method steps according to a second embodiment of the method according to the invention, in which the first cover layer 4 has two layers 4a, 4b. In contrast to the first embodiment, no further layer 2 is applied to the substrate 1, but rather the nanochannel sacrificial layer 3.

[0064] Figure 2a shows the third method step according to Figure 1d)—namely, the structuring and / or etching of the first cover layer 4 and the nanochannel sacrificial layer 3—in the second embodiment. A nanochannel sacrificial layer 3 and two layers 4a, 4b of a first cover layer 4 with different stress gradients are applied to a substrate 1. The different stress gradients are represented by the arrows 8a of the first layer 4a and the arrows 8b of the second layer 4b of the first cover layer 4, which point in different directions.

[0065] Figure 2b shows the layer structure according to Figure 2a after the fourth step of at least partially undercutting the sacrificial nanochannel layer 3 has taken place. The different stress gradients of the two layers 4a, 4b of the first cover layer 4 lead, for example, to the first cover layer 4, 4a, 4b bending downward in the area of ​​the undercut. As a result, a large part of the opening remaining after the undercut is covered by the bent-down first cover layer 4, 4a, 4b. For the resulting nanochannel 200, this means that, on the one hand, it has a smaller, in particular continuously decreasing, height in the area in which the first cover layer 4, 4a, 4b bends downward. The width-to-height aspect ratio of the nanochannel 200 is thus increased.

[0066] Figure 2c shows the layer structure according to Figure 2b, wherein in a fifth step a second cover layer 5 is deposited onto the second layer 4b of the first cover layer 4 and the first exposed region 10, so that a nanochannel 200 is formed which is sealed by the second cover layer 5.

[0067] Figure 3 shows a flow diagram of an embodiment of the method for producing a nanochannel 200. In a first method step 50, a nanochannel sacrificial layer 3 is deposited onto a substrate 1 and optionally onto a further layer, as shown, for example, in Figure 1b). In a second method step 51, a first cover layer 4, which optionally has two different layers 4a, 4b, is deposited onto the nanochannel sacrificial layer 3, as shown, for example, in Figure 1c). If the first cover layer 4 comprises two layers 4a, 4b, the deposition conditions for at least one of these layers can also be varied during the deposition, for example by varying the temperature or the pressure during the deposition.In a third method step 52, the first cover layer 4, 4a, 4b and the nanochannel sacrificial layer 3 are at least partially structured and / or etched, as shown, for example, in Figure 1d) or 2a), so that a first exposed region 10 is created that allows an etchant direct access to the nanochannel sacrificial layer 3. Furthermore, an adjacent layer, such as the further layer 2, can also be at least partially structured and / or etched.

[0068] In a fourth method step 53, the nanochannel sacrificial layer 3 is at least partially undercut, as shown, for example, in Figure 1e). In a fifth method step 54, a second cover layer 5 is deposited onto the first cover layer 4, 4b and the first exposed region 10, so that a nanochannel 200 is formed, as shown, for example, in Figure 1f) or 2c).

[0069] Optionally and not shown in Fig. 3, access openings can be introduced into the nanochannel 200 in a further method step, in particular by etching through the second cover layer 4, 4a, 4b.

Claims

Claims 1 . Method for producing a nanochannel (200) with the following steps: a) depositing a nanochannel sacrificial layer (3) using an ALD process on a substrate (1), which defines the later nanochannel height at least at one location; b) depositing a first cover layer (4) on the nanochannel sacrificial layer (3); c) at least partially structuring and / or etching the nanochannel sacrificial layer (3) and the first cover layer (4) so ​​that a first exposed region (10) is created; d) at least partially etching the now exposed nanochannel sacrificial layer (3) at an etching rate of <100 nm / min, preferably <10 nm / min, particularly preferably <5 nm / min, and even more preferably <2 nm / min, so that an under-etched second exposed region (20) is created, which defines the channel width; e) depositing a second cover layer (5) on the first cover layer (4) and the first exposed region (10);so that the second exposed region (20) is sealed and forms a nanochannel (200)., 2. Method according to claim 1, wherein at least one further layer (2), in particular a passivation layer and / or a metal layer, is applied to the substrate (1) 3. The method according to claim 2, wherein the at least one metal layer (2) is formed as at least one electrode or at least comprises such an electrode.

4. Method according to one of the preceding claims, wherein the nanochannel sacrificial layer (3) is formed from aluminum oxide (AlOx), silicon dioxide (SiO2) or silicon nitride (SiN).

5. Method according to one of the preceding claims, wherein the nanochannel sacrificial layer (3) is deposited with a height of 5-100nm, and preferably of 5-20nm.

6. Method according to one of the preceding claims, wherein the first covering layer (4) in step b) is an aluminum oxide (AlOx), silicon dioxide (SiCh) and / or silicon nitride (SiN).

7. Method according to one of the preceding claims, wherein the first cover layer (4) in step b) comprises a plurality of layers (4a, 4b) which in particular have different stress gradients.

8. The method according to claim 7, wherein the first cover layer (4a, 4b) comprises silicon dioxide (SiCh) and silicon nitride (SiN), in particular when the nanochannel sacrificial layer (3) is formed from AlOx.

9. Method according to one of the preceding claims, wherein in step d) an isotropic etchant is used for undercutting.

10. The method according to any one of the preceding claims, wherein in step d) the etchant does not attack the first capping layer (4, 4a, 4b) or wherein the selectivity between the nanochannel sacrificial layer (3) and the first capping layer (4, 4a, 4b) is 10:1 or higher.

11. Method according to one of the preceding claims, wherein the under-etching of the exposed nanochannel sacrificial layer (3) in step d) is carried out until the second exposed region (20) has a width of 5-200nm, preferably of 5-100nm and particularly preferably of 5-50nm.

12. Method according to one of the preceding claims, wherein the second covering layer (5) is made of silicon dioxide (SiO2) and / or silicon nitride (SiN).

13. Method according to one of the preceding claims, wherein the nanochannel (200) is produced such that the aspect ratio of width to height of the nanochannel (200) is > factor 2, and preferably >= factor 2.

5.

14. Method according to one of the preceding claims, wherein in a further Step f) access openings are introduced into the nanochannel (200), in particular by etching through the second cover layer (5).

15. Sequencing chip with a nanochannel (200) manufactured by a method according to one of claims 1-14.

16. A cartridge comprising a sequencing chip according to claim 15.

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