Method for adjusting an integrated circuit of a vehicle

Abstract

The invention relates to a computer-implemented method for, in particular cross-functionally, adjusting, in particular programming, an integrated circuit, in particular a system-on-a-chip (SoC) or a system-in-package, of a vehicle, in particular a software-defined vehicle (SDV), the method involving: controlling the integrated circuit, in particular the SoC or the SiP, via an interface, in particular a single interface, in particular a software library, wherein the interface, in particular the software library, is functionally independent and / or functionally decoupled from a standard architecture, in particular a semiconductor-specific standard architecture, of the integrated circuit, in particular the SoC or the SiP.

Description

[0001] Method for adapting an integrated circuit of a vehicle

[0002] The present invention relates to a computer-implemented method for adapting, in particular programming, an integrated circuit (IC), in particular a system-on-chip (SoC) or a system-in-package (SiP), a vehicle, in particular a software-defined vehicle (SDV), in particular across functions.

[0003] The software or software components in an SDV are often closely linked to the specific or standardized hardware, e.g., the chips used / installed therein, especially semiconductor chips, and can be specifically tailored or adapted to these. Expanding the chip and / or its functions may require extensive reworking of the existing software, for example, to support new functions and / or hardware components, especially to support them essentially completely. This is not only complex but also expensive.

[0004] In addition, SDV software architectures can be rigid or inflexible, offering little scope for integrating new features. This can complicate chip expansion, as adapting the software architecture may be necessary to support the new hardware components. Furthermore, some SDVs use proprietary software solutions that cannot be easily extended without access, especially direct access, to the source code and / or support from the manufacturer.

[0005] In addition to the challenges of semiconductor components and / or software integration, the different programming approaches of the chip, in particular the semiconductor chip, and / or its components can also complicate the expansion of chips in current SDVs. For example, some chip components can be programmed differently than other chip components, whereby the corresponding programming languages ​​and the further steps to the finished program can be completely or fundamentally different. A developer or programmer for a specific chip component is not always able to program another chip component, and vice versa. This means that expanding the chip may require not only an adaptation of the software but also a change in the programming paradigms and tools.This can further increase the complexity and effort required to expand chips in SDVs and pose additional obstacles to the integration of new hardware components. Known solutions, such as common libraries or software libraries, are inadequate because they often only include functions for one specific chip component or functions for another specific chip component. This forces developers to either rely on separate libraries to program the various chips, which can lead to inconsistencies and complexity, or to develop customized solutions, which requires time and resources. Another option would be to learn the appropriate programming skills / programming language, which also requires additional time and resources.In any case, these limited libraries make the integration and use of chips in SDVs difficult, as they do not provide comprehensive support for the multitude of different chip components.

[0006] It is an object of the present invention to overcome the disadvantages of the known prior art and in particular to provide an improved computer-implemented method for adapting, in particular programming, an integrated circuit (IC), in particular a system-on-chip (SoC) or a system-in-package (SiP), a vehicle, in particular a software-defined vehicle (SDV).

[0007] The problem is solved by the features of the independent claims. The dependent claims describe preferred embodiments. Further aspects, advantages, and features emerge from the dependent claims, the description, and the accompanying drawings.

[0008] One aspect of the invention relates to a computer-implemented method for adapting, in particular programming, an integrated circuit (IC), in particular a system-on-chip (SoC) or a system-in-package (SiP), a vehicle, in particular a software-defined vehicle (SDV), comprising:

[0009] Controlling the integrated circuit, in particular the SoC or the SiP, via one, in particular a single, interface, in particular a software library, wherein the interface, in particular the software library, is functionally independent and / or functionally decoupled from a, in particular semiconductor-specific, standard architecture of the integrated circuit, in particular the SoC or the SiP.One aspect of the invention relates to a computer-implemented method, in particular according to one or more of the invention aspects and / or embodiments described herein, for adapting, in particular programming, an integrated circuit (IC), in particular a system-on-chip (SoC) or a system-in-package (SiP), a vehicle, in particular a software-defined vehicle (SDV), wherein the SoC or the SiP comprises at least one central processing unit (CPU) and at least one field-programmable gate array (FPGA), in particular an embedded FPGA (E-FPGA), the method comprising:

[0010] Controlling the integrated circuit, in particular the SoC or the SiP, via one, in particular single, interface, in particular a software library, wherein the integrated circuit, in particular the SoC or the SiP, in particular the CPU and the FPGA, can be controlled cross-functionally by means of the, in particular single, interface, in particular the software library.

[0011] One aspect of the invention relates to a computer-implemented method, in particular according to one or more of the invention aspects and / or embodiments described herein, for adapting, in particular programming, an integrated circuit (IC), in particular a system-on-chip (SoC) or a system-in-package (SiP), a vehicle, in particular a software-defined vehicle (SDV), wherein the SoC or the SiP comprises at least one central processing unit (CPU) and at least one field-programmable gate array (FPGA), in particular an embedded FPGA (E-FPGA), wherein the method comprises:

[0012] Controlling the integrated circuit, in particular the SoC or the SiP, via one, in particular single, interface, in particular a software library, wherein the control is carried out, at least partially, using a central processing unit (CPU) control part and / or a field programmable gate array (FPGA) control part of the in particular single, interface, in particular the software library.

[0013] One aspect of the invention relates to a computer-implemented method, in particular according to one or more of the invention aspects and / or embodiments described herein, for adapting, in particular programming, an integrated circuit (IC), in particular a system-on-chip (SoC) or a system-in-package (SiP), of a vehicle, in particular a software-defined vehicle (SDV), wherein the integrated circuit, in particular the SoC or the SiP, comprises at least one central processing unit (CPU) and at least one field-programmable gate array (FPGA), in particular an embedded FPGA (E-FPGA), wherein the method comprises: controlling the integrated circuit, in particular the SoC or the SiP, via one, in particular single, interface, in particular a software library, wherein the integrated circuit, in particular the SoC or the SiP, in particular the CPU and the FPGA, by means of the, in particular single, interface,in particular the software library is dynamic, updatable and / or expandable in its functions.

[0014] One aspect of the invention relates to a computer program product comprising instructions which, when the program is executed by a computer, cause the computer to carry out the method according to the invention according to one or more of the aspects and / or embodiments described herein.

[0015] One aspect of the invention relates to a computer-readable storage medium comprising instructions which, when executed by a computer, cause the computer to carry out the method according to the invention according to one or more of the aspects and / or embodiments described herein.

[0016] One aspect of the invention relates to an integrated circuit (IC), in particular a system-on-chip (SoC) or a system-in-package (SiP), for a software-defined vehicle (SDV), comprising:

[0017] - at least one field-programmable gate array (FPGA), in particular an embedded FPGA (E-FPGA), and

[0018] - at least one central processing unit (CPU), wherein the integrated circuit, in particular the SoC or the SiP, is controllable and / or is controlled by means of the method according to one or more of the aspects of the invention and / or embodiments described herein and / or is configured to carry out the method according to one or more of the aspects of the invention and / or embodiments or steps thereof described herein.

[0019] One aspect of the invention relates to a software-defined vehicle (SDV), comprising: an integrated circuit, in particular a SoC or a SiP, in particular according to one or more of the invention aspects and / or embodiments described herein, and an interface, in particular a single interface, in particular a software library, for controlling the integrated circuit, in particular the SoC or the SiP, using the method according to one or more of the invention aspects and / or embodiments described herein. "Adapting" can be understood as controlling, configuring, changing, and / or modifying a functionality of the integrated circuit or the SoC or the SiP, for example, to fulfill specific tasks and / or functions for the SDV; for example, this can mean adapting the integrated circuit, in particular the SoC or the SiP, according to the specific requirements and / or functions of the SDV."Programming" can be understood as the creation of instructions, commands and / or algorithms that can adapt the functionality of the integrated circuit, SoC or SiP, for example, writing software code or at the software level.

[0020] An "integrated circuit" ("IC") can be understood as a circuit, in particular an electronic one, for example, comprising one or more, in particular electronic, components and / or devices (these terms can be interchangeable). These, in particular electronic, components can be applied, for example, to a single plate, for example a printed circuit board (PCB), and / or a die, wherein the plate can be made of at least one semiconductor material or at least one semiconductor-like material. These, in particular electronic, components can also be applied, for example, to multiple plates, for example printed circuit boards (PCBs), and / or dies, for example at least two. The IC can also be referred to as a chip, semiconductor chip, and / or semiconductor-based chip.Alternatively or additionally, the plate(s) may be referred to as chip area. These components may include transistors, diodes, resistors, capacitors, and / or other / similar components that may be interconnected to perform a specific function.

[0021] The integrated circuit (IC) can be or include a system-on-chip (SoC) and / or a system-in-package (SiP). The terms SoC and SiP can also be used interchangeably herein. In particular, at a point in the description where, for example, explicit reference is made to "SoC," a reference can automatically also be made to a "SiP," for example, implicitly, even if the suffix "SiP" is not explicitly mentioned / written, and vice versa. The same can also apply to "IC."

[0022] A "system-on-chip," "system-on-a-chip," or SoC can be a type of integrated circuit that, for example, implements a plurality of functions of a particularly programmable electronic system, in particular on one, particularly single, plate or one, particularly single die. In addition to the conventional circuit components, an SoC can also include one or more of the following components: central processing unit (CPU), processor cores, or cores, in particular RISC-V cores, preferably a multi-core RISC-V, memory, e.g., non-volatile memory, RAM, program memory, pins (e.g., in a specific number), hardware logic, input and output interfaces, and / or other integrated functions or components, which can, for example, be applied to a single chip or circuit board.

[0023] An SoC can be viewed as a particularly essentially complete computer system on a chip, in particular with different functionalities, such as including functionalities of a computer system, e.g. evaluating data, etc. The SoC can also comprise a field-programmable gate array (FPGA), in particular an embedded FPGA (E-FPGA). An FPGA can be understood as an integrated circuit that allows digital circuits and / or logic functions to be programmed or adapted as required. In contrast to conventional integrated circuits, which, for example, have a fixed function, an FPGA can perform various tasks by programming the internal logic blocks and / or connections. An FPGA is typically programmed using hardware description languages ​​such as VHDL (VHSIC Hardware Description Language) or Verilog.After a developer has created the code, it can be converted into a bitstream, which can then be loaded into the FPGA to implement, for example, the functionality assigned to the code. An E-FPGA (Embedded Field-Programmable Gate Array) is a special type of FPGA that is embedded within a larger integrated system, such as a chip or a System-on-Chip (SoC). E-FPGAs offer the flexibility and adaptability of an FPGA within the integrated system. A specific and particularly non-limiting example of an SoC is a PolarFire® SoC, which includes a CPU or CPU part and an FPGA or FPGA part.

[0024] A "system-in-package" can be a type of integrated circuit in which, for example, several individual integrated circuits (ICs), in particular electronic, devices and / or components and / or possibly even other components such as MEMS (microelectromechanical systems) are combined in a single package, for example on different dies. A SiP can perform a variety of different functions or even comprise entire subsystems in a compact package. SiPs can provide improved performance, smaller form factors, and / or higher integration compared to traditional circuit designs because they allow different components and technologies to be combined in a single package. SiPs can also be cheaper and / or have greater variance, for example in terms of CPU cores, FPGA size, memory size, etc. The SiP can therefore also contain a CPU and an FPGA (oralso include one or more of the components mentioned in relation to the SoC. In this regard, the statements and / or the advantages, particularly technical ones, may apply correspondingly / analogously to the SoC.

[0025] The components of the SoC or SiP can be connected via communication systems such as internal and / or external buses, bus systems, and / or bus interfaces. Non-exhaustive examples of external buses can include CAN (e.g., with at least 1 GbE "Gigabit Ethernet"), Ethernet, I2C, SPI, PCI, PCIe, and derivatives, which can connect to the SoC / SiP, e.g., via its peripherals. Non-exhaustive examples of internal buses can include Advanced Extensible Interface (AXI) and / or Advanced Burst Interface (ABI), which are designed for higher or very high bandwidth, flexibility, and / or scalability, and / or can support features such as burst transfers or pipelining. ABI can also ensure fast or efficient data transmission, e.g., between different IP blocks and / or components within the IC.

[0026] A "semiconductor-specific, standard architecture" of the integrated circuit, in particular of the SoC or SiP, can describe a structure, construction, element arrangement, and / or architecture that is standardized, e.g., depending on the manufacturer of the IC, in particular of the SoC or SiP, and refers to the typical structure and / or organization of the components and / or functions of the IC, in particular of the SoC or SiP. For example, different manufacturers may pursue different approaches in the design and / or implementation of the IC, in particular of the SoC or SiP, which may lead to differences in the standard architecture. For example, one manufacturer may place particular emphasis on energy-efficient processors, while another manufacturer may focus more on integrating high-performance graphics processors.The standard architecture of an IC, in particular of an SoC or a SiP, can evolve / change over time, for example to meet changing requirements and / or technologies. New versions of ICs, in particular SoCs / SiPs, can, for example, have improved functions, faster processors, larger memory, additional interfaces and / or other improvements that make them better suited for new applications and / or areas of use. However, the interface described here, in particular the software library, is not fixed or restricted / limited to a specific hardware or standard architecture. If, for example, a supplier's or manufacturer's supply chain is interrupted or disrupted, a chip from another semiconductor manufacturer can be installed essentially without any adjustments to the software.Even when switching from one performance class to the next or from one semiconductor generation to the next, the semiconductors can be compatible, and thanks to the interface described herein, in particular the software library, no adaptations, particularly software adaptations, are necessary. The interface described herein, in particular the software library, can define requirements for the standard architecture, in particular semiconductor-specific ones, or the standardized semiconductors in order to utilize, use, and / or deploy them, e.g., in a zone-specific and / or zone-selective manner, as described herein.

[0027] A "software-defined vehicle" ("SDV") can be a vehicle whose functionality and / or behavior can be substantially defined, regulated, and / or controlled by software, allowing a variety of functions to be implemented and / or controlled without, for example, requiring physical hardware changes. This may be in contrast to traditional vehicles, for example, where control is primarily provided by hardware components such as specialized control units.

[0028] A Software-Defined Vehicle (SDV) can have multiple, particularly zonal, Electronic Control Units (ECUs) (also called electronic control units), to which specific areas, regions, and / or sections (also called "zones") of the vehicle can be assigned, e.g., drive, braking, steering, safety, infotainment, and / or other. The ECUs can be responsible for controlling and / or managing the functions or components, devices, devices, and / or systems in these areas. Each, particularly zonal, ECU can assume specific tasks and / or functions within its assigned (sub)area, such as controlling drive systems, chassis components, safety functions, infotainment systems, etc. Each ECU can have its own operating system ("Operating System", OS). The IC or SoC / SiP described herein can be integrated into or comprised within one or more ECUs of the SDV.Each ECU can contain a hardware component (IC / SoC / SiP and, if applicable, an interface), an operating system (OS) with driver(s) for resource management (such as computing time, memory, and communication channels), and an application that can be divided into one or more different services. These services can also communicate with services of other ECUs.

[0029] A software-defined vehicle (SDV) may also contain a central control unit. This central control unit can serve as a central control and / or coordination center for the entire vehicle and / or coordinate or control the communication and data exchange between the various, particularly zonal, ECUs and other relevant systems and components in the vehicle.

[0030] Software-Defined Vehicles (SDVs) can be equipped with a variety of sensors, actuators, and / or communication technologies that enable the vehicle to communicate with its environment and / or collect and / or exchange data, e.g., during real-time operation. This data can be sent, e.g., to a cloud platform where it can be analyzed and / or processed. Communication with the cloud can enable manufacturers, e.g., to continuously collect data to improve the vehicle and / or its functions. Via, e.g., over-the-air updates, these improvements can then be sent directly back to the vehicles and implemented without the vehicles having to be physically brought into the workshop.

[0031] "Controlling" can be understood as addressing or using; communicating, connecting or interacting with; and / or accessing certain, particularly electronic, components of, for example, the integrated circuit or the SoC / SiP and / or at least one of its functions. Alternatively or additionally, it can also be understood as initiating, triggering, initiating, influencing, operating, controlling, regulating, and / or controlling, e.g., at least one function of the IC / SoC / SiP.

[0032] An "interface" can refer to an interaction point or location that can be configured to enable communication, connection, and / or exchange of information, data, instructions, inputs, and / or commands, e.g., with the integrated circuit or SoC / SiP. An interface can, for example, be a set of functions, methods, and / or protocols that can enable a program to interact with other programs, operating systems, devices, components, functions, and / or users.

[0033] A "software library" can be an exemplary interface and can be understood as a particularly defined collection or set of (software) functions, methods, programs, and / or routines that enables other programs and / or applications to interact with and / or access them, e.g., to perform specific tasks and / or provide specific functions. The library or software library can include code, code components, code blocks, and / or code segments that can perform specific tasks and / or provide specific functionalities that may be required, e.g., by various applications.

[0034] The software library can be used to control the integrated circuit or the SoC or the SiP and / or at least one of its functions. This can include, for example, reading and / or writing (e.g. also modifying) data in, for example, certain registers of the IC / SoC / SiP, configuring peripherals, managing memory resources and / or other tasks that are required, for example, to control the IC, in particular the SoC or the SiP. Using such a software library can simplify interaction with the IC, in particular the SoC / SiP, for developers, as they do not have to program from scratch each time to access the hardware. Instead, they can use the functions of the library that have already been developed to control or drive the IC / SoC / SiP.This can promote the efficiency, consistency and / or reusability of code in the development of applications that need to access the IC, SoC or SiP.

[0035] According to the invention, the interface, in particular the software library, can be functionally independent and / or functionally decoupled from a standard architecture, in particular a semiconductor-specific architecture, of the integrated circuit, in particular the SoC or the SiP.

[0036] “Functionally independent and / or functionally decoupled” can be understood to mean that the software library does not necessarily have to be tied to, for example, the specific and / or standardized semiconductor architecture of the integrated circuit, in particular the system-on-chip (SoC) or the system-in-package (SiP); the interface or the software library can therefore be designed in such a way that it is, for example, functionally separate from, for example, the internal structure, design, components and / or functionality of the IC or the SoC or the SiP, or does not essentially depend on it, for example, i.e. it is essentially independent. Even if, for example, changes are made to the integrated circuit orIf changes are made to the IC / SoC / SiP (for example because a different standardized chip, in particular a different semiconductor-specific, standard architecture of the integrated circuit, in particular the SoC or the SiP, is used), the interface or the software library can continue to be used and / or used. This can enable the interface or the software library to be flexible, scalable and / or adaptable, e.g. regardless of which IC or SoC / SiP is used. It can therefore be used in different ICs or SoCs / SiPs or in different semiconductor architectures without the need for comprehensive redevelopment. This functional independence and / or functional decoupling makes it easier for developers to reuse the interface or the software library and / or adapt it to new requirements or platforms.

[0037] According to the invention, in particular alternatively or additionally, the integrated circuit, in particular the SoC or the SiP, in particular the CPU and the FPGA (of the IC / SoC / SiP), can be controlled cross-functionally by means of the, in particular single, interface, in particular the software library.

[0038] "Cross-functional controllable" can mean that the software library can be designed to control or drive not only the CPU or the FPGA (or their functions) separately, but also both simultaneously and / or in conjunction with each other. In other words, using the single or the same interface, in particular the single or the same software library, the IC / SOC / SIP can be controlled across CPU and FPGA functions. It can enable an external program or programming to use and / or fully exploit both the processing tasks of the CPU and the functions of the FPGA, especially those that are configurable or programmable, depending on the application.

[0039] A developer of CPU software is usually unable to program or reprogram an FPGA and vice versa. Even if a developer has knowledge in both areas, switching between programming CPUs and FPGAs often requires complex reprogramming processes or additional tools and / or development environments. The use of the software library according to the invention or the interface according to the invention simplifies this process or solves this problem by consolidating, combining and / or merging the required functions for controlling CPUs and FPGAs in a single or the same interface or library. This allows a developer who is familiar with the software library, regardless of their field of expertise, to control, drive and / or adapt both CPUs and FPGAs (this can also mean, in particular, E-FPGAs), without, for example,requiring in-depth knowledge of the other programming domain. This can increase flexibility, efficiency, and / or usability when developing applications that utilize both CPUs and FPGAs.

[0040] A "single" software library can be understood as being suitable for both the CPU and the FPGA, e.g., with a single, essentially identical or the same software library, both the CPU and the FPGA of the IC / SoC / SiP can be controlled and / or adapted.

[0041] According to the invention, in particular alternatively or additionally, the control can be carried out, at least partially, using a central processing unit (CPU) control part and / or a field programmable gate array (FPGA) control part of the in particular single interface, in particular the software library.

[0042] A central processing unit (CPU) "control part" or a "field-programmable gate array (FPGA) control part" can be understood as a set, a collection of functions, methods and / or routines or as code, code blocks and / or code segments, for example with instructions, commands, instruction sets and / or components that enable a developer to accordingly drive, control, adapt and / or program the CPU or the FPGA of the integrated circuit or the SoC or the SiP.

[0043] The ability to selectively and / or cumulatively use the central processing unit (CPU) control part and / or the field-programmable gate array (FPGA) control part of the interface, particularly the software library, can enable integration and / or control of both CPU and FPGA resources, allowing developers or programmers (these terms can be used interchangeably) to work more efficiently without having to deal with the challenges associated with programming different hardware components. Developers can control the IC / SoC / SiP using both the CPU part and the FPGA part without requiring or having to acquire specific knowledge of programming the other or different components.Using both the CPU control part and the FPGA control part within the same interface, namely the software library, can enable efficiency and / or flexibility in the development of applications that utilize both CPU and FPGA resources. Using a single or the same interface for CPU and FPGA control also simplifies development processes. Developers do not have to deal with the complex details of CPU / FPGA programming, but can instead rely on the existing functions and libraries in the software library.

[0044] According to the invention, in particular alternatively or additionally, the integrated circuit, in particular the SoC or the SiP, in particular the CPU and the FPGA, can be updatable and / or expandable in its functions, in particular dynamically, by means of the, in particular single, interface, in particular the software library.

[0045] "Dynamic, updatable, and / or expandable" can be understood to mean that the IC, SoC, or SiP, in particular during operation, can be updated, updated, upgraded, and / or brought up to date, for example, by integrating innovations; and / or, for example, by expanding, expanding, and / or adding at least one function to the IC / SoC / SiP without, for example, requiring a physical change, modification, and / or adaptation of the hardware or the standard architecture of the IC / SoC / SiP or its components. This means that new functions, improvements, adaptations, and / or bug fixes can be integrated, incorporated, and / or incorporated, in particular directly, into the software library and then transferred to the IC / SoC / SiP.This flexibility enables the IC, especially the SoC or SiP, to be continuously improved and adapted to new requirements, thus increasing the vehicle's service life and competitiveness. The software library also enables dynamic extensibility of the IC / SoC / SiP. Developers can design new functions, algorithms, or the like and / or implement them via the software library or integrate them into the IC / SoC / SiP.

[0046] The control according to the invention may include:

[0047] Accessing and / or selecting one or more functional modules included in the, in particular single, interface, in particular the software library, and generating at least one instruction for the integrated circuit, in particular the SoC or SiP, using the one or more functional modules, and in particular transmitting, preferably loading, the at least one instruction into the integrated circuit, in particular the SoC or SiP. The generation of the at least one instruction can be carried out on the basis of a central processing unit (CPU) control part and / or a field-programmable gate array (FPGA) control part.

[0048] The generation of the at least one instruction can be carried out on the basis of a CPU control part and an FPGA control part of a first functional module and / or on the basis of a CPU control part and an FPGA control part of a second functional module.

[0049] The interface, in particular the software library, can comprise, for example, a, in particular first, function module that comprises a (first) CPU control part and a (second) FPGA control part. The interface, in particular the software library, can, for example, additionally comprise, in particular a second, function module that comprises a (first) CPU control part and a (second) FPGA control part. The at least one instruction can be a code, code block, code segment or the like that can be transferred, loaded and / or imported into the IC / SoC / SiP, for example. The at least one instruction can be generated by means of one or more (CPU and / or FPGA) compilers, in particular by means of compilation. The at least one instruction can control the IC / SoC / SiP, for example by execution.

[0050] The control according to the invention can comprise: assigning and / or changing at least one function of the integrated circuit, in particular of the SoC or the SiP, by means of the, in particular only, interface, in particular the software library.

[0051] "Assigning" at least one function of the integrated circuit, in particular of the SoC or the SiP, can be understood as meaning that one or more, for example, already existing functions of the IC, in particular of the SoC or the SiP, are assigned and / or allocated to another component or process, or that one or more new functions, in particular newly, are created and / or added to the IC / SoC / SiP. "Changing" at least one, in particular already assigned, function of the integrated circuit, in particular of the SoC or the SiP, can be understood as meaning that one or more new functions are modified, expanded, edited, adapted, and / or deleted, in particular at least partially.

[0052] The method according to the invention can comprise: connecting at least one component, in particular a hardware and / or software component, from at least one layer of the SDV to the integrated circuit, in particular the SoC or the SiP, via the interface, in particular the software library.

[0053] "Connecting" at least one component, in particular a hardware and / or software component, can be understood as a particularly communicative connection, coupling, linking, and / or linking of at least one component, in particular within the software-defined vehicle (SDV), with the integrated circuit or the SoC or the SiP, for example, in order to be able to control this or at least one component or at least one part, for example, to enable and / or execute certain functions. Connecting can enable the exchange of data, information, commands, and / or instructions, in particular after and / or substantially during the connecting process.

[0054] A "layer of the SDV" can be understood as a logical or functional level or entity, or a part of a logical or software structure that covers various aspects and / or functions of the vehicle, e.g., acting on and / or influencing a hardware structure, particularly a physical one, of the SDV. The SDV can comprise multiple layers or be divided / divided into multiple layers, which together or as a whole can also be referred to as a stack or layer stack of the SDV. These layers can be hierarchically structured, e.g., top (e.g., uppermost layer; Layer III), middle (e.g., middle layer; Layer II), and base (e.g., bottommost layer; Layer I). The layers can, for example, assign specific functions to one or more, particularly zonal, Electronic Control Units (ECUs) of the SDV. As already mentioned, the IC or SoC / SiP can be installed or integrated in the ECUs, for example, in every ECU of the SDV.

[0055] The software library described herein can, e.g., essentially during compilation, be integrated into the, in particular later, executable program or the software of one or more ECUs and can thus, e.g., become part of the overall program or the entire software of the SDV. One or more of the methods described herein can therefore also comprise the step of integrating the interface, in particular the software library, into at least one ECU of the SDV. Since the software library described herein can communicate with the hardware, e.g., the ECUs, it can also be referred to as a driver and / or as part of the operating system of the SDV. The SDV can comprise a plurality of, in particular, physical (hardware) components, elements, devices, devices, facilities and / or parts that are, e.g., installed in the SDV, including sensors (e.g., for recording measured values ​​such as temperature and / or light sensors or similar / other), possible switches, etc.), actuators (e.g., executive relays that control headlights, climate control, etc.), control units (e.g., engine controls, window regulators, seat adjusters, mirror adjusters, headlight range control, or similar), communication modules, and / or other, particularly electronic, components. These hardware components can collect data and / or information, e.g., from the vehicle's surroundings, and / or control its movements and / or enable communication with other vehicles or the infrastructure or at least one of its components.

[0056] The SDV can, for example, include a base layer. From a hierarchical perspective, this can represent the lowest layer of the stack and be referred to as Layer I. This layer can, for example, be used to control one or more hardware components, e.g., sensors / actuators, and / or enable programming, particularly function-specific programming, of the IC / SoC / SiP.

[0057] The SDV can, for example, comprise a middleware layer. From a hierarchical perspective, this can, for example, represent the middle layer of the stack (in particular, lie above the base layer) and be referred to as Layer II. This layer can accommodate algorithms and access at least one other layer, in particular Layer I, in order to, for example, query sensors and / or control actuators. Alternatively or additionally, the middleware layer can act as a link between one or more hardware components and at least one application or an application layer of the SDV and / or mediate between them. This layer can, for example, enable a flow of data, in particular from hardware components, e.g. between sensors and an application and / or between an application and one or more actuators.

[0058] The SDV can, for example, comprise an application layer. From a hierarchical perspective, this can represent the topmost layer of the stack (in particular, lying above the middle layer) and be referred to as Layer III. This layer can contain the actual applications (apps) and / or functions of the vehicle, which can be controlled, for example, by the user and / or by other systems. These can include functions such as autonomous driving, driver assistance systems, infotainment, vehicle diagnostics and maintenance, fleet management and / or other specific applications, such as air conditioning applications. These can also include comfort functions such as air conditioning, personalized settings, e.g. of the seat, mirrors, steering wheel, preferred music, interior lighting, adjustments of, for example, the chassis, drive dynamics, etc.

[0059] The method according to the invention can comprise: connecting at least one hardware component of the SDV, in particular at least one actuator of the SDV and / or at least one sensor of the SDV to the integrated circuit, in particular the SoC or SiP, via the interface, in particular the software library.

[0060] The method according to the invention can, in particular alternatively or additionally, comprise: connecting at least one component, in particular a software component, from an application layer of the SDV to the integrated circuit, in particular the SoC or SiP, via the interface, in particular the software library, in particular connecting at least one artificial intelligence, KI, module of the SDV and / or at least one state engine. Further connectable modules can also be a module for the parallel processing (e.g. the FPGA) of sensor data, for example in connection with Advanced Driver Assistance Systems (ADAS) such as radar, lidar, camera, etc. and / or preprocessing, e.g. by means of KI and / or their support by FPGA programming.

[0061] The method according to the invention may comprise:

[0062] Inserting, in particular implementing and / or using, the in particular semiconductor-specific, standard architecture of the integrated circuit, in particular the SoC or SiP and / or at least one of its functions via the, in particular only, interface, in particular the software library, wherein the insertion is zone-selective and / or zone-specific for the SDV.

[0063] "Zone-selective and / or zone-specific" can mean the deployment, application, use, and / or implementation of this architecture, or the standard architecture, in particular the semiconductor-specific architecture, and / or at least one of its functions in specific sections, parts, regions, zones, and / or areas of the vehicle or SDV. These zones can, for example, be different zones of the vehicle, each of which performs different functions and / or fulfills different tasks, such as drive systems, safety systems, infotainment, autonomous driving, driver assistance systems, etc. The method according to the invention can comprise:

[0064] Integrating and / or using the, in particular only, interface, in particular the software library, in the SDV, in particular in the base layer of the SDV, and / or in particular in each layer of the SDV.

[0065] The interface described herein, in particular the sole interface, in particular the software library, can be modularly constructed and / or divided. The interface, in particular the sole interface, in particular the software library, can comprise several modules or a plurality of modules, in particular functional modules, in particular for, in particular selectively, i) controlling and / or ii) assigning and / or changing the at least one function of the integrated circuit, in particular the SoC / SiP. The interface described herein, in particular the sole interface, in particular the software library, can be divided, divided and / or segmented into various functional modules.

[0066] The plurality of functional modules may comprise at least one local functional module, in particular for providing the at least one function of the integrated circuit, in particular of the SoC or the SiP, on a local control level of the SDV. A "local control level" may refer to the level or layer that focuses on specific components, elements, and / or subsystems within the SDV. At this level, for example, functions and / or tasks can be executed that may be directly connected to the local sensors, actuators, and / or other components. A local functional module may, for example, be responsible for controlling a specific sensor and / or actuator.

[0067] The plurality of functional modules may comprise at least one zonal functional module, in particular for providing the at least one function of the integrated circuit, in particular of the SoC or the SiP, on at least one zonal control level of the SDV. A "zonal control level" may refer to a section, a region, a zone, a part, and / or an area in the SDV, which may comprise or combine several, e.g., a group of components, elements, and / or subsystems within the SDV, e.g., zonally. At this level, functions and / or tasks can be executed that may relate to several or a group of local components, elements, and / or subsystems. A zonal functional module may, for example, be responsible for the coordination and control of several, in particular all, sensors and / or actuators, in particular in one or more specific zones, e.g., the chassis.

[0068] The plurality of functional modules can comprise at least one central functional module, in particular for providing the at least one function of the integrated circuit, in particular of the SoC or the SiP, on a central control level of the SDV. A "central control level" can refer to a, e.g., highest, level of control and / or coordination within the SDV. At this level, higher-level functions and / or tasks can be executed, for example, relating to the entire vehicle and / or communication with, e.g., external systems and / or infrastructures. A central functional module can, for example, be responsible for coordinating all vehicle functions, processing data, in particular at the highest level, and / or making strategic decisions.

[0069] By dividing the functional modules into different levels, e.g. local, zonal and / or central levels, the software library enables a hierarchical organization or control of the functionality in the SDV, whereby complex tasks and / or functions can be carried out or managed and / or provided or implemented efficiently, quickly and / or in a coordinated manner.

[0070] The assignment and / or changing of the at least one function of the integrated circuit, in particular of the SoC or the SiP, according to the method according to the invention can be carried out on the basis of at least one selected functional module of the interface, in particular of the software library, or on the basis of at least one functional module that is accessed.

[0071] At least one functional module, in particular each functional module, of the plurality or the majority of functional modules can comprise a central processing unit (CPU) control part and a field-programmable gate array (FPGA) control part. In this way, both the CPU and the FPGA components of the IC, in particular of the SoC or the SiP, can be controlled via the same or single software library. One or more of the modules described herein, in particular the functional modules, can enable developers to use CPU and FPGA components more effectively by providing a uniform interface or software library to control, modify, and / or integrate both types independently of one another. This means that developers no longer have to deal with the specific details of CPU and FPGA programming, for example, because the functional modules abstract this complexity.By using functional modules, various applications and functions can be implemented independently of the underlying hardware. Since at least one or each functional module has the option of including both a CPU and an FPGA control part, the SDV can be scalable, adaptable, and / or extensible.

[0072] The method according to the invention may comprise:

[0073] Assigning and / or changing the at least one function of the integrated circuit, in particular the SoC or the SiP, using the CPU control part and / or the FPGA control part.

[0074] For example, for controlling, assigning, and / or modifying, i) only the CPU control part; ii) only the FPGA control part; or iii) both the CPU control part and the FPGA control part can be used. In this context, the CPU control part and the FPGA control part can be used by only one functional module (e.g., a first one), or by a first and a second functional module. It is also possible to use all functional modules of the interface, in particular the software library.

[0075] This may mean that both the CPU and the FPGA control parts can be used, in particular dynamically and / or flexibly, in particular in the same library, to adapt and / or change the functions of the SoC or the SiP, for example i) essentially independently of each other, i) essentially together or in combination and / or essentially mutually complementing each other. Both control parts (CPU / FPGA) can, for example, be of equal status, e.g. each have the same authority to assign and / or change functions. In this case, the CPU and FPGA control parts could, for example, work independently of each other and / or assign and / or change various functions of the IC, in particular of the SoC or the SiP. The CPU and FPGA control parts can also work together to assign and / or change functions of the IC / SoC / SiP. In this case, they could, for example,They work essentially simultaneously to assign and / or modify various functions of the IC, particularly the SoC or SiP. It is also possible for the CPU control part and the FPGA control part to complement each other. For example, the CPU control part could be responsible for complex algorithmic calculations, while the FPGA control part is used for fast data processing tasks or low-level hardware operations.

[0076] The method according to the invention may comprise:

[0077] Assign and / or forward the

[0078] CPU control part or at least components thereof, and / or the FPGA control part or at least components thereof and / or the at least one instruction to a bitstream, which is to be used in particular for configuring and / or controlling or driving the integrated circuit, in particular the SoC or the SiP. The assignment and / or forwarding can take place at least partially, preferably essentially completely, during a compilation time. A functionality of the IC / SoC / SiP can be determined by assigning and / or embedding the CPU and FPGA control parts in a bitstream. The method according to the invention can comprise: integrating the CPU control part or at least components thereof, and / or the FPGA control part or at least components thereof and / or the at least one instruction in the bitstream.

[0079] As already mentioned, after creating code, a developer can convert and / or compile it into a bitstream, which can then be loaded into the FPGA, for example, to implement the functionality assigned to the code. A "bitstream" can be considered a sequence, order, and / or stream (bitstream) of bits that can represent a configuration of a, particularly programmable, IC or SoC / SiP. A bitstream can correspond to a binary representation of at least one function that the IC / SoC / SiP is intended to perform. The functionality of the SoC or SiP can thus be determined, for example, by assigning or embedding the CPU and FPGA control components in the bitstream, which can essentially be created at compile time.

[0080] Essentially, "compilation time" can describe the point in time at which the source code is converted or compiled into an executable form. In relation to FPGA or E-FPGA programming, this can mean that code (e.g., VHDL or Verilog) is converted / compiled into the corresponding bitstream, which can then be used to configure the FPGA. Compilation time can be, for example, after the developer has written the code and described the desired functionality. The code can then be analyzed and / or optimized, for example, by a special software tool, to translate or transfer it, e.g., into the required hardware structure. Finally, the optimized code can be converted or embedded into the bitstream, which can then be loaded onto the FPGA.During compile time, the abstract description code can be translated into a concrete, executable form that can be executed on the FPGA. The assignment and / or forwarding of the CPU and FPGA control components to the bitstream can therefore essentially be done at compile time. During this phase, for example, the source code for the CPU and FPGA components of the IC / SoC / SiP can be processed and converted or transferred into the corresponding bitstream, which can then be loaded onto the IC / SoC / SiP.

[0081] It is intended that the interface described here, in particular the software library, can also offer support in programming configuration code for the IC / SoC / SiP, in particular the FPGA, e.g. code for interfaces and their routing in the IC / SoC / SiP or FPGA. Alternatively or additionally, the interface described here, in particular the software library, can comprise functions up to and including the bootloader. The bootloader can load software updates (including over-the-air (OTA)) into the respective memories and, in particular functionally, correspond to a BIOS bootloader. The bootloader function is described below: From a technical point of view, the bootloader can be stored in the memory from which the CPU starts. The bootloader can initialize the CPU, e.g. at least to the extent that the actual operating system can be loaded from the memory.The bootloader can then set the CPU registers so that the operating system is executed. Further configurations can then be made, for example directly, from the operating system. Since the bootloader itself is operated / runs on the CPU, it can itself check individual system components, such as the memory, at startup, for example for software updates. If this is the case, it cannot transfer control to the operating system, but would update the existing operating system with the software update before loading the operating system and transferring control to it. An update can therefore only be carried out when the ECU starts up. As with a conventional computer, the operating system can terminate itself and call the bootloader, to which it can pass configuration parameters (e.g. PowerOff, Sleep, Restart, ...).Overall, the integration of a bootloader into the software library can improve and / or facilitate the flexibility, security and / or reliability of software updates for the SDV. It is intended that the interface described herein, in particular the software library, also enables adaptation or reprogramming of the IC, in particular the SoC or the SiP, in particular the FPGA, even during operation, e.g. to make a functional change for certain weather conditions. This function is described below: In contrast to the aforementioned bootloader, in this example the reprogramming of the FPGA can be initiated from the operating system. For this purpose, the bitstream for the FPGA can already be present in the CPU program memory, so that it overwrites the bitstream memory of the FPGA and starts the FPGA with a new function. The FPGA can independently read the bitstream from this memory area at startup.Therefore, it may be sufficient to simply restart the SDV after overwriting the bitstream memory. This program section for updating the bitstream memory and restarting the FPGA can be a function of the software library, which can be initiated, for example, by a service. This approach can enable the FPGA functionality to be updated dynamically and / or independently of the system boot process, increasing flexibility and efficiency in maintaining and configuring the SDV.

[0082] The control of the method according to the invention can comprise:

[0083] Transmitting at least one instruction by means of wireless transmission, in particular via over-the-air (OTA) communication, in particular for assigning and / or changing at least one function of the integrated circuit, in particular of the SoC or the SiP or at least one component thereof.

[0084] "Wireless transmission" can mean wireless communication, e.g., with other devices, such as a computer and / or a particularly mobile device, e.g., a cell phone and / or smartphone, without the need for physical cable connections. Typical technologies for wireless transmissions / channels can include Wi-Fi, Bluetooth, ZigBee, LoRaWAN, or mobile networks such as 4G (Long-Term Evolution, "LTE") or 5G (New Radio, "NR"), or others such as 3G or others. OTA communication can refer to the transmission of data, instructions, information, and / or commands over wireless channels.

[0085] One aspect of the invention relates to an integrated circuit, IC, in particular a system-on-chip (SoC) or a system-in-package (SiP), for a software-defined vehicle (SDV), comprising:

[0086] - at least one field-programmable gate array (FPGA), in particular an embedded FPGA (E-FPGA), and - at least one central processing unit (CPU), wherein the integrated circuit, in particular the SoC or the SiP, is controllable and / or controlled by the method according to one or more of the inventive aspects and / or embodiments described herein

[0087] The integrated circuit, in particular the SoC or the SiP, can comprise: at least one memory, in particular at least one non-volatile memory, and, optionally, at least one input / output (I / O) interface for establishing a connection to an external device. The components, elements, parts, and / or units of the integrated circuit, in particular the SoC or the SiP, can be located on one, in particular a single, circuit board or several, e.g., at least two, circuit boards and / or can be communicatively connected.

[0088] One aspect of the invention relates to a software-defined vehicle (SDV), comprising: an integrated circuit, in particular a SoC or SiP, in particular according to one or more of the invention aspects and / or embodiments described herein, and one, in particular a single, interface, in particular a software library, for controlling the integrated circuit, in particular the SoC or the SiP, by means of the method according to one or more of the invention aspects and / or embodiments described herein.

[0089] The software-defined vehicle may comprise a plurality of layers for controlling and / or managing the SDV, in particular at least one electronic control unit (ECU) of the SDV and / or at least one function of the at least one ECU. The SoC or SiP may be included in at least one ECU of the SDV.

[0090] The plurality of layers can be structured hierarchically, in particular in the following ascending or descending order, wherein the plurality of layers can comprise the following: a, in particular lowest, base layer, a, in particular middle, middleware layer, and a, in particular top, application layer.

[0091] BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the invention will now be described with reference to the accompanying drawings. In order that the above-mentioned features of the present disclosure may be understood in detail, a more detailed description of the disclosure, briefly summarized above, may be obtained by reference to embodiments. The accompanying drawings relate to embodiments of the disclosure and are described below:

[0092] Fig. 1 shows a flowchart of a method according to the invention according to one or more embodiments;

[0093] Fig. 2 shows a flowchart of a method according to the invention according to one or more embodiments;

[0094] Fig. 3 shows a flowchart of a method according to the invention according to one or more embodiments;

[0095] Fig. 4 shows a flowchart of a method according to the invention according to one or more embodiments;

[0096] Fig. 5A-G show flow diagrams according to one or more methods of Fig. 1-4 with one or more further steps according to the invention;

[0097] Fig. 6 shows an integrated circuit according to the invention, in particular a system-on-chip (SoC) or a system-in-package (SiP), according to one or more embodiments;

[0098] Fig. 7A-C show an exemplary use of various control parts or functional modules of the interface, in particular the software library for a method according to the invention according to one or more embodiments; and

[0099] Fig. 8 shows an exemplary stack of multiple layers of a software-defined vehicle.

[0100] DESCRIPTION OF PREFERRED EMBODIMENTS The invention will be explained in more detail below with reference to embodiments shown in the drawings, wherein in all drawings essentially functionally identical elements have the same reference numerals.

[0101] The drawings are schematic drawings and are not to scale. Some elements in the drawings may have exaggerated dimensions to emphasize aspects of the present disclosure and / or for presentation clarity. For simplicity, identical reference numerals are used to identify identical elements commonly included in the drawings. It is contemplated that elements and features of one embodiment may be advantageously incorporated into other embodiments without further notice. In general, only the differences with respect to individual embodiments will be described.

[0102] Each embodiment is provided to illustrate the disclosure and is not intended to limit the disclosure. Furthermore, features illustrated or described as part of one embodiment may be used in conjunction with other embodiments to create another embodiment. The description is intended to encompass such modifications and variations.

[0103] Fig. 1 shows a flowchart of a method 100 according to the invention according to one or more embodiments. In particular, Fig. 1 shows a computer-implemented method 100 for adapting, in particular programming, an integrated circuit (IC), in particular a system-on-chip (SoC) or a system-in-package (SiP), a vehicle, in particular a software-defined vehicle (SDV), in particular across functions. The method 100 can comprise: controlling 110 the integrated circuit, in particular the SoC or the SiP, via one, in particular single, interface, in particular a software library. According to the method 100 according to the invention or the control add-on 120, the interface, in particular the software library, can be functionally independent and / or functionally decoupled 120 from a, in particular semiconductor-specific, standard architecture of the integrated circuit, in particular the SoC or the SiP.The control 110 can therefore also be referred to as functionally independent and / or functionally decoupled control. A control addition can be understood as an additional feature or an addition for the control. The software library described herein does not necessarily have to be tied to, for example, the specific and / or standardized semiconductor architecture of the integrated circuit, in particular of the system-on-chip (SoC) or the system-in-package (SiP); the interface or the software library can therefore be designed in such a way that it is, for example, functionally separate from, or essentially does not directly depend on, the, for example, internal structure, design, components and / or the functioning of the SoC or the SiP, e.g., is essentially independent of, the internal structure, design, components and / or the functioning of the SoC or the SiP.are made to the SoC / SiP (for example, because a different standardized chip, in particular a different semiconductor-specific, standard architecture of the integrated circuit, in particular of the SoC or the SiP, is used), the interface or the software library can continue to be used and / or used. This can enable the interface or the software library to be flexible, scalable and / or adaptable, e.g. regardless of which IC or SoC / SiP is used. It can therefore be used in different ICs or SoCs / SiPs or in different semiconductor architectures without the need for comprehensive redevelopment. This functional independence and / or decoupling makes it easier for developers to reuse the interface or the software library and / or adapt it to new requirements or platforms.

[0104] Fig. 2 shows a flowchart of a method 200 according to the invention according to one or more embodiments, which can be combined with one or more aspects and / or embodiments described herein. In particular, Fig. 2 shows a computer-implemented method 200, in particular according to one or more of the aspects and / or embodiments of the invention described herein, for adapting, in particular programming, an integrated circuit (IC), in particular a system-on-chip (SoC) or the system-in-package (SiP), a vehicle, in particular a software-defined vehicle (SDV), wherein the integrated circuit, in particular the SoC / SiP, comprises at least one central processing unit (CPU) and at least one field-programmable gate array (FPGA), in particular an embedded FPGA (E-FPGA).

[0105] The method 200 may include

[0106] Controlling 210 the integrated circuit (IC), in particular the SoC or SiP, via one, in particular single, interface, in particular a software library. According to the inventive method 200 or the control add-on 220, the integrated circuit, in particular the SoC / SiP, in particular the CPU and the FPGA, can be controlled 220 in a cross-functional manner using the, in particular single, interface, in particular the software library. Controlling 210 can therefore also be referred to as cross-functional or CPU and FPGA cross-functional control.

[0107] The software library can therefore be designed in such a way that it can control or drive not only the CPU or the FPGA (or their functions) separately, but also both simultaneously and / or in conjunction with one another. In other words, the IC / SOC / SiP (CPU and FPGA) can be controlled across functions using the single interface, in particular the software library. It can enable an external program or programmer to use both the processing tasks of the CPU and the functions, in particular the configurable or programmable functions, of the FPGA, e.g. depending on the application. A developer of CPU software is usually not able to program or reprogram an FPGA and vice versa. Even if a developer has knowledge in both areas, switching between programming CPUs and FPGAs often requires complex reprogramming processes.additional tools and / or development environments. The use of the software library or interface according to the invention simplifies this process by consolidating, combining, and / or merging the required functions for controlling CPUs and FPGAs in a single interface or library. This allows a developer familiar with the software library, regardless of their discipline, to control, drive, and / or adapt both CPUs and FPGAs without, for example, requiring in-depth knowledge of the other programming domain. This can increase the flexibility, efficiency, and / or user-friendliness when developing applications that utilize both CPUs and FPGAs.

[0108] Fig. 3 shows a flowchart of a method 300 according to the invention according to one or more embodiments, which can be combined with one or more aspects and / or embodiments described herein. In particular, Fig. 3 shows a computer-implemented method 300, in particular according to one or more of the aspects and / or embodiments of the invention described herein, for adapting, in particular programming, an integrated circuit (IC), in particular a system-on-chip (SoC) or a system-in-package (SiP), a vehicle, in particular a software-defined vehicle (SDV), wherein the SoC comprises at least one central processing unit (CPU) and at least one field-programmable gate array (FPGA), in particular an embedded FPGA (E-FPGA).The method 300 can comprise: controlling 310 the integrated circuit, in particular the SoC or the SiP, via one, in particular single, interface, in particular a software library. According to the method 300 according to the invention or the control addition 320, the controlling 310 can be carried out, at least partially, using 320 a central processing unit (CPU) control part and / or a field programmable gate array (FPGA) control part of the in particular single, interface, in particular the software library, in particular essentially simultaneously. The step 320 or the control addition 320 can also be referred to as using 320 the central processing unit (CPU) control part and / or the field programmable gate array (FPGA) control part of the in particular single, interface, in particular the software library, orwhich are included in particular in the in particular only interface, in particular the software library, are referred to for controlling 310.

[0109] The inventive use or utilization 320 of the central processing unit (CPU) control part and the field-programmable gate array (FPGA) control part can enable integration and / or control of both CPU and FPGA resources, allowing developers or programmers (these terms can be interchangeable) to work more efficiently without having to deal with the challenges associated with programming different hardware components. Developers can control the IC / SoC / SiP using both the CPU part and the FPGA part without requiring specific knowledge of programming the other component. The use of both the CPU control part and the FPGA control part within the same interface, namely the software library, can enable efficiency and / or flexibility in developing applications that utilize both CPU and FPGA resources.Using a single interface for controlling the CPU and FPGA also simplifies development processes. Developers don't have to deal with the complex details of CPU / FPGA programming, but can instead rely on the existing functions and libraries in the software library.

[0110] Fig. 4 shows a flowchart of a method 400 according to the invention according to one or more embodiments, which can be combined with one or more aspects and / or embodiments described herein. In particular, Fig. 4 shows a computer-implemented method 400, in particular according to one or more of the aspects of the invention and / or embodiments described herein, for adapting, in particular programming, an integrated circuit (IC), system-on-chip (SoC) or system-in-package (SiP), of a vehicle, in particular a software-defined vehicle (SDV), wherein the integrated circuit, in particular the SoC or SiP, comprises at least one central processing unit (CPU) and at least one field-programmable gate array (FPGA), in particular an embedded FPGA (E-FPGA).The method 400 can comprise: controlling 410 the integrated circuit, in particular the SoC or the SiP, via one, in particular single, interface, in particular a software library. According to the inventive method 400 or the control add-on 420, the integrated circuit, in particular the SoC / SiP, in particular the CPU and the FPGA of the SoC / SiP, can be updated and / or expanded 420, in particular dynamically, in its functions, by means of the, in particular single, interface, in particular the software library. The step 420 or the control add-on 420 can also be referred to as, in particular dynamically, expanding and / or updating the SoC / SiP, in particular the CPU and the FPGA, in its functions by means of the, in particular single, interface, in particular the software library.

[0111] The IC or SoC / SiP can therefore be updated, upgraded, and / or brought up to date, particularly during operation; for example, innovations can be integrated; and / or the IC / SoC / SiP can be expanded or enhanced by at least one function, and / or this function can be added, without, for example, requiring a physical change, modification, and / or adaptation of the hardware or the standard architecture of the IC / SoC / SiP or its components. This means that new functions, improvements, adaptations, and / or bug fixes can be integrated, incorporated, and / or incorporated into the software library, particularly directly, and then transferred to the IC / SoC / SiP. This flexibility enables the SoC / SiP to be continuously improved and adapted to new requirements, thereby increasing the service life and competitiveness of the vehicle.The software library also enables dynamic extensibility of the SoC / SiP. Developers can design new functions, algorithms, or the like and / or implement them via the software library or integrate them into the IC / SoC / SiP.

[0112] Figs. 5A-G show flowcharts according to one or more of the methods of Figs. 1-4, cf. steps 110 / 210 / 310 / 410 and / or steps or control additions 120 / 220 / 320 / 420 with one or more further inventive steps of the inventive method. It should be noted that the steps of Figs. 5A-G can each be combined as desired, individually or in combination with the steps of the one or more methods of Figs. 1-4. The steps of the methods according to Figs. 5A-G can also be combined or combined with one another as desired.

[0113] According to Fig. 5A, the control 110, 210, 310, and / or 410 according to the invention may each optionally in combination with 120, 220, 320 and / or 420 (cf. Fig. 1-4), comprise:

[0114] Accessing 505 and / or selecting 505 one or more functional modules included in the, in particular single, interface, in particular the software library, and

[0115] Generating 510 at least one instruction for the integrated circuit, in particular the SoC or SiP, using the one or more functional modules, and in particular transmitting 520, preferably loading, the at least one instruction into the integrated circuit, in particular the SoC or SiP.

[0116] The generation 510 of the at least one instruction can be carried out on the basis of a central processing unit (CPU) control part and / or a field programmable gate array (FPGA) control part.

[0117] The generation 510 of the at least one instruction can be carried out on the basis of a CPU control part and an FPGA control part of a first functional module and / or on the basis of a CPU control part and an FPGA control part of a second functional module.

[0118] The interface, in particular the software library, can comprise, for example, a, in particular first, function module that comprises a (first) CPU control part and a (second) FPGA control part. The interface, in particular the software library, can, for example, additionally comprise, in particular a second, function module that comprises a (first) CPU control part and a (second) FPGA control part. The at least one instruction can be a code, code block, code segment or the like that can be transferred, loaded and / or imported into the IC / SoC / SiP, for example. The at least one instruction can be generated by means of one or more (CPU and / or FPGA) compilers, in particular by means of compilation. The at least one instruction can control the IC / SoC / SiP, for example by execution.

[0119] According to Fig. 5B, the control 110, 210, 310, and / or 410 according to the invention, each optionally in combination with 120, 220, 320 and / or 420 (cf. Fig. 1-4), may comprise: assigning 530 and / or changing 530 at least one function of the integrated circuit, in particular of the SoC or the SiP, by means of the, in particular single, interface, in particular of the software library.

[0120] According to Fig. 50, the method 500 according to the invention (or also one or more of the methods from 100-400; this may apply below to the further Figs. 5D-G without this being explicitly mentioned) may comprise:

[0121] Connecting 540 at least one component, in particular a hardware and / or software component, from at least one layer of the SDV to the integrated circuit, in particular the SoC or the SiP, via the interface, in particular the software library. In particular, the method 500 according to the invention can comprise: connecting 540 at least one hardware component of the SDV, in particular at least one actuator of the SDV and / or at least one sensor of the SDV to the integrated circuit, in particular the SoC or SiP, via the interface, in particular the software library. As mentioned, one or more of the steps 540 from Fig. 5C can also be combined with one or more steps of Figs. 5A-B, and vice versa.

[0122] The inventive method 500 according to Fig. 5C can, in particular alternatively or additionally, comprise: connecting 540 at least one component, in particular a software component, from an application layer of the SDV to the integrated circuit, in particular the SoC or SiP, via the interface, in particular the software library, in particular connecting 540 at least one artificial intelligence, Cl, module of the SDV and / or at least one state engine.

[0123] According to Fig. 5D, the inventive method 500 may include:

[0124] Inserting 550, in particular implementing 550 and / or using 550, the in particular semiconductor-specific standard architecture of the integrated circuit, in particular the SoC / SiP, and / or at least one of its functions via the, in particular only, interface, in particular the software library, wherein the insertion 550 is zone-selective and / or zone-specific for the SDV. As mentioned, step 540 of Fig. 5D can also be combined with one or more steps of Figs. 5A-C, and vice versa.

[0125] According to Fig. 5E, the assignment 530 and / or changing 530 of the at least one function of the integrated circuit, in particular of the SoC or the SiP, according to the method according to the invention may comprise: selection 560 of at least one function module from the plurality of function modules of the interface, in particular of the software library, and

[0126] Assigning 570 and / or changing 570 the at least one function of the integrated circuit, in particular the SoC or the SiP, based on the at least one selected functional module of the interface, in particular the software library. As mentioned, one or more of the steps from Fig. 5E can also be combined with one or more steps from Figs. 5A-D, and vice versa.

[0127] At least one functional module, in particular each functional module, of the plurality of functional modules can comprise a central processing unit (CPU) control part and a field programmable gate array (FPGA) control part.

[0128] In this way, both the CPU and the FPGA component of the IC / SoC / SiP can be controlled via the same or single software library. One or more of the modules described herein, in particular the function modules, can enable developers to use CPU and FPGA components more effectively by providing a unified interface or software library to control, modify and / or integrate both types independently of each other. This means that developers no longer have to deal with the specific details of CPU and FPGA programming, for example, because the function modules abstract this complexity. By using function modules, different applications and functions can be implemented independently of the underlying hardware. Since at least one or more of the modules described herein, in particular the function modules, can enable developers to use CPU and FPGA components more effectively by providing a unified interface or software library to control, modify and / or integrate both types independently of each other.Since each functional module has the possibility to include both a CPU and an FPGA control part, the SDV can be scalable, adaptable and / or extensible.

[0129] According to Fig. 5F, the inventive method 500 may include:

[0130] Assigning 530 and / or changing 530 the at least one function of the integrated circuit, in particular the SoC or the SiP, using 580 the CPU control part and / or the FPGA control part. As mentioned, one or more of the steps from Fig. 5F can also be combined with one or more steps from Figs. 5A-E, and vice versa.

[0131] This may mean that both the CPU and the FPGA control parts can be used, in particular dynamically and / or flexibly, in particular in the same library, to adapt and / or change the functions of the IC, in particular the SoC or the SiP, for example i) essentially independently of each other, i) essentially together or in combination and / or essentially mutually complementing each other. Both control parts (CPU / FPGA) can, for example, be of equal status, e.g. each have the same authority to assign and / or change functions. In this case, the CPU and FPGA control parts could, for example, work independently of each other and / or assign and / or change various functions of the SoC or the SiP. The CPU and FPGA control parts can also work together to assign and / or change functions of the IC, in particular the SoC or the SiP. In this case, they could, for example,They work essentially simultaneously to assign and / or modify various functions of the IC, particularly the SoC or SiP. It is also possible for the CPU control part and the FPGA control part to complement each other. For example, the CPU control part could be responsible for complex algorithmic calculations, while the FPGA control part is used for fast data processing tasks or low-level hardware operations.

[0132] The method 500 according to the invention (see, for example, Fig. 5A, in particular the step of transmitting 505 or loading 505) may further comprise:

[0133] Assign and / or forward the

[0134] CPU control part or at least components thereof, and / or the FPGA control part or at least components thereof, and / or the at least one instruction) to a bitstream, which is to be used in particular for configuring and / or controlling or driving the integrated circuit, in particular the SoC or the SiP. The assignment and / or forwarding can take place at least partially, preferably substantially completely, during a compilation time. A functionality of the IC / SoC / SiP can be determined by assigning and / or embedding the CPU and FPGA control parts in a bitstream. The inventive method 500 or the assignment and / or forwarding can comprise: integrating the CPU control part or at least components thereof, and / or the FPGA control part or at least components thereof and / or the at least one instruction in the bitstream.

[0135] As already mentioned, after creating code, a developer can convert it into a bitstream, which can then be loaded into the FPGA, for example, to implement the functionality assigned to the code. A "bitstream" can be considered a sequence, order, and / or stream (bitstream) of bits that can represent a configuration of an IC or SoC / SiP, in particular a programmable one. A bitstream can correspond to a binary representation of at least one function that the IC / SoC / SiP is intended to perform. The functionality of the IC, in particular the SoC or SiP, can thus be determined, for example, by assigning or embedding the CPU and FPGA control parts and / or the at least one instruction in the bitstream, which can essentially be created at compile time.

[0136] According to Fig. 5G, the control (see 110, 210, 310, and / or 410, each optionally in combination with 120, 220, 320 and / or 420 (cf. Fig. 1-4)) of the method 500 according to the invention may include:

[0137] Transmitting 590 at least one instruction (or command, information, and / or data) by wireless transmission, in particular via over-the-air (OTA) communication, in particular for assigning and / or changing at least one function of the integrated circuit, in particular the SoC or the SiP, or at least one component thereof. As mentioned, one or more of the steps from Fig. 5G can also be combined with one or more steps of Figs. 5A-F, and vice versa.

[0138] Fig. 6 shows an exemplary integrated circuit 600, in particular a system-on-chip (SoC) or a system-in-package (SiP), for a software-defined vehicle (SDV) (not shown) according to one embodiment. The integrated circuit 600, in particular the SoC / SiP, is shown as an example, i.e., detached from a single or multiple printed circuit boards (cf. SoC / SiP). The integrated circuit 600, in particular the SoC / SiP, can include:

[0139] - at least one field-programmable gate array (FPGA) 630, in particular an embedded FPGA (E-FPGA) 630, and

[0140] - at least one central processing unit (CPU) 620. The arrangement of the FPGA 630 on the right side and the CPU 620 on the left side should be understood as an example and not as a limitation.

[0141] As can be seen in Fig. 6, the integrated circuit 600, in particular the SoC or the SiP, can be controllable and / or controlled by means of the method according to one or more of the inventive aspects and / or exemplary embodiments described herein, in particular according to one or more of the methods 100-500 (from Figs. 1-5G) or one or more steps described therein (cf. steps 110 / 210 / 310 / 410 and / or control additions 120 / 220 / 320 / 420 or additional steps mentioned therein), for example via wireless communication. The integrated circuit 600, in particular the SoC or the SiP, can comprise: at least one memory 610, in particular at least one non-volatile memory 610 and, optionally, at least one input / output (I / O) interface 640 for establishing a connection to an external device.The components, elements, parts and / or units of the integrated circuit, in particular the SoC or the SiP, can be communicatively connected, for example via external / internal buses, as described herein.

[0142] 7A-C show an exemplary use of various control parts and / or functional modules of the interface according to the invention, in particular the software library 700 for a method according to the invention according to one or more embodiments.

[0143] As can be seen in Fig. 7A, access 710 to and / or selection 710 of one or more function modules 702 that are included in the, in particular, single, interface 700, in particular the software library 700, can take place. According to Fig. 7A, generation 720 of at least one instruction 715 for the integrated circuit 600, in particular the SoC or SiP (cf. Fig. 6), can take place using the one or more function modules 702. Subsequently, transmission 730, preferably loading 730, of the at least one instruction 715 into the integrated circuit 600, in particular the SoC or SiP (cf. Fig. 6) can take place. In Fig. 7A, access 710 can be initiated by a source code 705 or source code 705, in particular a CPU source code 705. As can be seen in Fig. 7A, the generation 720 of the at least one instruction 715 can be carried out solely on the basis of a central processing unit (CPU) control part.Specifically, this can mean that the CPU source code 705 only uses CPU program code from the function module 702 of the software library 700. This can be compiled in the compiler from 705 and 700 or 702. The result can be a common code 715 that can be loaded into the IC 600. The IC 600 can be controlled by executing the code 715.

[0144] As can be seen in Fig. 7B, access 710 to and / or selection 710 of one or more function modules 702, which are included in the, in particular single, interface 700, in particular the software library 700, can take place. According to Fig. 7B, generation 720 of at least one instruction 715 for the integrated circuit 600, in particular the SoC or SiP (cf. Fig. 6), can take place using the one or more function modules 702. Subsequently, transmission 730, preferably loading 730, of the at least one instruction 715 into the integrated circuit 600, in particular the SoC or SiP (cf. Fig. 6) can take place. In Fig. 7B, access 710 can be initiated by a source code 705 or source code 705, in particular a CPU source code 705. As can be seen in Fig. 7B, the generation 720 of the at least one instruction 715 can be carried out on the basis of a central processing unit (CPU) control part and an FPGA control part.Specifically, this can mean that CPU source code 705 uses the CPU program code and the FPGA program code of the function module 702 of the software library 700. These are compiled in the compiler (from 705 and 700) and the compiler (from 705 and 700), respectively. The result can be the combined code 715, which can be loaded into the IC 600. Executing the code 715 can control the IC 600.

[0145] As can be seen in Fig. 7C, access 710 to and / or selections 710 of one or more function modules 702A-702B, which are included in the, in particular single, interface 700, in particular the software library 700, can take place. According to Fig. 7C, generation 720 of at least one instruction 715 for the integrated circuit 600, in particular the SoC or SiP (cf. Fig. 6), can take place using the one or more function modules 702A-702B. Subsequently, transmission 730, preferably loading 730, of the at least one instruction 715 into the integrated circuit 600, in particular the SoC or SiP (cf. Fig. 6) can take place. In Fig. 7C, access 710 can be initiated by a source code 705 or source code 705, in particular a CPU source code 705. As can be seen in Fig. 7C, the generation 720 of the at least one instruction 715 can be carried out on the basis of a central processing unit (CPU) control part and an FPGA control part.The interface 700, in particular the software library 700, according to Fig. 7C can, for example, comprise a, in particular first, function module 702A that comprises a (first) CPU control part and a (second) FPGA control part, as well as a, in particular second, function module 702B that comprises a (first) CPU control part and a (second) FPGA control part. As can be seen in Fig. 7C, the generation 720 of the at least one instruction 715 can be carried out on the basis of a CPU control part and an FPGA control part of the first function module 702A and on the basis of a CPU control part and an FPGA control part of the second function module 702B. Specifically, this can mean that CPU source code 705 uses the CPU program code and the FPGA program code of the function modules 702A-B of the software library 700. These are compiled in the compiler (from 705 and 700) and the compiler (from 705 and 700).The result can be the common code 715, which can be loaded into IC 600. Executing code 715 can control IC 600. During program execution, the FPGA configuration can be changed via bitstream, resulting in a change in the FPGA's function. This reconfiguration of the FPGA can occur as often as required during program execution.

[0146] Fig. 8 shows a plurality of logical or functional levels, entities or parts of a logical structure or software structure that cover different aspects and / or functions of the SDV. In particular, Fig. 8 shows a plurality of layers 810-830 of an SDV (not shown), which together or as a whole can also be referred to as a stack or layer stack 800 of the SDV. These layers can be hierarchically structured, e.g., top (e.g., uppermost layer; Layer III; 830), middle (e.g., middle layer; Layer II; 820), and base (e.g., lowest layer; Layer I; 810). The layers can, for example, assign specific functions to one or more, in particular zonal, Electronic Control Units (ECUs) of the SDV.

[0147] The plurality of layers 800, as shown in Fig. 8, may comprise, in particular in the following ascending or descending order: a, in particular lowest, base layer 810, a, in particular middle, middleware layer 820, and a, in particular top, application layer 830.

[0148] While the foregoing is directed to embodiments of the disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope being determined by the following claims.

[0149] List of reference symbols

[0150] 100-500 procedures

[0151] 110-410 Control

[0152] 120-420 control accessories

[0153] 505 Access / Select

[0154] 510 Creating an instruction

[0155] 520 Transmit to IC

[0156] 530 Assign, Change

[0157] 540 Tie-up

[0158] 550 Insert

[0159] 560 selections

[0160] 570 Assign / Change based on selection

[0161] 580 Use

[0162] 590 Submit

[0163] 600 Integrated Circuit

[0164] 610 memory

[0165] 620 CPU

[0166] 630 FPGA

[0167] 640 I / O interface

[0168] 700 Software Library

[0169] 702, 702A-B functional module

[0170] 705 Source code

[0171] 710 Access

[0172] 715 Instruction / Code

[0173] 720 Generate

[0174] 730 Submit / Load

[0175] 800 stacks of layers of an SDV

[0176] 810 Base Layer

[0177] 820 Middleware layer

[0178] 830 Application layer

Claims

PATENT CLAIMS 1. Computer-implemented method for adapting, in particular programming, an integrated circuit (IC), in particular a system-on-chip (SoC) or a system-in-package (SiP), a vehicle, in particular a software-defined vehicle (SDV), comprising: Controlling the integrated circuit, in particular the SoC or the SiP, via one, in particular a single, interface, in particular a software library, wherein the interface, in particular the software library, is functionally independent and / or functionally decoupled from a, in particular semiconductor-specific, standard architecture of the integrated circuit, in particular the SoC or the SiP.

2. Computer-implemented method, in particular according to claim 1, for adapting, in particular programming, an integrated circuit (IC), in particular a system-on-chip (SoC) or a system-in-package (SiP), a vehicle, in particular a software-defined vehicle (SDV), wherein the IC, in particular the SoC or the SiP, comprises at least one central processing unit (CPU) and at least one field-programmable gate array (FPGA), in particular an embedded FPGA (E-FPGA), the method comprising: Controlling the integrated circuit, in particular the SoC or the SiP, via one, in particular single, interface, in particular a software library, wherein the integrated circuit, in particular the SoC or the SiP, in particular the CPU and the FPGA, can be controlled cross-functionally by means of the, in particular single, interface, in particular the software library.

3. Computer-implemented method, in particular according to one of claims 1-2, for adapting, in particular programming, an integrated circuit (IC), in particular a system-on-chip (SoC) or a system-in-package (SiP), a vehicle, in particular a software-defined vehicle (SDV), wherein the IC, in particular the SoC or the SiP comprises at least one central processing unit (CPU) and at least one field-programmable gate array (FPGA), in particular an embedded FPGA (E-FPGA), the method comprising: Controlling the integrated circuit, in particular the SoC or the SiP, via one, in particular single, interface, in particular a software library, wherein the control is carried out, at least partially, using a central processing unit (CPU) control part and / or a field-programmable gate array (FPGA) control part of the in particular only interface, in particular the software library.

4. Computer-implemented method, in particular according to one of claims 1-3, for adapting, in particular programming, an integrated circuit (IC), in particular a system-on-chip (SoC) or a system-in-package (SiP), a vehicle, in particular a software-defined vehicle (SDV), wherein the integrated circuit, in particular the SoC or the SiP, comprises at least one central processing unit (CPU) and at least one field-programmable gate array (FPGA), in particular an embedded FPGA (E-FPGA), the method comprising: Controlling the integrated circuit, in particular the SoC or the SiP, via one, in particular single, interface, in particular a software library, wherein the integrated circuit, in particular the SoC or the SiP, in particular the CPU and the FPGA, is updatable and / or expandable in its functions, in particular dynamically, by means of the one, in particular single, interface, in particular the software library.

5. A computer-implemented method according to any one of claims 1-4, wherein the controlling comprises: Accessing and / or selecting one or more functional modules included in the, in particular single, interface, in particular the software library, and generating at least one instruction for the integrated circuit, in particular the SoC or SiP, using the one or more functional modules, and in particular transmitting, preferably loading, the at least one instruction into the integrated circuit, in particular the SoC or SiP.

6. The computer-implemented method of claim 5, wherein the generation of the at least one instruction is performed on the basis of a central processing unit (CPU) control part and / or a field-programmable gate array (FPGA) control part.

7. Computer-implemented method according to one of claims 5-6, wherein the generation of the at least one instruction is carried out on the basis of a CPU control part and an FPGA control part of a first functional module and / or on the basis of a CPU control part and an FPGA control part of a second functional module.

8. A computer-implemented method according to any one of claims 1-7, wherein the controlling comprises: Assigning and / or changing at least one function of the integrated circuit, in particular the SoC or the SiP, by means of the, in particular only, interface, in particular the software library.

9. A computer-implemented method according to any one of claims 1-8, further comprising: Connecting at least one component, in particular a hardware and / or software component, from at least one layer of the SDV to the integrated circuit, in particular the SoC or the SiP, via the interface, in particular the software library.

10. The computer-implemented method of claim 9, further comprising: Connecting at least one hardware component of the SDV, in particular at least one actuator of the SDV and / or at least one sensor of the SDV to the integrated circuit, in particular the SoC or the SiP, via the interface, in particular the software library.

11. A computer-implemented method according to any one of claims 9-10, further comprising: Connecting at least one component, in particular a software component, from an application layer of the SDV to the integrated circuit, in particular the SoC or the SiP, via the interface, in particular the software library, in particular connecting at least one artificial intelligence, Kl, module of the SDV and / or at least one state engine.

12. A computer-implemented method according to any one of the preceding claims, further comprising: Inserting, in particular implementing and / or using, the in particular semiconductor-specific, standard architecture of the integrated circuit, in particular the SoC or the SiP and / or at least one of its functions via the, in particular only, interface, in particular the software library, wherein the insertion is zone-selective and / or zone-specific for the SDV.

13. A computer-implemented method according to any one of the preceding claims, further comprising: Integrating and / or using the, in particular only, interface, in particular the software library, in the SDV, in particular in the base layer of the SDV, and / or in particular in each layer of the SDV.

14. Computer-implemented method according to one of the preceding claims, wherein the, in particular only, interface, in particular the software library, is modularly constructed and / or divided.

15. Computer-implemented method according to one of the preceding claims, wherein the, in particular only, interface, in particular the software library, comprises a plurality of functional modules, in particular for, in particular selective, Control and / or Assigning and / or changing at least one function of the integrated circuit, in particular the SoC or the SiP.

16. The computer-implemented method according to claim 15, wherein the plurality of functional modules comprise: a local functional module for providing the at least one function of the integrated circuit, in particular of the SoC or the SiP, on a local control plane of the SDV; a zonal functional module for providing the at least one function of the integrated circuit, in particular of the SoC or the SiP, on at least one zonal control plane of the SDV; and / or a central functional module for providing the at least one function of the integrated circuit, in particular of the SoC or the SiP, on a central control plane of the SDV.

17. Computer-implemented method according to one of the preceding claims 8-16, wherein the assignment and / or changing of the at least one function of the integrated circuit, in particular of the SoC or the SiP, is carried out on the basis of at least one selected function module of the interface, in particular of the software library.

18. Computer-implemented method according to one of the preceding claims 5-17, wherein each functional module of the plurality of functional modules a central processing unit (CPU) control part and a field programmable gate array (FPGA) control part.

19. A computer-implemented method according to any one of claims 8-18, further comprising: Assigning and / or changing the at least one function of the integrated circuit, in particular the SoC or the SiP, using the CPU control part and / or the FPGA control part.

20. A computer-implemented method according to any one of the preceding claims 6-19, further comprising: Assigning and / or forwarding the CPU control part or at least components thereof, and / or the FPGA control part or at least components thereof, and / or the at least one instruction, to a bitstream to be used in particular for configuring the integrated circuit, in particular the SoC or the SiP.

21. A computer-implemented method according to claim 20, wherein the assigning and / or forwarding takes place at least partially, preferably substantially completely, during a compilation time, the method in particular comprising: Integrating the CPU control part or at least components thereof, and / or the FPGA control part or at least components and / or the at least one instruction thereof in the bitstream.

22. A computer-implemented method according to any one of the preceding claims, wherein the controlling comprises: Transmitting at least one instruction by means of wireless transmission, in particular via over-the-air (OTA) communication, in particular for assigning and / or changing at least one function of the integrated circuit, in particular of the SoC or the SiP or at least one component thereof.

23. A computer program product comprising instructions which, when executed by a computer, cause the computer to carry out the method according to any one of claims 1-22.

24. A computer-readable storage medium comprising instructions which, when executed by a computer, cause the computer to carry out the method according to any one of claims 1-22.

25. Integrated circuit (IC), in particular system-on-chip (SoC) or system-in-package (SiP), for a software-defined vehicle (SDV), comprising: - at least one field-programmable gate array (FPGA), in particular an embedded FPGA (E-FPGA), and - at least one central processing unit (CPU), wherein the integrated circuit, in particular the SoC or the SiP, is and / or can be controlled by means of the method according to one or more of the preceding claims 1-22.

26. Integrated circuit according to claim 25, further comprising: at least one memory, in particular at least one non-volatile Memory.

27. The integrated circuit of any one of the preceding claims 25-26, further comprising: at least one input / output, I / O, interface for establishing a connection to an external device.

28. Integrated circuit according to one of the preceding claims 25-27, wherein the components of the integrated circuit, in particular the SoC or the SiP, are communicatively connected.

29. Software-Defined Vehicle (SDV), comprising: an integrated circuit, in particular a SoC or a SiP, in particular according to one of claims 25-28, and one, in particular single, interface, in particular a software library, for controlling the integrated circuit, in particular the SoC or the SiP, by means of the method according to one or more of the preceding claims 1-22.

30. Software-defined vehicle according to claim 29, wherein the SDV comprises a plurality of layers for controlling and / or managing the SDV, in particular at least one Electronic Control Unit (ECU) of the SDV and / or at least one function of the at least one ECU.

31. Software-defined vehicle according to one of claims 29-30, wherein the SoC or the SiP is included in at least one ECU of the SDV.

32. Software-defined vehicle according to one of claims 31 to 33, wherein the plurality of layers are hierarchically structured, wherein the plurality of layers comprise: a, in particular lowest, base layer, a, in particular middle, middleware layer, and a, in particular top, application layer.

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