Power conversion device

Abstract

In the present invention, a power conversion device (1) comprises: a power converter (20) having at least one leg circuit in which semiconductor switching elements (50) are connected in series; and a semiconductor drive device (10) for driving the semiconductor switching elements (50) on or off. The semiconductor drive device (10) has: a first overcurrent determination unit (17) that determines the overcurrent of the semiconductor switching element (50) on the basis of the potential of an output terminal (Ea) of the leg circuit using the power supply voltage of a DC power supply as a reference voltage; and a second overcurrent determination unit (13) into which a detection signal based on the voltage current between the main terminals of the semiconductor switching element (50) is fed as an input, said second overcurrent determination unit (13) determining the overcurrent flowing through the semiconductor switching element (50). The determining performed by the second overcurrent determination unit (13) precedes the determining performed by the first overcurrent determination unit (17).

Description

Power Conversion Device

[0001] The present disclosure relates to a power conversion device.

[0002] Semiconductor switching elements are used in a variety of power conversion devices. The semiconductor driver that controls the on / off of these semiconductor switching elements is equipped with a protection function that instantly detects overcurrent in the semiconductor switching element caused by an arm short circuit due to a malfunction or failure, and safely stops the power conversion device.

[0003] Methods for overcurrent protection of semiconductor switching elements can be broadly divided into the following two methods. The first method detects an overcurrent state due to a short circuit based on a logical mismatch between the output voltage of the power conversion device, detected using the power supply potential of the power conversion device or a potential electrically connected thereto as a reference potential, and the on / off command signal generated by the control unit (see, for example, Patent Document 1). The second method directly detects the voltage between the main terminals of each semiconductor switching element or the current flowing through the main terminals (see, for example, Patent Document 2).

[0004] In the first method, overcurrent is detected using the power supply potential as a reference potential, and the detection signal is transmitted directly to the control unit, allowing the entire power conversion device to be easily shut down. This allows for a low-cost configuration to achieve the protection function. Furthermore, since the output voltage of the power conversion device is detected, there is also the advantage that control can be performed with high precision using information on the output pulse width of the power conversion device. However, since the voltage between the main terminals of the semiconductor switching elements or the current flowing through the main terminals is not directly detected, there are limitations to the detection precision, making it difficult to detect relatively small overcurrents and to detect them quickly.

[0005] In contrast, the second method detects overcurrents at the reference potential of the semiconductor switching elements, which not only enables high-accuracy and high-speed detection of overcurrent events, but also enables the gate voltage of the semiconductor switching elements to be instantly reduced upon detection of an overcurrent, thereby temporarily mitigating or eliminating the overcurrent state. However, it is then necessary to transmit the detection information to an electrically isolated control unit and shut down the entire power conversion device.

[0006] Conventionally, the protection function of a power conversion device has been realized by using each method depending on its merits. However, by combining the two methods, it is expected that the protection function of the power conversion device will be improved. That is, the second method detects an overcurrent in a semiconductor switching element with high accuracy and speed and controls to temporarily alleviate the overcurrent state, and then the first method detects a continued overcurrent state and transmits the detection result to the control unit to safely shut down the power conversion device.

[0007] Japanese Patent Application Laid-Open No. 10-257779 International Publication No. 2023 / 032024

[0008] However, there is a concern that simply using these two conventional methods in combination may not provide sufficient protection. For example, when a relatively large short-circuit current occurs instantaneously and causes a steep transition in the output voltage of a power conversion device, it is possible that the overcurrent detection by the first method occurs at approximately the same timing as the overcurrent detection by the second method. In this case, the first method turns off the semiconductor switching element to stop the power conversion device, and the second method reduces the gate voltage to alleviate the overcurrent in the semiconductor switching element. This results in a faster-than-normal turn-off of the semiconductor switching element, generating an excessive surge voltage. This excessive surge voltage may then cause secondary damage to the semiconductor switching element. Therefore, a technology that combines the two methods and solves this problem is desired.

[0009] The present disclosure discloses a technique for solving the above-described problems, and aims to provide a highly reliable power conversion device by protecting semiconductor switching elements and a power conversion device from overcurrent using the above-described two methods.

[0010] a gate drive unit that applies a voltage to the control terminal of the semiconductor switching element based on the on / off command signal; a first overcurrent determination unit that determines an overcurrent of the semiconductor switching element based on a potential of an output terminal of the leg circuit, using a power supply voltage of a DC power supply as a reference voltage; and an overcurrent protection unit that protects the semiconductor switching element by receiving a detection signal based on a voltage current between main terminals of the semiconductor switching element and determining an overcurrent flowing through the semiconductor switching element, and a gate voltage reduction unit that reduces the voltage applied to the control terminal when an overcurrent is determined, wherein the overcurrent determination by the second overcurrent determination unit precedes the overcurrent determination by the first overcurrent determination unit. When the first overcurrent determination unit determines that an overcurrent has occurred, the control unit controls at least the semiconductor switching element of the leg circuit determined to be experiencing an overcurrent to an off state.

[0011] According to the present disclosure, it is possible to provide a highly reliable power conversion device that protects semiconductor switching elements and a power conversion device from overcurrent.

[0012] FIG. 1 is a block diagram showing a schematic configuration of a power conversion device according to a first embodiment. FIG. 2 is a diagram showing a schematic configuration of a power conversion device according to the first embodiment. FIG. 3 is a diagram showing a circuit configuration of an overcurrent protection unit according to the first embodiment. FIG. 4 is a waveform diagram of each unit showing the operation of the power conversion device according to the first embodiment. FIG. 5 is a diagram showing a circuit configuration of an overcurrent protection unit according to the second embodiment. FIG. 6 is a waveform diagram of each unit showing the operation of the power conversion device according to the second embodiment. FIG. 7 is a diagram showing a schematic configuration of a power conversion device according to the seventh embodiment. FIG. 8 is a diagram showing a schematic configuration of a power conversion device according to the eighth embodiment. FIG. 9 is a diagram showing a circuit configuration of an overcurrent protection unit according to the eighth embodiment. FIG. 10 is a waveform diagram of each unit showing the operation of the power conversion device according to the eighth embodiment. 12 is a diagram showing a configuration of a power conversion device according to embodiment 9. FIG. 13 is a diagram showing another configuration of a power conversion device according to embodiment 9. FIG. 14 is a diagram showing yet another configuration of a power conversion device according to embodiment 9. FIG. 15 is a diagram showing a schematic configuration of a power conversion device using another semiconductor switching element. FIG. 16 is a diagram showing a hardware configuration of a control unit of the power conversion devices according to embodiments 1 to 9.

[0013] The present embodiment will be described below with reference to the drawings, in which the same reference numerals indicate the same or corresponding parts.

[0014] Embodiment 1. A power conversion device according to Embodiment 1 will now be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a power conversion device 1 according to Embodiment 1. In FIG. 1, the power conversion device 1 includes a power converter 20 having semiconductor switching elements and converting power from a DC power supply (not shown) to supply power to a load 70, and a semiconductor drive device 10 that drives the semiconductor switching elements of the power converter 20. The semiconductor drive device 10 includes a control unit 18 that receives a command signal SIN transmitted from a higher-level control device (not shown) and generates an on / off command signal for the semiconductor switching elements based on a signal from a first overcurrent determination unit 17, a gate drive unit 11 that applies a voltage to the semiconductor switching elements to drive them based on the on / off command signal input via an insulated communication unit 16, and an overcurrent protection unit 12 that detects and protects the semiconductor switching elements from overcurrent. Next, a detailed circuit configuration will be described with reference to FIGS. 2 and 3.

[0015] FIG. 2 is a diagram showing the circuit configuration of the main components of the power conversion device according to the first embodiment, and FIG. 3 is a diagram showing the circuit configuration of the overcurrent protection unit 12. The power converter 20 includes an arm section in which a semiconductor switching element 50a and a semiconductor switching element 50b are connected in series. An on / off command signal GDOa output from the control unit 18 is input to the gate driver 11a via the insulated communication unit 16a, and a voltage based on this on / off command signal GDOa is applied to the control terminal (hereinafter, gate terminal) Ga of the semiconductor switching element 50a in the upper arm. An overcurrent protection unit 12a is also provided, which detects an overcurrent flowing through the semiconductor switching element 50a and reduces the gate voltage if an overcurrent is detected. Similarly, an on / off command signal GDOb output from the control unit 18 is input to the gate driver 11b via the insulated communication unit 16b, and a voltage based on this on / off command signal GDOb is applied to the gate terminal Gb of the semiconductor switching element 50b in the lower arm. An overcurrent protection unit 12b is also provided which detects an overcurrent flowing through the semiconductor switching element 50b and reduces the gate voltage if it is determined that an overcurrent is flowing.

[0016] As described above, the functional units and the semiconductor switching elements 50a, 50b related to the control of the upper and lower arms are equivalent, and in the following description, the reference numerals may be appended with "a" or "b," respectively, or the description of one of them may be omitted. Also, the functional units may be collectively referred to without the "a" or "b." While FIG. 2 shows an example of a single-phase power converter 20 with one leg circuit formed by upper and lower arms, the power converter 20 may be a three-phase power converter with, for example, three leg circuits connected in parallel. The power converter 20 includes at least one leg circuit.

[0017] The semiconductor driver 10 controls the conductive / non-conductive state between the collector C and emitter E, which are the main terminals of the semiconductor switching element 50, by a gate voltage Vge applied between a gate terminal G and a reference terminal (hereinafter referred to as an emitter control terminal) ES. In this case, an IGBT is shown as an example of the semiconductor switching element 50, but the invention can also be applied to other semiconductor switching elements, such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) having a control terminal.

[0018] The overcurrent protection unit 12 is disposed immediately adjacent to or immediately above the semiconductor switching element 50, and the gate drive unit 11 and the overcurrent protection unit 12 are connected by two connection wires 15. As will be described in detail later, the overcurrent protection unit 12 includes a second overcurrent determination unit 13 and a gate voltage reduction unit 14. The gate drive unit 11 includes an output stage circuit composed of a positive power supply PG1 and a negative power supply PG2, a P-type MOSFET MG1 and an N-type MOSFET MG2, and gate resistors RG1 and RG2, and is connected to a control unit 18 that controls this output stage circuit via an insulated communication unit 16. The emitter control terminal ES of the semiconductor switching element 50 is connected to a reference potential VG0 at the connection point between the positive power supply PG1 and the negative power supply PG2.

[0019] As described above, the control unit 18 receives the command signal SIN transmitted from the higher-level control device (not shown), and controls the output stage circuit via the insulating communication unit 16 based on the determination signal OCD1 from the first overcurrent determination unit 17. The control unit 18 may control the output stage circuit by logically combining the determination signal OCD1 with various abnormality detection signals such as overtemperature or power supply drop. The operation of the first overcurrent determination unit 17 will be described later.

[0020] The insulating communication unit 16 is configured to electrically insulate the input from the output and transmit an instruction signal from the input to the output, and receives an on / off command signal GDO generated by the control unit 18 and outputs it to the gates of the P-type MOSFET MG1 and the N-type MOSFET MG2 of the gate drive unit 11. The insulating communication unit 16 is configured, for example, by a photocoupler, but may be configured by means other than a photocoupler as long as it is configured to electrically insulate the input from the output and to transmit an instruction signal from the input to the output.

[0021] In addition, in the gate driver 11, an example is shown in which the output stage circuit outputs a positive power supply potential VG1 or a negative power supply potential VG2, but a configuration without using a negative power supply PG2, i.e., a configuration in which the negative power supply potential VG2 is equal to the reference potential VG0, is also possible. In this case, a constant voltage drive is shown in which a P-type MOSFET MG1 and an N-type MOSFET MG2 are used as the output stage buffer of the gate driver 11, and the switching speed is adjusted by gate resistors RG1 and RG2, but the present invention is not limited to this.

[0022] The overcurrent protection unit 12 includes a second overcurrent determination unit 13 that determines whether an overcurrent flows through the semiconductor switching element 50, and a gate voltage reduction unit 14 that, when an overcurrent is determined, reduces the voltage applied to the gate terminal G of the semiconductor switching element 50. Note that, although Fig. 2 simply shows the structure of the overcurrent protection unit 12b connected to the lower arm, as described above, the structure of the overcurrent protection unit 12a connected to the upper arm is similar to the structure of the overcurrent protection unit 12b.

[0023] The second overcurrent determination unit 13 includes a first transistor Q1, a clamp diode D1, and a low-pass filter (R, C1) made up of a resistor R and a capacitor C1. A detection signal SOC based on a collector voltage Vce, which is the voltage between the main terminals of the semiconductor switching element 50, is input to the first transistor Q1 via the low-pass filter (R, C1), and the first transistor Q1 outputs an overcurrent determination signal OCD2.

[0024] In this case, when the first transistor Q1 is turned on, the determination signal OCD2 changes and an overcurrent is determined in the semiconductor switching element 50. The gate voltage reducing unit 14 receives the overcurrent determination signal OCD2 and operates to reduce the gate voltage Vge applied to the gate terminal G to a level lower than the voltage (VG1) of the positive power supply PG1. The detection signal SOC input to the second overcurrent determining unit 13 is the voltage (collector voltage Vce) at the collector sense terminal CS.

[0025] FIG. 2 shows the parasitic inductance Lc between the collector C and the collector sense terminal CS, and the parasitic inductance Le between the emitter E and the emitter control terminal ES (reference symbols not shown). The emitter control terminal ES and the collector sense terminal CS are typically located close to the main element to minimize the parasitic inductance L on the main element side. This eliminates the effects of the electromotive force (L·dI / dt) caused by the parasitic inductance L. Semiconductor switching elements 50 used in large-capacity power modules and the like typically have an emitter control terminal ES to prevent a drop in the gate voltage Vge due to the electromotive force (L·dI / dt). Furthermore, when detecting the collector voltage Vce, a collector sense terminal CS is provided to detect the collector voltage Vce while preventing the addition of extra voltage due to the electromotive force (L·dI / dt).

[0026] In this embodiment, the case where the emitter control terminal ES and the collector sense terminal CS are provided is shown, but it is also possible to use the emitter E and the collector C, which are the main terminals used by the semiconductor switching element 50 to connect to external elements, without providing the emitter control terminal ES and the collector sense terminal CS. The collector voltage Vce in this embodiment is slightly different from the voltage between the actual main terminals (collector C, emitter E), but is the voltage between the main terminals (Vce) used for control.

[0027] FIG. 3 is a circuit diagram showing details of the overcurrent protection unit 12 according to the first embodiment. Details of the circuit configuration and the basic operation of the overcurrent protection unit 12 are described below. As described above, when the overcurrent protection unit 12 is for the upper arm, the reference numerals of the components in FIG. 3 are marked with "a," and when the overcurrent protection unit 12 is for the lower arm, the reference numerals of the components are marked with "b." As shown in FIG. 3 , the overcurrent protection unit 12 includes a second overcurrent determination unit 13 that receives the detection signal SOC and outputs an overcurrent determination signal OCD2, and a gate voltage reduction unit 14 that reduces the gate voltage Vge based on the determination signal OCD2. The gate voltage reduction unit 14 also includes a drive circuit 141 that reduces the gate voltage Vge, and an amplifier circuit 142 that amplifies the output signal from the second overcurrent determination unit 13 to drive the drive circuit 141.

[0028] The second overcurrent detector 13 includes series-connected resistors R1, R2, R3, and R4, a clamp diode D1, and a capacitor C1. It also includes a series circuit consisting of a first transistor Q1 (an NPN bipolar transistor), resistors R5 and R6, and a reverse current prevention diode D3. Capacitor C2 is connected in parallel with resistor R6, and a protection diode D2 is provided between the base and emitter of the first transistor Q1. In this case, the resistor R (composed of the three resistors R1, R2, and R3) and capacitor C1 form a low-pass filter (R, C1). A junction P1 between resistor R (R1, R2, and R3) and resistor R4 serves as an input for the detection signal SOC and is connected to the base of the first transistor Q1. The potential at junction P1, which corresponds to the base potential of the first transistor Q1 relative to the emitter control terminal ES, is defined as an input potential VA1.

[0029] The anode of the clamp diode D1 is connected to the capacitor C1 of the low-pass filter (R, C1), and the connection point is connected to the connection point P1 and the base of the first transistor Q1. The detection signal SOC is divided by resistors R1, R2, R3, and R4 and input to the base of the first transistor Q1 via the low-pass filter (R, C1) composed of the voltage-dividing resistor R (R1, R2, R3) and the capacitor C1. When the semiconductor switching element 50 is in the off state, the base of the first transistor Q1 is clamped to the negative power supply potential VG2 by the clamp diode D1. Note that, although an example is shown in which the clamp diode D1 is connected to the output side of the low-pass filter (R, C1), it may also be connected to the input side of the low-pass filter (R, C1).

[0030] In this case, when the semiconductor switching element 50 is turned off, the gate driver 11 negatively biases the gate voltage Vge, so that the base potential and collector potential of the first transistor Q1 are also negatively biased. For this reason, a protection diode D2 and a backflow prevention diode D3 are provided to protect the first transistor Q1. The protection diode D2 is an anti-parallel diode typically used in bipolar transistors, and prevents a large negative voltage from being applied between the base and emitter of the first transistor Q1, which would otherwise deteriorate its characteristics.

[0031] The blocking diode D3 protects the first transistor Q1 by preventing current from flowing backward in the conduction direction of the first transistor Q1. In this case, when the first transistor Q1 is off, a negative voltage is applied to the gate terminal G, preventing reverse bias between the collector and emitter of the first transistor Q1 for protection. The blocking diode D3 is also provided on the emitter side of the first transistor Q1, and can raise the voltage level required to turn on the first transistor Q1, based on the base potential (input potential VA1) of the first transistor Q1 relative to the emitter control terminal ES. This improves resistance to voltage-related noise. The blocking diode D3 may also be provided on the collector side of the first transistor Q1.

[0032] The base and emitter of a bipolar transistor are a PN junction, just like a diode. For simplicity's sake, the base threshold voltage, which is the voltage between the base and emitter required to turn on the bipolar transistor, and the forward voltage of the diode are both defined as Vf. In this case, an overcurrent is detected when the first transistor Q1 turns on. The base potential (input potential VA1) when the first transistor Q1 turns on is expressed by the following equation (1): VA1=Vce×R4 / (R1+R2+R3+R4)=2Vf (1)

[0033] When the semiconductor switching element 50 is turned off, the base potential (input potential VA1) of the first transistor Q1 is immediately negatively biased by the action of the clamp diode D1. This makes it possible to prevent erroneous detection of an overcurrent due to an increase in the collector voltage Vce when the semiconductor switching element 50 is turned off. Furthermore, by negatively biasing the initial state of the capacitor C1 in the low-pass filter (R, C1), it is possible to prevent erroneous detection of an overcurrent during the period until the collector voltage Vce drops when the semiconductor switching element 50 is turned on.

[0034] Next, the amplifier circuit 142 in the gate voltage reduction unit 14 amplifies the determination signal OCD2 from the second overcurrent determination unit 13. It includes a series circuit consisting of a second transistor Q2, a PNP bipolar transistor, and resistors R7 and R8. A capacitor C3 is connected in parallel with the resistor R8, and a protective diode D4 is provided between the base and emitter of the second transistor Q2. The voltage of the determination signal OCD2 is applied to the base of the second transistor Q2. The drive circuit 141 in the gate voltage reduction unit 14 amplifies the output signal from the second overcurrent determination unit 13. It includes a series circuit consisting of a third transistor Q3, an NPN bipolar transistor, a resistor R10, and a diode D6. A resistor R9 is provided between this series circuit and the base of the second transistor Q2, and a protective diode D5 is provided between the base and emitter of the third transistor Q3.

[0035] When the first transistor Q1 turns on and determines that the semiconductor switching element 50 is in an overcurrent state, the second transistor Q2 turns on, and then the third transistor Q3 turns on. Specifically, the operation is as follows. When the semiconductor switching element 50 is in a normal on-state, the first transistor Q1 is off, and therefore the potential of the determination signal OCD2, i.e., the base potential of the second transistor Q2, is the same as the gate potential (positive power supply potential VG1) of the semiconductor switching element 50. When an overcurrent occurs and the first transistor Q1 turns on, the potential of the determination signal OCD2 drops, and when it drops to a potential (VG1-Vf) that is lower than the positive power supply potential VG1 by the threshold voltage Vf of the second transistor Q2, the second transistor Q2 turns on.

[0036] The resistors R5 and R6 connected in series to the first transistor Q1 are set in advance to satisfy the following formula: (VG1-Vf) x R6 / (R5+R6)>Vf

[0037] When the second transistor Q2 turns on, the collector potential of the second transistor Q2 rises to the positive power supply potential VG1, which causes the base potential of the third transistor Q3 to rise, and a voltage equal to or greater than the threshold voltage Vf is applied to the base of the third transistor Q3, turning on the third transistor Q3.

[0038] The resistors R7 and R8 connected in series to the second transistor Q2 are set in advance to satisfy the following formula: VG1×R8 / (R7+R8)>Vf

[0039] In this way, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are sequentially turned on. Then, a gate discharge current IA that discharges the capacitance (gate charge) between the gate and emitter of the semiconductor switching element 50 flows through the third transistor Q3, reducing the gate voltage Vge. This makes it possible to suppress overcurrent in the semiconductor switching element 50.

[0040] In the semiconductor switching element 50, the gate input capacitance increases as the current capacity increases. Therefore, in order to reduce the gate voltage Vge of the semiconductor switching element 50 with a large current capacity and protect it from overcurrent, it is necessary to discharge a large amount of gate charge. For example, in the case of a semiconductor switching element 50 with a current capacity of several hundred amperes, it is necessary to flow a gate discharge current IA of several amperes.

[0041] The base current of the first transistor Q1 is determined by the constraint of minimizing the parasitic leakage current, i.e., heat generation, during the period when the semiconductor switching element 50 is off, and therefore the collector current of the first transistor Q1 is also limited. The base current of the first transistor Q1, which becomes the parasitic leakage current, is approximately 1 mA. Considering the temperature and frequency characteristics, the current amplification factor of the first transistor Q1 and the third transistor Q3 is, for example, approximately 30. If two-stage current amplification were performed without the amplifier circuit 142, only a gate discharge current IA of approximately 1 A or less would be possible. In this case, by sequentially turning on the first transistor Q1, the second transistor Q2, and the third transistor Q3, the base current increases sequentially, and the three-stage current amplification achieves the discharge of a large gate charge in a short period of time. The three-stage current amplification allows for a gate discharge current IA of, for example, several tens of amperes.

[0042] It should be noted that the drive circuit 141 in the gate voltage reducing unit 14 can operate even without the amplifier circuit 142, and therefore can be omitted as necessary.

[0043] Generally, when the third transistor Q3 turns on and the gate voltage Vge is reduced, this operation causes the overcurrent detection signal SOC to approach a non-overcurrent state, the operation of reducing the gate voltage Vge is canceled, and the overcurrent state reoccurs, resulting in an oscillation that repeats this process. In this embodiment, the resistor R9 is provided to provide deep hysteresis to the overcurrent determination operation, thereby preventing this oscillation. That is, when the third transistor Q3 turns on, the resistor R9 acts to reduce the base potential of the second transistor Q2, and the overcurrent determination operation is maintained for a predetermined period of time. As a result, the gate voltage reducing unit 14 continues to reduce the gate voltage Vge for the predetermined period of time.

[0044] The value of resistor R10, which determines the gate discharge current IA that flows during overcurrent protection, must be designed to prevent a surge voltage that occurs when the gate voltage Vge of the semiconductor switching element 50 suddenly drops to a value equal to or lower than the gate threshold voltage Vth, and is set to satisfy, for example, the following equation (2): (VG1-VG0) x R10 / (RG1+R10)>Vth (2)

[0045] In addition, since the semiconductor switching element 50 is generally provided with an internal gate resistor, in practice, even if the above formula (2) is not satisfied, the gate voltage inside the semiconductor switching element 50 will be maintained higher than the gate threshold voltage Vth as long as the period during which the gate voltage Vge is reduced is short. Therefore, the surge voltage may not be a problem.

[0046] Next, the first overcurrent determination unit 17 will be described with reference to FIG. 2. The first overcurrent determination unit 17 includes a first comparator VHD that determines whether the potential of the output terminal Ea of the power converter 20, which is made up of upper and lower arms, is near a positive electrode potential, and a second comparator VLD that determines whether the potential of the output terminal Ea is near a negative electrode potential. The first overcurrent determination unit 17 further includes a logic synthesis unit 171 that detects an overcurrent in the semiconductor switching elements 50a, 50b based on the outputs of the first comparator VHD and the second comparator VLD and on / off command signals GDOa, GDOb that control the on / off of the semiconductor switching elements 50a, 50b, and outputs a determination signal OCD1 to the control unit 18. The first overcurrent determination unit 17 will be described in detail below.

[0047] The potential at the junction P0 is divided by resistors R173, R174, R175 and resistors R177, R178 and input as a reference voltage to the negative input terminal of the first comparator VHD, and the potential at the emitter control terminal ESa of the semiconductor switching element 50a is divided by resistors R170, R171, R172 and resistor R176 and input as a reference voltage to the positive input terminal of the second comparator VLD, and the potential at the junction P0 is divided by resistors R173, R174, R175, R178 and resistor R177 and input as a reference voltage to the negative input terminal of the second comparator VLD.

[0048] Although the potential of the emitter control terminal ESa of the semiconductor switching element 50a is strictly different from the potential of the output terminal Ea of the power converter 20, they are equivalent in a steady state after the switching of the semiconductor switching element 50a is complete. Therefore, assuming this state, the two will be treated as equivalent here. While the upper-arm semiconductor switching element 50a is on, the potential of the output terminal Ea is the positive potential of a current power supply (not shown). While the lower-arm semiconductor switching element 50b is on, the potential of the output terminal Ea is the negative potential of the current power supply (not shown). Therefore, the potential of the emitter control terminal ESa or the potential of the output terminal Ea of the power converter 20 corresponds to the output potential of the leg circuit. Furthermore, one end of the wiring connected to the connection point P0 is connected to the positive side of a DC power supply (not shown) and the other end is connected to the positive side of the upper arm. The potential of the connection point P0 is the power supply potential, which corresponds to the positive-negative voltage of the leg circuit consisting of the upper and lower arms. Therefore, by generating the reference voltages of the first comparator VHD and the second comparator VLD from the main circuit power supply voltage, the robustness of the voltage determination accuracy against fluctuations in the main circuit power supply voltage is improved.

[0049] Here, resistors R170, R171, and R172 and a capacitor C170 constitute a low-pass filter LF1. Also, a bypass capacitor for stabilizing the reference voltage input to the negative input terminal of the first comparator VHD and the positive input terminal of the second comparator VLD is omitted.

[0050] The first comparator VHD and the second comparator VLD are configured as window comparators. The first comparator VHD compares the divided potential of the emitter control terminal ESa with a reference voltage and outputs a high (H) signal if the voltage is within a preset range. That is, it determines that the potential of the emitter control terminal ESa is near a positive potential. Similarly, the second comparator VLD compares the divided potential of the emitter control terminal ESa with a reference voltage and outputs a high (H) signal if the voltage is within a preset range. That is, it determines that the potential of the emitter control terminal ESa is near a negative potential. Note that the potential of the emitter control terminal ESa does not have to be the same as the power supply potential; as long as it is within a certain range, it can be considered to be the power supply potential. Here, the term "near" is used because a potential within a preset range of the power supply potential can be considered to be at or near that potential. The setting value of the window comparator is set to a value that can be considered to be near that potential.

[0051] The outputs of the first comparator VHD and the second comparator VLD are input to the logic synthesis unit 171 and subjected to a logical operation with the input on / off command signals GDOa and GDOb. The on / off command signal GDOa for the upper arm is output in a state that is substantially inverted from the on / off command signal GDOb. Under normal conditions, when the on / off command signal GDOa is output (high: H), the upper arm semiconductor switching element 50a is on and the potential of the emitter control terminal ESa is near the positive potential of the current power supply (not shown), so the output from the first comparator VHD is high. In this case, the logic synthesis unit 171 outputs the determination signal OCD1 as low (L). Similarly, under normal circumstances, when the on / off command signal GDOb is being output (high: H), the lower arm semiconductor switching element 50b is in the on-state, and the potential of the emitter control terminal ESa is close to the negative potential of the current power supply (not shown), so the output from the second comparator VLD is high. In this case, the logic synthesis unit 171 outputs the determination signal OCD1 at low (L).

[0052] If any other case continues for a preset time or longer, it is determined that an overcurrent has flowed in one of the arms, and the logic synthesis unit 171 outputs a high (H) determination signal OCD1 to the control unit 18. During the dead time and voltage transition period when the semiconductor switching elements 50a and 50b are switching, the on / off command signals GDOa and GDOb and the outputs of the first and second comparators VHD and VLD are in a state different from the normal state described above. To avoid erroneously detecting this state as an overcurrent state, it is determined whether an overcurrent has flowed based on whether the state has continued for a preset time or longer.

[0053] When the control unit 18 receives the high (H) determination signal OCD1, it stops the operation of the power converter 20 without outputting the on / off command signals GDOa and GDOb.

[0054] FIG. 4 is a waveform diagram of each component showing the operation of the power conversion device 1 according to the first embodiment. Details of the overcurrent protection operation of the power conversion device 1 will be described below with reference to FIGS. 2, 3, and 4. Here, an example in which a fault occurs in the upper arm will be described. During normal operation before time t0, the lower arm outputs a gate voltage Vgeb in response to an on / off command signal GDOb generated by a command signal SIN transmitted from a higher-level control device. The collector current Icb of the semiconductor switching element 50b and the collector voltage Vceb serving as the detection signal SOCb also have waveforms corresponding to the on / off command signal GDOb. When the semiconductor switching element 50b is in the off state, the base potential (input potential) VA1b of the first transistor Q1b, relative to the emitter control terminal ESb, is clamped to a potential (VG2b+Vf) obtained by adding the forward voltage Vf of the clamp diode D1b to the negative power supply potential VG2b. Furthermore, when the semiconductor switching element 50b is in the ON state, the collector voltage Vceb drops to several volts, and the voltage VA1b divided by the resistors Rb (R1b, R2b, R3b) and R4b becomes close to the reference potential VG0b.

[0055] The potential of the determination signal OCD2b, i.e., the base potential of the second transistor Q2b, is the same as the gate potential (positive power supply potential VG1b) when the semiconductor switching element 50b is in the on state, and is pulled down to the negative power supply potential VG2b when the semiconductor switching element 50b is in the off state. Note that since the on / off command signal GDOa for the upper arm is approximately inverted from the on / off command signal GDOb, the collector voltage Vcea which serves as the detection signal SOCa of the semiconductor switching element 50a of the upper arm also has a waveform which is approximately inverted from the collector voltage Vceb of the lower arm.

[0056] The output waveform of the second comparator VLD is a waveform corresponding to the on / off command signal GDOb for the lower arm, and the output waveform of the first comparator VHD is a waveform that is inverted from the on / off command signal GDOb for the lower arm. That is, when the on / off command signal GDOb for the lower arm is high, the output waveform of the second comparator VLD is high and the output waveform of the first comparator VHD is low. When the on / off command signal GDOb for the lower arm is low, the output waveform of the second comparator VLD is low and the output waveform of the first comparator VHD is high. Note that in Figure 4, because the on / off duty of the semiconductor switching element is not 50%, the output waveforms of the first comparator VHD and the second comparator VLD are not completely inverted in phase.

[0057] Assume that a fault occurs in the upper arm at time t0. At this time, the upper arm on / off command signal GDOa (not shown) transitions from high to low, turning off the semiconductor switching element 50a, and the collector voltage Vcea should be maintained at a high voltage. However, due to the fault (voltage resistance abnormality) in the upper arm, the collector voltage Vcea begins to drop while it was rising. As a result, the output waveform of the first comparator VHD also drops in a pulse-like manner in response to the collector voltage Vcea.

[0058] Subsequently, at time t1, the upper arm remains conductive due to the fault, so the lower arm on / off command signal GDOb goes high, turning on the semiconductor switching element 50b, and an overcurrent occurs due to an arm short circuit. As a result, the peak value Icbp of the collector current Icb saturates, and the collector voltage Vceb, which normally decreases, becomes high. This causes the base potential (input potential) VA1b of the first transistor Q1b to rise above the reference potential VG0b. Normally, the output of the first comparator VHD would switch low at this time, but the high state is maintained due to the overcurrent.

[0059] At time t2, the base potential (input potential) VA1b of the first transistor Q1b rises to 2Vf, i.e., when the above formula (1) is satisfied, the first transistor Q1b turns on. This detects an overcurrent in the semiconductor switching element 50b. When the first transistor Q1b turns on, the potential of the determination signal OCD2b drops. When it drops from the positive power supply potential VG1b to a potential (VG1b - Vf) that is lower than the threshold voltage Vf of the second transistor Q2b, the second transistor Q2b turns on. This also increases the base potential of the third transistor Q3b, applying a voltage equal to or greater than the threshold voltage Vf to the base and turning on the third transistor Q3b. This causes a gate discharge current IAb to flow, reducing the gate voltage Vgeb. At this time, the collector current Icb decreases from its peak value Icbp to a value Icba corresponding to the reduced gate voltage Vgeb, generating a surge voltage Vsa in the collector voltage Vceb.

[0060] At time t3, first overcurrent determination unit 17 detects an overcurrent in power converter 20, causing determination signal OCD1 to go high. Between time t3 and time t4, control unit 18 stops the operation of power converter 20. Specifically, it stops the on / off command signals GDOa and GDOb and performs a current interruption operation on semiconductor switching elements 50a and 50b to turn them off. At this time, surge voltage Vsb is generated in collector voltage Vceb.

[0061] When the control unit 18 turns off the semiconductor switching element 50, if the gate voltage Vgeb is too large even after being reduced, there is a concern that a sudden current interruption will occur, causing a surge voltage to degrade the semiconductor switching element 50. For this reason, it is desirable to adjust the value of the resistor R10 so that the surge voltage Vsa generated in the collector voltage Vce during the protection operation and the surge voltage Vsb generated in the collector voltage Vceb when the semiconductor switching element 50 is subsequently turned off are approximately the same. This eliminates the need to provide a separate function, a so-called soft shutdown function, that increases the gate resistance when the control unit 18 turns off the semiconductor switching element 50 compared to when it is normally off.

[0062] Immediately after time t0 in FIG. 4 , the logic synthesis unit 171 of the first overcurrent determination unit 17 should output a high determination signal OCD1 because the output waveform of the first comparator VHD went low, even though the on / off command signal GDOa switched low. However, in this embodiment, the determination signal OCD1 is generated at time t3, which is later than time t0. If, at time t0, the first overcurrent determination unit 17 detects an overcurrent in the power converter 20, the determination signal OCD1 goes high, and the control unit 18 controls the semiconductor switching element 50 to turn off in order to shut down the power converter 20, the problem described above occurs. That is, the turning-off operation of the semiconductor switching element 50 and the gate voltage reduction operation by the overcurrent protection unit 12 to mitigate the overcurrent in the semiconductor switching element 50 occur simultaneously, causing the turn-off operation of the semiconductor switching element 50 to be faster than normal. This results in an excessive surge voltage. This excessive surge voltage may cause secondary damage to the semiconductor switching element 50 .

[0063] In this embodiment, the determination signal OCD1 that can be generated at time t0 is controlled to be delayed until time t3, thereby suppressing the generation of an excessive surge voltage and preventing the semiconductor switching element 50 from suffering secondary damage.

[0064] Next, the timing for outputting the determination signal OCD1 will be described. (1) Method for Delaying the Output of the Determination Signal OCD1 Because the second overcurrent determination unit 13 and the first overcurrent determination unit 17 of the overcurrent protection unit 12 each include a low-pass filter, one method is to set the time constant of the low-pass filter LF1 of the first overcurrent determination unit 17 to be larger than the time constant of the low-pass filter of the second overcurrent determination unit 13. The low-pass filter (R, C1) of the second overcurrent determination unit 13, together with the clamp diode D1, has a time constant and other settings that are set to suppress malfunctions due to noise and provide overcurrent protection. Therefore, by setting the time constant of the low-pass filter LF1 of the first overcurrent determination unit 17 to be larger than the time constant, the generation of the determination signal OCD1 can be delayed from time t0. Methods for delaying the generation of the determination signal OCD1 are not limited to adjusting the time constant. For example, the output of the determination signal OCD1 can be delayed by providing a signal mask circuit in the logic synthesis unit 171 of the first overcurrent determination unit 17 that inhibits output for a certain period of time. The signal masking circuit is, for example, a timer.

[0065] (2) Timing for Outputting the Determination Signal OCD1 The determination signal OCD1 is output, turning off the semiconductor switching element 50, and shutting down the power converter 20 during the time (short-circuit tolerance time) after the gate voltage Vge of the semiconductor switching element 50 is reduced until the short-circuit tolerance of the semiconductor switching element 50 is reached. Specifically, as shown in FIG. 4 , this time is after the collector current Icb is reduced from its peak value Icbp to a value Icba due to the gate voltage reduction operation. In other words, this time is after the gate discharge current IAb begins to flow. For example, if the time from the occurrence of an overcurrent due to a fault (time t0) until the semiconductor switching element 50 reaches its short-circuit tolerance is 10 μs, the time (t3) at which the determination signal OCD1 is output is preferably approximately 7 or 8 μs. In this case, the secondary breakdown described above can be prevented by adjusting the timing at which the overcurrent protection unit 12 reduces the gate voltage of the semiconductor switching element 50 to approximately half that time, for example, approximately 3 or 4 μs.

[0066] As described above, after the second overcurrent determination unit 13 detects an overcurrent, the gate voltage reducing unit 14 maintains the operation of reducing the gate voltage Vge for a predetermined time, but it is desirable that the maintenance time exceed the time when the first overcurrent determination unit 17 determines an overcurrent. That is, the state of reducing the gate voltage Vge is released before the time when the first overcurrent determination unit 17 determines an overcurrent, and so that an excessive short-circuit current does not occur again, the predetermined time period during which the state of reducing the gate voltage Vge is maintained should be set to be longer than the time difference between the time when the second overcurrent determination unit 13 determines an overcurrent and the time when the first overcurrent determination unit 17 determines an overcurrent.

[0067] 5 is a waveform diagram of each part showing the operation of the power conversion device 1 when a fault occurs in the lower arm at time t0a. In FIGS. 4 and 5, the on / off duty of the semiconductor switching elements is not 50%, so the waveforms of each part in FIGS. 4 and 5 are not completely inverted in phase. However, the behavior of each part of the overcurrent protection unit 12a connected to the upper arm in order from time t0a to time t1a is the same as that of the overcurrent protection unit 12b in FIG. 4, and the first overcurrent determination unit 17 also detects an overcurrent in the power converter 20 and the determination signal OCD1 goes high, so a description thereof will be omitted.

[0068] The functions of the clamp diode D1 and the low-pass filter (R, C1) are described below. When the collector voltage Vce is used as the detection signal SOC as in this embodiment, if the timing at which the collector voltage Vce changes due to switching exceeds the design range, or if the voltage amplitude of the collector voltage Vce exceeds the design range, erroneous detection of an overcurrent may occur.

[0069] For example, the former occurs when the drop in collector voltage Vce is delayed due to noise or other factors during an on-state of the semiconductor switching element 50. In this case, the gate voltage Vge rises, preventing the clamp diode D1 from clamping the input potential VA1, resulting in the delayed drop in collector voltage Vce, i.e., a normal on-state operation, being erroneously determined as an overcurrent. On the other hand, the latter occurs when electric field coupling or magnetic coupling noise is superimposed on the semiconductor switching element 50 during an off-state or recovery state. When the clamp diode D1 clamps the input potential VA1, voltage or current changes at the main terminal of the semiconductor switching element 50 can cause noise equal to or greater than the threshold voltage to be superimposed on the input potential VA1, i.e., the base of the first transistor Q1. In this case, a normal off-state or recovery state of the semiconductor switching element 50 is erroneously determined as an overcurrent.

[0070] In this embodiment, the provision of a clamp diode D1 that clamps the input potential VA1 to the gate potential prevents erroneous detection of an overcurrent due to noise when the semiconductor switching element 50 is in the off state. Furthermore, the provision of the clamp diode D1 and the low-pass filter (R, C1) also makes it possible to suppress the above-mentioned erroneous detection of an overcurrent.

[0071] For example, the problem of false detection during ON operation of the semiconductor switching element 50 can be improved as follows. During the delay period from when the clamp diode D1 no longer clamps the input potential VA1 until the collector voltage Vce actually drops, false detection of an overcurrent can be prevented by the low-pass filter (R, C1). Furthermore, if the gate potential is negatively biased while the semiconductor switching element 50 is in the OFF state, the capacitor C1 for the low-pass filter (R, C1) is also negatively biased via the clamp diode D1. This increases both the voltage margin and charge margin that would lead to false detection of an overcurrent, and improves electric field coupling or magnetic coupling noise resistance during OFF operation or recovery of the semiconductor switching element 50.

[0072] In this embodiment, a blocking diode D3 is provided to prevent current from flowing backward in the direction of conduction of the first transistor Q1, protecting the first transistor Q1. A large negative bias (VG2+Vf) is applied to the capacitor C1 without being affected by the protective diode D2. This configuration improves the noise immunity of the first transistor Q1 and reduces false overcurrent detection. Furthermore, an NPN bipolar transistor is used for the first transistor Q1, and a signal based on the input potential VA1 used for determination is input to the base, which provides current amplification. This allows the first transistor Q1 to operate effectively with a small signal input.

[0073] Furthermore, since the first overcurrent determination unit 17 uses the potential of the emitter control terminal ESa, which corresponds to the potential of the output terminal Ea of the power converter 20, the control unit 18 can confirm whether the output on / off command signal is being output with the correct pulse width. For example, it can compare the high period of the on / off command signal GDOa with the high period of the comparator VHD. Normally, the pulse width of the output voltage of the power converter 20 varies depending on the characteristics of the semiconductor switching elements and the circuit constants of the gate driver, but the control unit 18 compares the high period of the on / off command signal GDOa it generates with the high period of the output of the comparator VHD, and feeds this back to the control unit 18, thereby enabling the generation of an on / off signal with the difference corrected. In other words, highly accurate control can be achieved.

[0074] In addition, the control unit 18 can divide and obtain the potential of the emitter control terminal ESa, which corresponds to the potential of the output terminal Ea of the power converter 20, via the first overcurrent judgment unit 17, and can therefore detect abnormalities in the main withstand voltage of the semiconductor switching element.

[0075] For example, the logic synthesis unit 171 may be configured to detect a main withstand voltage abnormality based on the outputs of the comparators VHD and VLD during a period when both the upper-arm semiconductor switching element 50a and the lower-arm semiconductor switching element 50b connected in series are off, and transmit the detected abnormality to the control unit 18. That is, during a power converter stop period when neither on / off command signal GDOa nor GDOb is output, and when there is no need to detect an overcurrent state, the logic synthesis unit 171 is configured to set the determination signal OCD1 low when the outputs of the comparators VHD and VLD are low, and set OCD1 high otherwise. As a result, when there is no main withstand voltage abnormality, the potential of the output terminal Ea is set near the midpoint depending on the ratio of the resistors provided in the semiconductor drive device 10. However, when a main withstand voltage abnormality occurs, the potential of the output terminal Ea becomes near the positive or negative side, so that the output of the comparator VHD or VLD becomes high, causing the determination signal OCD1 to become high, and this state can be identified as a state in which a main withstand voltage abnormality has occurred. As a specific determination method, a known method proposed by the applicant can be used (for example, International Publication No. 2024 / 004208).

[0076] As described above, the power conversion device of the first embodiment is a power conversion device including a power converter having at least one or more leg circuits in which semiconductor switching elements are connected in series, and a semiconductor drive device that applies a voltage to the control terminal of the semiconductor switching element to drive the semiconductor switching element on and off. The semiconductor drive device includes a control unit that generates an on / off command signal that determines the on / off state of the semiconductor switching element, a gate drive unit that applies a voltage to the control terminal of the semiconductor switching element based on the on / off command signal, a first overcurrent determination unit that uses the power supply voltage of the DC power supply as a reference voltage and determines an overcurrent in the semiconductor switching element based on the potential of the output terminal of the leg circuit, a second overcurrent determination unit that inputs a detection signal based on the voltage current between the main terminals of the semiconductor switching element to determine an overcurrent flowing in the semiconductor switching element, and a gate voltage reduction unit that reduces the voltage applied to the control terminal when an overcurrent is determined, thereby protecting the semiconductor switching element. The overcurrent determination by the second overcurrent determination unit precedes the overcurrent determination by the first overcurrent determination unit, and the control unit is configured to control at least the semiconductor switching elements of the leg circuit determined to be experiencing an overcurrent to an off state when the first overcurrent determination unit determines an overcurrent. This prevents the semiconductor switching elements from turning off to stop the power conversion device and the gate voltage reduction operation to mitigate the overcurrent in the semiconductor switching elements from functioning simultaneously. Therefore, if both operations function simultaneously, the semiconductor switching elements would turn off faster than normal, generating an excessive surge voltage that could potentially cause secondary damage to the semiconductor switching elements. However, this configuration eliminates this problem. Therefore, this configuration protects the semiconductor switching elements and the power conversion device from overcurrent, providing a highly reliable power conversion device.

[0077] Furthermore, the first overcurrent judgment unit and the second overcurrent judgment unit each have a filter element that sets the time from when the signal input to each unit is in an overcurrent state until the first overcurrent judgment unit and the second overcurrent judgment unit judge that an overcurrent has occurred. Therefore, by using circuit design, it is possible to easily make the overcurrent judgment by the second overcurrent judgment unit precede the overcurrent judgment by the first overcurrent judgment unit.

[0078] In this case, the time constant of the first filter element provided in the first overcurrent judgment unit is larger than the time constant of the second filter element provided in the second overcurrent judgment unit, and the time from when an overcurrent state signal is input to when the first overcurrent judgment unit makes an overcurrent judgment is set to be shorter than the short-circuit allowable time determined by the short-circuit withstand capability of the semiconductor switching element. This not only prevents the off operation of the semiconductor switching element to stop the power conversion device and the operation to reduce the gate voltage to alleviate the overcurrent of the semiconductor switching element from functioning simultaneously, but also makes it possible to stop (turn off) the semiconductor switching element within the short-circuit withstand capability of the semiconductor switching element, thereby providing a more reliable power conversion device.

[0079] Furthermore, when the second overcurrent determination unit determines that an overcurrent has occurred, the gate voltage reduction unit continues to reduce the voltage applied to the control terminal of the semiconductor switching element for a predetermined period of time, and by setting this period to be longer than the time difference between when the second overcurrent determination unit determines that an overcurrent has occurred and when the first overcurrent determination unit determines that an overcurrent has occurred, it is possible to suppress the generation of surge voltage that also accompanies sudden fluctuations in the gate voltage.

[0080] In the power conversion device of the first embodiment, the first overcurrent determination unit uses the potential of the output terminal of the leg circuit to determine whether an overcurrent has occurred in the semiconductor switching element. Therefore, the control unit can generate an on / off command signal with an adjusted pulse width based on the potential of the output terminal of the leg circuit. Furthermore, the first overcurrent determination unit can determine whether there is an abnormality in the main withstand voltage of the semiconductor switching element based on the potential of the output terminal of the leg circuit during a period when no on / off command signal is being output. This makes it possible to provide a power conversion device that enables highly accurate control.

[0081] Second Embodiment A power conversion device according to a second embodiment will now be described with reference to the drawings. In the first embodiment, the first transistor Q1, which is an NPN bipolar transistor, is used in the overcurrent protection unit 12. In the second embodiment, the first transistor Q1 is configured as a PNP bipolar transistor. The second transistor Q2 is configured as an NPN bipolar transistor, and the third transistor Q3 is configured as a PNP bipolar transistor.

[0082] Fig. 6 is a diagram showing a circuit configuration of an overcurrent protection unit 12A of a power conversion device 1 according to embodiment 2. The configuration of the power conversion device 1 according to embodiment 2 corresponds to a configuration in which the overcurrent protection unit 12 in Fig. 2 and Fig. 3 is replaced with the overcurrent protection unit 12A in Fig. 6, and the configuration other than the overcurrent protection unit 12A is the same as that of embodiment 1, so a description of the power conversion device 1 as a whole will be omitted.

[0083] The overcurrent protection unit 12A uses the detection signal SOC similar to that in the first embodiment and includes a second overcurrent determination unit 13A that receives the detection signal SOC and outputs an overcurrent determination signal OCD2, and a gate voltage reduction unit 14A that reduces the gate voltage Vge based on the determination signal OCD2. The gate voltage reduction unit 14A also includes a drive circuit 141A that reduces the gate voltage Vge, and an amplifier circuit 142A that amplifies the output signal from the second overcurrent determination unit 13A to drive the drive circuit 141A.

[0084] The second overcurrent detection unit 13A includes series-connected resistors R1, R2, R3, and R4, a clamp diode D1, and a capacitor C1. It also includes a series circuit consisting of a first transistor Q1 (a PNP bipolar transistor), resistors R5 and R6, and a reverse current prevention diode D3. A capacitor C2 is connected in parallel with the resistor R6, and a protection diode D2 is provided between the base and emitter of the first transistor Q1. It also includes series-connected resistors R11 and R12 and a capacitor C4 connected in parallel with the resistor R12.

[0085] In this case, the resistor R (R1, R2, R3) and the capacitor C1 form a low-pass filter (R, C1). A connection point P2 between the resistor R (R1, R2, R3) and the resistor R4 serves as an input for the detection signal SOC and is connected to the emitter of the first transistor Q1. The potential of the connection point P2, which is the emitter potential of the first transistor Q1 with respect to the emitter control terminal ES, is defined as an input potential VA2.

[0086] The emitter potential (input potential VA2) of the first transistor Q1 is given by the following formula: VA2=Vce×R4 / (R1+R2+R3+R4) The base potential VB of the first transistor Q1 is the potential at the connection point between the resistors R11 and R12, and is given by the following formula: VB=Vge×R12 / (R11+R12)

[0087] In the second embodiment, the first transistor Q1 is also turned on to detect an overcurrent. The emitter potential (input potential VA2) when the first transistor Q1 is turned on is expressed by the following equation (3): VA2=VB+Vf (3)

[0088] When the semiconductor switching element 50 is turned off, the emitter potential (input potential VA2) of the first transistor Q1 is immediately negatively biased by the action of the clamp diode D1. This makes it possible to prevent erroneous detection of an overcurrent when the semiconductor switching element 50 is turned off. Furthermore, by initially negatively biasing the capacitor C1 in the low-pass filter (R, C1), it is possible to prevent erroneous detection of an overcurrent when the semiconductor switching element 50 is turned on.

[0089] Next, the amplifier circuit 142A in the gate voltage reduction unit 14A amplifies the determination signal OCD2 from the second overcurrent determination unit 13A. It includes a series circuit consisting of a second transistor Q2 (an NPN bipolar transistor), resistors R7 and R8, and a backflow prevention diode D7. A capacitor C3 is connected in parallel with the resistor R8, and a protective diode D4 is provided between the base and emitter of the second transistor Q2. The voltage of the determination signal OCD2 is applied to the base of the second transistor Q2. The drive circuit 141A in the gate voltage reduction unit 14A amplifies the output signal from the second overcurrent determination unit 13A. It includes a series circuit consisting of a third transistor Q3 (a PNP bipolar transistor), resistor R10, and diode D6. A resistor R9 is provided between this series circuit and the base of the second transistor Q2, and a protective diode D5 is provided between the base and emitter of the third transistor Q3.

[0090] In this second embodiment, as in the first embodiment, when the first transistor Q1 turns on and determines that the semiconductor switching element 50 is in an overcurrent state, the second transistor Q2 turns on, and then the third transistor Q3 turns on. In this case, too, by appropriately setting the resistors R5 and R6 connected in series to the first transistor Q1, the second transistor Q2 turns on after the first transistor Q1 turns on. Furthermore, by appropriately setting the resistors R7 and R8 connected in series to the second transistor Q2, the third transistor Q3 turns on after the second transistor Q2 turns on.

[0091] Then, a gate discharge current IA that discharges the capacitance (gate charge) between the gate and emitter of the semiconductor switching element 50 flows through the third transistor Q3, reducing the gate voltage Vge, thereby suppressing overcurrent in the semiconductor switching element 50.

[0092] 7 is a waveform diagram of each part showing the operation of the power conversion device 1 according to the second embodiment. The overcurrent protection operation of the power conversion device 1 will be described below with reference to FIGS. 6 and 7. Note that the description of the same parts as those in the first embodiment will be omitted as appropriate, and the following description will mainly focus on the emitter potential (input potential) VA2 of the first transistor Q1 and the determination signal OCD2.

[0093] Under normal conditions (before time t0), the emitter potential (input potential) VA2b of the first transistor Q1b, relative to the emitter control terminal ESb, is clamped to a potential (VG2b+Vf) obtained by adding the forward voltage Vf of the clamp diode D1b to the negative power supply potential VG2b when the semiconductor switching element 50b is in the off state. When the semiconductor switching element 50b is in the on state, the collector voltage Vceb drops to several volts, and the voltage VA2b divided by the resistors Rb (R1b, R2b, R3b) and R4b becomes close to the reference potential VG0. The potential of the determination signal OCD2b, i.e., the base potential of the second transistor Q2b, is maintained at the reference potential VG0b regardless of the on / off state of the semiconductor switching element 50b.

[0094] Assume that a fault occurs in the upper arm at time t0. At this time, the upper arm on / off command signal GDOa (not shown) transitions from high to low, turning off the semiconductor switching element 50a, and the collector voltage Vcea should be maintained at a high voltage. However, due to the fault (voltage resistance abnormality) in the upper arm, the collector voltage Vcea begins to drop while it was rising. As a result, the output waveform of the first comparator VHD also drops in a pulse-like manner in response to the collector voltage Vcea.

[0095] Subsequently, at time t1, the upper arm remains conductive due to the fault, so the lower arm on / off command signal GDOb goes high, turning on the semiconductor switching element 50b, and an overcurrent occurs due to an arm short circuit. As a result, the peak value Icbp of the collector current Icb saturates, and the collector voltage Vceb, which normally decreases, becomes high. This causes the emitter potential (input potential) VA2b of the first transistor Q1b to rise above the reference potential VG0b. Normally, the output of the first comparator VHD would switch low at this time, but the overcurrent keeps it high.

[0096] At time t2, the emitter potential (input potential) VA2b of the first transistor Q1b rises to (VBb + Vf), i.e., when the above equation (3) is satisfied, the first transistor Q1b turns on. This detects an overcurrent in the semiconductor switching element 50b. When the first transistor Q1b turns on, the potential of the determination signal OCD2b rises and reaches a potential (VG0b + Vf) higher than the reference potential VG0b by the threshold voltage Vf of the second transistor Q2, turning on the second transistor Q2. This also reduces the base potential of the third transistor Q3, applying a voltage equal to or greater than the threshold voltage Vf to the base and turning on the third transistor Q3. This causes a gate discharge current IAb to flow, reducing the gate voltage Vgeb. At this time, the collector current Ic decreases from its peak value Icbp to a value Icba corresponding to the reduced gate voltage Vgeb, generating a surge voltage Vsa in the collector voltage Vceb.

[0097] At time t3, first overcurrent determination unit 17 detects an overcurrent in power converter 20, causing determination signal OCD1 to go high. Between time t3 and time t4, control unit 18 stops the operation of power converter 20. Specifically, it stops the on / off command signals GDOa and GDOb and performs a current interruption operation on semiconductor switching elements 50a and 50b to turn them off. At this time, surge voltage Vsb is generated in collector voltage Vceb.

[0098] In the second embodiment, as in the first embodiment, the overcurrent protection unit 12A does not require a power supply for itself, but can detect and protect the semiconductor switching element 50 from an overcurrent by utilizing the threshold voltage of the first transistor Q1. Furthermore, the clamp diode D1 and the low-pass filter (R, C1) function to suppress malfunctions due to noise and provide overcurrent protection. As a result, even when the semiconductor switching element 50 and the gate drive unit 11 of the semiconductor drive device 10 are disposed apart, the overcurrent protection unit 12, which does not require a power supply, can be disposed close to the semiconductor switching element 50, thereby providing highly reliable overcurrent protection.

[0099] Furthermore, the provision of the reverse current prevention diode D3 not only protects the first transistor Q1 but also improves the noise resistance of the first transistor Q1, thereby making it possible to suppress erroneous detection of an overcurrent.

[0100] In addition, in this embodiment 2, a PNP bipolar transistor is used for the first transistor Q1 in the second overcurrent judgment unit 13A, so the input potential VA2 used for judgment can be set to a higher level, thereby improving voltage noise resistance.

[0101] Furthermore, in the second embodiment as well, the determination signal OCD1 that can be generated at time t0 is controlled to be delayed until time t3, thereby suppressing the generation of an excessive surge voltage and preventing the semiconductor switching element 50 from suffering secondary damage, thereby achieving the same effects as those of the first embodiment.

[0102] Third Embodiment A power conversion device according to a third embodiment will now be described with reference to the drawings. In the first and second embodiments, the overcurrent protection unit 12 determines whether an overcurrent has occurred based on the input potentials VA1 and VA2 obtained by attenuating the collector voltage Vce (detection signal SOC) of the semiconductor switching element 50 using a voltage dividing resistor. However, the third embodiment uses a different method.

[0103] Fig. 8 is a diagram showing a circuit configuration of an overcurrent protection unit 12B of a power conversion device 1 according to embodiment 3. The configuration of the power conversion device 1 according to embodiment 3 corresponds to a configuration in which the overcurrent protection unit 12 of embodiment 1 shown in Figs. 2 and 3 is replaced with the overcurrent protection unit 12B of Fig. 8, and the configuration other than the overcurrent protection unit 12B is the same as that of embodiment 1, so a description of the power conversion device 1 as a whole will be omitted.

[0104] Furthermore, this embodiment 3 is similar to the above-described embodiment 2 except that the detection signal SOC is connected to the second overcurrent determination unit 13B. In this case, a DESAT method is used to determine the collector voltage Vce (detection signal SOC) by flowing a constant current to the collector sense terminal CS of the semiconductor switching element 50 via a high-voltage diode D8. Differences from the above-described embodiment 2 will be described below. In the second overcurrent determination unit 13B, a constant current diode CRD, a resistor R1, and a high-voltage diode D8 are connected in series to the collector sense terminal CS. The constant current diode CRD is connected to the power supply line connected to the gate terminal G, and the junction point between the constant current diode CRD and the resistor R1 is connected to the emitter of the first transistor Q1.

[0105] In this case, the low-pass filter (CRD, C1) is formed of a constant current diode CRD instead of a resistor. A connection point P2 connecting the constant current diode CRD to the emitter of the first transistor Q1 serves as an input for the detection signal SOC, and the potential of the connection point P2, which is the emitter potential of the first transistor Q1, serves as an input potential VA2.

[0106] When the semiconductor switching element 50 is in the on state, the constant current diode CRD acts to pass a constant current of about several mA from the positive power supply potential VG1. In a normal state where the semiconductor switching element 50 is not in current saturation, the collector voltage Vce drops to several volts, causing the current of the constant current diode CRD to flow to the collector sense terminal CS. At this time, the emitter potential (input potential VA2) of the first transistor Q1 drops to several volts, preventing the first transistor Q1 from turning on.

[0107] When the semiconductor switching element 50 reaches current saturation and the collector voltage Vce rises, the current from the constant current diode CRD cannot flow to the collector sense terminal CS, but instead flows through the capacitor C1 and resistor R4. This causes the emitter potential (input potential) VA2 of the first transistor Q1 to rise to (VB + Vf), which satisfies the above equation (3), turning on the first transistor Q1. This detects an overcurrent in the semiconductor switching element 50. Note that the product of the constant current value of the constant current diode CRD and the resistance value of resistor R4 is designed in advance to be greater than VB + Vf.

[0108] When the first transistor Q1 is turned on, the second transistor Q2 is turned on, and then the third transistor Q3 is turned on, causing the gate discharge current IA to flow and reducing the gate voltage Vge.

[0109] The operational waveforms of the various components in this third embodiment are the same as those shown in FIG. 7 for the second embodiment, and the same effects as those of the second embodiment can be achieved. That is, the determination signal OCD1 that can be generated at time t0 is controlled to be delayed until time t3. This suppresses the generation of an excessive surge voltage, preventing secondary breakdown of the semiconductor switching element 50, and achieving the same effects as those of the first embodiment. Furthermore, this embodiment can detect the collector voltage Vce to a lower level than the first and second embodiments, in which the collector voltage Vce is attenuated by a voltage-dividing resistor before detection.

[0110] Fourth Embodiment A power conversion device according to a fourth embodiment will now be described with reference to the drawings. FIG. 9 is a diagram showing the configuration of a power conversion device 1 according to the fourth embodiment. In this fourth embodiment, a first overcurrent determination unit 17A is used that has a circuit configuration different from that of the first overcurrent determination unit 17 in the first to third embodiments. The overcurrent protection unit 12 is the same as that in the first embodiment. In the first to third embodiments, the power supply voltage of the DC power supply, which is the potential at the connection point P0, is used as the reference voltage. However, in this embodiment, a reference voltage generation unit 172 is provided in the first overcurrent determination unit 17A, and a single comparator VHLD is used to determine whether the potential at the output terminal Ea is near the positive electrode potential or the negative electrode potential.

[0111] 9, the reference voltage generator 172 receives the on / off command signals GDOa and GDOb from the control unit 18 and switches between outputting a reference voltage for determining whether the potential is near the positive electrode potential and a reference voltage for determining whether the potential is near the negative electrode potential depending on the state of the input on / off command signals GDOa and GDOb. That is, when the on / off command signal GDOa is high, the reference voltage for determining whether the potential is near the positive electrode potential is output to the negative input terminal of the comparator VHLD. When the on / off command signal GDOb is high, the reference voltage for determining whether the potential is near the negative electrode potential is output to the negative input terminal of the comparator VHLD. The potential of the emitter control terminal ESa of the semiconductor switching element 50a is divided by resistors R170, R171, and R172 and resistor R176 and input to the positive input terminal of the comparator VHLD. As described above, the potential of the emitter control terminal ESa corresponds to the potential of the output terminal Ea of the power converter 20.

[0112] The comparator VHLD is configured to switch the reference voltage using the reference voltage generator 172 instead of a window comparator, and compares the reference voltage with the divided potential of the emitter control terminal ESa. A reference voltage for determining proximity to a positive electrode potential is input, and if the potential of the emitter control terminal ESa is within a set value range, the comparator determines that the potential of the emitter control terminal ESa is near a positive electrode potential and outputs a high (H) signal. Also, a reference voltage for determining proximity to a negative electrode potential is input, and if the reference voltage is within a set value range, the comparator determines that the potential of the emitter control terminal ESa is near a negative electrode potential and outputs a low (L) signal. Specifically, the timing for detecting a short circuit in the upper arm is limited to when the upper arm is in the on state, i.e., when the on / off command signal GDOa is in the high state, and during that period, there is no need to detect a short circuit in the lower arm. Therefore, while the upper arm is in the on state, the set value of the comparator VHLD is set to a high level value Vrefa close to the positive electrode potential, and if it is in the range between the positive electrode potential and Vrefa, it is determined that the potential of the emitter control terminal ESa is near the positive electrode potential, and if it does not reach Vrefa, it is determined that a short circuit has occurred by the logic synthesis unit 171. Conversely, while the lower arm is in the on state, the set value of the comparator VHLD is set to a low level value Vrefb close to the negative electrode potential, and if it is in the range between the negative electrode potential and Vrefb, it is determined that the potential of the emitter control terminal ESa is near the negative electrode voltage, and if it is not in that range, it is determined that a short circuit has occurred by the logic synthesis unit 171.

[0113] The output of the comparator VHLD is input to the logic synthesis unit 171 and subjected to a logical operation with the input on / off command signals GDOa and GDOb. Under normal conditions, when the on / off command signal GDOa is output (high: H), the output voltage of the power converter 20 is the output voltage from the upper arm, i.e., the potential of the emitter control terminal ESa is near the positive voltage, so the output from the comparator VHLD is high. In this case, the logic synthesis unit 171 outputs a low (L) determination signal OCD1. Similarly, when the on / off command signal GDOb is output (high: H), the output voltage of the power converter 20 is the output voltage from the lower arm, i.e., the potential of the emitter control terminal ESa is near the negative voltage, so the output from the comparator VHLD is low. In this case, the logic synthesis unit 171 outputs a low (L) determination signal OCD1. In other cases, it is determined that an overcurrent has flowed in one of the arms, and the logic synthesis unit 171 outputs a high (H) determination signal OCD1 to the control unit 18.

[0114] When the control unit 18 receives the determination signal OCD1 at high (H), it does not output the on / off command signals GDOa and GDOb and stops the operation of the power converter 20.

[0115] In this first overcurrent determination unit 17A, a low-pass filter LF2 is formed by a resistor R179 and a capacitor C170. Here, as in the first embodiment, the output of the determination signal OCD1 is delayed. That is, the time constant of the low-pass filter LF2 of the first overcurrent determination unit 17A is set to be greater than the time constant of the low-pass filter of the second overcurrent determination unit 13. Alternatively, a signal masking circuit such as a timer may be provided in the logic synthesis unit 171. This allows the gate voltage of the semiconductor switching element 50 to be reduced after the second overcurrent determination unit 13 makes a determination, and then the first overcurrent determination unit 17A can stop the semiconductor switching element 50, thereby preventing damage to the semiconductor switching element 50 due to an excessive surge voltage.

[0116] 10 is a waveform diagram of each part showing the operation of the power conversion device 1 according to embodiment 4. The following description will focus on the differences from FIG. 3 of embodiment 1, and omit overlapping points. In a normal state before time t0, the signal of the comparator VHLD is inverted from the on / off command signal GDOb. In other words, when the on / off command signal GDOb is high, the comparator VHLD is low, and it is determined that the potential of the emitter control terminal ESa is near the negative voltage.

[0117] Assume that a fault occurs in the upper arm at time t0. At this time, the upper arm on / off command signal GDOa (not shown) transitions from high to low, turning off the semiconductor switching element 50a, and the collector voltage Vcea should be maintained at a high voltage. However, due to the fault (voltage resistance abnormality) in the upper arm, the collector voltage Vcea begins to drop while it was rising. As a result, the output waveform of the comparator VHLD also drops in a pulse-like manner in response to the collector voltage Vcea.

[0118] Subsequently, at time t1, the upper arm remains conductive due to the fault, so the lower arm on / off command signal GDOb goes high, turning on the semiconductor switching element 50b, generating an overcurrent due to an arm short circuit. As a result, the peak value Icbp of the collector current Icb saturates, and the collector voltage Vceb, which normally decreases, rises to a high level. This causes the emitter potential (input potential) VA2b of the first transistor Q1b to rise to 2Vf, exceeding the reference potential VG0b. At this time, under normal circumstances, the output of the comparator VHLD would normally switch to low, but the overcurrent keeps it high.

[0119] Thereafter, the second overcurrent determination unit 13 detects an overcurrent in the semiconductor switching element 50b, and the gate voltage Vgeb is reduced by the gate voltage reduction unit 14. At this time, the collector current Ic decreases from the peak value Icbp to a value Icba corresponding to the reduced gate voltage Vgeb, and a surge voltage Vsa is generated in the collector voltage Vceb.

[0120] At time t3, first overcurrent determination unit 17A detects an overcurrent in power converter 20, causing determination signal OCD1 to go high. Between time t3 and time t4, control unit 18 stops the operation of power converter 20. Specifically, it stops the on / off command signals GDOa and GDOb and performs a current interruption operation on semiconductor switching elements 50a and 50b to turn them off. At this time, surge voltage Vsb is generated in collector voltage Vceb.

[0121] As in the first embodiment, the first overcurrent determination unit 17A uses the potential of the emitter control terminal ESa, which corresponds to the potential of the output terminal Ea of the power converter 20. This allows the control unit 18 to confirm whether the output on-off command signal is being output with the correct pulse width. For example, the control unit 18 can compare the high period of the on-off command signal GDOa with the high period of the comparator VHLD. While the pulse width of the output voltage of the power converter 20 typically varies depending on the characteristics of the semiconductor switching elements and the circuit constants of the gate driver, the control unit 18 can compare the high period of the on-off command signal GDOa it generates with the high period of the output of the comparator VHLD and feed this back to the control unit 18, thereby correcting the difference.

[0122] Furthermore, similar to the first embodiment, the control unit 18 can divide and obtain the potential of the emitter control terminal ESa, which corresponds to the potential of the output terminal Ea of the power converter 20, via the first overcurrent determination unit 17A, and therefore can detect an abnormality in the main withstand voltage of the semiconductor switching element.

[0123] For example, the logic synthesis unit 171 may be configured to detect a main withstand voltage anomaly based on the output of the comparator VHLD during a period when both the upper-arm semiconductor switching element 50a and the lower-arm semiconductor switching element 50b connected in series are off, and to transmit the detected anomaly to the control unit 18. That is, during a power converter stop period when neither on / off command signal GDOa nor GDOb is output, during which it is not necessary to detect an overcurrent state, the logic synthesis unit 171 is configured to set the determination signal OCD1 low when the output of the comparator VHLD is low, and set OCD1 high when the output of the comparator VHLD is high. As a result, when there is no main withstand voltage anomaly, the potential of the output terminal Ea is set near the midpoint in accordance with the ratio of the resistors provided in the semiconductor drive device 10. However, when a main withstand voltage anomaly occurs, the potential of the output terminal Ea becomes near the positive or negative side, so that the output of the comparator VHLD becomes high, causing the determination signal OCD1 to become high, and this state can be identified as a state in which a main withstand voltage anomaly has occurred. As a specific determination method, a known method proposed by the applicant can be used (for example, International Publication No. 2024 / 004208).

[0124] As described above, the fourth embodiment can also achieve the same effects as the first embodiment. That is, the determination signal OCD1 that can be generated at time t0 is controlled to be delayed until time t3, thereby suppressing the generation of an excessive surge voltage and preventing the semiconductor switching element 50 from suffering secondary damage.

[0125] In addition, in the fourth embodiment, an example in which the overcurrent protection unit 12 of the first embodiment is applied has been described, but the same effect can be achieved by applying the overcurrent protection unit 12A of the second embodiment or the overcurrent protection unit 12B of the third embodiment.

[0126] Fifth Embodiment. A power conversion device according to a fifth embodiment will now be described with reference to the drawings. In each of the first to fourth embodiments, the collector voltage Vce of the semiconductor switching element 50 is detected from the collector sense terminal CS to provide the detection signal SOC. However, in this embodiment, a different detection signal SOC is used. FIG. 11 is a diagram showing a schematic configuration of a power conversion device 1 according to a fifth embodiment. In this fifth embodiment, the semiconductor switching element 50b includes a current detection element on the emitter side through which a current reduced to, for example, several thousandths flows, and the reduced emitter current Ieeb flowing from the current detection terminal EEb is used as the detection signal SOCb. The upper arm semiconductor switching element 50a also includes a current detection element and a current detection terminal EEa, and redundant description will be omitted below.

[0127] As shown in FIG. 11 , the power conversion device 1 includes a power converter 20 and a semiconductor driver 10 that drives semiconductor switching elements of the power converter 20. The semiconductor driver 10 includes a control unit 18, insulated communication units 16a and 16b, gate drivers 11a and 11b, overcurrent protection units 12a and 12b, and a first overcurrent determination unit 17. The overcurrent protection units 12a and 12b include a second overcurrent determination unit 13 that outputs an overcurrent determination signal OCD2 based on the emitter current Iee (detection signal SOC), and a gate voltage reduction unit 14 that reduces the gate voltage Vge based on the determination signal OCD2. The gate driver 11 and the gate voltage reduction unit 14 are the same as those in the first embodiment. The second overcurrent determination unit 13 also has a circuit configuration similar to that of the second overcurrent determination unit 13 in the first embodiment, although it handles a different detection signal SOC.

[0128] FIG. 12 is a waveform diagram of each part showing the operation of the power conversion device 1 according to the fifth embodiment. In FIG. 12 , it is assumed that the power conversion device 1 operates normally before time t0, and that at time t0, a fault such as a voltage breakdown abnormality occurs in the upper arm. In FIG. 12 , the emitter current Ieeb, which becomes the detection signal SOCb, is connected to the base of the first transistor Q1b and serves as the base current input to the base. When an overcurrent occurs while the semiconductor switching element 50b is on (time t1), the emitter current Ieeb (detection signal SOCb) increases, and when it exceeds a set threshold value IX, the first transistor Q1b turns on. This detects an overcurrent in the semiconductor switching element 50b. Except for the use of the emitter current Ieeb as the detection signal SOCb, the operational waveforms of each part are the same as those shown in FIG. 4 of the first embodiment.

[0129] In the present embodiment 5, the same effects as those of the above-described embodiment 1 can be obtained. In addition, although the present embodiment is applicable only to semiconductor switching elements 50 equipped with current detection elements, overcurrent can be detected with higher accuracy because the current value itself is detected and an overcurrent is determined without needing to come into contact with a high-voltage section.

[0130] In addition, in Figure 11, an example is described in which the first overcurrent judgment unit 17 of the power conversion device 1 of embodiment 5 is provided, but it goes without saying that the first overcurrent judgment unit 17A described in embodiment 4 can also be applied.

[0131] Sixth Embodiment A power conversion device according to a sixth embodiment will be described below with reference to the drawings. In the sixth embodiment, a detection signal SOC different from the detection signal SOC used in the first to fourth embodiments and the detection signal SOC used in the fifth embodiment is used.

[0132] 13 is a diagram showing a schematic configuration of a power conversion device 1 according to a sixth embodiment. In this sixth embodiment, an emitter voltage VEe between an emitter E, which is a low-voltage main terminal of a semiconductor switching element 50, and an emitter control terminal ES is used as a detection signal SOC. This utilizes an electromotive force (Le·dIc / dt) generated across a parasitic inductance Le on the emitter side.

[0133] 13 , the power conversion device 1 includes a power converter 20 and a semiconductor driving device 10 that drives semiconductor switching elements of the power converter 20. The semiconductor driving device 10 includes a control unit 18, insulated communication units 16a and 16b, gate driving units 11a and 11b, overcurrent protection units 12a and 12b, and a first overcurrent determination unit 17. The overcurrent protection units 12a and 12b include a second overcurrent determination unit 13 that outputs an overcurrent determination signal OCD2 based on the emitter voltage VEe (detection signal SOC), and a gate voltage reduction unit 14 that reduces the gate voltage Vge based on the determination signal OCD2. The other configurations are the same as those of the first embodiment.

[0134] The second overcurrent determination unit 13 also has a circuit configuration similar to that of the second overcurrent determination unit 13 in the first embodiment, although it handles a different detection signal SOC. However, while the entire overcurrent protection unit 12 in the first embodiment is configured with the potential of the emitter control terminal ES as its reference, in this embodiment, only the second overcurrent determination unit 13 in the overcurrent protection unit 12 is configured with the potential of the emitter E as its reference, and the rest are configured with the potential of the emitter control terminal ES as their reference. That is, the emitter control terminal ES is connected to the high-voltage side of resistor R1, and the emitter voltage VEe (detection signal SOC) from the emitter E is connected to the low-voltage side of resistor R4.

[0135] FIG. 14 is a waveform diagram of each part showing the operation of the power conversion device 1 according to the sixth embodiment. In FIG. 14 , it is assumed that the power conversion device 1 operates normally before time t0, and that a failure such as a voltage breakdown abnormality occurs in the upper arm at time t0. In FIG. 14 , the emitter voltage VEeb, which serves as the detection signal SOCb, has a waveform similar to the differential value (dIcb / dt) of the collector current Ic. When an overcurrent occurs while the semiconductor switching element 50b is on, the emitter voltage VEeb (detection signal SOCb) decreases. When the emitter voltage VEeb decreases beyond a set threshold VX, the first transistor Q1b turns on. This detects an overcurrent in the semiconductor switching element 50b. Except for the use of the emitter voltage VEeb as the detection signal SOCb, the operational waveforms of each part are the same as those shown in FIG. 4 of the first embodiment.

[0136] In the sixth embodiment, the same effects as those of the first embodiment can be obtained. Moreover, by utilizing the electromotive force generated in the parasitic inductance Le on the emitter side, it is possible to obtain current information at high speed and with high accuracy and detect an overcurrent without providing a current detection element.

[0137] In the above embodiment, the emitter voltage VEe is compared with the threshold value VX, which serves as the judgment voltage. However, the voltage amplitude (Le·dIc / dt) of the emitter voltage VEe may be integrated using an integrating circuit to obtain information similar to the collector current Ic and to judge an overcurrent.

[0138] In addition, in Figure 13, an example is described in which the first overcurrent judgment unit 17 of the power conversion device 1 of embodiment 6 is provided, but it goes without saying that the first overcurrent judgment unit 17A described in embodiment 4 can also be applied.

[0139] Seventh Embodiment A power conversion device according to a seventh embodiment will now be described with reference to the drawings. In this seventh embodiment, a signal obtained by detecting the rate of change of the current between the main terminals and converting it into a voltage is used as the detection signal SOC. FIG. 15 is a diagram showing a schematic configuration of a power conversion device 1 according to the seventh embodiment. As shown in FIG. 15, a current-voltage conversion element CT is provided on the outside of the emitter E, which is one of the main terminals of the semiconductor switching element 50. The current-voltage conversion element CT detects the rate of change of the collector current Ic, which is the current between the main terminals, and outputs voltage information Vct (detection signal SOC). An example of the current-voltage conversion element CT is a Rogowski coil formed on a printed circuit board constituting the overcurrent protection unit 12.

[0140] As shown in FIG. 15 , the power conversion device 1 includes a power converter 20 and a semiconductor driver 10 that drives semiconductor switching elements of the power converter 20. The semiconductor driver 10 includes a control unit 18, insulated communication units 16a and 16b, gate drivers 11a and 11b, overcurrent protection units 12a and 12b, and a first overcurrent determination unit 17. The overcurrent protection units 12a and 12b include a second overcurrent determination unit 13 that outputs an overcurrent determination signal OCD2 based on voltage information Vct (detection signal SOC), and a gate voltage reduction unit 14 that reduces a gate voltage Vge based on the determination signal OCD2. Other configurations are similar to those of the first embodiment. The second overcurrent determination unit 13 also has a circuit configuration similar to that of the second overcurrent determination unit 13 of the first embodiment, except for the detection signal SOC it handles.

[0141] FIG. 16 is a waveform diagram of each component showing the operation of the power conversion device 1 according to the seventh embodiment. In FIG. 16 , the power conversion device 1 operates normally before time t0, and at time t0, a fault such as a voltage breakdown abnormality occurs in the upper arm. In FIG. 16 , the voltage information Vctb serving as the detection signal SOCb has a waveform similar to the differential value (dIcb / dt) of the collector current Icb. When an overcurrent occurs while the semiconductor switching element 50b is on (time t1), the voltage information Vctb (detection signal SOCb) rises, and when it exceeds the set threshold value VXa (time t2), the first transistor Q1b turns on. This detects an overcurrent in the semiconductor switching element 50b. Except for the use of the voltage information Vctb as the detection signal SOCb, the operational waveforms of each component are the same as those shown in FIG. 4 of the first embodiment.

[0142] In the seventh embodiment, the same effects as those of the first embodiment can be obtained. Furthermore, by mounting the overcurrent protection unit 12 on a printed circuit board and using a Rogowski coil (current-voltage conversion element CT) formed on the printed circuit board, it is possible to realize non-contact, highly accurate overcurrent detection.

[0143] In addition, in Figure 15, an example is described in which the first overcurrent judgment unit 17 of the power conversion device 1 of embodiment 7 is provided, but it goes without saying that the first overcurrent judgment unit 17A described in embodiment 4 can also be applied.

[0144] Eighth Embodiment A power conversion device according to an eighth embodiment will now be described with reference to the drawings. In the first embodiment described above, as shown in FIG. 3, a low-pass filter (R, C1) is provided at the input section of the detection signal SOC of the second overcurrent determination section 13. In the eighth embodiment, a first low-pass filter and a second low-pass filter are provided as the low-pass filters of the second overcurrent determination section 13.

[0145] 17 is a diagram showing a schematic configuration of a power conversion device 1 according to an eighth embodiment. As shown in FIG. 17 , the power conversion device 1 includes a power converter 20 and a semiconductor driving device 10 that drives semiconductor switching elements of the power converter 20. The semiconductor driving device 10 includes a control unit 18, insulated communication units 16a and 16b, gate driving units 11a and 11b, overcurrent protection units 12a and 12b, and a first overcurrent determination unit 17. The overcurrent protection units 12a and 12b include a second overcurrent determination unit 13 that determines an overcurrent flowing through the semiconductor switching element 50, and a gate voltage reduction unit 14 that reduces the voltage applied to the gate terminal G of the semiconductor switching element 50 when an overcurrent is determined. The gate driving unit 11 and the gate voltage reduction unit 14 are the same as those in the first embodiment.

[0146] The second overcurrent determination unit 13 according to the eighth embodiment includes a first transistor Q1, a clamp diode D1, a backflow prevention diode D3, a resistor R, capacitors C1a and C1b, and a diode DL. In this case, a first low-pass filter (R, C1a) formed by the resistor R and the capacitor C1a and a second low-pass filter (R, C1b) formed by the resistor R and the capacitor C1b are formed. A detection signal SOC based on a collector voltage Vce, which is the voltage between the main terminals of the semiconductor switching element 50, is input to the first transistor Q1 via the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b), and the first transistor Q1 outputs an overcurrent determination signal OCD2.

[0147] FIG. 18 is a diagram showing the circuit configuration of an overcurrent protection unit 12F according to the eighth embodiment. As shown in FIG. 18, in the second overcurrent determination unit 13F, a resistor R consisting of three resistors R1, R2, and R3 and capacitors C1a and C1b constitute a first low-pass filter (R, C1a) and a second low-pass filter (R, C1b). A connection point P1 between the resistor R (R1, R2, R3) and the resistor R4 serves as an input for the detection signal SOC and is connected to the base of the first transistor Q1. The potential of the connection point P1, which is the base potential of the first transistor Q1 relative to the emitter control terminal ES, is defined as an input potential VA1.

[0148] The anode of a clamp diode D1, which clamps the gate potential (Vge), is connected to the capacitor C1 of the first low-pass filter (R, C1a). The connection point is connected to the connection point P1 and the base of the first transistor Q1, and is also connected to the capacitor C1b of the second low-pass filter (R, C1b) via a diode DL. The detection signal SOC is divided by resistors R1 to R4 and input to the base of the first transistor Q1 via the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b), which are composed of the voltage-dividing resistor R (R1, R2, R3) and two capacitors C1a and C1b.

[0149] When the semiconductor switching element 50 is in the off state, the base of the first transistor Q1 is clamped to the negative power supply potential VG2 by the clamp diode D1. The first low-pass filter (R, C1a) is clamped to the gate potential (Vge) via the clamp diode D1. On the other hand, the second low-pass filter (R, C1b) is not clamped to the gate potential (Vge) due to the action of the diode DL.

[0150] The diode DL is provided to prevent the second low-pass filter (R, C1b) from being clamped to the negative power supply potential VG2, but its forward voltage becomes an offset voltage of the second low-pass filter (R, C1b). This offset voltage reduces the noise immunity of the first transistor Q1. For this reason, the offset voltage is suppressed by using a diode with a small forward voltage, such as a Schottky barrier diode. Furthermore, as shown in FIG. 18, the offset voltage can be eliminated by providing a backflow prevention diode D3 on the emitter side of the first transistor Q1.

[0151] Furthermore, the capacitor C1a of the first low-pass filter (R, C1a) is configured with a small capacitance, while the capacitor C1b of the second low-pass filter (R, C1b) is configured with a large capacitance. When the semiconductor switching element 50 is in the off state, the capacitor C1a of the first low-pass filter (R, C1a) is negatively biased. When the semiconductor switching element 50 is turned on and the capacitor C1a recovers from the negative bias state, recovery takes time if the capacitance of the capacitor C1a is large. Here, the capacitance of the capacitor C1a is small, so the capacitor C1a recovers from the negative bias quickly, enabling overcurrent detection within a predetermined delay time. The first low-pass filter (R, C1a) functions in the same way as the low-pass filter (R, C1) described in the first embodiment, suppressing erroneous overcurrent detection.

[0152] If the second low-pass filter (R, C1b) were not present, i.e., in the same case as in the first embodiment, when the semiconductor switching element 50 is in the on state, the first low-pass filter (R, C1a) with a small capacitance capacitor C1a alone would have low resistance to current noise. In this case, the provision of the second low-pass filter (R, C1b) with a large capacitance capacitor C1b makes it possible to suppress erroneous detection of overcurrent due to current noise, even when the semiconductor switching element 50 is in the on state.

[0153] FIG. 19 is a waveform diagram of each part showing the operation of the power conversion device 1 according to the eighth embodiment. In FIG. 19, it is assumed that the device is operating normally before time t0, and that at time t0, a fault such as a voltage abnormality occurs in the upper arm. In FIG. 19, the operating waveforms other than the base potential (input potential) VA1b of the first transistor Q1b relative to the emitter control terminal ESb are the same as those shown in FIG. 4 of the first embodiment. The VA1b waveform in the first embodiment is indicated by a dotted line.

[0154] During normal operation before time t0, when the semiconductor switching element 50b is in the off state, the base potential (input potential) VA1b of the first transistor Q1b is clamped to a potential (VG2+Vf) obtained by adding the negative power supply potential VG2b to the forward voltage Vf of the clamp diode D1. When the semiconductor switching element 50b is in the on state, the collector voltage Vceb drops to several volts, and the voltage VA1b divided by the resistors Rb (R1b, R2b, R3b) and R4b becomes close to the reference potential VG0b. In this case, because a small-capacity capacitor C1pb is used in the first low-pass filter (Rb, C1pb) clamped by the clamp diode D1b, the time it takes for the base potential (input potential) VA1b to recover from a negative bias is shortened when the semiconductor switching element 50b transitions from the off state to the on state.

[0155] At time t0, a fault such as a breakdown voltage abnormality occurs in the upper arm. At time t1, the upper arm remains conductive due to the fault. Therefore, when an overcurrent occurs due to an arm short circuit at the timing when semiconductor switching element 50b turns on, the peak value Icbp of collector current Icb saturates, and collector voltage Vceb, which normally decreases, becomes high. Here again, after semiconductor switching element 50b turns on, base potential (input potential) VA1b quickly recovers from the negative bias and further rises above reference potential VG0b.

[0156] In this embodiment, as in the first embodiment, the overcurrent protection unit 12 does not require a power supply for itself, but can detect and protect the semiconductor switching element 50 by using the threshold voltage of the first transistor Q1. Furthermore, the clamp diode D1, the first low-pass filter (R, C1a), and the second low-pass filter (R, C1b) work to suppress malfunctions caused by noise and provide overcurrent protection. As a result, even when the semiconductor switching element 50 and the gate driver 11 of the semiconductor driver 10 are disposed apart, the overcurrent protection unit 12, which does not require a power supply, can be disposed close to the semiconductor switching element 50, thereby providing highly reliable overcurrent protection.

[0157] Furthermore, the first low-pass filter (R, C1a) is configured to be clamped to the gate potential (Vge), while the second low-pass filter (R, C1b) is configured not to be clamped to the gate potential (Vge). This allows the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b) to be used independently when the semiconductor switching element 50 is in the off state and on state, effectively eliminating the effects of noise. Furthermore, the capacitor C1a of the first low-pass filter (R, C1a) is configured to have a small capacitance, while the capacitor C1b of the second low-pass filter (R, C1b) is configured to have a large capacitance. This shortens the time it takes for the base potential (input potential) VA1 of the first transistor Q1 to recover from a negative bias, enabling rapid overcurrent detection and improved noise immunity.

[0158] In this embodiment, as in the first embodiment, at time t3, the first overcurrent determination unit 17 detects an overcurrent in the power converter 20, causing the determination signal OCD1 to go high. Between time t3 and time t4, the control unit 18 stops the operation of the power converter 20. Specifically, the on / off command signals GDOa and GDOb are stopped, and the semiconductor switching elements 50a and 50b are turned off by performing a current interruption operation. At this time, a surge voltage Vsb is generated in the collector voltage Vceb. In this embodiment, the time constant of the low-pass filter LF1 included in the first overcurrent determination unit 17 is set larger than both the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b) of the overcurrent protection unit 12. As a result, after the gate voltage is reduced by the overcurrent protection unit 12, the determination signal OCD1 from the first overcurrent determination unit 17 causes a current interruption operation for the semiconductor switching element 50.

[0159] 17 has been described as an example in which the first overcurrent determination unit 17 of the power conversion device 1 of embodiment 8 is provided, but it goes without saying that the first overcurrent determination unit 17A described in embodiment 4 can also be applied. In this case, too, the time constant of the low-pass filter LF2 provided in the first overcurrent determination unit 17A is set to be larger than both the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b) of the overcurrent protection unit 12.

[0160] Ninth Embodiment Fig. 20 is a diagram showing the configuration of a power conversion device according to a ninth embodiment. As shown in Fig. 20, the power conversion device 1 includes a power converter 20A configured with a plurality of semiconductor switching elements 50, and a semiconductor drive device 10 that drives each of the semiconductor switching elements 50 in the power converter 20A. In this case, the power conversion device 1 is an inverter that converts DC power from a DC power supply 60 into AC power and supplies it to an AC motor 70. A semiconductor drive device 10 according to the first embodiment is provided for each upper and lower arm, i.e., each leg circuit, and a collection of the semiconductor drive devices 10 is referred to as a semiconductor drive device 10X of this embodiment.

[0161] The power converter 20A is an inverter circuit having a three-phase (U, V, W) configuration and including a smoothing capacitor 40 between DC buses and leg circuits 23 for each phase. The leg circuits 23 for each phase are configured by connecting in series an upper arm 21A and a lower arm 22A, each of which has a semiconductor switching element 50.

[0162] In this embodiment 9, each semiconductor switching element 50 in the power converter 20A is driven by a semiconductor driving element 10X that employs the semiconductor driving element 10 according to the above embodiment 1, so that overcurrent protection of the semiconductor switching elements 50 can be implemented with high reliability without requiring an additional power supply. Therefore, even when the semiconductor switching elements 50 and the gate driving unit of the semiconductor driving element 10X are disposed apart, overcurrent protection of the semiconductor switching elements 50 can be implemented with high reliability, and an inexpensive and highly reliable power conversion apparatus 1 can be obtained.

[0163] Although the power converter 20A has been described as outputting two-level AC voltages, positive and negative, it may be an inverter capable of outputting multilevel voltages in which any number of semiconductor switching elements 50 are connected in series and parallel. In this case, the power converter 20A also has a configuration including a leg circuit 23 formed by connecting in series an upper arm 21A and a lower arm 22A, each of which has a semiconductor switching element 50.

[0164] Fig. 21 is a diagram showing the configuration of a power conversion device according to another example of the ninth embodiment. As shown in Fig. 21, the power conversion device 1 includes a power converter 20B having a plurality of semiconductor switching elements 50, and a semiconductor driving device 10 that drives each of the semiconductor switching elements 50 in the power converter 20B. In this case, the power conversion device 1 operates as a boost converter that boosts the DC voltage of a DC power supply 60 and supplies it to a DC load 70A. As described above, the semiconductor driving device 10 may be a collection of individual semiconductor driving devices 10 that drive each of the semiconductor switching elements 50.

[0165] The power converter 20B includes an input-side smoothing capacitor 41, an output-side smoothing capacitor 42, a leg circuit 23A, and a boost reactor 43. The leg circuit 23A is configured by connecting in series an upper arm 21B and a lower arm 22B, each of which has a semiconductor switching element 50.

[0166] In this case, too, the semiconductor switching element 50 can be reliably protected from overcurrent without the need for an additional power supply. Therefore, even when the semiconductor switching element 50 and the gate drive unit of the semiconductor drive device 10 are disposed apart, the semiconductor switching element 50 can be reliably protected from overcurrent, thereby providing an inexpensive and highly reliable power conversion device 1.

[0167] Although the above example shows a boost converter, the present invention can also be applied to a buck converter or a buck-boost converter that combines a boost converter and a buck converter. Furthermore, a wide bandgap semiconductor material may be used for the semiconductor switching element 50, which can speed up the switching operation of the semiconductor switching element 50 and reduce the size of the boost reactor 43. The wide bandgap semiconductor material can be silicon carbide (SiC), gallium nitride, gallium oxide-based material, or diamond.

[0168] Fig. 22 is a diagram showing the configuration of a power conversion device according to yet another example of embodiment 9. As shown in Fig. 22, power conversion device 1 includes a main circuit (power converter) in which power converter 20B shown in Fig. 21 is connected to the DC side of power converter 20A shown in Fig. 20, and a semiconductor driver 10X that drives each semiconductor switching element 50. In this case, power conversion device 1 boosts the DC voltage of DC power supply 60 using power converter 20B, and the boosted DC power is converted into AC power by power converter 20A and supplied to AC motor 70.

[0169] This power conversion device 1 operates as a boost inverter system and is applied to, for example, electric vehicles. In this case, too, overcurrent protection of the semiconductor switching element 50 can be implemented with high reliability without requiring an additional power supply. Therefore, even when the semiconductor switching element 50 and the gate drive unit of the semiconductor drive device 10X are disposed apart, overcurrent protection of the semiconductor switching element 50 can be implemented with high reliability, resulting in an inexpensive and highly reliable power conversion device 1.

[0170] The power converter 20A in the power conversion device 1 may be an inverter capable of outputting multilevel voltages. The power converter 20B in the power conversion device 1 is not limited to a boost converter, but may be a buck converter or a buck-boost converter that combines a boost converter and a buck converter.

[0171] Furthermore, the semiconductor driving device 10 according to each of the second to eighth embodiments other than the first embodiment may be applied to the semiconductor driving device 10X, and similar effects can be obtained. In such cases, the semiconductor driving device 10X is also a collection of semiconductor driving devices 10 that drive each semiconductor switching element 50 in leg circuit units. Furthermore, although an IGBT is illustrated as the semiconductor switching element 50, it may also be another semiconductor switching element having a control terminal, such as a MOSFET.

[0172] Furthermore, a multi-gate semiconductor switching element having multiple gate terminals may be used as the semiconductor switching element. Fig. 23 shows an example of a power conversion device 1 using a double-gate semiconductor switching element 50wG. As shown in Fig. 23, the double-gate semiconductor switching element 50wG has two gate terminals G1, G2, and by controlling the on / off timing of the two gate terminals G1, G2, advantages such as improved turn-off speed can be obtained.

[0173] In the above-described single-gate semiconductor switching element, when the second overcurrent determination unit 13 detects an overcurrent, the gate voltage Vge is reduced by the gate voltage reduction unit 14, thereby reducing the collector current Ic. Since the double-gate semiconductor switching element 50wG can independently control the gate terminals G1 and G2, the voltage applied to each gate terminal can be controlled to reduce the voltage applied to the double-gate semiconductor switching element 50wG. For example, when an overcurrent is detected, one of the gate terminals can be reduced to a value equal to or lower than the gate threshold voltage Vth, or one of the gate terminals can be turned off, thereby reducing the gate voltage Vge applied to the double-gate semiconductor switching element 50wG and reducing the collector current Ic.

[0174] Similarly, when a multi-gate semiconductor switching element is used, at least one gate terminal can be reduced to a gate threshold voltage Vth or lower or at least one gate terminal can be turned off when an overcurrent is detected, thereby reducing the gate voltage Vge applied to the multi-gate semiconductor switching element and reducing the collector current Ic. In this way, by using a semiconductor switching element with multiple gates, it is possible to precisely control the gate voltage when an overcurrent occurs.

[0175] 23 shows the semiconductor switching element of one arm as the configuration of power converter 20 of power conversion device 1, and shows a simplified view of power conversion device 1 as a whole, but it goes without saying that, as in embodiments 1 to 8, double-gate type semiconductor switching elements 50wG or multi-gate type semiconductor switching elements may be used as the switching elements used in power converter 20. When an overcurrent flowing through double-gate type semiconductor switching element 50wG is detected, overcurrent protection unit 12 reduces the gate voltages applied to two gate terminals G1, G2, and power converter 20 is stopped by the output of first overcurrent determination unit 17.

[0176] The power conversion device shown in the ninth embodiment can also be configured using a double-gate type semiconductor switching element or a multi-gate type semiconductor switching element as the semiconductor switching element 50. Although an IGBT is illustrated as the double-gate type semiconductor switching element 50, other semiconductor switching elements having gate terminals, such as a MOSFET, can also be used.

[0177] An example of the hardware configuration of the control unit 18 of the power conversion device 1 according to the first to ninth embodiments is shown in Fig. 24. As shown in Fig. 24, the control unit 18 includes, for example, a processor 1000 and a storage device 1100 as processing circuits.

[0178] The processor 1000 may include a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), an IC (Integrated Circuit), an FPGA (Field Programmable Gate Array), various logic circuits, various signal processing circuits, etc. Furthermore, the processor 1000 may include a plurality of processors of the same type or different types, and each process may be shared among them.

[0179] The storage device 1100 includes a RAM (Random Access Memory) configured to be able to read and write data from the processor 1000, and a ROM (Read Only Memory) configured to be able to read data from the processor 1000. The processor 1000 executes a program input from the storage device 1100 such as a ROM.

[0180] Although various exemplary embodiments and examples are described in this disclosure, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless variations not illustrated are anticipated within the scope of the technology disclosed in this specification. For example, this includes cases where at least one component is modified, added, or omitted, or where at least one component is extracted and combined with components of another embodiment.

[0181] 1: power conversion device; 10, 10X: semiconductor drive device; 11, 11a, 11b: gate drive unit; 12, 12a, 12b, 12A, 12B, 12F: overcurrent protection unit; 13, 13b, 13A, 13B, 13F: second overcurrent determination unit; 14, 14b, 14A: gate voltage reduction unit; 16, 16a, 16b: insulated communication unit; 17, 17A: first overcurrent determination unit; 18: control unit; 141, 141A: drive circuit; 142, 142A: amplifier circuit; 20, 20A, 20B: power converter; 21A, 21B: upper arm; 22A, 22B: lower arm; 23, 23A: leg circuit; 50, 50a, 50b, 50wG: semiconductor switching element; CS: collector sense terminal, CT: current-voltage conversion element, D1: clamp diode, D3: backflow prevention diode, EEa, EEb: current detection terminal, ES: emitter control terminal, G, Ga, Gb, G1, G2: gate terminal, OCD1, OCD2a, OCD2b: determination signal, Q1: first transistor, Q2: second transistor, Q3: third transistor, VA1, VA2: input potential, (R, C1): low-pass filter, (R, C1a): first low-pass filter, (R, C1b): second low-pass filter, CRD: constant current diode, (CRD, C1): low-pass filter, LF1, LF2: low-pass filters.

Claims

1. A power conversion apparatus comprising: a power converter having at least one leg circuit in which semiconductor switching elements are connected in series; and a semiconductor drive device that applies a voltage to the control terminal of the semiconductor switching element to drive the semiconductor switching element on and off, wherein the semiconductor drive device comprises: a control unit that generates an on / off command signal that determines the on / off state of the semiconductor switching element; a gate drive unit that applies a voltage to the control terminal of the semiconductor switching element based on the on / off command signal; a first overcurrent determination unit that uses a power supply voltage of a DC power supply as a reference voltage and determines an overcurrent in the semiconductor switching element based on the potential of the output terminal of the leg circuit; and an overcurrent protection unit that protects the semiconductor switching element by receiving a detection signal based on the voltage current between the main terminals of the semiconductor switching element and determining an overcurrent flowing in the semiconductor switching element, and a gate voltage reduction unit that reduces the voltage applied to the control terminal when an overcurrent is determined, wherein the overcurrent determination by the second overcurrent determination unit precedes the overcurrent determination by the first overcurrent determination unit, When the first overcurrent determination unit determines that an overcurrent is occurring, the control unit controls at least a semiconductor switching element of the leg circuit determined to be experiencing an overcurrent to an off state.

2. The power conversion device according to claim 1, wherein the first overcurrent judgment unit and the second overcurrent judgment unit each include a filter element that sets the time from when the signal input to each unit indicates an overcurrent state until the first overcurrent judgment unit and the second overcurrent judgment unit judge that an overcurrent has occurred.

3. A power conversion device as described in claim 2, wherein the time constant of the first filter element provided in the first overcurrent judgment unit is larger than the time constant of the second filter element provided in the second overcurrent judgment unit, and the time from when an overcurrent state signal is input to when the first overcurrent judgment unit judges that an overcurrent has occurred is shorter than the short-circuit allowable time determined by the short-circuit withstand capability of the semiconductor switching element.

4. A power conversion device as described in any one of claims 1 to 3, wherein the gate voltage reduction unit continues to reduce the voltage applied to the control terminal of the semiconductor switching element for a preset period when the second overcurrent determination unit determines that an overcurrent has occurred.

5. A power conversion device as described in claim 4, wherein the predetermined period during which the voltage applied to the control terminal is reduced is longer than the time difference between when the second overcurrent determination unit determines an overcurrent and when the first overcurrent determination unit determines an overcurrent.

6. The power conversion device according to any one of claims 1 to 5, wherein the first overcurrent determination unit comprises a first comparator that determines whether the potential of the output terminal of the leg circuit is near the positive potential of the DC power supply, and a second comparator that determines whether the potential of the output terminal of the leg circuit is near the negative potential of the DC power supply, and determines an overcurrent in the semiconductor switching element based on the output signal of the first comparator, the output signal of the second comparator, and the on / off command signal generated by the control unit.

7. The power conversion device according to claim 6, wherein the control unit generates the on / off command signal using at least one of the output signal of the first comparator and the output signal of the second comparator.

8. A power conversion device according to any one of claims 1 to 5, wherein the first overcurrent determination unit includes a third comparator that determines whether the potential of the output terminal of the leg circuit is near the positive electrode potential or near the negative electrode potential of the DC power supply, and switches the reference voltage input to the third comparator between a voltage that detects a potential near the positive electrode potential and a voltage that detects a potential near the negative electrode potential based on the on / off command signal generated by the control unit.

9. The power conversion device according to claim 8, wherein the control unit generates the on / off command signal using an output signal of the third comparator.

10. A power conversion device as described in any one of claims 1 to 9, wherein the first overcurrent judgment unit judges whether there is an abnormality in the main withstand voltage of the semiconductor switching element based on the potential of the output terminal of the leg circuit input to the first overcurrent judgment unit during a period when both semiconductor switching elements connected in series in the leg circuit are turned off.

11. A power conversion device as claimed in any one of claims 1 to 10, wherein the second overcurrent determination unit comprises a clamp diode that clamps the potential of a signal input unit that is an input unit for the detection signal to the potential of the control terminal, a first transistor to which the signal input unit is connected, and a low-pass filter provided in the signal input unit, and when the potential of the signal input unit reaches a set value, the first transistor turns on to determine an overcurrent in the semiconductor switching element.

12. The power conversion device according to claim 11, wherein the clamp diode clamps the potential of the input section of the detection signal to the potential of the control terminal when the semiconductor switching element is in an off state.

13. The power conversion device according to claim 11 or 12, wherein the second overcurrent determination section includes a backflow prevention diode connected in series to the first transistor.

14. A power conversion device according to any one of claims 11 to 13, wherein the low-pass filter provided in the signal input section comprises a first low-pass filter that is clamped to the potential of the control terminal by the clamp diode, and a second low-pass filter that has a larger capacitance than the first low-pass filter and is not clamped to the potential of the control terminal.

15. A power conversion device as described in any one of claims 1 to 14, wherein the gate voltage reduction unit comprises a drive circuit that reduces the voltage applied to the control terminal, and an amplifier circuit that amplifies the output signal from the second overcurrent determination unit to drive the drive circuit.

16. A power conversion device according to claim 15, comprising: a clamp diode that clamps the potential of a signal input section that is an input section for the detection signal to the potential of the control terminal; a first transistor to which the signal input section is connected; and a low-pass filter provided in the signal input section, wherein when the potential of the signal input section reaches a set value, the first transistor turns on to determine an overcurrent of the semiconductor switching element; the amplifier circuit of the gate voltage reduction section has a second transistor, and the drive circuit of the gate voltage reduction section has a third transistor; the first, second, and third transistors are each bipolar transistors, and when the first transistor turns on, the second transistor turns on and then the third transistor turns on, so that the base currents of the first, second, and third transistors increase in that order; and the voltage applied to the control terminal is reduced by the main terminal current of the third transistor.

17. A power conversion device according to any one of claims 1 to 16, wherein the semiconductor switching element is a multi-gate type semiconductor switching element having at least two or more control terminals, and the gate voltage reduction unit reduces the voltage of at least one control terminal of the multi-gate type semiconductor switching element to a gate threshold voltage or less when an overcurrent is determined to exist by the second overcurrent determination unit.

18. A power conversion device as claimed in any one of claims 1 to 17, wherein the second overcurrent determination unit determines an overcurrent in the semiconductor switching element based on any of the voltage between the main terminals of the semiconductor switching element, a current detected by a current detection element for detecting the main terminal current of the semiconductor switching element or a small current similar thereto, a voltage generated between the low-voltage side main terminal and a control reference terminal of the semiconductor switching element, and a detection signal based on a signal obtained by voltage-converting the rate of change of the main terminal current of the semiconductor switching element.

19. A power conversion device according to any one of claims 1 to 18, wherein the semiconductor switching element is a wide bandgap semiconductor formed from any one of semiconductor materials selected from the group consisting of silicon carbide, gallium nitride, gallium oxide-based material, and diamond.

20. The power conversion device according to any one of claims 1 to 19, which is an inverter that converts the DC voltage between the positive and negative terminals of the leg circuit into an AC voltage, or a step-up or step-down converter that has a reactor between the DC power source and the leg circuit, or a step-up or step-down inverter system that combines the inverter and the step-up or step-down converter.

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