Photovoltaic modules and methods of making same

Abstract

A photovoltaic (PV) module includes a substrate structure, a plurality of patterned substrate conductor elements, and a dielectric layer provided over the substrate and over the patterned substrate conductor elements. Adjacent first and second PV cells are part of a set of series-connected PV cells. A first set of top via structures extends through the first PV cell and the dielectric layer to a first set of the patterned substrate conductor elements, wherein each patterned substrate conductor element of the first set of patterned substrate conductor elements respectively is a bridge conductor that extends from a first point underneath the first PV cell to a second point underneath the second PV cell. A first set of bottom via structures extend through the dielectric layer to the first set of patterned substrate conductor elements at portions corresponding to the second PV cell.

Description

[0001] PHOTOVOLTAIC MODULES AND METHODS OF MAKING SAME

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to, and any other benefit of, U.S. Provisional Patent Application Serial No. 63 / 636,422 entitled PHOTOVOLTAIC MODULES AND METHODS OF MAKING SAME, filed April 19, 2024, and to U.S. Provisional Patent Application Serial No. 63 / 700,895 entitled PHOTOVOLTAIC MODULES AND METHODS OF MAKING SAME, filed September 30, 2024, the entire disclosures of which are fully incorporated by reference.

[0004] TECHNICAL FIELD

[0005] The present disclosure relates to photovoltaic modules, particularly those having one or more sets of photovoltaic cells connected in series, and to methods of making interconnections using via structures.

[0006] BACKGROUND

[0007] Since their first report in 2009, rapid improvements have enabled perovskite solar cells (PSCs) to become a promising technology for converting light to electricity as part of optoelectronic devices. To date, the power conversion efficiencies (PCEs) of solution-processed PSCs have been certified above 25 percent, which is higher than the current dominant photovoltaic technology based on multi-crystalline silicon. Whereas crystalline silicon is rigid, brittle, and requires costly, energy-intensive fabrication procedures, perovskites are flexible, easily processed at low temperatures, and up to a thousand times thinner. Furthermore, perovskites are solution- processable, which enables their manufacture with scalable, low-cost methods. These attributes open new opportunities to integrate solar power creatively and inexpensively into previously inaccessible markets, such as electric vehicles and buildings. PSCs also have the important advantage of maintaining acceptable PCE as the temperature increases, unlike silicon-based solar cells, which exhibit significant power loss in typical operating environments. The manufacturing and PCE advantages of PSCs have put them on the path to be the next generation technology for utility, commercial, and residential photovoltaic applications.

[0008] Commercial photovoltaic (PV) modules usually include a plurality of PV cells that are connected in series. Such series connection between cells is often referred to as the “interconnect”. In many cases, the PV module includes multiple sets of series-connected PV cells. In operation, the sets are typically connected in parallel and such a design can create a module that is more robust in operation, e.g., less sensitive to shadows or defective cells. Conventional interconnects are typically fabricated using a multi -scribe method using laser etching / ablation. Often three scribe steps are used to make an interconnect, commonly referred to as scribes Pl, P2, and P3 (“interconnect scribes”). The multiple sets of series-connected PV cells are typically made through another scribing step (often referred to in the art as a “P4 scribe”) that is generally orthogonal to the interconnect scribe direction. The P4 scribe isolates both the top and bottom electrodes by removing the entire device stack, and its function is to segment the device stack into one or more isolated “strings” of cells (sets of series-connected PV cells). The separate strings are later electrically connected in parallel to each other. The P4 scribes generally require less precision than conventional interconnect scribes.

[0009] While conventional scribing can be applied to flexible PV modules, e.g., those based on perovskite absorber layers, making the interconnects for flexible modules can be challenging. There are several drawbacks to the traditional 3 -scribe process. First, laser etching equipment can be very expensive. Along a manufacturing line three or more distinct laser scribing machines may be needed, which is costly. Alternatively, structures may be returned to a common laser etcher after deposition of the absorber layer for P2 and again after deposition of the top electrode layer for P3. This can seriously impact manufacturing takt time which also adds cost. Further, the laser etching steps require careful alignment to make sure P2 is properly spaced from Pl and P3 is properly spaced from P2. The need for alignment and high precision can slow production, add cost, and introduce sources for defects.

[0010] In addition, the traditional 3 -scribe process results in a significant amount of “inactive area” (i.e., dead zone) width where the PV module does not produce electricity, thus reducing the areal power production of the module. Each laser etch step requires a certain level of manufacturing tolerance, and the laser scribes themselves are limited in size by optical and process window constraints, which limits how small this inactive area can be made. Typically, flexible modules cannot be held as flat as a plane of rigid glass which negatively impacts manufacturing tolerances for the interconnect scribes.

[0011] As another challenge, transparent electrodes (e.g., conductive metal oxides) typically have relatively high sheet resistance. Conventional interconnects formed using P1-P3 require current to flow from one end of a PV cell electrode to the other end adjacent to the next PV cell in series. Resistance can cause numerous problems including overall reduction in PCE. To improve conductivity, metal lines (e.g., made from silver) may be patterned in contact with the transparent conductive metal oxide. This can lower the effective sheet resistance, but the metal lines cause some efficiency loss by shading and add complexity to the manufacturing process.

[0012] Despite research into various approaches, PVs based primarily on perovskites have yet to make a large market impact due at least in part to some of the unresolved problems noted above.

[0013] SUMMARY

[0014] There remains a desire for PSC devices that can be reliably manufactured at large scale at high speeds, at low cost, have high PCEs, and that can be made having large sizes or surface areas without unacceptable power loss.

[0015] In accordance with an embodiment of this disclosure, a photovoltaic (PV) module includes a substrate structure having a substrate, a plurality of patterned substrate conductor elements provided over the substrate, and a dielectric layer provided over the substrate and over the patterned substrate conductor elements. First and second PV cells are provided over the substrate structure, wherein the first and second PV cells are adjacent cells within a set of series-connected PV cells separated by a first scribe structure. Each of the first and second PV cells independently include i) a bottom electrode overlaying the dielectric layer, ii) a photoactive layer overlaying the bottom electrode, the photoactive layer having at least an absorber layer, and iii) a transparent top electrode overlaying the photoactive layer. A first set of top via structures extends through the first PV cell and the dielectric layer to a first set of the patterned substrate conductor elements, wherein each patterned substrate conductor element of the first set of patterned substrate conductor elements respectively is a bridge conductor that extends from a first point underneath the first PV cell to a second point underneath the second PV cell. The first set of top via structures include a first top via conductor that electrically connects the first set of patterned substrate conductor elements to the top electrode of the first PV cell. A first set of bottom via structures extends through at least the dielectric layer to the first set of patterned substrate conductor elements at portions corresponding to the second PV cell, wherein the first set of bottom via structures includes a first bottom via conductor that electrically connects the first set of patterned substrate conductor elements to the bottom electrode of the second PV cell. The first set of patterned substrate conductor elements, the first top via conductor, and the first bottom via conductor collectively form the series connection between the first and second cells.

[0016] In accordance with another embodiment of this disclosure, a method is provided for making a PV module having a plurality of sets of series-connected PV cells. The method includes forming a patterned substrate conductor over a substrate, the patterned substrate conductor including a plurality of bridge conductors. A patterned dielectric layer is formed over the patterned substrate conductor and substrate, the patterned dielectric layer including tapered bottom via openings corresponding to bottom via contact areas. A bottom electrode layer is deposited over the patterned dielectric layer and into the tapered bottom via openings to make electrical contact between the bottom electrode layer and the underlying patterned substrate conductor. A plurality of first top via scribes is formed, wherein each first top via scribe is formed by removing a portion of the bottom electrode layer along with a portion of the dielectric layer underneath the portion of the bottom electrode layer. A photoactive layer is deposited over the structure wherein the photoactive layer includes an absorber layer. A plurality of second top via scribes are formed in alignment with the first top via scribes, wherein each second top via scribe produces tapered top via openings extending to the underlying patterned substrate conductor corresponding to top via contact areas. A transparent top electrode layer is deposited over the structure and into the top via openings to make electrical contact between the transparent top electrode layer and the underlying patterned substrate conductor. One or more first scribe structures and one or more second scribe structures are formed to produce two or more sets of PV cells, each set including two or more PV cells, wherein adjacent cells in a set of PV cells are connected in series by a set two or more bridge conductors.

[0017] The present disclosure provides forPV modules and methods of their manufacture that may have one or more of the following advantages relative to conventional PV technology: improved manufacturing scalability, shorter manufacturing takt times, reduced manufacturing costs, simplified manufacturing processes; reduced manufacturing defects (higher yield); more reproducible manufacturing processes; reduced environmental impact; improved areal PCE; lower resistance electrodes; electrodes with higher optical transparency; increased physical durability or increased lifetime.

[0018] BRIEF DESCRIPTION OF DRAWINGS

[0019] FIGS. 1 A - ID are various views of a portion of a PV module according to some embodiments.

[0020] FIG. 2A is a top view of a PV module according to some embodiments.

[0021] FIG. 2B is a top view illustrating patterned substrate conductor elements provided over a substrate that may be used for the PV module of FIG. 2A according to some embodiments.

[0022] FIGS. 3A - 3D are top views showing the fabrication of a top via structure according to some embodiments. FIGS. 4A - 4E are top views showing the fabrication of a bottom via structure according to some embodiments.

[0023] FIG. 5A is a cross-sectional view of another non-limiting example of a substrate structure according to some embodiments.

[0024] FIG. 5B is a cross-sectional view of a portion of PV module including a bottom via structure using the substrate structure from FIG. 5A.

[0025] FIGS. 5C and 5D are top views of non-limiting examples of substrate structures according to some embodiments.

[0026] FIGS. 6A - 6M are cross-sectional views illustrating various non-limiting examples of top via structures and methods of their fabrication.

[0027] FIGS. 7A and 7B are each a top view of patterned substrate conductor elements (bridge conductors) provided on a substrate according to some embodiments

[0028] FIGS. 8A - 8C are top views of patterned substrate conductor elements and substrate structures that may be used for monofacial PV modules according to some embodiments.

[0029] FIG. 9 is a cross-sectional view of a non-limiting example of a perovskite PV structure according to some embodiments.

[0030] FIG. 10A is a top view of patterned substrate conductor elements that may optionally be used for monofacial PV modules according to some embodiments.

[0031] FIG. 10B is a top view of a substrate structure made using the patterned substrate conductor elements of FIG. 10A according to some embodiments.

[0032] FIG. IOC is a top view of a portion of a PV structure made using the substrate structure of FIG. 10B according to some embodiments.

[0033] FIG. 11 A is a top view of patterned substrate conductor elements that may optionally be used for monofacial PV modules according to some embodiments.

[0034] FIG. 1 IB is a top view of a portion of a PV structure made using the patterned substrate conductor elements of FIG. 11A according to some embodiments.

[0035] FIG. 12A is a top view of patterned substrate conductor elements that may optionally be used for monofacial PV modules according to some embodiments.

[0036] FIG. 12B is a top view of a portion of a PV structure made using the patterned substrate conductor elements of FIG. 12A according to some embodiments. FIG. 13 is a flow diagram illustrating general steps for manufacturing a PV module according to some embodiments.

[0037] DETAILED DESCRIPTION

[0038] It is to be understood that the drawings are for purposes of illustrating the concepts of the disclosure and may not be to scale. Terms like “overlaying”, “over” or the like include, but do not necessarily require, direct contact (unless such direct contact is noted or clearly required for functionality). Additional details of certain features useful in some embodiments of the present application may be found in U.S. Patent No. 11,108,007, U.S. Patent No. 11,342,130, U.S. Application Publication No. 2020 / 0377532, U.S. Application Publication No. 2022 / 0238807, PCT Application No. PCT / US2023 / 030527, PCT Application No. PCT / US2023 / 030576, PCT Application No. PCT / US2023 / 034120, PCT Application No. PCT / US2023 / 034146, PCT Application No. PCT / US2023 / 034137, and PCT Application No. PCT / US2023 / 078892, the entire contents of which are incorporated herein by reference for all uses.

[0039] A photovoltaic structure, e.g., a perovskite PV structure, is intended to receive light (typically visible, IR, or UV light) and convert it into electricity. As such, various layers and features may need to be reasonably transparent to this light to ensure that an appropriate amount reaches the perovskite layer(s). Herein, unless otherwise noted, the terms “transparent”, “transparency”, “transmissivity” or the like, are generally relative to the target wavelength or wavelength range for conversion to electricity. This target wavelength or wavelength range may be different for different systems. In some embodiments, the target wavelength range may correspond to the solar radiation spectrum or a portion thereof. In some cases, the target wavelength range may correspond to the visible light spectrum or a portion thereof. In some cases, the target wavelength range may correspond to the infrared or UV spectrum, or a portion thereof. In some embodiments, the target wavelength range may be defined as a particular wavelength, e.g., 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, or 750 nm, or any other wavelength of interest in the IR, visible, or UV portions of the spectrum intended for energy conversion. In some cases, a target wavelength range may be defined as an explicit range, e.g., 400 - 425 nm, 425 - 450 nm, 450 - 475 nm, 475 - 500 nm, 500 - 525 nm, 525 - 575 nm, 575 - 600 nm, 600 - 625 nm, 625 - 650 nm, 650 - 675 nm, 675 - 700 nm, 700 - 725 nm, 725 - 750 nm, or any combination of ranges thereof, or any other wavelength range of interest. In some embodiments, something (e g., a layer, a component, a structure, or the like) that is “transparent” transmits at least 50% of incident radiation within the target wavelength range, i.c., a transmittance (%T) of 50%. Something that is considered light transmissive generally transmits at least 10% of incident radiation within the target wavelength range. Transmittivities in the range of 10% up to 50% may be considered partially transparent. A light-transmissive component, layer, or structure may be either transparent or partially transparent. A transmittance of less than 10% may generally be considered opaque.

[0040] Besides the light-absorbing properties of a layer, a component, a structure, or the like, its apparent transparency may in some cases be affected by refractive index mismatches, surface structures, or other factors that may result in reflective losses and / or light scattering. Another way to describe transparency is in terms of absorptance (%A). In some embodiments, something that is “transparent” may have an absorptance of 50% or less with respect to incident radiation within the target wavelength range. Something that is considered light transmissive may have an absorptance of 90% or less of incident radiation within the target wavelength range. Absorptances in a range of 50% up to 90% may be considered partially transparent. An absorptance of greater than 90% may generally be considered opaque.

[0041] FIGS. 1 A - ID illustrate various aspects of a portion of a PV module according to some embodiments. FIG. 1 A is a top view of a portion of PV module 100 and FIG. IB is a cross- sectional view along cutline B-B from FIG. 1A. For added perspective, XYZ coordinate axes are also shown. The PV module may in some cases be based on a perovskite photovoltaic structure (where the photoactive layer includes a perovskite material absorber layer) but may alternatively be based on some other PV technology. For example, the photoactive layer may instead include an organic PV material absorbing layer, a CIGS (copper-indium-gallium-selenide) material absorbing layer, or a cadmium telluride material absorbing layer, optionally along with appropriate charge injecting layers and other materials suitable for these other systems.

[0042] PV module 100 may include one or more sets of PV cells such that the PV cells of each set are connected in series (PV cell 102-1, 102-2, and 102- 3). The PV cells are provided over substrate structure 170. Substrate structure 170 may in some cases include substrate 101, a plurality of patterned substrate conductor elements (144), and a dielectric layer 171. The patterned substrate conductor elements may be provided in a plane below dielectric layer 171, in particular, below the general plane of the upper surface (away from the substrate) of the dielectric layer 171. Note that dielectric layer 171 is electrically non-conductive and may alternatively be referred to as an insulating layer. In some embodiments, the patterned substrate conductor elements may have a thickness of 2 pm or less, alternatively 1 pm or less, 0.5 pm or less, 0.3 pm or less, or 0.2 pm or less.

[0043] Each PV cell may have a bottom electrode 105 overlaying dielectric layer 171. The bottom electrode may be a single conducting layer as shown in FIG. IB, but in some embodiments may instead have a multilayer structure or be a composite electrode that includes a bottom pattern of metal lines, e.g., provided on the dielectric layer 171 and a conducting layer such as a transparent conductive oxide, e.g., overlaying the metal lines and portions of the dielectric layer not covered by the metal lines. The bottom electrode may be transmissive or transparent to a target wavelength. In some other embodiments, the bottom electrode may instead be substantially opaque, e.g., the bottom electrode may include a metal layer (optionally a bilayer or multilayer stack of one or more metal sublayers and one or more conductive metal oxide sublayers) that may be continuous or alternatively patterned where the metal occupies more than about 90% of the electrode area.

[0044] A photoactive layer 106 is provided over the bottom electrode 105 and may include, e.g., a perovskite absorber layer. In some other cases, the photoactive layer may include an organic PV material absorber layer, a cadmium-telluride material absorber layer, or a CIGS (copper indium gallium selenide) material absorber layer. The photoactive layer may have a multilayer structure and include one or more carrier transport layers or other layers as described elsewhere herein, e.g., with respect to FIG. 9. In some embodiments, the photoactive layer may be 2 pm thick or less, alternatively 1 pm thick or less. The PV stack may in some cases have a tandem structure that includes multiple absorber layers.

[0045] A transparent top electrode 107 overlays the photoactive layer 106. Although shown as a single layer, the top electrode may optionally have a multilayer structure or be a composite electrode including a conducting layer, e.g., provided over the photoactive layer 106 and a top (second) pattern of metal lines provided on the conducting layer.

[0046] The PV cells in a series may be separated (isolated) by a series scribe 132 (along the X- axis) that extends through the PV cell stack (i.e., through the top electrode, photoactive layer, and bottom electrode) to the dielectric layer 171. In some cases, the series scribe may extend partly or fully through the dielectric layer, but it should not cut through or functionally damage the patterned substrate conductor elements. Series scribe 132 may also be referred to herein as a first scribe structure. Although not shown here, the different sets of PV cells may be separated by a second scribe structure (along the Y-axis), which may be referred to as a P4 scribe, also extending through the PV cell stack. In some embodiments, the first and second scribe structures may have similar widths and may even be formed from similar or the same laser equipment. Unlike traditional P1-P3 interconnect scribes, series scribe 132 is relatively easy to make, does not require high precision, and can be made on less expensive laser equipment.

[0047] FIG. 1 A highlights the positions of the underlying first set of patterned substrate conductor elements 144-1 and second set of patterned substrate conductor elements 144-2 as dotted lines. Other patterned substrate conductor elements are present, but not labelled in this view. For example, FIG. 1C is a top view showing various sets of substrate conductor elements 144 (144-0, - 1, -2, -3) provided on substrate 101 from the area of the PV module corresponding to FIG. 1A, but with the overlying layers removed for clarity. The first patterned substrate conductor elements 144-1 of the first set each extends from a first point under first PV cell 102-1 to a second point under second point PV cell 102-2 and are used to form a series electrical connection between the first and second PV cells. Similarly, the second patterned substrate conductor elements 144-2 of the second set each extend from a first point under second PV cell 102-2 to a second point under third PV cell 102-3 and are used to form a series electrical connection between the second and third PV cells. Patterned substrate conductor elements 144 may also be referred to herein as bridge conductors. Note that patterned substrate conductor element 144-3 may optionally connect the third PV cell to a fourth PV cell or to a busbar (neither of which are shown). Similarly, substrate conductor element 144-0 may connect the first PV cell 102-1 to a preceding PV cell in the series or to a busbar (neither of which are shown). Note that the use of “first PV cell” and “second PV cell” in the present discussion is intended only to convey that they are adjacent. They may not necessarily represent the very first and second PV cells of the full series.

[0048] At least a first PV cell 102-1 includes a first set of two or more top via structure 151-1 that extends through the first PV cell 102-1 and through the dielectric layer 171 to a first portion of one of the first set of patterned substrate conductor elements 144-1 underlying PV cell 102-1. In some embodiments, a via hole used to make the top via structure may be formed by laser etching / ablation. In some cases, the first top via structures 151-1 may each include a first top via conductor 153 that electrically connects the first portion of the first patterned substrate conductor element 144-1 to the top electrode 107 of the first PV cell 102-1. The top via conductor 153 is electrically isolated from at least the bottom electrode 105 and in some cases, may also be isolated from photoactive layer 106, e.g., by a patterned insulating material 152. In some cases, insulating material 152 is provided by patterned printing, e.g., by inkjet, onto the sidewalls of the via hole prior to application of the top via conductor 153. In some cases, the top via conductor may be applied by patterned printing, e.g., by inkjet into the via hole and onto a portion of the top electrode. A portion of the patterned insulating material 152 provided on the top electrode 107 may optionally act as a wall or barrier to help contain conductive ink of the first via conductor. A portion of the patterned insulating material 152 may be used to prevent top via conductor from coming in contact with the photoactive layer 106 so as to prevent or reduce interactions that may degrade either the photoactive layer 106 or the top via conductor 153. The conductive ink may include metal particles or a conductive carbon material or both. Although shown with vertical sidewalls, the top via structure / via hole may instead have tapered sidewalls. Top via structures are also discussed elsewhere herein, and may include alternative structures where the top electrode 107 acts as top via conductor.

[0049] At least a second PV cell, adjacent to the first PV cell, includes a first set of two or more bottom via structures 156-1 extending through the dielectric layer 171, and optionally through the second PV cell 102-2 (as illustrated in FIG. IB), to a second portion of the first patterned substrate conductor element 144-1 underlying second PV cell 102-2. In some embodiments, the via hole used to make the bottom via structure may be formed, e.g., by laser etching / ablation. The bottom via hole may in some cases include an upper via hole portion that extends through the top electrode and the photoactive layer to reveal the bottom electrode 105, and a lower via hole portion, narrower than the upper portion, that extends all the way through the bottom electrode and the dielectric layer 171 to the first patterned substrate conductor element 144-1. The first bottom via structures 156-1 each include a first bottom via conductor 158 that electrically connects the second portion of the patterned substrate conductor element 144-1 to the bottom electrode 105 of PV cell 102-2. The bottom via conductor 158 is electrically isolated from the top electrode 107, and optionally from the photoactive layer 106, e.g., by a patterned insulating material 157, although a physical separation is also envisioned that may later be filled by a non-patterned material (not shown here), e.g., an encapsulation layer. In some cases, insulating material 157 is provided by patterned printing, e.g., by inkjet, onto the sidewalls of the bottom via hole prior to application of the bottom via conductor 158. In some cases, the bottom via conductor may be applied by patterned printing, e.g., by inkjet into the via. The conductive ink may include metal particles or a conductive carbon material or both. Although shown with vertical sidewalls, the bottom via structure / via hole may instead have tapered sidewalls. Bottom via structures are also discussed elsewhere herein, and may include alternative structures where the bottom electrode 105 acts as bottom via conductor.

[0050] The first set of patterned substrate conductor elements 144-1, the first top via conductors 153 and the first bottom via conductors 158 collectively form a series connection between the first PV cell 102-1 and the second PV cell 102-2. In FIG. 1 A, there are a total of 3 patterned substrate conductor elements 144-1 in the first set, using a total of 6 first top via structures in the first PV cell 102-1 (2 per substrate conductor element) and 6 first bottom via structures in the second PV cell 102-2 (2 per substrate conductor element). However, this is just one embodiment and there can be more or fewer of each feature. That is, each patterned substrate conductor element has at least one top via structure and at least one bottom via structure, but there can be any number of top via structures and bottom via structures per patterned conductor element. The number of top via structures per patterned conductor element may be different than the number of bottom via structures per patterned conductor elements. The number of via structures may optionally vary between different patterned conductor elements.

[0051] As discussed elsewhere, the dimensions and number of each feature depend in part on, among other factors, the conductivity of the top and bottom electrodes, the conductivity of the via conductors, and the desired attributes of the PV module such as PCE and manufacturing costs. FIG. ID is a slightly magnified view of FIG. 1C illustrating just a few of the dimensions that may be considered with respect to the substrate conductor elements and via structure placement (dl - d8; discussed elsewhere). In some cases, the top and bottom via structures are distributed uniformly throughout their respective PV cell areas in order to ensure a relatively even collection of charge that is transferred in series to the adjacent cell. In some cases, a bridge conductor 144-1 of the first set of patterned substrate conductor elements and an adjacent bridge conductor 144-2 of the second set of patterned substrate conductor elements, may be considered a “bridge conductor pair”. Although patterned conductor elements are often shown in top view as having sharp comers, they may instead have rounded comers or simply be rounded at the end.

[0052] Turning again to FIG. 1 A, the second PV cell 102-2 is connected in series to a third PV cell 102-3 by a second set of patterned conductor elements 144-2 (bridge conductors) in a manner that may be analogous to the connection between PV cells 102-1 and 102-2. The second PV cell includes a second set of top via structures 151-2 which electrically connect the second set of patterned conductor elements 144-2 to the top electrode 107 of the second PV cell 102-2. The second set of top via structures 151-2 may be similar to first set of top via structures 151-1, but alternatively may be different. The third PV cell 102-3 includes a second set of bottom via structures 156-2 which electrically connect the second set of patterned conductor element 144-2 to the bottom electrode 105 of the third PV cell 102-3. The second set of bottom via structures 156-2 may be similar to first set of bottom via structures 156-1, but alternatively may be different.

[0053] FIG. 2A is a top view of a PV module 200 according to some embodiments. PV module 200 may include two or more sets of PV cells (202- l,y and 202-2, y), such that each PV cell of a set of is connected in series (202-x,l, 202-x,2, 202-x,3, and 202-x,4). For convenience, various cells may be referred to herein by their coordinates in the module using the nomenclature 202-x,y, where “x” represents the particular set of PV cells (i.e., which column) and “y” refers to which series position in the set (i.e., which row). This naming convention is completely arbitrary and non-limiting. FIG. 2A illustrates two sets of series-connected PV cells, where each set includes four cells connected in series. Although only two series sets are shown, the PV module may contain any number of such sets. Similarly, although four cells are shown connected in series for each set, there may be more or fewer such PV cells. PV module 200 may in some cases include PV cells as described with respect to the FIGS. 1A - ID and the portion of PV module 100 from these figures may represent a portion of PV module 200.

[0054] In addition to features previously described, the different sets of PV cells are separated by scribe 136 (along the Y-axis), which may be referred to as a P4 scribe, also extending through the PV cell stack. Scribe 136 may also be referred to herein as a second scribe structure. In some embodiments, the series scribe 132 and the P4 scribe 136 may have similar widths and may even be formed from similar or the same laser equipment. Unlike traditional P1-P3 interconnect scribes, series scribe 132 is relatively easy to make, does not require high precision, and can be made on less expensive laser equipment. PV module further includes a first busbar 140 and a second busbar 142 each of which collect current generated by the PV cells. A portion of the busbars are covered by dielectric layer 171, but at least an end portion of the busbars (along their long edges) are generally uncovered so as to allow further electrical contact. For simplicity, only a couple of the top via structures 151 (circles) and bottom via structures 156 (squares) are labelled, but these may be as previously described with respect to FIGS. 1 A - ID, or have some alternative structure, such as those described in FIGS. 5A - 5D and FIGS. 6A - 6K. FIG. 2A also indicates some additional PV cell dimensions, d9 and dlO, that are discussed elsewhere herein.

[0055] FIG. 2B is a top view illustrating a patterned substrate conductor provided over substrate 101 that may correspond to the patterned substrate conductor elements of perovskite module 200. If not noted otherwise, the term “patterned substrate conductor” may generally refer to any or all of the patterned substrate conductor elements which may include a first busbar 140, a second busbar 142, and the bridge conductors 144 for connecting adjacent cells in series as discussed elsewhere. In some embodiments, the busbars may include patterned extensions targeting areas for connection, e.g., busbar extensions 140e and 142e for busbars 140 and 142 respectively. In some cases, PV cells 202-1,1 and 202-2,1 may include a plurality of bottom via structures that connect the bottom electrodes of these cells to busbar extension 140e of first busbar 140. Similarly, PV cells 202-1,4 and 202-2,4 may include a plurality of top via structures that connect the top electrodes of these cells to busbar extension 142e of second busbar 142.

[0056] Suitable substrates 101 are discussed elsewhere herein. Although the substrate may in some cases be rigid, it preferably includes a flexible material such as PET or the like. The patterned substrate conductor may include any electrically conductive material. The conductivity of the patterned substrate conductor is higher than at least one of the PV cell electrodes to which it is connected, and usually both. The patterned substrate conductor may in some preferred embodiments, include a metal such as copper, silver, aluminum, or the like. Alternatively, the conductive material may include a conductive carbon material, metal nanowires, a conductive polymer, a conductive metal oxide, or even a mixture. The patterned substrate conductor may be printed from a conductive ink, e.g., by flexographic printing, inkjet printing, gravure printing, or some other printing technology. Alternatively, the patterned substrate conductor may be electroplated or pattern-etched from a continuous layer of conductive material. In some embodiments, the patterned substrate conductor may be pattern-applied by vapor deposition through a shadow mask, e.g., aluminum onto PET. The patterned substrate conductor may include a multilayer stack of metals to impart various useful properties. For example, a thin metal layer (e.g., 0.5 - 10 nm) of chromium or molybdenum may assist a thicker primary conductive metal layer (e.g. copper) by promoting adhesion, providing corrosion resistance, or reducing ion migration into sensitive PV stack layers. In some case, the primary conductive metal layer is sandwiched between two thin metal layers. The conductive material of a busbar may be the same as or different than that of another busbar or of the bridge conductors. The patterned substrate conductor may in some cases be transparent or transmissive, but in order to achieve higher conductivity than the top or bottom electrodes, they are most commonly opaque (transmitting less than 10%) to target radiation. The patterned substrate conductor material may also be designed to be highly reflective, to scatter light back into the absorbing layer or to aid laser ablation processes such as top via formation.

[0057] The thickness (Z direction) of the patterned substrate conductor is not particularly limiting so long as the PV cell structure may be uniformly applied over the substrate structure and the elements have sufficient electrical conductivity. In some cases, the thickness of the patterned substrate conductor elements is in a range of 50 - 100 nm, 100 - 200 nm, 200 - 400 nm, 400 - 600 nm, 600 - 800 nm, 800 nm - 1.0 microns, 1.0 - 1.5 microns, 1.5 - 2.0 microns, 2 - 3 microns, 3 - 4 microns, 4 - 5 microns, 5 - 7 microns, 7 - 10 microns, 10 - 15 microns, 15 - 20 microns, or any combination of ranges thereof. In some cases, the thickness of dielectric layer 171 relative to the patterned substrate conductor elements, especially bridge conductor 144, is in a range of 1 - 1.5x, 1.5 - 2x, 2 - 3x, 3 - 4x, 4 - 5x, 5 - 7x, 7 - lOx, 10 - 15x, 15 - 20x, or any combination of ranges thereof.

[0058] In some embodiments, substrate structure 170 may be well suited for bifacial PV modules that receive primary light from the top (through top electrode) and some light from the bottom (through the patterned substrate conductor and bottom electrode). In some embodiments for bifacial PV modules, the area of substrate 101 occupied by the patterned substrate conductor elements (140, 142, 144), or alternatively by just the bridge conductors 144, is in a range of 1 - 2%, 2 - 3%, 3 - 5%, 5 - 7%, 7 - 10%, 10 - 15%, 15 - 20%, 20 - 30%, 30 - 40%, 40 - 50%, or any combination of ranges thereof. Such values may apply particularly to patterned substrate conductor elements that are substantially opaque. Alternatively, the occupied areas may be higher if the patterned substrate conductor elements are transparent or transmissive. In the case of monofacial PV modules, e.g., where the substrate or the bottom electrode is not transmissive, there is no particular limit on this surface area occupied by the patterned substrate conductor elements, which may include any of the above ranges or even higher levels, e.g., 50 - 60%, 60 - 70%, 70 - 80%, 80 - 90%, 90 - 95%, 95 - 99%, or any combination of ranges thereof. Dielectric layer 171 may include an electrically insulating (dielectric) polymeric material, an inorganic material (e.g., a glass, ceramic, or certain metal oxides), or a mixture. In some embodiments, the material of the dielectric layer has a resistivity of at least 105ohm-cm, or alternatively, at least IO10ohm-cm. In some embodiments, depending on the material, dielectric layer 171 may, e.g., be extruded or coated from a fluid mixture. The dielectric layer may in some cases be formed from a curable material, such as a UV-cured polymer or a thermally cured polymer. In some cases, dielectric layer 171 may have a multilayer structure to tailor interfacial properties between it and the underlying substrate / patterned substrate conductor and the overlying bottom electrode of the PV cell structure. The surface of the dielectric layer may also be modified to increase reflection back into the device, for example, using nanoimprinting methods to form nano- or micro- light trapping features (i.e. plasmonic or pyramidal). This may increase the total pathlength of light through the device, enabling high efficiencies or reduced absorber layer thickness and easier processability.

[0059] Dielectric layer 171 may optionally be pattern applied (e.g., by printing) or patterned after application of a dielectric material layer (e.g., by laser ablation, photolithography, or the like). For example, it may be useful to pattern the dielectric layer so that it does not cover edge areas of the busbars. In some cases, dielectric layer 171 may be formed from a photo-patternable material, e.g., a photopolymer that it may be coated, exposed with desired pattern, and chemically developed to form a desired pattern in the dielectric layer. In some embodiments, the dielectric material may be selected or modified with dyes so that it absorbs radiation to aid in laser ablation, e.g., it may have functionally useful optical absorption at about 212 nm, 266 nm, 343 nm, 355 nm, 488 nm, 515 nm, 532 nm, 1030 nm, 1064 nm, or 1321 nm (or any other common laser wavelength). In some cases, the dielectric layer may absorb at least 10% of incident laser radiation at one or more of these wavelengths. Such laser radiation may, e g., be used when forming the top vias, bottom vias, the first scribe structure, or second scribe structures. If the dielectric is UV-curable, one may in some cases use a laser wavelength other than UV, since the dielectrics absorption properties in that range may vary with time, process, and formulation. If using a dye in the dielectric layer to improve laser ablation efficiency with a UV-cured dielectric layer, it may be desirable to use a dye having relatively low absorption in the UV-range (for example, with an absorption peak at 515 nm or in the infrared). This way, the laser absorption of the material can be liberally modified without concern for affecting the UV-cure depth or quality. If bifaciality is desired, the light absorption of the dielectric layer should also be selected for compatibility so that it does not absorb too much of the target radiation for photovoltaic energy conversion. As described elsewhere, in some embodiments, the insulating layer may be pattern applied to form a bottom via hole without the need for a laser ablation step.

[0060] The dielectric layer may in some instances be applied in multiple coatings. For example, instead of applying a single 2 pm thick dielectric layer, two 1 pm layers (first and second dielectric sublayers) may instead be applied. Thin fluidic coatings may be susceptible to defects such as random voids that may produce shorts or other issues in the PV module that degrade performance or manufacturing yield. By coating multiple layers, the risks of voids may be substantially reduced since there is a low probability that two such defects will overlap. In some cases, multiple thin layers may produce a more effective dielectric layer than a single coating of the same total thickness. That is, a single-step application may require a significantly higher thickness to meet the performance of multiple thin layers having a lower total thickness. Thinner dielectric layers have cost advantages and are generally better for laser ablation steps. In some cases, thinner dielectric layer may reduce the energy needed for ablation, e.g., during a via scribe step. Higher ablation energies, e.g., with thicker dielectric layers, may make it more difficult to avoid unwanted damage to underlying patterned conductive substrate elements, delamination of PV stack layers, and discontinuities along via sidewalls.

[0061] FIGS. 3A - 3D are top views showing the fabrication of a top via structure according to some embodiments. FIG. 3 A represents a zoomed in portion of a PV cell illustrating the top electrode conducting layer 107. In FIG. 3B, a via hole 150 has been formed through the PV cell layers, through the dielectric layer, and to a first portion of a patterned substrate conductor element 144. In FIG. 3C, patterned insulating material 152 has been applied to via hole sidewalls. In some cases (as shown), the pattern of insulating material may include a well structure 154 to contain conductive ink and prevent it from spreading too far from beyond the via structure area. The outer perimeter of the pattern may have a thicker deposit of the insulating material than the center line. FIG. 3D shows the finished top via structure 151 after deposition of the top via conductor 153. Top via structure 151 in this figure may correspond to the top via structures shown in FIG. IB. Although shown as rectangular, the via hole may be any shape. Further, although shown with respect to substrate conductor element 144 (e.g., a bridge conductor), it may alternatively be used when connecting to a busbar or busbar extension. As viewed from the top (e g., along the Z axis in the relevant figures), a via hole 150 may have a length, width, or diameter in a range of 5 - 10 pm, 10 - 20 pm, 20 - 40 pm, 40 - 60 pm, 60

[0062] - 80 pm, 80 - 100 pm, 100 - 120 pm, 120 - 150 pm, 150 - 200 pm, 200 - 300 pm, 300 - 500 pm, 500 - 700 pm, 700 - 1000 pm, or any combination of ranges thereof, or even greater than 1 mm in some cases. In some embodiments, via hole 150 may occupy an area in a range of 0.0004 - 0.001 mm2, 0.001 - 0.002 mm2, 0.002 - 0.005 mm2, 0.005 - 0.01 mm2, 0.01 - 0.02 mm2, 0.02 - 0.05 mm2, 0.05 - 0.1 mm2, 0.1 - 0.2 mm2, 0.2 - 0.5 mm2, 0.5 - 1.0 mm2, or any combination of ranges thereof. In some embodiments, these areas may correspond to a contact area between a top via conductor and a corresponding patterned substrate conductor element.

[0063] FIGS. 4A - 4D are top views showing the fabrication of a bottom via structure according to some embodiments. FIG. 4A represents a zoomed in portion of a PV cell illustrating the top electrode conducting layer 107. In FIG. 4B, an upper via hole 155 has been formed through the top electrode and the photoactive layer, but not through the bottom electrode (105). In FIG. 4C, a lower via hole 155’ is formed through the bottom electrode, through the dielectric layer 171, and to a second portion of patterned substrate conductor element 144 (e.g., a bridge conductor). An optional patterned insulating material 157 is provided along the sidewalls of the upper via hole 155 (either before or after forming the lower via hole 155’. FIG. 4D shows the finished bottom via structure 156 after deposition of the bottom via conductor 158. Bottom via structure 156 in this figure may correspond to the second via structures shown in FIG. IB. In some embodiments, upper via hole 155 may have a length, width, or diameter in a range of 40 - 60 pm, 60 - 80 pm, 80 - 100 pm, 100 - 120 pm, 120 - 150 pm, 150 - 200 pm, 200 - 300 pm, 300 - 500 pm, 500 - 700 pm, 700 - 1000 pm, or any combination of ranges thereof, or even greater than 1 mm in some cases. In some embodiments, via hole 155 may occupy an area in a range of 0.001 - 0.002 mm2, 0.002 - 0.005 mm2, 0.005 - 0.01 mm2, 0.01 - 0.02 mm2, 0.02 - 0.05 mm2, 0.05 - 0.1 mm2, 0.1 - 0.2 mm2, 0.2 - 0.5 mm2, 0.5 - 1.0 mm2, 1.0 mm2- 1.5 mm2or any combination of ranges thereof. The lower via hole 155’ is generally smaller than the upper via hole with respect to length, width, or diameter, and may occupy an area that is, relative to the upper via hole 155, in a range of 1 - 2%, 2

[0064] - 5%, 5 - 10%, 10 - 20%, 20 - 30%, 30 - 50%, 50 - 70%, or 70 - 90%, or any combination of ranges thereof. As viewed from the top, the dimensions of lower via hole 155’ may in some embodiments be similar to that of via hole 150 for the top via structure. In some embodiments a contact area between a bottom via conductor and a corresponding patterned substrate conductor element may be in a range of 0.0004 - 0.001 mm2, 0.001 - 0.002 mm2, 0.002 - 0.005 mm2, 0.005 - 0.01 mm2, 0.01 - 0.02 mm2, 0.02 - 0.05 mm2, 0.05 - 0.1 mm2, 0.1 - 0.2 mm2, 0.2 - 0.5 mm2, 0.5 - 1.0 mm2, or any combination of ranges thereof.

[0065] FIG. 4E illustrates an alternative embodiment where bottom via structure 156E does not use the patterned insulating material 157, but instead includes bottom via conductor 158E patterned with sufficient precision so that it does not touch the sidewalls of via hole 155.

[0066] Although generally illustrated in FIGS. 3 and 4 as being square, a via hole may be any shape such as circular, oval, rectangular, triangular, pentagonal, hexagonal, polygonal, or irregular, and comers (if any) may be sharp or rounded. For efficient manufacturing purposes, a via formed by laser ablation may advantageously be formed by a single laser pulse (or pulse burst) and therefore will generally be circular. The profile of a laser-ablated via may be tuned using beamshaping optics such as top hat or Bessel beam diffractive optical elements. These optics can modify the slope and continuity of the via sidewall, prevent delamination of target layers, and reduce undesirable damage to underlying structures, as well as reduce the laser energy required. In some cases, a top or bottom via structure may be characterized by a via opening length that is substantially aligned with the longer dimension of the patterned substrate conductor element (e.g., in top view, along the Y axis) and by a via opening width that substantially orthogonal to the via opening length (e.g., in top view, along the X axis). In some embodiments, the via opening length is larger than the via opening width, e.g., at least l. lx, 1.5x, or 2x larger. In some cases, the via opening or via structure may be characterized as having an oblong shape with an aspect ratio of at least 2: 1, alternatively at least 3:1.

[0067] In some cases, a laser etching system used for forming via holes may be in communication with a machine vision system to ensure alignment of via holes with the desired underlying patterned substrate conductor. Due to the high density of vias that may in some cases be required over a large area, ultra-high speed scanners such as polygon scanners may be used with laser etching tools, instead of galvanometric scanners. Since the underlying substrate conductor may not be readily visible from the top, fiducial marks may optionally be added, e.g., near an edge of the substrate structure, that align with features of the patterned substrate conductor or other elements. In some cases, a machine vision system may be provided beneath the PV module during its fabrication to locate patterned substrate conductor areas. Eddy currents or other indirect methods of locating patterned substrate conductor areas may also be used. Insulating material 152, 157 may in some cases be applied from an insulator ink applicator which may in part be housed in a processing station, optionally along with some or all of the laser etching equipment. Such processing station may further include sensors to ensure quality control, alignment, and proper application of insulating materials.

[0068] Some non-limiting examples of insulator inks and insulating materials may include polymers, ceramics, and graphitic materials. Some non-limiting examples of polymeric materials may include acrylics, epoxies, urethanes, silicones, polyamines, or polyimides. Some non-limiting examples of ceramic materials may include aluminum oxide, silicon dioxide, magnesium oxide, and titanium oxide. Some non-limiting examples of graphitic materials may include graphene oxide and carbon nitride. Additionally, such insulating materials may be dyed or selected to absorb light over a specific wavelength range, in order to facilitate via formation by laser ablation.

[0069] Although described as formed from patterned deposition of a fluid material, which has high-speed manufacturing benefits, the patterned insulating materials may in some cases be formed using alternative methods such as vapor deposition of an appropriately insulating material, e.g., through a shadow mask. Alternatively, an insulating precursor material (a type of insulator ink) may be itself photo-patternable so that it may be generally coated, exposed with desired pattern, and chemically developed, to form the patterned insulating materials.

[0070] In some embodiments, the via conductors may in some cases be formed from a conductive ink which may be deposited from a conductive ink applicator. In some cases, the ink applicator may be an inkjet device, but other applicators may be used such as a screen printing, syringe, an extruder, or some other appropriate device capable of patterned deposition. The conductive ink may be dried, cured, sintered, or some combination. Drying may be used to remove solvents and may include heating (e.g., in an oven, contact with a hot gas (air or inert), exposure to infrared radiation, use of a flashlamp, or the like) optionally at reduced pressure. Curing may initiate a chemical reaction that causes the conductive ink to become more solid, e.g., polymerization, crosslinking, or the like. In some cases, curing includes exposure to UV radiation, but may alternatively or in combination, include a heating step, e.g., in an oven, contact with a hot gas (air or inert), or exposure to infrared radiation. In many cases, the deposited conductive ink may include a sintering step which is also a type of heating step that may improve the conductivity of the via conductors, particularly those formed from metal-containing conductive inks. In some cases, a flashlamp, a laser, an infrared source, or some other photonic device may be used to induce sintering (or drying or curing).

[0071] Although described as formed from patterned deposition of a fluid material, which has high-speed manufacturing benefits, the via conductor may in some cases be formed using alternative methods such as vapor deposition of an appropriately conducting material, e.g., through a patterned shadow mask.

[0072] Although various figures herein show the via conductor filling the via, the via conductor may instead be applied along sidewalls of the via hole when making connection between an electrode and patterned substrate conductor element, and not necessarily fill the entire space. This may save on the amount of conductive ink used for the via conductor, which may have cost and manufacturing process benefits. As also discussed elsewhere herein, the top or bottom via conductors may in some cases be formed in a common step when forming the respective top or bottom electrodes.

[0073] In some embodiments, laser ablating through a PV cell stack to form a bottom via structure may not be necessary, and instead, a patterned dielectric layer 171 may be used. FIG. 5A is a cross-sectional view of another non-limiting example of a substrate structure 170 according to some embodiments. Substrate structure 170 may include a patterned substrate conductor element 144 (e.g., a bridge conductor) provided on a surface of substrate 101. In some embodiments, the edge of substrate conductor element 144 may be rounded or tapered and characterized by a conductor element taper angle 0ce, e.g., as measured relative to the plane of the substrate 101 surface. The presence of a taper may improve the coating characteristics of the overlaying dielectric layer 171 (this may be the case for other embodiments, too). In some embodiments, the conductor element taper angle 0cemay be less than about 70°, alternatively, less than 60°, or less than 45°. In some cases, taper angle 0ceis in a range of 10° - 20°, 20° - 30°, 30° - 40°, 40° - 50°, 50° - 60°, or any combination of ranges thereof.

[0074] Substrate structure 170 further includes a patterned dielectric layer 171 (which may also be referred to as a patterned insulating layer 171) provided over the substrate and the patterned substrate conductor. Patterned dielectric layer 171 may include a rounded or tapered opening 555 that exposes a contact area of the underlying patterned substrate conductor element 144 (e.g., a bridge conductor). The tapered opening of the patterned dielectric layer for a bottom via structure may be characterized by a bottom via dielectric taper angle 0db, e.g., measured relative to the plane of the upper surface of patterned substrate conductor element 144. The presence of a taper may improve the coating characteristics of the overlaying PV cell layers as shown in FIG. 5B. In some embodiments, the bottom via dielectric taper angle 0db may be less than about 70°, alternatively, less than 60°, or less than 45°. In some cases, taper angle 0db is in a range of 10° - 20°, 20° - 30°, 30° - 40°, 40° - 50°, 50° - 60°, or any combination of ranges thereof. The patterned dielectric layer 171 may be formed from a photopolymer, by photolithography, or by patterned printing, e.g., by screen printing, inkjet, or the like. Alternatively, the pattern in the dielectric layer 171 may be formed by removing a portion of the dielectric layer with a laser. A subsequent heat treatment may optionally occur at a later stage in order to modify the via sidewall, such as softening the dielectric or stack layers to reduce undercutting and create a continuous slope down to the substrate conductor element.

[0075] As shown in FIG. 5B, the bottom electrode 105, photoactive layer 106, and top electrode 107 may be applied over the substrate structure 170 of FIG. 5 A. In this embodiment, the bottom electrode 105 makes direct contact to the exposed contact area of the patterned substrate conductor element 144, i.e., the bottom electrode acts as the bottom via conductor to form bottom via structure 556. The taper or rounded edge in the patterned dielectric ensures that these PV cell layers remain continuous throughout this section. The bottom via structure of FIG. 5B may in some cases be simpler and less expensive to manufacture than the process illustrated in FIGS. 4A - 4D, e.g., fewer steps, no need for laser ablation, no need for patterned metal deposition, and the like. Further, the bottom via structure of FIG. 5B does not create any PV cell dead zone with respect to light coming through top transparent electrode 107. Also, the conductive materials of the bottom electrode are designed to be highly compatible with the PV cell whereas metal inks (especially silver) can sometimes migrate over time and cause performance degradation.

[0076] FIG. 5C is a top view of a portion of a substrate structure 570c showing how a patterned dielectric 171 may be used to provide multiple bottom via openings 555 in alignment with the underlying patterned substrate conductor elements 144. Though not visible except at the bottom via openings, the position of each patterned substrate conductor element 144 is shown by the dashed outline for clarity. Substrate structure 570c of this embodiment includes two bottom via openings per patterned substrate conductor element, but as mentioned elsewhere, there can be just one or more than two per patterned substrate conductor element. FIG. 5D is a top view of a portion of another substrate structure 570d according to some embodiments. Here, instead of multiple bottom via openings per patterned substrate conductor, there may be just one relatively large bottom via 555’ extending across much of the portion of the substrate conductor elements 144 intended for bottom vias. This may further simplify patterning and provide a larger overall contact area between the bottom electrode and the patterned substrate conductor element.

[0077] In some embodiments, the top via structure may be made in a manner that utilizes the top electrode as the top via conductor rather than a separately applied metal ink. FIG. 6A is a cross- sectional view of a starting structure 681 for such fabrication. The starting structure 681 may include substrate structure 170 (including substrate 101, patterned substrate conductor element 144 (e.g., a bridge conductor that may optionally be tapered at its edge) provided on the substrate, and dielectric layer 171 provided over the substrate and substrate conductor element. The bottom electrode 105 is also provided over the top of dielectric layer 171. In FIG. 6B, a first tapered opening 650’ is formed in the dielectric layer / bottom electrode (e.g., by laser ablation / etching) that exposes an area of the underlying patterned substrate conductor element 144 and forms intermediate structure 682. The dielectric layer at the opening 650’ may be characterized by a top via dielectric taper angle 0*, e.g., as measured relative to the plane of the top surface of patterned substrate conductor element 144. The presence of a taper may improve the coating or deposition characteristics (e.g., continuity) of the overlaying PV cell layers, e.g., ensuring continuity. In some embodiments, the top via dielectric taper angle Gat may be less than about 70°, alternatively, less than 60°, or less than 45°. In some cases, taper angle 0dt is in a range of 10° - 20°, 20° - 30°, 30° - 40°, 40° - 50°, 50° - 60°, or any combination of ranges thereof.

[0078] Next, as shown in FIG. 6C, a photoactive layer 106 is coated over intermediate structure 682 to form intermediate structure 683. The photoactive layer 106 optionally includes an interfacial layer 812 interposed between the bottom electrode 105 and the other layers of photoactive layer 106. As described elsewhere herein, there are numerous potential uses for interfacial layers. Here, one particular use may be to cover the exposed edge of bottom electrode 105. In some embodiments, the bottom electrode may include a metal layer, or a set metal lines, e.g., made of copper or silver. The interfacial layer 812 may act as a barrier layer to reduce diffusion of the metal into the rest of the photoactive layer 106. In some non-limiting examples, the interfacial layer may include a metal oxide such as a titanium oxide, an aluminum oxide, a tin oxide, a zinc oxide, an indium oxide, a nickel oxide, ITO, AZO, or the like, optionally formed by atomic layer deposition. In some other non-limiting examples, the interfacial layer may include graphene, graphene oxide, reduced graphene oxide, or a polymer. In some cases (not shown), the photoactive layer may include a protective interfacial layer at its upper surface that may help protect the surface from subsequent processing steps, such as laser ablation / etching. Although not illustrated, a top electrode layer may also be provided over the photoactive layer 106 so long as it permits patterned removal as described in FIG. 6D.

[0079] In FIG. 6D, a portion of the photoactive layer 106 including interfacial layer 812 (and any optional top electrode or protection layer) is removed (e.g., by laser ablation / etching) in the area of the tapered dielectric opening to expose a contact area 650 of the patterned substrate conductor element, thereby forming intermediate structure 684. Although shown as approximately the same in size, contact area 650 may be different than opening 650’. The patterned removal of the photoactive layer 106 forms a tapered photoactive layer opening characterized by a photoactive layer taper angle 9Pt. The photoactive layer taper angle 0pt(e.g., as measured from the plane of the patterned substrate conductor element 144) may be less than about 70°, alternatively, less than 60°, or less than 45°. In some cases, taper angle 0pt is in a range of 10° - 20°, 20° - 30°, 30° - 40°, 40° - 50°, 50° - 60°, or any combination of ranges thereof. As shown in FIG. 6D, taper angle 0ptis larger than taper angle 0*, but in other embodiments, it may be about the same or even smaller, e.g., when contact area 650 is smaller than area 650’.

[0080] Some other non-limiting embodiments of intermediate structure 684 are illustrated in FIG. 6F (intermediate structure 684f, contact area 650f) and FIG. 6G (intermediate structure 684g, contact area 650g). For intermediate structure 684f, the photoactive layer 106 is only partially removed over opening 650’ (some of photoactive layer 106 still covers the patterned substrate conductor element 144) and contact area 650 is smaller than opening 650’. For intermediate structure 684g, the photoactive layer 106 is removed from both the opening 650’ and also partway up the sidewalls of the taper of dielectric layer 171 . An advantage of intermediate structure 684g relative to 684f is that none of the photoactive layer 106 is in direct contact with the substrate conductor element 144. This can reduce potentially harmful metal migration from the substrate conductor element into the photoactive layer. That is, in some embodiments, the photoactive layer or absorber layer does not contact the patterned substrate conductor element. A non-limiting method for making intermediate structure 684g is shown briefly in FIGS. 6L and 6M. Structure 681 / in FIG. 6L includes an opening 665 / that may be formed from structure 681 (FIG. 6A) by patterned removal of the bottom electrode 105 and some of dielectric layer 171, e.g., by laser ablation. This may be referred to as first top via scribe step. Next a photoactive layer 106 (including interfacial layer 812) is applied over structure 681 / to form structure 683m. A second top via scribe step may be used on this structure to form intermediate structure 684g shown in FIG. 6G.

[0081] Numerous other intermediate structures corresponding to 684 can be envisioned. For all embodiments, it is particularly important to ensure that the bottom electrode 105, including at its edge, remains covered with photoactive layer 106 (which may optionally include interfacial layer 812)

[0082] Turning to FIG. 6E, a transparent top electrode 107 is next deposited onto intermediate structure 684. The top electrode extends down the taper of the photoactive layer 106 to contact area 650 of patterned substrate conductor element 144 thereby forming top via structure 651 where the top electrode acts as the top via conductor. The method shown in FIGS. 6A - 6G (as well as in FIGS. 6H - 6K below) may have manufacturing throughput and cost advantages, e g., by eliminating the need for patterning a top via conductor, e.g., by a metal ink. Also, the conductive materials of the top electrode are designed to be highly compatible with the PV cell whereas metal inks (especially silver) can sometimes migrate over time and cause performance degradation. While still creating some dead zone, (e.g., approximately corresponding to the bracket used to label top via structure 651 in FIG. 6E) the inactive area may be less than some other top via structures.

[0083] FIGS. 6H - 6K are cross-sectional views illustrating another embodiment for making top via structures that utilize the top electrode as the top via conductor. FIG. 6H is similar to FIG. 6A, except that the bottom electrode 105h has been patterned to include areas or openings 665 where there is no bottom electrode over the dielectric layer to form structure 681h. The pattern can be made by pattern printing bottom electrode 105h or by patterned removal of the bottom electrode to form electrode opening 665.

[0084] Next, as shown in FIG. 61, a photoactive layer 106 (in this case including optional interfacial layer 812) is coated over structure 681h to form intermediate structure 683i. In FIG. 6J, both the photoactive layer and the dielectric layer are removed (e.g., by laser ablation / etching) in alignment with bottom electrode opening 665 to form a tapered opening and expose contact area 650j of the patterned substrate conductor element, thereby forming intermediate structure 684j . Note that the removal is such that the edge of bottom electrode remains covered with photoactive layer 106. A taper angle 0db (e.g., as measured from the plane of the patterned substrate conductor element 144) may be less than about 70°, alternatively, less than 60°, or less than 45°. In some cases, taper angle 0db is in a range of 10° - 20°, 20° - 30°, 30° - 40°, 40° - 50°, 50° - 60°, or any combination of ranges thereof.

[0085] Turning to FIG. 6K, a transparent top electrode 107 is next deposited onto intermediate structure 684j The top electrode extends down the taper of the photoactive layer 106 and dielectric layer 171 to contact area 650j of patterned substrate conductor element 144 thereby forming top via structure 651k where the top electrode acts as the top via conductor. The photoactive layer 106 advantageously does not contact the patterned substrate conductor element 144 in the present embodiment.

[0086] In some cases, a PV module may use bottom via structures where the bottom via conductor includes the bottom electrode (e.g., as described in FIGS. 5A - 5D) in combination with top via structures where the top via conductor includes the top electrode (e.g., as described in FIGS. 6A - 6K).

[0087] Feature dimensions

[0088] The performance of the PV module depends in part on the dimensions and properties of the various features forming the series connections in addition to the size of the PV cells themselves.

[0089] Referring again to FIG. ID, there is shown a non-limiting set of dimensional considerations. For example, each patterned substrate conductor element 144 (e.g., a bridge connector) may be characterized by a width dl (X-axis), length d2 (Y-axis), spacing d3 between first and second sets of patterned conductor elements (or spacing between the patterned conductor elements of the bridge conductor pair), distance d4 between patterned conductor elements within a set, spacing d5 between an end of a patterned conductor element and the edge of a PV cell in the Y direction, spacing d6 between a patterned conductor element and the edge of a PV cell in the X direction, spacing d7 between top via structures, and spacing d8 between bottom via structures, just to name a few. Other non-limiting factors for consideration include the conductivity / resistance of the substrate conductor element, the resistance of the via conductor, the length or height of the via conductor connecting the substrate conductor element to the respective electrode, the number of bridge conductors between PV cells (i.e., the number of bridge conductors within a set), the number of top via structures per PV cell and / or per bridge conductor, the number of bottom via structures per cell and / or per bridge conductor, the conductivity / resistance of the bottom and top electrodes, the diameter, contact area, and / or “dead zone” area of the top via structures, the diameter, contact area, and / or “dead zone” area of the bottom via structures.

[0090] Referring again to FIG. 2A, the first scribe structure 132 may have a width (measured along the Y-axis) that is the same as or different from the width of the second scribe structure 136 (measured along the X-axis). The width of each scribe structure may be independently selected and may in some embodiments be in a range (which may be measured as minimum, maximum, or an average) of 5 - 10 pm, 10 - 20 pm, 20 - 40 pm, 40 - 60 pm, 60 - 80 pm, 80 - 100 pm, 100 - 120 pm, 120 - 150 pm, 150 - 200 pm, 200 - 300 pm, 300 - 400 pm, 400 - 500 pm or any combination of ranges thereof. In some preferred embodiments, a scribe structure has a width that is less than 60 pm, alternatively less than 40 pm. The width of a scribe structure may vary across the module.

[0091] In some embodiments, the spacing between second scribe structures 136 (e.g., when a PV module has 3 or more sets of series-connected PV cells) may be larger than the spacing between first scribe structures 132. In some cases, the spacing between first scribe structures 132, or alternatively the width d9 of a PV cell (which may also be referred to as Wceii), may be in a range of about 0.3 - 0.4 cm, 0.4 - 0.5 cm, 0.5 - 0.7 cm, 0.7 - 1.0 cm, 1 - 2 cm, 2 - 3 cm, 3 - 4 cm, 4 - 5 cm, or any combination of ranges thereof, or even higher than 5 cm. In some preferred cases, the spacing between first scribe structures 132, or alternatively the width d9 of a PV cell, may be in a range of 0.4 - 1.7 cm. In some embodiments, the spacing between second scribe structures 136, or alternatively the length dlO of a PV cell (which may also be referred to as Lceii), may be in a range of 1 - 2 cm, 2 - 4 cm, 4 - 6 cm, 8 - 10 cm, 10 - 12 cm, 12 - 15 cm, 15 - 20 cm, 20 - 40 cm, any combination of ranges thereof, or even higher than 40 cm. In some preferred cases, the spacing between second scribe structures, or alternatively the length dlO of a PV cell, may be in a range of 2 - 6 cm. In some embodiments, the width of the PV cell is less than the length of the PV cell. In some cases, a ratio of (Wceii / Lceii) is in a range of 0.02 - 0.05, 0.05 - 0.1, 0.1 - 0.2, 0.2 - 0.3, 0.3 - 0.4, 0.4 - 0.5, 0.5 - 0.6, 0.6 - 0.7, 0.7 - 0.8, 0.8 - 0.9, 0.9 - 0.95, or any combination of ranges thereof. In some embodiments, the area of a PV cell may be at least 0.2 cm2. In some cases, the area of a PV cell may be less than 200 cm2. In some embodiments, the area of a PV cell may be in a range of 0.2 - 0.5 cm2, 0.5 - 1.0 cm2, 1.0 - 1.5 cm2, 1.5 - 2.0 cm2, 2 - 3 cm2, 3 - 5 cm2, 5 - 7 cm2, 7 - 10 cm2, 10 - 15 cm2, 15 - 20 cm2, 20 - 30 cm2, 30 - 50 cm2, 50 - 100 cm2, 100 - 200 cm2, or any combination of ranges thereof, or even higher than 200 cm2.

[0092] In some cases, dimension d2 is at least as large as the width d9 of a PV cell, but practically does not exceed 2 times d9 (i.e. less than 2*d9) plus the width of first scribe structure 132. In many cases, the width of first scribe structure 132 structure is 20% the width d9 of a PV cell or less, preferably 10% or less. In some embodiments, d2 may be in a range of (1.0- 1.2)*d9, (1.2 - 1 ,4)*d9, (1.4 - 1 ,6)*d9, (1.6 - 1 8)*d9, (1.8 - 1 ,9)*d9, (1.9 - 2.0)*d9, (2.0 - 2.1)*d9, or any combination of ranges thereof.

[0093] In some embodiments, dimension dl is less than dimension d2. In some cases, the dl may be in a range of (0.005 - 0.01)*d2, (0.01 - 0.02)*d2, (0.02 - 0.03)*d2, (0.03 - 0.05)*d2, (0.05 - 0.07)*d2, (0.07 - 0.1 )*d2, (0.1 - 0.2)*d2, (0.2 - 0.3)*d2, (0.3 - 0.5)*d2, or any combination of ranges thereof.

[0094] In some embodiments, dimension d6 may be similar to dimension d4, but may be larger, or in some preferred embodiments, smaller. For example, the ratio of d6 / d4 may be in a range of 0.1 - 0.2, 0.2 - 0.3, 0.3 - 0.5, 0.5 - 0.7, 0.7 - 0.9, 0.9 - 1.1, 1.1 - 1.3, 1.3 - 1.5, 1.5 - 2, 2 - 3, 3 - 4, 4 - 5, or any combination of ranges thereof, for example, 0.3 - 0.7. In some cases, d6 may be zero when patterned substrate conductor element (e.g., bridge conductor 144) is at the very edge of the PV cell.

[0095] In some embodiments, dimension d5 is less than 40% of cell width d9, alternatively, less than 20%. In some cases, the ratio of d5 / d9 is in a range of 0 - 0.01, 0.01 - 0.05, 0.05 - 0.1, 0.1 - 0.2, 0.2 - 0.3, 0.3 - 0.4, or any combination of ranges thereof. In some cases, d5 may be about zero when the end patterned substrate conductor element (e.g., bridge conductor 144) is at the very edge of the PV cell.

[0096] Each PV cell includes at least one top via structure per bridge conductor. In cases where the sheet resistance of the top electrode is relatively high and / or the PV cell width d9 is relatively large, it can be advantageous for a PV cell to include at least 2 top via structures per bridge conductor (e.g., as shown in FIGS. 1 A - 2B). In some embodiments, the number of top via structures per bridge conductor for a PV cell is in a range of 1 - 2, 2 - 3, 3 - 4, 4 - 5, 5 - 10, or any combination of ranges thereof, or even more than 10. The spacing d7 between top via structures depends in part on the length d2 of the bridge conductor, the number of via structures to be connected to the bridge conductor, and the width d9 of the PV cell. In some cases, the spacing d7 is selected so that via structures are relatively evenly distributed along the PV cell width d9 dimension to ensure uniform current collection. Although not labelled, the spacing of the top via structure closest to the width edge of a PV cell (defining cell width d9) may be similar to spacing d7, but in some cases may be less (e.g., less than equal to 0.9*d7, 0.7*d7, or 0.5*d7).

[0097] Each PV cell includes at least one bottom via structure per bridge conductor. In cases where the sheet resistance of the bottom electrode is relatively high and / or the PV cell width d9 is relatively large, it can be advantageous for a PV cell to include at least 2 bottom via structures per bridge conductor (e.g., as shown in FIGS. 1A - 2B). In some embodiments, the number of bottom via structures per bridge conductor for a PV cell is in a range of 1 - 2, 2 - 3, 3 - 4, 4 - 5, 5 - 10, or any combination of ranges thereof, or even more than 10. The spacing d8 between bottom via structures depends in part on the length d2 of the bridge conductor, the number of via structures to be connected to the bridge conductor, and the width d9 of the PV cell. In some cases, the spacing d8 is selected so that via structures are relatively evenly distributed along the PV cell width d9 dimension to ensure uniform current collection. Although not labelled, the spacing of the bottom via structure closest to the width edge of a PV cell (defining cell width d9) may be similar to spacing d8, but in some cases may be less (e.g., less than equal to 0.9*d8, 0.7* d8, or 0.5* d8).

[0098] In some embodiments, each set of patterned conductor elements (e.g., a set of bridge conductors 144) may include at least 2 of such patterned conductor elements, e.g., at least 2 bridge conductors. In some cases, the number of bridge conductors within a set of bridge conductors is in a range of 2 - 3, 3 - 4, 4 - 5, 5 - 7, 7 - 10, 10 - 15, 15 - 20, 20 - 30, 30 - 40, 40 - 50, 50 - 70, 70 - 100, or any combination of ranges thereof, or even more than 100. The distance d4 depends in part on the number of bridge conductors within a set and length dlO of the PV cell. As shown in FIG. ID, adjacent first and second bridge conductor elements 144-1 and 144-2 may be considered a bridge conductor pair. Spacing d3 may in some cases be less than d4. For example, the ratio of d3 / d4 may in some cases be in a range of 0.05 - 0.1, 0.1 - 0.2, 0.2 - 0.3, 0.3 - 0.5, 0.5 - 1, or any combination of ranges thereof. In some embodiments (not shown), the first and second bridge conductors may be spaced (along the x-axis) about halfway in between each other, rather than having d3 be much smaller than d4. In many cases, it can be beneficial to have d3 to be as small as possible to reduce or minimize power losses in the transparent conductor, but not so small as to impact manufacturing yield. Note that there is a practical limit to minimizing the d3 spacing in manufacturing. The bridge conductor pairs must not be shorted to each other since such shorting can cause much or all of the power generated in the cell to be lost. Even if the initial manufacturing yield is good for patterning the bridge conductor pairs themselves (i.e., they are not shorted), if they are very close together, then an error in subsequent processing (e.g., printing or patterning the dielectric layer, a via conductor, an electrode, or the like) may occur that shorts the pair and cause power loss.

[0099] The total number of top via structures per PV cell depends on the number of bridge conductors and top via structures per bridge conductor. Similarly, the number of bottom via structures per PV cell depends on the number of bridge conductors and bottom via structures per bridge conductor. Although FIGS. 1 A and 2A show the same number of top and bottom via structures per PV cell, in some cases, there may be more or fewer bottom via structures per PV cell (per bridge conductor) relative top via structures. It is noted that some embodiments of bottom via structures (e.g., as shown in FIG. 5B) may have less or no dead zone area, thus potentially allowing more bottom vias without an efficiency penalty. The pattern of top vias of a PV cell may be characterized by a relatively even distribution across the PV cell area in order to ensure uniform collection of current. In some embodiments, an even distribution of top vias across a PV cell area may correspond to when d7 is similar to d4, for example, when a ratio of d7 / d4 is be in a range 0.25 - 0.35, 0.35 - 0.45, 0.45 - 0.55, 0.55 - 0.65, 0.65 - 0.75, or any combination of ranges thereof. Similarly, the pattern of bottom vias of a PV cell may be characterized by a relatively even distribution across the PV cell in order to ensure uniform collection of current. In some embodiments, an even distribution of bottom vias across a PV cell area may correspond to when d8 is similar to d4, for example, when a ratio of d8 / d4 is be in a range 0.25 - 0.35, 0.35 - 0.45, 0.45 - 0.55, 0.55 - 0.65, 0.65 - 0.75, or any combination of ranges thereof.

[0100] A few non-limiting example embodiments that address some of above dimensional and other considerations are discussed elsewhere.

[0101] Although the shapes of the bridge conductors have been shown as approximately rectangular, there is no particular limitation on the shape. FIG. 7A is a top view of another nonlimiting example of patterned substrate conductor elements (bridge conductors) 744 provided on substrate 101. This view is similar to that of FIG. ID except that now the bridge conductors 744 each have pad portions 745 and narrower connection portions 756 connecting the pad portions together. The pad portions 745 may correspond to the intended top or bottom via location. The pad portions may be square, rectangular, circular, oval, pentagonal, hexagonal, or some other shape. Corners (if any) of the pad portions may optionally be rounded. The pad portions and connection portions may in some cases be made from the same material and in a common step (e.g., printing, evaporation through a shadow mask, photolithography, etc.). Alternatively, the pad portions and connection portions may be provided in separate steps and / or may include different conductive materials. Although not illustrated, the height of the bridge conductor may vary across its length or width such that thicker areas may have lower resistance than thinner areas. For example, referring again to FIG. 7A, the connector portions 746 may be thicker than the pad portions 745 or vice versa.

[0102] In some cases, the shape of the bridge conductors can be selected to increase bifacial performance, reduce power loss (e.g., reduce resistance), reduce cost of conductive ink if printed, or the like. FIG. 7B is a top view of another non-limiting example of patterned substrate conductor elements (bridge conductors) 744b where a middle area is wider than near the bridge conductor ends. In some cases, lower resistance in the bridge conductor may be beneficial in the area between the two PV cells. Although not illustrated, the height of the bridge conductor may vary across its length or width, where thicker areas can carrier higher currents (have lower resistance) than thinner areas.

[0103] Many of the embodiments discussed herein may be used for bifacial PV modules. When the PV module is intended just for monofacial use with light coming through the top electrode, the patterned substrate conductors (e.g., bridge conductors) may optionally occupy significantly more of the substrate surface. FIG. 8A is a top view of a non-limiting example of closely packed patterned substrate conductor elements (bridge conductors) 844 having large area portions 844bv for bottom vias and narrow area portions 844tv for top vias and provided over substrate 101. In the present embodiment, bridge conductor 844 may be characterized as having a paddle shape. FIG. 8B is a top view after application of patterned dielectric 871 to form substrate structure 870b. For clarity, the outlines of underlying bridge conductors are shown with dashed lines. In some embodiments, it may be useful to ensure that all edge areas of the bridge conductors are covered with dielectric layer 871b as shown. However, in some other embodiments as shown in FIG. 8C, the patterned dielectric layer 871c may be provided only over the narrow area portions. Although not illustrated, the subsequent PV module (optionally monofacial when the bridge conductor elements are opaque) may advantageously have a bottom via structure that utilizes the bottom electrode as the bottom via conductor (e.g., as discussed with respect to FIGS. 5 A - 5D) and a top via structure that utilizes the top electrode as the top via conductor (e.g., as discussed with respect to FIGS. 6A - 6M). Alternatively, one or both of the bottom and top via structures may use a separate via conductor material, e.g., as described with respect to FIGS. IB, 3 A - 3C, and 4A - 4E.

[0104] Note that in some alternative embodiments using similar bridge conductor elements as in FIG. 8A, the portions used for top and bottom vias may be reversed. FIG. 10A is a top view of a non-limiting example of closely packed patterned substrate conductor elements (bridge conductors) 1044 having large area portions 1044tv for top vias and narrow area portions 1044bv for bottom vias provided on substrate 101. FIG. 1 OB is a top view after application of a patterned dielectric 1071 to form substrate structure 1070b. In a non-limiting example, FIG. 10C is a top view of a portion of a PV module 1000 made from substrate structure 1070b including top via structures 1051 and bottom via structures 1056. In this non-limiting example, there are 4 top via structures and 1 bottom via structure per bridge conductor, but there is no particular limitation. In some cases, the top electrode may have higher resistance than the bottom electrode. As such, to carry current in series it can be useful for there to be a plurality of top via structures per bridge conductor so that current can easily flow to the conductive bridge conductor which generally has higher conductivity (lower resistivity) than the top electrode. That is, a higher number of vias can reduce the path length for current in the top electrode to reach the bridge conductor.

[0105] Some additional non-limiting examples where the bridge conductors occupy a significant area are shown in FIGS. 11A - 1 IB and 12A - 12B. For simplicity, the layout of the patterned substrate conductor elements (bridge conductors) is shown (FIG. 11 A, 12A) and then a portion of the final PV module with just the top and bottom via structures labeled (FIGS. 1 IB, 12B).

[0106] FIG. 11 A is a top view of a non-limiting example of closely packed patterned substrate conductor elements (bridge conductors) 1144 having an approximately rectangular shape provided on a substrate 101. FIG. 1 IB is a top view of a portion of a PV module 1100 made from the structure of FIG. 11 A, and includes top via structures 1151 and bottom via structures 1156. In this non-limiting example, there are 2 top via structures and 1 bottom via structure per bridge conductor, but there is no particular limitation. FIG. 12A is a top view of a non-limiting example of closely packed patterned substrate conductor elements (bridge conductors) 1244 having a diamond shape provided on a substrate 101. FIG. 12B is a top view of a portion of a PV module 1200 made from the structure of FIG. 12A and includes top via structures 1251 and bottom via structures 1256. In this non-limiting example, there are 3 top via structures and 3 bottom via structures per bridge conductor, but there is no particular limitation. Methods for making the patterned substrate conductor elements are discussed elsewhere and, for example, may include printing, vapor deposition through a mask, etching of a conductive layer such as a metal layer. In some cases, laser ablation may be used to form the bridge conductors. Laser ablation (laser scribing) is particularly amenable to the diamond pattern of FIG. 12A. The diamond shapes can be formed by crisscrossing a laser beam in long lines across the substrate, e.g., having the desired blanket metal layer. Compared to, for example, the pattern of FIG. 11A, the overall length of the laser scribe and the time it takes to make the pattern can be significantly reduced. In some cases, the tapered shape of the diamond bridge conductor may help alleviate what is known as “current crowding”. The diamond shape can be characterized by respective corner-to-corner widths, 1244x in the X-direction (width of the bridge conductor), and 1244y in the Y-direction (length of the bridge conductor). The length-to-width aspect ratio can be easily controlled by selection of the laser ablation path and used to tailor the properties of the PV module. The number of via structures required for good performance may be based in part on this aspect ratio and the number of bridge conductors per PV cell pair. In some cases, the diamond bridge conductor aspect ratio is at least 1.5: 1 , alternatively at least 2:1 , or alternatively at least 2.5: 1. Higher aspect ratios may in some cases require fewer via structures and / or reduce the current path for the top electrode to a top via.

[0107] FIG. 13 is a non-limiting example of a flow diagram of steps that may be used making a photovoltaic module. The details and structures are mostly discussed elsewhere herein and this flow chart is intended to provide a general summary.

[0108] In Step 1401, a patterned substrate conductor is formed over a (optionally flexible) substrate. The patterned substrate conductor may include a plurality of bridge conductors. In some preferred embodiments, the patterned substrate conductor is made from aluminum or copper.

[0109] In Step 1402, a patterned dielectric layer is formed over the patterned substrate conductor and substrate. The patterned dielectric layer preferably has a tapered bottom via openings corresponding to bottom via contact areas (e.g., as shown in FIG. 5A). Tn some cases, the patterned dielectric layer may be applied by printing.

[0110] In Step 1403, a bottom electrode layer is deposited over the patterned dielectric layer and into the tapered bottom via openings to make electrical contact with the underlying patterned substrate conductor. The bottom electrode may act as the bottom via conductor. In some cases, the bottom electrode layer may be a transparent or transmissive electrode. In some other cases, it may be substantially opaque, e.g., a bilayer of copper and a transparent conductive oxide.

[0111] In Step 1404, a plurality of first top via scribes is formed. Each first top via scribe may be formed by removing a portion of the bottom electrode layer along with a portion of the dielectric layer underneath the portion of the bottom electrode layer (e.g., as shown in FIG. 6L).

[0112] In Step 1405, a photoactive layer is deposited over the structure from FIG. 1404 (e.g., as shown in FIG. 6M). The photoactive layer includes at least an absorber layer (e.g., a perovskite material, an organic photovoltaic material, a CIGS material, or a cadmium telluride material), but the photoactive layer may have a multilayer structure (e.g., as shown in FIG. 9). In some cases, Step

[0113] 1405 may with application of an interfacial layer to cover exposed edges of the bottom electrode. For example, if the bottom electrode includes copper, the interfacial layer may act as a barrier to diffusion of metal into the other photoactive layers. In some cases, the interfacial layer may be metal oxide deposited by atomic layer deposition.

[0114] In Step 1406, a plurality of second top via scribes is formed in alignment with the first top via scribes. Each second top via scribe produces tapered top via openings extending to the underlying patterned substrate conductor corresponding to top via contact areas (e.g., as shown in FIG. 6G).

[0115] In Step 1407, a transparent top electrode layer is deposited over the structure from step

[0116] 1406 and into the top via openings to make electrical contact with the underlying patterned substrate conductor. The transparent top electrode layer may act as the top via conductor.

[0117] In Step 1408, first and second scribe structures are formed (e.g., as shown in FIG. 2A) to produce two or more sets of PV cells, each set including two or more PV cells. The adjacent cells in a set of PV cells are connected in series by a set of two or more bridge conductors.

[0118] Laser ablation

[0119] Laser ablation (also referred to herein as laser etching) can be carried out using various laser etch tools. The dimensions and depths of a via or scribe can be controlled by the properties of the laser. Some of the controllable properties of laser radiation may include wavelength, beam width, beam shape, beam focus, power, pulse profde / width, position, movement, and the like.

[0120] Any or all of the laser etching steps may optionally be performed under an inert atmosphere and / or in combination with an evacuation stream to carry away any potential debris. The laser radiation may be in the form of a spot or line that moves across the substrate. For example, the laser source may be on a moveable arm or the beam may be coupled to redirection optics (mirrors, lenses or the like) to reposition the laser radiation impingement. Depending on the power and other properties of the laser source, laser radiation may be applied to multiple areas concurrently.

[0121] The lasers may in part be housed in one or more processing stations. In some cases, the first and second scribe structures and / or via holes may be formed in a common processing station. In other cases, there may be multiple laser processing stations. Such processing station(s) may further include sensors to ensure quality control, alignment, and proper production of the scribe structure.

[0122] Laser scribes and via holes may in some cases be formed by directing a laser beam through a series of optics to achieve the desired focused spot size, thus creating the desired scribe / via width and depth. For example, the raw beam out of the laser may be passed through a collimating beam expander that may be set to a predetermined magnification in order to select the input beam size incident on the focusing optic. Selecting a smaller input beam size can result in a wider focused spot, and thus a wider scribe. The focusing optic (such as a plano-convex lens) may also be selected to have a specific focal length in order to achieve a target focused spot width. The focal window for these scribe processes is related to the Rayleigh length, which also improves with increasing focused spot size, resulting in a more robust and manufacturable process.

[0123] A scribe structure (first or second) may be composed of one or more scribes of various widths; however, there are multiple considerations to make when choosing a particular structure. Via holes have similar options and considerations and may include multiple etch steps. Laser etch dimensions and other properties may be driven by the printer accuracy, repeatability, and wetting characteristics of the layers and printer inks to be applied after etching. A wider scribe or via width may result in a wider process window, but this may result in a larger inactive area (dead zone), so these factors should be considered in balance. Manufacturability may also be considered when selecting scribe or via width. A larger scribe or via width likely requires higher laser energy or power for a given source, and this could be limited by laser cost and the number of split beam paths used in a manufacturing tool. Laser sources may include, but are not limited to, all permutations of nanosecond, picosecond and femtosecond pulse widths, with wavelengths in the UV, visible, NIR or IR ranges. For example, a pulsed green laser source (e.g., with a wavelength of 532 nm) may be used to selectively ablate the layers above a bottom transparent electrode without damaging the transparent bottom electrode, as it is absorbed strongly by the absorber layers, but not the transparent bottom electrode. The required pulse energy and pulse-to-pulse overlap will vary depending on the pulse width, pulse shape, beam incidence, spot size and shape, as well as the composition and thickness of the various layers of the PV cells.

[0124] In some cases when removal of the bottom electrode is desired, an IR source (e.g., at a wavelength of 1064 nm) may be used as it may be absorbed significantly by a bottom transparent conducting layer. The required pulse energy and pulse-to-pulse overlap will vary depending on the pulse width, pulse shape, spot size and shape, and also the composition and thickness of the various layers, as well as the substrate itself.

[0125] Given the right parameters (pulse width, pulse energy, pulse overlap, spot size, etc.) any of these lasers may be a suitable source to form any portion or the whole of a scribe or via structure. Perovskite PV structure

[0126] Although various PV technologies may be used, in some embodiments, the PV stack may be based on a perovskite absorber layer. FIG. 9 is a cross-sectional view of a non-limiting example of a perovskite PV structure according to some embodiments. The PV structure may represent a PV cell or a module precursor structure. The photovoltaic structure 900 may include a substrate structure 170, which may include an optionally transparent, substrate and which may in some cases be flexible. For clarity, the patterned substrate conductor, substrate and dielectric layers are not individually illustrated. A bottom electrode 105 may be provided over the substrate structure. In some cases (not shown), the bottom electrode may be a composite conductor including a bottom set of conductive metal lines and a bottom transparent conducting layer provided in contact with the bottom set of metal lines, as previously mentioned. The bottom electrode may be opaque, light transmissive, or transparent.

[0127] A first (or lower) carrier transport layer 163 may be provided overlaying the bottom electrode. A perovskite absorbing layer 164 (sometimes referred to herein simply as a perovskite layer) may be provided overlaying the first carrier transport layer. A second (or upper) carrier transport layer 165 may be provided overlaying the perovskite absorbing layer. A transparent top electrode 107 may be provided overlaying the second carrier transport layer. In some embodiments (not shown), the top electrode may be top composite conductor including a top electrode conducting layer and a top set of conductive metal lines provided in contact with the top electrode conducting layer.

[0128] In some embodiments, the photovoltaic structure may optionally include a transparent adhesion layer 167 provided over the top electrode 107. Adhesion layer 167 may in some cases have planarizing properties, act as an encapsulation layer, or both. In some embodiments, 167 may be referred to as an encapsulation layer that in part functions to reduce the ingress of water or other materials to improve device lifetime. In some cases, the photovoltaic structure may optionally include a transparent superstrate 168 provided over adhesion layer 167. In some embodiments, the transparent superstrate may be flexible. In some cases, the adhesion layer 167 may be first applied over the top electrode and the transparent superstrate may be adherently applied over the adhesion layer. In some embodiments, the adhesion layer 167 is pre-applied to the superstrate 168 and that assembly may be laminated over the top electrode. The adhesion layer in combination with the superstrate may also fill and scribe and via structures thereby protecting exposed areas of the PV stack.

[0129] The layers between the top and bottom electrodes may sometimes be referred to herein as photovoltaic “active layers” or photoactive layer 106. Further, the bottom electrode 105, photoactive layer 106, and top electrode 107 may sometimes be collectively referred to herein as a PV stack. Although not illustrated in FIG. 9, in some embodiments, one or more interfacial layers may optionally be provided between any adjacent active layers, between an active layer and an electrode, over the top electrode or under the bottom electrode. Herein the term “interfacial layer” is used broadly, with the purpose, e.g., of altering one or more properties of the interface between two layers such as changing the work function, increasing the barrier properties to mobile ions, passivating defects in a neighboring layer, or altering the band gap. In some cases, an interfacial layer may more specifically act as a barrier to diffusion of water, solvents, molecules, ions (e.g., metal ions and / or halide ions). In some embodiments an interfacial layer may passivate, deactivate or otherwise ameliorate unwanted trap states or carrier transport barriers at layer interfaces or even grain boundaries. In some embodiments, an interfacial layer may aid in the deposition of a subsequent layer, e.g., by providing uniform chemical and / or physical properties across a surface such as surface tension, adhesion, reactive groups for bonding, or the like. An interfacial layer may in some embodiments include a generally electrically insulating metal oxide (e g., aluminum oxide, titanium dioxide, or the like) that is sufficiently thin so as not to seriously impede the transport of charge between layers. In some embodiments, an interfacial layer may be less than 6 nm thick, alternatively less than 2 nm thick. In some cases, an interfacial layer may be a few monolayers thick, alternatively a single monolayer thick. In some cases, an interfacial layer may be a continuous layer or film, but in other cases may be discontinuous. In some embodiments, an interfacial layer may be applied by an inline tool compatible with roll-to-roll manufacturing. In some cases, an interfacial layer may be applied by spatial ALD (SALD), a reduced pressure metal oxide deposition tool, or coating (or other contact) with a solution, liquid, gas, or aerosol that includes an interfacial material. Additionally, anywhere the phrase “interfacial layer” or similar concepts appear herein, they may be replaced by “interfacial treatment”. In some cases, an interfacial treatment may not result in deposition of an interfacial layer but may instead treat a layer at its surface or even internally to provide the desired treatment result.

[0130] Photovoltaic structure 900 may in some cases be a bifacial photovoltaic structure capable of receiving light 180 from its upper (or front) surface and light 182 from its lower (or back) surface. In some embodiments, light 180 may be primary light that is more intense than albedo light 182. For example, light 180 may include sunlight and light 182 may include reflected sunlight or some other ambient light source. Alternatively, the photovoltaic structure may be monofacial where it is designed to only receive light 180.

[0131] In operation, positive and negative charges (holes and electrons) are produced in the perovskite absorbing layer 164 in response to absorption of appropriate radiation. The first (lower) and second (upper) carrier transport layers (163, 165) receive these separated charges and transfer them to the respective bottom and top electrodes (105, 107). The bottom and top electrodes may be in electrical contact with an electrical device (not shown in FIG. 9) where the collected charges serve to power the device, or alternatively charge it in the case where the electrical device is an energy storage battery of some sort.

[0132] In some embodiments, the first carrier transport layer may include a hole transporting material and the bottom electrode may act as an anode in the photovoltaic structure. In such embodiments, the second carrier transport layer may include an electron transporting material and the top electrode may act as a cathode in the photovoltaic structure. Such an arrangement of layers may for convenience be referred to as a PIN structure. In some alternative embodiments, the first carrier transport layer may include an electron transporting material and the bottom electrode may act as cathode in the photovoltaic structure. In such embodiments, the second carrier transport layer may include a hole transporting material and the top electrode may act as an anode in the photovoltaic structure. Such an arrangement of layers may for convenience be referred to as a NIP structure.

[0133] In some embodiments, the materials and methods used for forming one or more layers of the photovoltaic structure are compatible with high-speed manufacturing. In some cases, one or more layers may be formed using roll-to-roll processes. In some embodiments, one or more manufacturing steps may instead use batch deposition methods or a series of substrates in a “cut sheet” format, e.g., with each mounted in a frame.

[0134] Substrate

[0135] The substrate is generally electrically insulating and may be formed from any suitable material(s). For use with transparent bottom electrodes or bifacial designs, the substrate may be formed from any suitable transparent material(s), such as a glass, a polymer (plastic), or a combination of different materials. For monofacial designs receiving light through the top electrode, the substrate may optionally be opaque instead of transparent or transmissive. The substrate may in some cases be rigid, but in preferred embodiments, the substrate is flexible. Some non-limiting examples of transparent substrates may include thin flexible glass such as Corning® Willow® Glass, a polyethylene terephthalate (PET) (which may optionally be a heat-stabilized PET), a polyethylene naphthalate (PEN), a polycarbonate (PC), a polysulfone (PS), a polyether sulfone (PES), a polyamide, p-nitrophenylbutyrate (PNB), a polyetherketone (PEEK), a polyetherimide (PEI), a polyarylate (PAR), a polyvinyl acetate, a polyimide, a cyclic olefin polymer (COP), a cellulose triacetate (TAC), a polyacrylate, or an epoxide. For some applications, some particularly useful transparent substrates include thin flexible glass, PET and heat-stabilized PET. The substrate may optionally include multiple materials or have a multilayer structure. The substrate may include a surface treatment to modify the surface energy for improved coating quality and / or adhesion of subsequent layers. Some non-limiting examples of surface treatments include corona discharge, ozone (created, for example, with ultraviolet radiation), and plasma. Surface treatment devices may operate in ambient air, conditioned air (where temperature and relative humidity are controlled), oxygen, or inert gas such as nitrogen or argon. In some embodiments, a surface-modifying treatment may involve a wet chemical treatment or even an additional surface layer deposited by a wet- or dry-coating method. In some cases, a surface layer may be referred to as a primer layer. In some cases, the substrate may act as a water vapor or oxygen barrier, e.g., through choice of substrate material or by addition of one or more barrier layers.

[0136] Note that by “flexible” it is generally meant that the material can undergo some shape changes at least in one dimension in response to some force or stress without significant damage. In some cases, flexibility of a substrate or material may be measured by its bend radius, which is the minimum radius that it can be bent without functionally damaging it. In some embodiments, a flexible support may have a bend radius of less than 100 cm, alternatively less than 50 cm, 20 cm, 10 cm, 5 cm, 4 cm, 3 cm, 2 cm, or 1 cm. In some preferred embodiments, a flexible substrate may have a bend radius of less than 10 cm.

[0137] There are no particular limitations on the thickness of the substrate if flexibility is not desired, so long as it remains sufficiently transparent when required. In some preferred embodiments, a flexible substrate is suitable for roll-to-roll manufacturing and may have a thickness of less than about 350 pm if it is flexible glass (e.g., a thickness in a range of 50 to 350 pm), or alternatively less than about 250 pm if it is a flexible plastic (e.g., a thickness in a range of 20 to 250 pm).

[0138] First and Second Carrier Transport Layers

[0139] As mentioned, one carrier transport layer includes a hole transporting material, and the other carrier transport layer includes an electron transporting material. A carrier transport material that includes a hole transporting material may be referred to as a hole transport layer. In addition to transporting holes, a hole transporting material may also effectively block the transport of electrons. A carrier transport material that includes an electron transporting material may be referred to as an electron transport layer. In addition to transporting electrons, an electron transporting material may also effectively block the transport of holes. In some embodiments, a carrier transport layer may include multiple layers of materials. A non-limiting example of a multilayer charge transport layer may include embodiments where one sublayer is especially for transporting the desired charge and another sublayer especially for blocking the opposite charge. In some cases, a blocking sublayer may be adjacent to the perovskite blocking layer. The thickness of a carrier transport layer depends in part on the properties of the overall photovoltaic stack, but in some embodiments, may have an average thickness in a range of 10’s to 100’s of nanometers. Some non-limiting examples of hole-transporting materials may include a poly(triaryl amine) (e.g., poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine]), a poly-(N-vinyl carbazole), PEDOT complex, a poly(3-hexylthiophene), spiro-MeOTAD (also known as N2,N2,N2\N2\N7,N7,N7,NT-octakis(4-methoxyphenyl)-9,9'-spirobi[9H-fluorene]-2,2',7,7'- tetramine), poly-TPD, EH44, certain metal oxides (e.g. nickel oxide, molybdenum oxide, and vanadium oxide, any of which may optionally be doped), copper thiocyanate and copper iodide, and certain self-assembled monolayers (e.g. 2-(9H-Carbazol-9-yl)ethyl]phosphonic acid).

[0140] Some non-limiting examples of electron-transporting materials may include fullerenes, (e.g., phenyl-C61 -butyric acid methyl ester (PCBM) and fullerene-C60), bathocuproine (BCP), TPBI, PFN, PC71BM, ICBA, graphene, reduced graphene oxide, certain metal oxides (e.g., tin oxide, zinc oxide, cerium oxide, and TiCh, any of which may optionally be doped).

[0141] Depending in part upon the particular material, a carrier transport layer may in some cases be deposited by a dry deposition process. Some non-limiting examples of dry processes may include sputtering, thermal evaporation, physical vapor deposition, chemical vapor deposition, atomic layer deposition, e-beam deposition, or some other process that may in some cases operate under reduced pressure. In some cases, dry deposition may be performed inline in a roll-to-roll system, e.g., by using spatial ALD (SALD) or a reduced pressure material deposition (RPMD) tool. Such RPMD tools operate at pressures above normal vacuum deposition systems, e.g., in a range of 0.01 mBar to 200 mBar. In some embodiments, a carrier transport layer may be deposited from an aerosol of nanoparticles. Some non-limiting examples of aerosol-based deposition are described in US 10092926, which is incorporated by reference herein in its entirety for all purposes. In some cases, aerosol deposition has been found to be less damaging to underlying device layers.

[0142] In some embodiments, a carrier transport layer may be deposited by a coating process that does not require reduced pressure. Some non-limiting examples of coating processes may include gravure, slot die, spray, dip coat, inkjet, flexographic, rod, or blade coating methods. In some cases, a coating process may be followed by a thermal treatment to drive off solvent, anneal the carrier transport material, or the like.

[0143] In some embodiments, a carrier transport layer may be deposited by transfer of the carrier transport material from a donor sheet, e.g., by application of heat or some other stimulus to release it from the donor sheet with adherent transfer to the appropriate device layer or substrate. In some cases, the deposition method is suitable for high-speed manufacturing. In some embodiments, the deposition of one or more carrier transport layers may be performed using a roll- to-roll manufacturing process.

[0144] Perovskite absorbing Layer

[0145] Although not limiting, in some cases, perovskite materials and methods for forming perovskite absorbing layers may be as described in U.S. Patent No. 11,108,007, U.S. Patent No. 11,342,130, U.S. Application No. 2020 / 0377532, and U.S. Application Publication No. 2022 / 0238807, the entire contents of which are incorporated herein by reference. In some embodiments, a perovskite absorbing layer may be coated from a fluid mixture, which may be referred to as a perovskite solution. Any coating method suitable for coating a fluid mixture may be used including, but not limited to, gravure, slot die, spray, dip coat, inkjet, flexographic, rod, or blade coating methods. In some cases, the perovskite deposition method is suitable for high-speed manufacturing. In some embodiments, a perovskite absorbing layer may be performed using a roll- to-roll manufacturing process.

[0146] The term “perovskite solution” refers to a solution or colloidal suspension that can be used to generate a continuous layer of organic-inorganic hybrid perovskite material (the perovskite layer), e.g., one with an ABX3 crystal lattice where ‘A’ and ‘B’ are two cations of very different sizes, and X is an anion that coordinates to both cations. A perovskite solution typically includes an appropriate set of perovskite precursor materials and one or more solvents in which the precursor material is dissolved or suspended. A perovskite solution may also contain additives, e.g., to aid in crystal growth or to modify crystal properties or for some other purpose. A perovskite precursor material is typically an ionic species where at least one of its constituents becomes incorporated into the final perovskite layer ABX3 crystal lattice. Organic perovskite precursor materials are materials whose cation contains carbon atoms while inorganic perovskite precursor materials are materials whose cation contains metal but does not contain carbon.

[0147] When the perovskite solution dries, perovskite crystals or an intermediate precursor phase for hybrid perovskite crystals (intermediate phase) form. The intermediate phase is a crystal, adduct, or mesophase that is not the desired final crystal lattice, which is ABX3. The intermediate phase, if present, may be converted to the desired final crystal lattice by annealing. In some cases, annealing or other heating methods may include the use of heated nip rollers, optionally under nitrogen. Some non-limiting examples of inorganic perovskite precursor materials for making perovskite solutions may include lead (II) iodide, lead (II) acetate, lead (II) acetate trihydrate, lead (II) chloride, lead (II) bromide, lead nitrate, lead thiocyanate, tin (II) iodide, rubidium halide, potassium halide, and cesium halide. In some cases, the halide may include iodide. Some nonlimiting examples of organic perovskite precursor materials for making perovskite solutions may include methylammonium iodide, methylammonium bromide, methylammonium chloride, methylammonium acetate, formamidinium bromide, and formamidinium iodide. To produce a high-performance perovskite device, it is generally preferred in some cases that the organic perovskite precursor material has a purity greater than 99 percent by weight and the inorganic perovskite precursor has a purity greater than 99.9 percent by weight. The inorganic perovskite precursor material contains a metal cation, and in some preferred embodiments, the metal cation is lead. In some preferred embodiment, the molar ratio of organic perovskite precursor material to inorganic perovskite precursor material may be in a range of one to three.

[0148] Electrodes

[0149] In some embodiments, at least the top electrode is transparent. In some cases both the top and bottom electrodes are transparent (or one is transparent and the other is partially transparent (transmissive)) and the PV module may be a bifacial device. An electrode may be a single layer of electrically conductive material or have a multilayer structure. If transparency is not required, then the electrode may optionally include a non-transparent metal layer. A non-transparent metal layer for the bottom electrode may include, for example, silver, copper, gold, aluminum, molybdenum, tungsten, zinc, nickel, iron, tin, palladium, platinum, titanium, or alloys containing one or more of these metals. Non-transparent electrodes may be deposited from solution (e.g., coating, printing, electrodeposition), or alternatively, deposited using a physical vapor deposition method (e.g., sputtering or evaporation), or even a chemical vapor deposition method. In some cases, a solution deposition method may be preferred for high-speed manufacturing.

[0150] If transparency is desired for the electrode, there are several options. In some cases, a single layer or a multilayer of substantially transparent conductive material may be applied. In some cases, a transparent composite conductor may be used. A transparent composite conductor includes a transparent conducting layer and a pattern of metal (typically opaque, non-transparent) lines. The pattern of metal lines may be provided over the transparent conducting layer, or the transparent conducting layer may instead be provided over the pattern of metal lines. Transparent Conducting layers

[0151] In some embodiments, the transparent electrode may include one or more transparent conducting layers. In some cases, the transparent electrode or conducting layer may include a conductive polymer material such as PEDOT:PSS, a poly(pyrrole), a polyaniline, a polyphenylene, or a poly(acetylene). Conductive polymers may be applied by a coating from a suspension or solution, e.g., using any of the coating methods described above with respect to the perovskite absorbing layer. After coating, the conducting layer may optionally be subjected to heating or some other drying step to drive off solvent or otherwise improve conductivity properties of the conductive polymer.

[0152] In some embodiments, a transparent conducting layer may include high aspect ratio metal nanowires (e.g., silver nanowires) or carbon nanotubes. Such materials may be coated from a dispersion (optionally with a binder) at a density sufficient to form an interconnected, conductive mesh, but low enough to achieve a desired transparency. After coating, the conducting layer may optionally be subjected to heating or some other drying step to drive off solvent or otherwise improve conductivity properties of the metal nanowires or carbon nanotubes.

[0153] In some preferred embodiments, a transparent conducting layer or transparent electrode may include one or more conductive metal oxides such as indium tin oxide [ITO], fluorine-doped tin oxide [FTO], indium zinc oxide [IZO], aluminum zinc oxide [AZO] or molybdenum oxide. Such metal oxides are sometimes referred to as transparent conductive oxides (TCOs). A TCO conducting layer may in some cases act as a barrier layer to diffusion of the metal and / or halide ions. TCOs may in some cases be coated from a suspension of metal oxide particles or formed from a sol-gel precursor solution, typically followed by a heating step to drive off solvent and anneal or sinter the metal oxide particles. TCOs may in some cases be deposited using dry deposition methods such as sputtering, physical vapor deposition, chemical vapor deposition, atomic layer deposition, e-beam deposition, or the like. In some preferred embodiments, a TCO may be deposited from an aerosol of nanoparticles (also considered a dry process). Some nonlimiting examples of aerosol-based deposition are described in U.S. Pat. No. 10,092,926, which is incorporated by reference herein in its entirety for all purposes. In some cases, aerosol deposition may be less damaging to underlying device layers. A heating step may optionally follow such dry deposition processes, e.g., to improve conductivity of the deposited layer. In some embodiments, the applied conducting layer, e.g., a TCO layer or conductive polymer, may have an intrinsic sheet resistance (i.e., as measured in the absence of optional metal lines) of less than 1000 £2 / square, preferably less than 300 £2 / square, or more preferably less than 200 £2 / square. In some embodiments, the conducting layer may have an intrinsic sheet resistance in a range of 5 - 15 £2 / square, 15 - 25 £2 / square, 25 - 50 £2 / square, 50 - 75 £2 / square, 75 - 100 £2 / square, 100 - 150 £2 / square, 150 - 200 £2 / square, 200 - 250 £2 / square, 250 - 300 £2 / square, 300

[0154] - 400 £2 / square, 400 - 500 £2 / square, 500 - 1000 £1 / square, or any combination of ranges thereof. While lower resistance is generally favored, in some embodiments, these ranges may provide a practical balance of resistance with optical transparency. In some embodiments, the conducting layer may have a %T within a target wavelength range of at least 80%, alternatively at least 90%, at least 95%, or at least 97% (as measured in the absence of the metal lines). In some embodiments, the second conducting layer may have an absorptance %A within a target wavelength range of less than 20%, alternatively, less than 10%, less than 5%, or less than 3% (as measured in the absence of metal lines).

[0155] In some embodiments, the presence of the top via structures and substrate conductor elements may allow the use of more transparent top electrodes having higher resistivity. For example, the sheet resistance of the top transparent electrode may in some embodiments be 50 - 75 £1 / square, 75 - 100 £2 / square, 100 - 150 £2 / square, 150 - 200 £2 / square, 200 - 250 £1 / square, 250

[0156] - 300 £2 / square, 300 - 400 £2 / square, 400 - 500 £2 / square, 500 - 1000 £2 / square, or any combination of ranges thereof. As mentioned, in some cases the top electrode may have a higher resistivity than the bottom electrode. Even in bifacial systems, the transparency demands on the bottom electrode may be relaxed relative to the top electrode thereby allowing a lower resistance. When the PV module is monofacial, the bottom electrode can include a highly conductive metal layer or more metal lines. In some embodiments, a ratio of sheet resistance (or other relevant resistivity metric) of the top electrode to the bottom electrode may be at least 2: 1, alternatively at least 5: 1, or alternatively at least 10: 1. In some cases, the sheet resistance of the bottom electrode is less than 50 £2 / square, alternatively less than 25 £2 / square, alternatively less than 10 £2 / square, alternatively less than 5 £2 / square.

[0157] The thickness of a conducting layer or transparent electrode depends in part on the electrical and optical properties of the selected material and may also depend on the deposition method. In some embodiments, the conducting layer may have a thickness of less than 500 nm, alternatively less than 200 nm, alternatively less than 100 nm, alternatively less than 50 nm, alternatively less than 20 nm, or alternatively less than 10 nm. In some embodiments, the conducting layer may be an aerosol-applied TCO having an average thickness in a range of 30 nm to 100 nm. When a conducting layer is applied over a set of metal lines, the average thickness may correspond to areas between the metal lines. When applied over metal lines, it is desirable in many cases that the conducting layer also substantially covers the metal lines to help ensure electrical continuity and prevent or reduce migration of metal ions into the active layers.

[0158] Metal lines

[0159] There is no particular limitation on the metal material that may be used for the optional metal lines. In some embodiments, the metal lines may include silver or copper, or alloys containing one or both of these metals. In some cases, other metals may be suitable including, but not limited to, gold, aluminum, molybdenum, tungsten, zinc, nickel, iron, tin, palladium, platinum, titanium, and alloys containing one or more of these metals. In some embodiments, the metal lines may be formed of a metal material having a conductivity of at least 105S / m.

[0160] In some embodiments, metal lines may be deposited using a dry metal deposition process coupled with some patterning process. For example, metal lines may be deposited by thermal evaporation, sputtering, physical vapor deposition, chemical vapor deposition, atomic layer deposition, e-beam deposition, or the like. Patterned metal lines may be formed, for example, by deposition through a shadow mask or by using known photolithographic methods that may involve etching and / or lift-off processes. In some embodiments, a metal layer may be electrochemically or electrolessly deposited and then patterned into metal lines, for example, by photolithography. In some embodiments, metal lines may be deposited by transfer of prepatterned metal lines from a donor sheet to the intended surface, optionally in combination with heat and / or pressure.

[0161] In some embodiments, metal lines may be formed by printing. In some embodiments, printing may involve patterned application of an electroless metallization catalyst (e.g., palladium) followed by contact with an electroless plating solution (e.g., copper or nickel). In some preferred embodiments, metal lines may be printed using a metal -containing fluid mixture or “metal ink” (e.g., a suspension, slurry, paste, or the like). In some cases, printing metal lines may be performed by flexographic printing, inkjet printing, gravure printing, or some other printing technology. The printed metal lines may in some cases be followed by a heat treatment to drive off solvent or cause metal particles to fuse or sinter, which can increase the metal conductivity. Heat treatments may include an oven, IR heaters, flashlamps, heated rollers (with or without pressure), or the like. US Pat. 8,907,258, incorporated herein by reference for all purposes, discloses a non-limiting example of a pulsed radiation apparatus that may be suitable for metal particle sintering in a roll-to-roll manner. In some cases, a printed metal ink may be subjected to a secondary chemical treatment such as a reducing agent. The metal ink may include metal particulates of various shapes and sizes (e.g., spherical, oblong, nanoparticles, nanowires) in an appropriate liquid carrier and may further include other agents such as binders, surfactants, or the like. A few non-limiting examples of metal inks may include those disclosed in US20220025200, which is incorporated herein by reference for all purposes. In some embodiments, a surface receiving the metal ink may first be treated to modify its surface energy, e.g., by corona discharge, a plasma, UV / ozone, or a chemical treatment. Modification of this surface energy can in some cases be used to control the shape, dimension, and / or adhesion of the deposited metal ink.

[0162] It should be appreciated that the inks, materials, and printing methods discussed above with respect to the metal lines may be similar to those used to make an electrically conductive connector such as a via conductor (e.g., in embodiments where the via conductor is not the top or bottom electrodes).

[0163] In some embodiments, a set of metal lines (bottom or top, if used) occupies less than 15% of the active cell surface area, alternatively less than 10%, less than 5%, less than 3%, less than 2%, or less than 1%. In some cases, a set of metal lines (if used) occupies an active cell surface area in a range of 0.5% - 1 %, 1 % - 2 %, 2% - 3%, 3% - 5%, 5% - 7%, 7% - 10%, 10% - 15%, or any combination of ranges thereof. In some embodiments, both electrodes use a set of metal lines, but alternatively, only one electrode uses metal lines, or sometimes neither electrode uses metal lines.

[0164] While not using metal lines may make a transparent electrode less conductive, avoiding metal lines (or using fewer) may offer manufacturing advantages such as higher throughput, higher yield, and lower cost. In particular, applying metal lines to the transparent top electrode can be challenging. It has been found that the present via structures can effectively compensate for the absence (or reduced number) of metal lines with respect to conductivity, and still offer significant manufacturing advantages.

[0165] Example 1 - Monofacial PV Module In a non-limiting example, a monofacial perovskite PV module (where the top electrode is transparent, and the bottom electrode is not) may be manufactured by the following general steps:

[0166] 1) form patterned substrate conductor by vapor deposition of 0.2 um thick aluminum through a shadow mask onto a PET substrate, where the Al has sheet resistance of < 0.06 ohm / sq, and where there are 20 bridge conductors within a set of bridge conductors. 2) pattern deposit (e.g., print) ~ 2 um thick dielectric layer with bottom via holes provided in alignment with the patterned substrate conductor (to form the substrate structure);

[0167] 3) deposit non-transparent bottom electrode by vapor deposition of 0.2 um thick aluminum over the substrate structure where the Al has sheet resistance of < 0.06 ohm / sq (the Al bottom electrode acts as the bottom via conductor);

[0168] 4) form tapered top via opening (e.g., opening 650’ by laser etching as in FIG. 6B);

[0169] 5) optionally deposit ~ 1 nm of aluminum oxide by spatial ALD (this optional step may happen after step 4, before step 4, or even before step 3, or any combination);

[0170] 6) coat the photoactive layer including a first carrier transport layer (CTL1) over the bottom electrode, the perovskite absorber layer (PAL) over CTL1, and a second carrier transport layer (CTL2) over the PAL;

[0171] 7) optionally deposit about 15 nm or optionally 10 nm of a tin oxide by spatial ALD, optionally doped with indium;

[0172] 8) form top via contact areas (e.g., contact area 650 by laser etching as shown in FIG 6D), e.g., 40 per top vias per PV cell, corresponding to an inactive rectangular area of about 0.2mm x 0.4 mm;

[0173] 9) deposit transparent top electrode, e.g., a transparent conductive oxide (TCO) having a sheet resistance of about 100 ohm / sq by sputtering or aerosol deposition (the TCO acts as the top via conductor);

[0174] 10) form first and second scribe structures, each about 40 um wide to form PV cells that are about 5.0 cm long (dlO) and 0.51 cm wide (d9).

[0175] For the Example 1 module, each PV cell includes 40 top via structures (2 per bridge conductor of a first set of 20) and 40 bottom via structures (2 per bridge conductor of another set of 10). The PV module of Example 1 may be characterized as having a 187V design. The total power loss caused by the conductors, scribes and vias (dead zones, resistance, light absorption by top electrode... etc.) is only 3.5%, whereas a comparative monofacial module using conventional Pl- P3 connectors with a composite conductor top electrode have about 10.7% power loss - about 3 times more. Although metal lines may optionally be used for the top electrode (i.e., a composite conductor), the present example does not need them, which saves on manufacturing cost and equipment needs. However, one may potentially reduce the number of vias by using a composite conductor as top electrode, but relative to other systems not using any via connections, the thickness and number of metal lines may be substantially reduced.

[0176] Example 2 - Bifacial PV Module

[0177] In a non-limiting example, a bifacial perovskite PV module (where the top electrode is transparent, and the bottom electrode is transmissive or transparent) may be manufactured by the following general steps:

[0178] 1) form patterned substrate conductor by vapor deposition of 0.5 um thick aluminum through a shadow mask onto a PET substrate, where the Al has sheet resistance of < 0.06 ohm / sq, where there are 20 bridge conductors within a set of bridge conductors, and for each PV cell, the bridge conductors occupy about 20% of the surface area of the substrate.

[0179] 2) pattern deposit (e.g., print) ~ 2 um thick dielectric layer with bottom via holes provided in alignment with the patterned substrate conductor (to form the substrate structure);

[0180] 3) deposit a transparent bottom electrode, e.g., a transparent conductive oxide (TCO) having a sheet resistance of about 100 ohm / sq by sputtering or aerosol deposition (the TCO acts as the bottom via conductor);

[0181] 4) form tapered top via opening (e g., opening 650’ by laser etching as in FIG. 6B);

[0182] 5) optionally deposit ~ 1 nm of aluminum oxide by spatial ALD (this optional step may happen after step 4, before step 4, or even before step 3, or any combination);

[0183] 6) coat the photoactive layer including a first carrier transport layer (CTL1) over the bottom electrode, the perovskite absorber layer (PAL) over CTL1, and a second carrier transport layer (CTL2) over the PAL;

[0184] 7) optionally deposit about 15 nm or optionally 10 nm of a tin oxide by spatial ALD, optionally doped with indium;

[0185] 8) form top via contact areas (e.g., contact area 650 by laser etching as shown in FIG 6D), e.g., 20 per top vias per PV cell, corresponding to an inactive rectangular area of about 0.2mm x 0.4 mm where the long dimension of the scribe aligns with the long dimension of the patterned substrate conductor; 9) deposit transparent top electrode, e.g., a transparent conductive oxide (TCO) having a sheet resistance of about 100 ohm / sq by sputtering or aerosol deposition (the TCO acts as the top via conductor);

[0186] 10) form first and second scribe structures, each about 40 um wide to form PV cells that are about 5.0 cm long (dlO) and 0.51 cm wide (d9).

[0187] For the Example 2 module, each PV cell includes 40 top via structures (2 per bridge conductor of a first set of 20) and 40 bottom via structures (2 per bridge conductor of another set of 10). The PV module of Example 2 may be characterized as having a 187V design. The total “window side” power loss caused by the scribes and vias (dead zones, resistance, light absorption by top electrode... etc.) is only 4% , whereas a comparative bifacial module using conventional PIPS connectors with a composite conductor top electrode has about 11% window side power loss - more than twice. The Example 2 bifaciality factor (a measure of how much energy the rear of the panel will produce compared to the front of the panel under equal illumination) is about 80% whereas the conventional comparative is about 95%. Although the Example 2 module has a lower bifaciality factor, only a relatively small fraction of total power is generated from albedo light, so that the total power loss (window and albedo sides combined) is much less for Example 2 than for the comparative.

[0188] As with Example 1, although metal lines may optionally be used for the top electrode (i.e., a composite conductor), the present example does not need them which saves on manufacturing cost and equipment needs. However, one may potentially reduce the number of vias by using a composite conductor as top electrode, but relative to other systems not using any via connections, the thickness and number of metal lines may be substantially reduced.

[0189] Still further embodiments herein include the following non-limiting enumerated embodiments.

[0190] Enumerated embodiment 1. A photovoltaic (PV) module including: a) a substrate structure including a substrate, a plurality of patterned substrate conductor elements provided over the substrate, and a dielectric layer provided over the substrate and over the patterned substrate conductor elements; b) first and second PV cells provided over the substrate structure, wherein the first and second PV cells are adjacent cells within a set of series-connected PV cells separated by a first scribe structure, and wherein each of the first and second PV cells independently include: i) a bottom electrode overlaying the dielectric layer; ii) a photoactive layer overlaying the bottom electrode, the photoactive layer including at least an absorber layer; and iii) a transparent top electrode overlaying the photoactive layer; c) a first set of top via structures extending through the first PV cell and the dielectric layer to a first set of the patterned substrate conductor elements, wherein each patterned substrate conductor element of the first set of patterned substrate conductor elements respectively is a bridge conductor that extends from a first point underneath the first PV cell to a second point underneath the second PV cell, and wherein the first set of top via structures includes a first top via conductor that electrically connects the first set of patterned substrate conductor elements to the top electrode of the first PV cell; and d) a first set of bottom via structures extending through at least the dielectric layer to the first set of patterned substrate conductor elements at portions corresponding to the second PV cell, wherein the first set of bottom via structures includes a first bottom via conductor that electrically connects the first set of patterned substrate conductor elements to the bottom electrode of the second PV cell, wherein the first set of patterned substrate conductor elements, the first top via conductor, and the first bottom via conductor collectively form the series electrical connection between the first and second PV cells.

[0191] Enumerated embodiment 2. The photovoltaic module of enumerated embodiment 1, wherein the top via conductor includes the same conductive material as the transparent top electrode of the first PV cell.

[0192] Enumerated embodiment 3. The photovoltaic module of enumerated embodiment 1 or 2, wherein the bottom via conductor includes the same conductive material as the bottom electrode of the second PV cell.

[0193] Enumerated embodiment 4. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the top via conductor includes a metal, optionally formed from a pattern-deposited metal ink.

[0194] Enumerated embodiment 5. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the bottom via conductor includes a metal, optionally formed from a pattern-deposited metal ink.

[0195] Enumerated embodiment 6. The photovoltaic module according to any of the preceding enumerated embodiments, wherein top transparent electrode includes a top transparent conductive oxide, optionally selected from ITO, IZO, AZO, or FTO. Enumerated embodiment 7. The photovoltaic module of enumerated embodiment 6, wherein the top transparent electrode is a composite conductor including a top pattern of metal lines provided over the top transparent conductive oxide.

[0196] Enumerated embodiment 8. The photovoltaic module of enumerated embodiment 6, wherein the top transparent electrode is not a composite conductor and is substantially free of metal lines.

[0197] Enumerated embodiment 9. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the top electrode has a sheet resistance in a range of 50 - 1000 ohm / sq.

[0198] Enumerated embodiment 10. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the patterned substrate conductor elements include aluminum.

[0199] Enumerated embodiment 11. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the patterned substrate conductor elements include copper.

[0200] Enumerated embodiment 12. The photovoltaic module according to any of the preceding enumerated embodiments, further including: e) a third PV cell adjacent the second PV cell and part of the set of series-connected PV cells, wherein the third PV cell includes i) a bottom electrode overlaying the dielectric layer, ii) a photoactive layer overlaying the bottom electrode, the photoactive layer including at least an absorber layer, and iii) a transparent top electrode overlaying the photoactive layer; f) a second set of top via structures extending through the second PV cell and the dielectric layer to a second set of the patterned substrate conductor elements, wherein each patterned substrate conductor element of the second set of patterned substrate conductor elements respectively is a bridge conductor that extends from a first point underneath the second PV cell to a second point underneath the third PV cell, and wherein the second set of top via structures includes a second top via conductor that electrically connects the second set of patterned substrate conductor elements to the top electrode of the second PV cell; and g) a second set of bottom via structures extending through at least the dielectric layer to the second set of patterned substrate conductor elements at portions corresponding to the third PV cell, wherein the second set of bottom via structures includes a second bottom via conductor that electrically connects the second set of patterned substrate conductor elements to the bottom electrode of the third PV cell, wherein the second set of patterned substrate conductor elements, the second top via conductor, and the second bottom via conductor collectively form the series electrical connection between the second and third PV cells.

[0201] Enumerated embodiment 13. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the pattern substrate conductor elements further include first and second busbars provided at opposite ends of the module.

[0202] Enumerated embodiment 14. The photovoltaic module of enumerated embodiment 13, wherein a PV cell of the set of series-connected PV cells that is adjacent to the first busbar is electrically connected to the first busbar by a bottom via structure, and wherein a PV cell of the set of series-connected PV cells that is adjacent the second busbar is electrically connected to the second busbar by a top via structure.

[0203] Enumerated embodiment 15. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the bottom electrode is substantially opaque.

[0204] Enumerated embodiment 16. The photovoltaic module according to any of enumerated embodiments 1 - 15, wherein the bottom electrode is transmissive or transparent.

[0205] Enumerated embodiment 17. The photovoltaic module of enumerated embodiment 16, wherein the bottom electrode includes a bottom transparent conductive oxide, optionally selected from ITO, IZO, AZO, or FTO.

[0206] Enumerated embodiment 18. The photovoltaic module of enumerated embodiment 17, wherein the bottom transparent electrode is a composite conductor including a bottom pattern of metal lines provided between the bottom transparent conductive oxide and the substrate structure.

[0207] Enumerated embodiment 19. The photovoltaic module of enumerated embodiment 17, wherein the bottom transparent electrode is not a composite conductor and is substantially free of metal lines.

[0208] Enumerated embodiment 20. The photovoltaic module according to any of the preceding enumerated embodiments, a ratio of top electrode sheet resistance to bottom electrode sheet resistance is at least 2: 1, optionally at least 10: 1.

[0209] Enumerated embodiment 21. The photovoltaic module according to any of the preceding enumerated embodiments, wherein i) the photovoltaic module is a bifacial module and an area of the substrate occupied by the bridge conductors is in a range of 5 - 50%, or ii) the photovoltaic module is a monofacial module and the area of the substrate occupied by the bridge conductors is in a range of 50 - 95%. Enumerated embodiment 22. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the top or bottom via structures include via holes through the dielectric layer that each occupy an area in a range of 0.001 - 0.2 mm2.

[0210] Enumerated embodiment 23. The photovoltaic module according to any of the preceding enumerated embodiments, wherein a contact area between any top via conductor and its corresponding patterned substrate conductor is in a range of 0.001 - 0.2 mm2.

[0211] Enumerated embodiment 24. The photovoltaic module according to any of the preceding enumerated embodiments, wherein a contact area between any bottom via conductor and its corresponding patterned substrate conductor is in a range of 0.001 - 0.2 mm2.

[0212] Enumerated embodiment 25. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the first set of patterned substrate conductor elements includes at least 3 bridge conductors, optionally 4 - 15 bridge conductors.

[0213] Enumerated embodiment 26. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the first PV cell includes at least 4 top via structures, optionally 5 - 60 top via structures.

[0214] Enumerated embodiment 27. The photovoltaic module according to any of the preceding enumerated embodiments, wherein each PV cell includes at least as many bottom via structures as top via structures, optionally more bottom via structures than top via structures.

[0215] Enumerated embodiment 28. The photovoltaic module according to any of enumerated embodiments 1 - 26, wherein the bottom via conductor includes the same conductive material as the bottom electrode of the second PV cell, and wherein each PV cell includes fewer bottom via structures than top via structures.

[0216] Enumerated embodiment 29. The photovoltaic module of enumerated embodiment 28, wherein a contact area between any bottom via conductor with a patterned substrate conductor element is larger than a contact area between any top via conductor with the same patterned conductor element.

[0217] Enumerated embodiment 30. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the first scribe structure has a width in a range of 20 to 60 pm.

[0218] Enumerated embodiment 3 E The photovoltaic module according to any of the preceding enumerated embodiments, wherein each PV cell is characterized by a width Wceii along a width dimension corresponding to the direction of series connections and by a length LCeii along a length dimension orthogonal to the width dimension, and wherein Wceii is less than Lceii, and optionally wherein a ratio of (WCeii / Lceii) is in a range of 0.05 to 0.5.

[0219] Enumerated embodiment 32. The photovoltaic module according to any of the preceding enumerated embodiments, wherein each PV cell has an area in a range of 1 - 5 cm2.

[0220] Enumerated embodiment 33. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the dielectric layer has a thickness of 10 microns thick or less, optionally 2 microns or less.

[0221] Enumerated embodiment 36. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the patterned substrate conductor elements have a thickness of 2 microns or less, optionally 0.2 microns or less.

[0222] Enumerated embodiment 37. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the photoactive layer has a thickness of less than 2 microns, optionally less than 1 micron.

[0223] Enumerated embodiment 38. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the absorber layer includes a perovskite.

[0224] Enumerated embodiment 39. The photovoltaic module according to any of enumerated embodiments 1 - 35, wherein the absorber layer includes an organic photovoltaic material, a CIGS material, or a cadmium telluride material.

[0225] Enumerated embodiment 40. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the dielectric layer absorbs at least 10% of incident radiation at a wavelength of about 1321 nm, 1064 nm, 1030 nm, 532 nm, 515 nm, 488 nm, 355 nm, 343 nm, 266 nm, or 212 nm, optionally wherein the incident radiation is laser radiation.

[0226] Enumerated embodiment 41. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the patterned substrate conductor elements are shaped to have relatively longer and shorter dimensions and the top or bottom via structure is characterized by a via opening length that is substantially aligned with a longer dimension of a patterned substrate conductor element and a via opening width that is substantially orthogonal to the via opening length, wherein the via opening length is larger than the via opening width.

[0227] Enumerated embodiment 42. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the top or bottom via structure has a tapered sidewall characterized by taper angle less than about 70°, optionally less than about 45°. Enumerated embodiment 43. The photovoltaic module according to any of the preceding enumerated embodiments, wherein the substrate is flexible.

[0228] Enumerated embodiment 44. A method of making a photovoltaic (PV) module including a plurality of sets of series-connected PV cells, the method including: a) forming a patterned substrate conductor over a substrate, the patterned substrate conductor including a plurality of bridge conductors; b) fonning a patterned dielectric layer over the patterned substrate conductor and substrate, the patterned dielectric layer including tapered bottom via openings corresponding to bottom via contact areas; c) depositing a bottom electrode layer over the patterned dielectric layer and into the tapered bottom via openings to make electrical contact between the bottom electrode layer and the underlying patterned substrate conductor; d) fonning a plurality of first top via scribes, wherein each first top via scribe is fonned by removing a portion of the bottom electrode layer along with a portion of the dielectric layer underneath the portion of the bottom electrode layer; e) depositing a photoactive layer over the structure from step (d). the photoactive layer including an absorber layer; f) forming a plurality of second top via scribes in alignment with the first top via scribes, wherein each second top via scribe produces tapered top via openings extending to the underlying patterned substrate conductor corresponding to top via contact areas; g) depositing a transparent top electrode layer over the structure from step (f) and into the top via openings to make electrical contact between the transparent top electrode layer and the underlying patterned substrate conductor; and h) fonning one or more first scribe structures and one or more second scribe structures to fonn two or more sets of PV cells, each set including two or more PV cells, wherein adjacent cells in a set of PV cells are connected in series by a set two or more bridge conductors.

[0229] Enumerated embodiment 45. The method of enumerated embodiment 44, wherein step (e) starts with depositing an interfacial layer including a metal oxide over the structure from step (d), optionally by atomic layer deposition.

[0230] Enumerated embodiment 46. The method of enumerated embodiment 44 or 45, wherein the absorber layer includes a perovskite.

[0231] Enumerated embodiment 47. The method of enumerated embodiment 44 or 45, wherein the absorber layer includes an organic photovoltaic material, a CIGS material, or a cadmium telluride material.

[0232] Enumerated embodiment 48. The method according to any of enumerated embodiments 44 - 47, wherein forming the patterned dielectric layer includes coating a first dielectric sublayer and coating a second dielectric sublayer over the first dielectric sublayer.

[0233] Enumerated embodiment 49. The method according to any of enumerated embodiments 44 - 48, wherein forming the first top via scribes and the second top via scribes includes laser ablation. Enumerated embodiment 50. The method according to any of enumerated embodiments 44 - 49, wherein forming the first and second scribe structures includes laser ablation.

[0234] Enumerated embodiment 51. The method according to any of enumerated embodiments 44 - 50, wherein the substrate is flexible.

[0235] Enumerated embodiment 52. The method according to any of enumerated embodiments 44 - 51 , wherein the substrate moves at a speed of at least 5 meter per minute during the deposition of the bottom electrode layer, the deposition of the photoactive layer, and the deposition of the top electrode layer, optionally wherein the substrate structure is a flexible substrate structure provided as a web of a roll-to-roll manufacturing process.

[0236] Although the present disclosure has been made with emphasis on perovskite photovoltaic structures, various embodiments of PV modules and methods of manufacture described herein may be compatible with some other flexible PV systems. For example, the photoactive layer may instead include an organic PV material absorbing layer, a CIGS (copper-indium-gallium-selenide) material absorbing layer, or a cadmium telluride material absorbing layer, optionally along with appropriate charge injecting layers and other materials suitable for these other systems.

[0237] The specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of embodiments of the invention. However, other embodiments of the invention may be directed to specific embodiments relating to each individual aspect, or specific combinations of these individual aspects.

[0238] The above description of example embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form described, and many modifications and variations are possible in light of the teaching above.

[0239] In the preceding description, for the purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. It will be apparent to one skilled in the art, however, that certain embodiments may be practiced without some of these details, or with additional details.

[0240] Having described several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the invention. Additionally, a number of well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present invention.

[0241] Additionally, details of any specific embodiment may not always be present in variations of that embodiment or may be added to other embodiments. It should be noted that, unless otherwise explicitly noted or required by context, the word “or” is used in this disclosure in a non-exclusive sense.

[0242] Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither, or both limits are included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0243] As used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a method” includes a plurality of such methods and reference to “the device” includes reference to one or more devices and equivalents thereof known to those skilled in the art, and so forth. The invention has now been described in detail for the purposes of clarity and understanding. However, it will be appreciated that certain changes and modifications may be practice within the scope of the appended claims.

[0244] All publications, patents, and patent applications cited herein are hereby incorporated by reference in their entirety for all purposes. None is admitted to be prior art.

Claims

We claim:

1. A photovoltaic (PV) module comprising: a) a substrate structure comprising a substrate, a plurality of patterned substrate conductor elements provided over the substrate, and a dielectric layer provided over the substrate and over the patterned substrate conductor elements; b) first and second PV cells provided over the substrate structure, wherein the first and second PV cells are adjacent cells within a set of series-connected PV cells separated by a first scribe structure, and wherein each of the first and second PV cells independently comprise: i) a bottom electrode overlaying the dielectric layer; ii) a photoactive layer overlaying the bottom electrode, the photoactive layer comprising at least an absorber layer; and iii) a transparent top electrode overlaying the photoactive layer, c) a first set of top via structures extending through the first PV cell and the dielectric layer to a first set of the patterned substrate conductor elements, wherein each patterned substrate conductor element of the first set of patterned substrate conductor elements respectively is a bridge conductor that extends from a first point underneath the first PV cell to a second point underneath the second PV cell, and wherein the first set of top via structures comprises a first top via conductor that electrically connects the first set of patterned substrate conductor elements to the top electrode of the first PV cell; and d) a first set of bottom via structures extending through at least the dielectric layer to the first set of patterned substrate conductor elements at portions corresponding to the second PV cell, wherein the first set of bottom via structures comprises a first bottom via conductor that electrically connects the first set of patterned substrate conductor elements to the bottom electrode of the second PV cell, wherein the first set of patterned substrate conductor elements, the first top via conductor, and the first bottom via conductor collectively form the series electrical connection between the first and second PV cells.

2. The photovoltaic module of claim 1, wherein the top via conductor comprises the same conductive material as the transparent top electrode of the first PV cell.

3. The photovoltaic module of claim 1 or 2, wherein the bottom via conductor comprises the same conductive material as the bottom electrode of the second PV cell.

4. The photovoltaic module of claim 1, wherein the top via conductor comprises a metal, optionally formed from a pattern-deposited metal ink.

5. The photovoltaic module of claim 1, wherein the bottom via conductor comprises a metal, optionally formed from a pattern-deposited metal ink.

6. The photovoltaic module of claim 1, wherein the top transparent electrode includes a top transparent conductive oxide, optionally selected from ITO, IZO, AZO, or FTO.

7. The photovoltaic module of claim 6, wherein the top transparent electrode is a composite conductor including a top pattern of metal lines provided over the top transparent conductive oxide.

8. The photovoltaic module of claim 6, wherein the top transparent electrode is not a composite conductor and is substantially free of metal lines.

9. The photovoltaic module of claim 1, wherein the top electrode has a sheet resistance of in a range of 50 - 1000 ohm / sq.

10. The photovoltaic module of claim 1, wherein the patterned substrate conductor elements comprise aluminum.

11. The photovoltaic module of claim 1, wherein the patterned substrate conductor elements comprise copper.

12. The photovoltaic of claim 1, further comprising: e) a third PV cell adjacent the second PV cell and part of the set of series-connected PV cells, wherein the third PV cell comprises i) a bottom electrode overlaying the dielectric layer, ii) a photoactive layer overlaying the bottom electrode, the photoactive layer comprising at least an absorber layer, and iii) a transparent top electrode overlaying the photoactive layer; f) a second set of top via structures extending through the second PV cell and the dielectric layer to a second set of the patterned substrate conductor elements, wherein each patterned substrate conductor element of the second set of patterned substrate conductor elements respectively is a bridge conductor that extends from a first point underneath the second PV cell to a second point underneath the third PV cell, and wherein the second set of top via structures comprises a second top via conductor that electrically connects the second set of patterned substrate conductor elements to the top electrode of the second PV cell; and g) a second set of bottom via structures extending through at least the dielectric layer to the second set of patterned substrate conductor elements at portions corresponding to the thirdPV cell, wherein the second set of bottom via structures comprises a second bottom via conductor that electrically connects the second set of patterned substrate conductor elements to the bottom electrode of the third PV cell, wherein the second set of patterned substrate conductor elements, the second top via conductor, and the second bottom via conductor collectively form the series electrical connection between the second and third PV cells.

13. The photovoltaic module of claim 1, wherein the pattern substrate conductor elements further comprise first and second busbars provided at opposite ends of the module.

14. The photovoltaic module of claim 13, wherein a PV cell of the set of series- connected PV cells that is adjacent to the first busbar is electrically connected to the first busbar by a bottom via structure, and wherein a PV cell of the set of series-connected PV cells that is adjacent the second busbar is electrically connected to the second busbar by a top via structure.

15. The photovoltaic module of claim 1, wherein the bottom electrode is substantially opaque.

16. The photovoltaic module of claim 1, wherein the bottom electrode is transmissive or transparent.

17. The photovoltaic module of claim 16, wherein the bottom electrode comprises a bottom transparent conductive oxide, optionally selected from ITO, IZO, AZO, or FTO.

18. The photovoltaic module of claim 17, wherein the bottom transparent electrode is a composite conductor including a bottom pattern of metal lines provided between the bottom transparent conductive oxide and the substrate structure.

19. The photovoltaic module of claim 17, wherein the bottom transparent electrode is not a composite conductor and is substantially free of metal lines.

20. The photovoltaic module of claim 1, wherein a ratio of top electrode sheet resistance to bottom electrode sheet resistance is at least 2:1.

21. The photovoltaic module of claim 1, wherein i) the photovoltaic module is a bifacial module and an area of the substrate occupied by the bridge conductors is in a range of 5 - 50%, or ii) the photovoltaic module is a monofacial module and the area of the substrate occupied by the bridge conductors is in a range of 50 - 95%.. The photovoltaic module of claim 1 , wherein the top or bottom via structures comprise via holes through the dielectric layer that each occupy an area in a range of 0.001 - 0.2 mm 2.

23. The photovoltaic module of claim 1, wherein a contact area between any top via conductor and its corresponding patterned substrate conductor is in a range of 0.001 - 0.2 mm2.

24. The photovoltaic module of claim 1, wherein a contact area between any bottom via conductor and its corresponding patterned substrate conductor is in a range of 0.001 - 0.2 mm2.

25. The photovoltaic module of claim 1, wherein the first set of patterned substrate conductor elements comprises at least 3 bridge conductors, optionally 4 - 15 bridge conductors.

26. The photovoltaic module of claim 1, wherein the first PV cell comprises at least 4 top via structures, optionally 5 - 60 top via structures.

27. The photovoltaic module of claim 1, wherein each PV cell comprises at least as many bottom via structures as top via structures, optionally more bottom via structures than top via structures.

28. The photovoltaic module of claim 1, wherein the bottom via conductor comprises the same conductive material as the bottom electrode of the second PV cell, and wherein each PV cell comprises fewer bottom via structures than top via structures.

29. The photovoltaic module of claim 28, wherein a contact area between any bottom via conductor with a patterned substrate conductor element is larger than a contact area between any top via conductor with the same patterned conductor element.

30. The photovoltaic module of claim 1, wherein the first scribe structure has a width in a range of 20 to 60 pm.

31. The photovoltaic module of claim 1, wherein each PV cell is characterized by a width Wceii along a width dimension corresponding to the direction of series connections and by a length Lceii along a length dimension orthogonal to the width dimension, and wherein Wceii is less than LCeii, and optionally wherein a ratio of (WCeii / Lceii) is in a range of 0.05 to 0.5.

32. The photovoltaic module of claim 1, wherein each PV cell has an area in a range of 1 - 5 cm2.

33. The photovoltaic module of claim 1, wherein the dielectric layer has a thickness of 10 microns thick or less, optionally 2 microns or less.

36. The photovoltaic module of claim 1 , wherein the patterned substrate conductor elements have a thickness of 2 microns or less, optionally 0.2 microns or less.

37. The photovoltaic module of claim 1, wherein the photoactive layer has a thickness of less than 2 microns, optionally less than 1 micron.

38. The photovoltaic module of claim 1, wherein the absorber layer comprises a perovskite.

39. The photovoltaic module of claim 1, wherein the absorber layer comprises an organic photovoltaic material, a CIGS material, or a cadmium telluride material.

40. The photovoltaic module of claim 1, wherein the dielectric layer absorbs at least 10% of incident radiation at a wavelength of about 1321 nm, 1064 nm, 1030 nm, 532 nm, 515 nm, 488 nm, 355 nm, 343 nm, 266 nm, or 212 nm, optionally wherein the incident radiation is laser radiation.

41. The photovoltaic module of claim 1, wherein the patterned substrate conductor elements are shaped to have relatively longer and shorter dimensions and the top or bottom via structure is characterized by a via opening length that is substantially aligned with a longer dimension of a patterned substrate conductor element and a via opening width that is substantially orthogonal to the via opening length, wherein the via opening length is larger than the via opening width.

42. The photovoltaic module of claim 1, wherein the top or bottom via structure has a tapered sidewall characterized by taper angle less than about 70°, optionally less than about 45°.

43. The photovoltaic module of claim 1, wherein the substrate is flexible.

44. A method of making a photovoltaic (PV) module comprising a plurality of sets of series-connected PV cells, the method comprising: a) forming a patterned substrate conductor over a substrate, the patterned substrate conductor comprising a plurality of bridge conductors; b) forming a patterned dielectric layer over the patterned substrate conductor and substrate, the patterned dielectric layer comprising tapered bottom via openings corresponding to bottom via contact areas; c) depositing a bottom electrode layer over the patterned dielectric layer and into the tapered bottom via openings to make electrical contact between the bottom electrode layer and the underlying patterned substrate conductor;d) forming a plurality of first top via scribes, wherein each first top via scribe is formed by removing a portion of the bottom electrode layer along with a portion of the dielectric layer underneath the portion of the bottom electrode layer; e) depositing a photoactive layer over the structure from step (d), the photoactive layer comprising an absorber layer; f) forming a plurality of second top via scribes in alignment with the first top via scribes, wherein each second top via scribe produces tapered top via openings extending to the underlying patterned substrate conductor corresponding to top via contact areas; g) depositing a transparent top electrode layer over the structure from step (f) and into the top via openings to make electrical contact between the transparent top electrode layer and the underlying patterned substrate conductor; and h) forming one or more first scribe structures and one or more second scribe structures to fonn two or more sets of PV cells, each set comprising two or more PV cells, wherein adjacent cells in a set of PV cells are connected in series by a set two or more bridge conductors.

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