Fabrication of metasurfaces in standard semiconductor foundry processes

Abstract

An interconnecting wire layer configured to be integrated into a semiconductor chip. The interconnecting wire layer may comprise one or more wires configured to connect a plurality of electronic components integrated into the semiconductor chip. The one or more wires may be shaped, arranged, or both shaped and arranged to form one or more metasurfaces. This allows for a bulk semiconductor manufacturing process for metasurface fabrication.

Description

FABRICATION OF METASURFACES INSTANDARD SEMICONDUCTOR FOUNDRY PROCESSESCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims benefit of U.S. Provisional Application No. 63 / 636,258 filed April 19, 2024, the specification(s) of which is / are incorporated herein in their entirety by reference.FIELD OF THE INVENTION

[0002] The present invention is directed to a bulk semiconductor manufacturing process for metasurface fabrication.BACKGROUND OF THE INVENTION

[0003] Metasurfaces are two-dimensional arrays of nanostructures that can manipulate the phase, amplitude, and polarization of light at subwavelength scales. Due to their compactness and versatile functionalities, metasurfaces hold promising potential in advanced imaging systems, optical computing, beam steering for LiDAR and telecommunication technologies, displays, augmented and virtual reality, sensors, and energy harvesting. The subwavelength scale of the meta-atoms enables a spatially varying optical response across a metasurface.

[0004] Based on operational principles, plasmonic metasurfaces can be categorized into several main types, including resonant, geometric, and Huygens’ metasurfaces. Resonant metasurfaces are the earliest type and control the phase and / or amplitude of light through resonant constituent elements (meta-atoms) with spatially varying resonance wavelengths. They exhibit high efficiency at resonance frequency and enhanced local fields at resonance but suffer from a narrow bandwidth. Geometric metasurfaces rely on the geometric phase (Pancharatnam-Berry phase) that light acquires upon reflection or transmission through elements with spatially varying orientations. The phase change is independent of the resonance properties and depends solely on the geometry of the meta-atoms, which makes geometric metasurfaces suitable for broadband operation. Huygens’ metasurfaces mimic Huygens’ sources, where each meta-atom comprises electric and magnetic dipole responses balanced to maximize transmission and minimize reflection losses. Fabricating Huygens’ metasurfaces, however, is more complex due to the requirement for Isimultaneous electric and magnetic responses.

[0005] Another important type is high-index dielectric nano-post metasurfaces, which use arrays of closely packed, subwavelength-scale nano-posts of high refractive index materials. These plasmonic metasurfaces control the phase of incident light by adjusting the height and diameter of each nano-post, enabling polarization-dependent phase manipulation. Their high refractive index contrasts with the surrounding medium and allows for effective phase delay without relying on resonant effects that contribute to low optical losses and broad operational bandwidths. Additionally, high-index dielectric nano-post metasurfaces can be fabricated directly from the same material as the substrate (e.g., silicon) for simpler manufacturing processes and better integration with existing silicon-based photonic and electronic platforms. This compatibility with standard semiconductor processes makes them particularly attractive for scalable production and diverse applications, including lensing, beam shaping, and imaging systems. Thus, there exists a present need for a bulk semiconductor manufacturing process for metasurface fabrication.BRIEF SUMMARY OF THE INVENTION

[0006] It is an objective of the present invention to provide devices and methods that allow for a bulk semiconductor manufacturing process for metasurface fabrication, as specified in the independent claims. Embodiments of the invention are given in the dependent claims. Embodiments of the present invention can be freely combined with each other if they are not mutually exclusive.

[0007] According to some embodiments, the present invention features an interconnecting wire layer configured to be integrated into a semiconductor chip. The interconnecting wire layer may comprise one or more wires configured to connect a plurality of electronic components integrated into the semiconductor chip. The one or more wires may be shaped, arranged, or both shaped and arranged to form one or more metasurfaces.

[0008] In other embodiments, the present invention features a semiconductor chip having one or more metasurfaces. In some embodiments, the semiconductor chip may comprise a front-end-of-the-line (FOEL) layer comprising a plurality of electronic components. The semiconductor chip may further comprise a back-end-of-the-line(BOEL) layer comprising one or more wires configured to connect the plurality of electronic components integrated into the semiconductor chip. In some embodiments, the one or more wires may be shaped, arranged, or both shaped and arranged to form the one or more metasurfaces.

[0009] According to some other embodiments, the present invention features a method for fabricating a semiconductor chip comprising one or more metasurfaces. In some embodiments, the method may comprise forming a front-end-of-the-line (FOEL) layer comprising a plurality of electronic components and forming a back-end-of-the-line (BOEL) layer coupled to the FOEL layer. The method may further comprise applying one or more wires to the BOEL layer such that the one or more wires connect the plurality of electronic components integrated into the semiconductor chip and form the one or more metasurfaces.

[0010] One of the unique and inventive technical features of the present invention is the shaping and arrangement of wires on a back-end-of-the-line layer to form one or more metasurfaces. Without wishing to limit the invention to any theory or mechanism, it is believed that the technical feature of the present invention advantageously provides for efficient manufacturing of semiconductor chips with metasurfaces through standard semiconductor foundry processes. None of the presently known prior references or work has the unique inventive technical feature of the present invention.

[0011] Any feature or combination of features described herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one of ordinary skill in the art. Additional advantages and aspects of the present invention are apparent in the following detailed description and claims.BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

[0012] The features and advantages of the present invention will become apparent from a consideration of the following detailed description presented in connection with the accompanying drawings in which:

[0013] FIG. 1 shows an embodiment of the present invention featuring a semiconductorchip with a metasurface.

[0014] FIG. 2A shows a schematic diagram of a resonant metasurface implemented on a semiconductor chip of the present invention.

[0015] FIG. 2B shows a schematic diagram of a geometric metasurface implemented on a semiconductor chip of the present invention.

[0016] FIG. 2C shows a schematic diagram of a Huygens’ metasurface implemented on a semiconductor chip of the present invention.

[0017] FIG. 2D shows a schematic diagram of a silicon nanopost metasurface implemented on a semiconductor chip of the present invention.

[0018] FIG. 3 shows a flow chart of a method for fabricating a metasurface semiconductor chip of the present invention.DETAILED DESCRIPTION OF THE INVENTION

[0019] Following is a list of elements corresponding to a particular element referred to herein:

[0020] 100 interconnecting wire layer

[0021] 150 wires

[0022] 200 front-end-of-the-line layer

[0023] 250 electronic components

[0024] 800 second interconnecting wire layer

[0025] 1000 semiconductor chip

[0026] The term “etch mask” is defined herein as a template that has a pattern, wherein plasma particles bombard the surface of the template and the exposed underlying surface, thus forming the pattern that was laid down by the mask on the underlying surface.

[0027] Referring now to FIG. 1 , the present invention features an interconnecting wire layer (100) configured to be integrated into a semiconductor chip (1000). The interconnecting wire layer (100) may comprise one or more wires (150) configured to connect a plurality of electronic components (250) integrated into the semiconductor chip (1000). The one or more wires (150) may be shaped, arranged, or both shaped and arranged to form one or more metasurfaces.

[0028] As shown in 2A-2D, the present invention features a semiconductor chip (1000). In some embodiments, the semiconductor chip (1000) may comprise a front-end-of-the-line (FOEL) layer (200) comprising a plurality of electronic components (250). The semiconductor chip (1000) may further comprise a back-end-of-the-line (BOEL) layer (100) comprising one or more wires (150) configured to connect the plurality of electronic components (250) integrated into the semiconductor chip (1000). In some embodiments, the one or more wires (150) may be shaped, arranged, or both shaped and arranged to form one or more metasurfaces.

[0029] Referring now to FIG. 3, the present invention features a method for fabricating a semiconductor chip (1000) comprising one or more metasurfaces. In some embodiments, the method may comprise forming a front-end-of-the-line (FOEL) layer (200) comprising a plurality of electronic components (250) and forming a back-end-of-the-line (BOEL) layer (100) coupled to the FOEL layer. The method may further comprise applying one or more wires (150) to the BOEL layer (100) such that the one or more wires (150) connect the plurality of electronic components (250) integrated into the semiconductor chip (1000) and form the one or more metasurfaces.

[0030] In some embodiments, the one or more wires (150) may be further configured to be resonantly excited at one or more frequencies. In some embodiments, the one or more metasurfaces may comprise one or more resonant metasurfaces.

[0031] In some embodiments, the one or more wires (150) may comprise one or more metallic nanorods. In some embodiments, the one or more metallic nanorods may be arranged such that when the one or more metallic nanorods are exposed to light, a Pancharatnam-Berry phase is achieved. In some embodiments, the one or more metasurfaces may comprise one or more geometric metasurfaces. In some embodiments, the one or more metallic nanorods may be arranged such that a geometric phase is added to the incident circularly polarized light directed towards the one or more metallic nanorods.

[0032] In some embodiments, the one or more wires (150) may each comprise a first electric pole and a first magnetic pole. The BOEL layer (100) may be further configured to couple to a second interconnecting wire layer (800) comprising a second electric poleand a second magnetic pole. The first electric pole and the second electric pole may be configured to form an electric dipole. The first magnetic pole and the second magnetic pole may be configured to form a magnetic dipole. The one or more metasurfaces may comprise one or more Huygens’ metasurfaces. In some embodiments, if the second interconnecting wire layer (800) is integrated into a second semiconductor chip, the Huygens’ metasurface may be achieved on both the first semiconductor chip and the second semiconductor chip.

[0033] In some embodiments, the one or more wires (150) may form an etch mask. In some embodiments, the one or more metasurfaces may comprise one or more silicon nano-post metasurfaces. In some embodiments, the BOEL layer may further comprise a substrate layer upon which the one or more wires are disposed. In some embodiments, the etch mask of the one or more silicon-nanopost metasurfaces may further comprise one or more posts extending from a substrate of the BOEL layer. In some embodiments, the substrate layer and the one or more posts may comprise silicon. In some embodiments, the one or more silicon nano-post metasurfaces may be optically in-line with one or more plasma particle generators configured to direct plasma particles towards the one or more silicon nano-post generators.

[0034] In some embodiments, the resonant metasurfaces may add a phase depending on how close the elements disposed thereon are from resonance. In some embodiments, Huygens’ metasurfaces may cover the phase range through a combination of magnetic and electric dipoles. In some embodiments, the silicon nanopost metasurfaces may add a propagating phase depending on its aspect ratio.

[0035] In some embodiments, a material of the one or more wires (150) may comprise copper, aluminum, titanium nitride, tungsten, or a combination thereof.

[0036] In some embodiments, the plurality of electronic components (250) may comprise transistors, p-n junctions, inductors, gates, or a combination thereof.

[0037] In some embodiments, the semiconductor chips of the present invention may comprise complementary metal-oxide-sem iconductors (CMOS) chips, silicon-on-insulator (SOI) chips, silicon photonics chips, or a combination thereof.

[0038] In some embodiments, the metasurface semiconductor chips of the present invention may be implemented in lensing applications, beam-shaping applications, imaging applications, or any other optical applications. In some embodiments, the metasurface semiconductor chips of the present invention are capable of being manufactured at any semiconductor foundry.According to some embodiments, the present invention features a metasurface formed on a surface of a semiconductor chip (1000). The metasurface may be operatively connected to a plurality of electronic components (250) of the semiconductor chip (1000) including, but not limited to, transistors, p-n junctions, inductors, gates, or a combination thereof. In some embodiments, the metasurface is a resonant metasurface, a geometric metasurface, a dielectric metasurface, or a Huygens’ plasmonic metasurface.

[0039] In non-limiting embodiments, the metasurface is a resonant metasurface comprising metallic interconnects configured to excite resonances. In other embodiments, the metasurface is a geometric metasurface comprising metallic nanorods having been altered in orientation and geometry such that when the one or more metallic nanorods are exposed to light, a Pancharatnam-Berry phase is achieved. In some other embodiments, the metasurface is a dielectric metasurface comprising etched silicon nano-posts.

[0040] Without wishing for a particular theory or mechanism, the present invention features the integration of metasurfaces within standard semiconductor foundry processes by designing, post-processing, and characterizing both plasmonic and silicon nano-post metasurfaces (FIGs 2A-2D). By repurposing the back-end-of-the-line (BEOL) metal layers in standard semiconductor processes, resonant, geometric, and Huygens’ plasmonic metasurfaces can be created to achieve the desired optical functions.

[0041] Metallic interconnects can be designed to excite resonances for resonant metasurfaces (FIG. 2A). Further, by altering the orientation and geometry of metallic nanorods, geometric metasurfaces can be developed (FIG. 2B). Additionally, using two metal interconnect layers, in some manifestation, to support the electric and magnetic dipoles Huygens’ metasurfaces can be created (FIG. 2C). Alongside plasmonic metasurfaces, it is possible to develop dielectric metasurfaces within semiconductor chips by leveraging a metallic interconnect layer as an etch mask for silicon nano-postmetasurfaces (FIG. 2D). Without sacrificing optical performance, the overarching objective is to create plasmonic and dielectric metasurfaces that adhere to the Design Rule Checks of a typical semiconductor foundry process.

[0042] Although there has been shown and described the preferred embodiment of the present invention, it will be readily apparent to those skilled in the art that modifications may be made thereto which do not exceed the scope of the appended claims. Therefore, the scope of the invention is only to be limited by the following claims. In some embodiments, the figures presented in this patent application are drawn to scale, including the angles, ratios of dimensions, etc. In some embodiments, the figures are representative only and the claims are not limited by the dimensions of the figures. In some embodiments, descriptions of the inventions described herein using the phrase “comprising” includes embodiments that could be described as “consisting essentially of” or “consisting of”, and as such the written description requirement for claiming one or more embodiments of the present invention using the phrase “consisting essentially of” or “consisting of” is met.

[0043] The reference numbers recited in the below claims are solely for ease of examination of this patent application, and are exemplary, and are not intended in any way to limit the scope of the claims to the particular features having the corresponding reference numbers in the drawings.

Claims

WHAT IS CLAIMED IS:

1. An interconnecting wire layer (100) configured to be integrated into a semiconductor chip (1000), the interconnecting wire layer (100) comprising one or more wires (150) configured to connect a plurality of electronic components (250) integrated into the semiconductor chip (1000), wherein the one or more wires (150) are shaped, arranged, or both shaped and arranged to form one or more metasurfaces.

2. The interconnecting wire layer (100) of claim 1 , wherein the one or more wires (150) are further configured to be resonantly excited at one or more frequencies, wherein the one or more metasurfaces comprise one or more resonant metasurfaces.

3. The interconnecting wire layer (100) of claim 1 , wherein the one or more wires (150) comprise one or more metallic nanorods, wherein the one or more metallic nanorods are arranged such that when the one or more metallic nanorods are exposed to light a Pancharatnam-Berry phase is achieved, wherein the one or more metasurfaces comprise one or more geometric metasurfaces.

4. The interconnecting wire layer (100) of claim 1 , wherein the one or more wires (150) each comprise a first electric pole and a first magnetic pole, wherein the interconnecting wire layer (100) is further configured to couple to a second interconnecting wire layer (800) comprising a second electric pole and a second magnetic pole, wherein the first electric pole and the second electric pole are configured to form an electric dipole, wherein the first magnetic pole and the second magnetic pole are configured to form a magnetic dipole, wherein the one or more metasurfaces comprise one or more Huygens’ metasurfaces.

5. The interconnecting wire layer (100) of claim 1 , wherein the one or more wires (150) form an etch mask, wherein the one or more metasurfaces comprise one or more silicon nano-post metasurfaces.

6. The interconnecting wire layer (100) of claim 1 , wherein a material of the one or more wires (150) comprises copper, aluminum, titanium nitride, tungsten, or a combination thereof.

7. The interconnecting wire layer (100) of claim 1 , wherein the plurality of electronic components (250) comprise transistors, p-n junctions, inductors, gates, or a combination thereof.

8. A metasurface formed on a surface of a semiconductor chip (1000), wherein the metasurface is operatively connected to a plurality of electronic components (250) of the semiconductor chip (1000).

9. The metasurface of claim 8, wherein the metasurface is a resonant metasurface, a geometric metasurface, a dielectric metasurface, or a Huygens’ plasmonic metasurface.

10. The metasurface of claim 8, wherein the metasurface is a resonant metasurface comprising metallic interconnects configured to excite resonances.11 . The metasurface of claim 8, wherein the metasurface is a geometric metasurface comprising metallic nanorods having been altered in orientation and geometry such that when the one or more metallic nanorods are exposed to light, a Pancharatnam-Berry phase is achieved.

12. The metasurface of claim 8, wherein the metasurface is a dielectric metasurface comprising etched silicon nano-posts.

13. The metasurface of claim 8, wherein the plurality of electronic components (250) comprise transistors, p-n junctions, inductors, gates, or a combination thereof.

14. A semiconductor chip (1000) comprising: a. a front-end-of-the-line (FOEL) layer (200) comprising a plurality of electronic components (250); and a. a back-end-of-the-line (BOEL) layer (100) comprising one or more wires (150) configured to connect the plurality of electronic components (250) integrated into the semiconductor chip (1000), wherein the one or more wires (150) are shaped, arranged, or both shaped and arranged to form one or more metasurfaces.

15. The semiconductor chip (1000) of claim 14, wherein the one or more wires (150)are further configured to be resonantly excited at one or more frequencies, wherein the one or more metasurfaces comprise one or more resonant metasurfaces.

16. The semiconductor chip (1000) of claim 14, wherein the one or more wires (150) comprise one or more metallic nanorods, wherein the one or more metallic nanorods are arranged such that when the one or more metallic nanorods are exposed to light a Pancharatnam-Berry phase is achieved, wherein the one or more metasurfaces comprise one or more geometric metasurfaces.

17. The semiconductor chip (1000) of claim 14, wherein the one or more wires (150) each comprise a first electric pole and a first magnetic pole, wherein the BOEL layer (100) is further configured to couple to a second interconnecting wire layer (800) comprising a second electric pole and a second magnetic pole, wherein the first electric pole and the second electric pole are configured to form an electric dipole, wherein the first magnetic pole and the second magnetic pole are configured to form a magnetic dipole, wherein the one or more metasurfaces comprise one or more Huygens’ metasurfaces.

18. The semiconductor chip (1000) of claim 14, wherein the one or more wires (150) form an etch mask, wherein the one or more metasurfaces comprise one or more silicon nano-post metasurfaces.

19. The semiconductor chip (1000) of claim 14, wherein a material of the one or more wires (150) comprises copper, aluminum, titanium nitride, tungsten, or a combination thereof.

20. The semiconductor chip (1000) of claim 14, wherein the plurality of electronic components (250) comprise transistors, p-n junctions, inductors, gates, or a combination thereof.

21. A method for fabricating a semiconductor chip (1000) comprising one or more metasurfaces, the method comprising: a. forming a front-end-of-the-line (FOEL) layer (200) comprising a plurality of electronic components (250);b. forming a back-end-of-the-line (BOEL) layer (100) coupled to the FOEL layer; and c. applying one or more wires (150) to the BOEL layer (100) such that the one or more wires (150) connect the plurality of electronic components (250) integrated into the semiconductor chip (1000) and form the one or more metasurfaces.

22. The method of claim 21 , wherein the one or more wires (150) are further configured to be resonantly excited at one or more frequencies, wherein the one or more metasurfaces comprise one or more resonant metasurfaces.

23. The method of claim 21 , wherein the one or more wires (150) comprise one or more metallic nanorods, wherein the one or more metallic nanorods are arranged such that when the one or more metallic nanorods are exposed to light a Pancharatnam-Berry phase is achieved, wherein the one or more metasurfaces comprise one or more geometric metasurfaces.

24. The method of claim 21 , wherein the one or more wires (150) each comprise a first electric pole and a first magnetic pole, wherein the BOEL layer (100) is further configured to couple to a second interconnecting wire layer (800) comprising a second electric pole and a second magnetic pole, wherein the first electric pole and the second electric pole are configured to form an electric dipole, wherein the first magnetic pole and the second magnetic pole are configured to form a magnetic dipole, wherein the one or more metasurfaces comprise one or more Huygens’ metasurfaces.

25. The method of claim 21 , wherein the one or more wires (150) form an etch mask, wherein the one or more metasurfaces comprise one or more silicon nano-post metasurfaces.

26. The method of claim 21 , wherein the plurality of electronic components (250) comprise transistors, p-n junctions, inductors, gates, or a combination thereof.

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