Display substrate, display panel, and display device

Abstract

Provided are a display substrate (100), a display panel, and a display device. The display substrate (100) comprises: a base substrate (1), and a first conductive layer (11), a first insulating layer (31), a second conductive layer (12), a second insulating layer (32) and a third conductive layer (13) sequentially away from the base substrate (1), wherein the first conductive layer (11) comprises a plurality of data lines (DL) and electrode lines (CL) alternately arranged in a first direction and extending in a second direction, and a first electrode (S1) and a second electrode (D1) of a thin film transistor; the second conductive layer (12) comprises a common electrode (2) and a plurality of protective electrode blocks (120), the common electrode (2) comprises a plurality of openings (21), and the orthographic projection of the at least one protective electrode block (120) on the base substrate (1) falls within the orthographic projection of at least one opening (21) of the common electrode (2) on the base substrate (1); the third conductive layer (13) comprises a plurality of pixel electrodes (4), and the pixel electrodes (4) are connected to the protective electrode blocks (120) and the second electrode (D1) of the thin film transistor by means of first via holes (VH1); and the overlapping portion between the orthographic projections of the second electrode (D1) of the thin film transistor and the protective electrode blocks (120) on the base substrate (1) at least partially overlaps with the orthographic projection of the first via holes (VH1) on the base substrate (1).

Description

Display substrate, display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate, a display panel and a display device. BACKGROUND

[0002] Liquid crystal display (LCD) is widely used due to its advantages of small volume, low power consumption, no radiation, etc. With the resolution of display products being higher and higher, the pixel size is smaller and smaller, and the aperture ratio is smaller and smaller. How to optimize the pixel design and improve the pixel aperture ratio is crucial for high-resolution display products.

[0003] The above information disclosed in this section is only for the understanding of the background of the technical concept of the present disclosure, and therefore, the above information can contain information which does not constitute the prior art.

[0004] SUMMARY

[0005] In one aspect, a display substrate is provided, wherein the display substrate comprises a plurality of sub-pixels arranged in an array along a first direction and a second direction, the first direction and the second direction being perpendicular to each other; the display substrate comprises: a substrate; a first conductive layer located on one side of the substrate, the first conductive layer comprising a plurality of data lines and a plurality of electrode lines arranged alternately along the first direction, each of the data lines and the electrode lines extending along the second direction, each column of sub-pixels being located between adjacent data lines and electrode lines; the first conductive layer further comprising a first electrode and a second electrode of a thin film transistor, wherein the data lines are connected to the first electrodes of the thin film transistors, and the second electrodes of the thin film transistors are located between adjacent data lines and electrode lines; a first insulating layer located on a side of the first conductive layer away from the substrate; a second conductive layer located on a side of the first insulating layer away from the substrate, the second conductive layer comprising a common electrode and a plurality of protection electrode blocks, the common electrode comprising a plurality of openings, wherein a projection of at least one of the protection electrode blocks on the substrate falls within a projection of at least one of the openings of the common electrode on the substrate; a second insulating layer located on a side of the second conductive layer away from the substrate; and a third conductive layer located on a side of the second insulating layer away from the substrate, the third conductive layer comprising a plurality of pixel electrodes, one pixel electrode being provided in an area where each of the sub-pixels is located, wherein the pixel electrodes are connected to the protection electrode blocks through first vias, and the pixel electrodes are connected to the second electrodes of the thin film transistors through the first vias, wherein a projection of the second electrode of the thin film transistor on the substrate at least partially overlaps with a projection of the protection electrode block on the substrate, and an overlapping part of the projection of the second electrode of the thin film transistor and the projection of the protection electrode block on the substrate at least partially overlaps with a projection of the first via on the substrate.

[0006] According to some exemplary embodiments, the first via comprises a first sub-via and a second sub-via, wherein the first sub-via and the second sub-via are arranged adjacent to each other in the first direction; the first sub-via penetrates the first insulating layer and the second insulating layer, and the pixel electrode is connected to the second electrode of the thin film transistor through the first sub-via; the second sub-via penetrates the second insulating layer, and the pixel electrode is connected to the protection electrode block through the second sub-via.

[0007] According to some exemplary embodiments, the first sub-via has a first width in the first direction, and the second sub-via has a second width in the first direction, the first width being smaller than the second width.

[0008] According to some exemplary embodiments, the second electrode of the thin film transistor has a first side edge and a second side edge extending along the second direction, the first via hole has a third side edge and a fourth side edge extending along the second direction, and the protective electrode block has a fifth side edge and a sixth side edge extending along the second direction, wherein the first side edge, the third side edge, the fifth side edge, the second side edge, the fourth side edge and the sixth side edge are sequentially and spaced apart along the first direction.

[0009] According to some exemplary embodiments, a first preset distance is provided between the first side edge and the third side edge.

[0010] According to some exemplary embodiments, a second preset distance is provided between the fifth side edge and the second side edge.

[0011] According to some exemplary embodiments, a third preset distance is provided between the fourth side edge and the sixth side edge.

[0012] According to some exemplary embodiments, the first insulating layer includes a first portion adjacent to the first sub-via hole and having a projection on the substrate which does not overlap with a projection of the second sub-via hole on the substrate, wherein the first portion includes a first side wall adjacent to the first sub-via hole, and the first side wall has a first slope angle; and the second insulating layer includes a second portion adjacent to the first sub-via hole and having a projection on the substrate which does not overlap with a projection of the second sub-via hole on the substrate, wherein the second portion includes a second side wall adjacent to the first sub-via hole, and the second side wall has a second slope angle, and the first slope angle is greater than the second slope angle.

[0013] According to some exemplary embodiments, the first insulating layer further includes a third portion adjacent to the first sub-via hole, and a projection of the third portion on the substrate falls within a projection of the second electrode of the thin film transistor on the substrate and a projection of the protective electrode block on the substrate, wherein the third portion includes a third side wall away from the first sub-via hole, and the third side wall has a third slope angle; and the protective electrode block includes a fourth portion having a projection on the substrate which falls within a projection of the third portion of the first insulating layer on the substrate, and the fourth portion of the protective electrode block includes a fourth side wall away from the first sub-via hole, and the fourth side wall has a fourth slope angle, and the third slope angle is greater than or equal to twice the fourth slope angle.

[0014] According to some exemplary embodiments, the second insulating layer further comprises a fifth portion, the fifth portion is adjacent to the second sub-via hole and a projection of the fifth portion on the substrate substrate at least partially overlaps with a projection of the protective electrode block on the substrate substrate, wherein the fifth portion comprises a fifth side wall close to the second sub-via hole, the fifth side wall has a fifth slope angle, the fifth slope angle is greater than or equal to 30°.

[0015] According to some exemplary embodiments, the display substrate further comprises: a third insulating layer located on a side of the first conductive layer close to the substrate substrate; and a fourth conductive layer located on a side of the third insulating layer close to the substrate substrate, the fourth conductive layer comprises a gate electrode of the thin film transistor and a gate line connected with the gate electrode, the gate line comprises a widened portion and a connecting portion, the gate electrode is located in the widened portion, a projection of the second electrode of the thin film transistor on the substrate substrate at least partially overlaps with a projection of the widened portion on the substrate substrate; and a projection of the second electrode of the thin film transistor on the substrate substrate does not overlap with a projection of the connecting portion on the substrate substrate.

[0016] According to some exemplary embodiments, a projection of the protective electrode block on the substrate substrate at least partially overlaps with a projection of the widened portion on the substrate substrate; a projection of the protective electrode block on the substrate substrate at least partially overlaps with a projection of the connecting portion on the substrate substrate.

[0017] According to some exemplary embodiments, the display substrate comprises a plurality of gate lines, the gate lines extend along the first direction, the gate lines are located between two adjacent rows of sub-pixel regions; the pixel electrode comprises a plurality of pixel electrode strips located in the regions where the sub-pixels are located and arranged at intervals, the pixel electrode further comprises a first connecting portion and a second connecting portion, the first connecting portion is located at one end of the plurality of pixel electrode strips and connected with the plurality of pixel electrode strips, the second connecting portion is located at the other end of the plurality of pixel electrode strips and connected with the plurality of pixel electrode strips, the first connecting portion is connected with the second electrode of the corresponding thin film transistor through the first via hole, and a projection of the second connecting portion on the substrate substrate at least partially overlaps with a projection of the gate line on the substrate substrate on the corresponding side.

[0018] According to some exemplary embodiments, the display substrate comprises a plurality of gate lines extending along the first direction, the gate lines being located between two adjacent rows of sub-pixel regions, and two of the gate lines being arranged between each two adjacent rows of sub-pixel regions; the plurality of sub-pixels comprises a plurality of rows of sub-pixels located at an i-th row and an (i+1)-th row respectively, and a plurality of columns of sub-pixels located at a j-th column and a (j+1)-th column respectively, where i is greater than or equal to 1, and j is greater than or equal to 1; the gate lines comprise a first gate line and a second gate line located between the i-th row of sub-pixels and the (i+1)-th row of sub-pixels, the first gate line being connected to a gate electrode of a thin film transistor of a sub-pixel at the (i+1)-th row and the j-th column, and the second gate line being connected to a gate electrode of a thin film transistor of a sub-pixel at the i-th row and the j-th column.

[0019] According to some exemplary embodiments, the first via hole comprises a seventh side extending along the first direction; the seventh side of the sub-pixel in the i-th row is located between the first gate line and the second gate line, and a fourth preset distance is arranged between the seventh side and the second gate line.

[0020] According to some exemplary embodiments, the first via hole further comprises an eighth side extending along the first direction, and a projection of the eighth side on the substrate substrate falls within a projection of the gate line on the substrate substrate; the protection electrode block comprises a ninth side extending along the first direction, and a projection of the ninth side on the substrate substrate at least partially overlaps with a projection of the widened portion of the gate line on the substrate substrate, wherein a fifth preset distance is arranged between the eighth side and the ninth side.

[0021] According to some exemplary embodiments, a projection of the protection electrode block on the substrate substrate at least partially overlaps with a projection of the gate line on the substrate substrate, wherein the protection electrode block comprises a protruding portion protruding relative to the gate line in the second direction, the protruding portion being located between two adjacent gate lines, and the protruding portion has a first protruding distance in the second direction.

[0022] According to some exemplary embodiments, the display substrate comprises a first sub-pixel located at an i-th row and a j-th column, a second sub-pixel located at the i-th row and a (j+1)-th column, and a third sub-pixel located at the i-th row and a (j+2)-th column, wherein the second sub-pixel comprises a second sub-pixel electrode; the display substrate further comprises a first data line located between the j-th column of sub-pixels and the (j+1)-th column of sub-pixels, and a first electrode line located between the (j+1)-th column of sub-pixels and the (j+2)-th column of sub-pixels, wherein a projection of the second sub-pixel electrode on the substrate substrate at least partially overlaps with a projection of the first electrode line on the substrate substrate.

[0023] According to some exemplary embodiments, the data line comprises a main body portion and a connecting portion, the connecting portion is connected with the first electrode of the thin film transistor, wherein the connecting portion extends along the second direction, a projection of the connecting portion on the substrate substrate at least partially overlaps with a projection of the main body portion on the substrate substrate; the connecting portion has a third width along the first direction, the main body portion has a fourth width along the first direction, a ratio of the third width to the fourth width is between 0.8 and 1.2.

[0024] According to some exemplary embodiments, the data line comprises a main body portion and a connecting portion, the connecting portion is connected with the first electrode of the thin film transistor, wherein the connecting portion protrudes from the main body portion along the first direction by a second protruding distance, the main body portion has a fourth width along the first direction, the second protruding distance is greater than the fourth width.

[0025] According to some exemplary embodiments, a projection of the common electrode on the substrate substrate at least partially overlaps with a projection of the gate line on the substrate substrate.

[0026] According to some exemplary embodiments, the display substrate comprises a plurality of gate lines, the gate lines extend along the first direction, the gate lines are located between two adjacent rows of sub-pixel regions, the gate lines comprise a widened portion and a connecting portion, two gate lines are arranged between each two adjacent rows of sub-pixel regions; the plurality of sub-pixels comprises a plurality of rows of sub-pixels located in an i-th row and an i+1-th row, wherein i is greater than or equal to 1, the gate lines comprise a first gate line and a second gate line located between the region of the i-th row of sub-pixels and the region of the i+1-th row of sub-pixels, wherein a projection of the common electrode on the substrate substrate at least partially overlaps with a projection of the widened portion of the first gate line on the substrate substrate, the projection of the common electrode and the widened portion of the first gate line has a first overlapping width along the second direction, the first overlapping width is greater than or equal to 0.85 microns.

[0027] According to some exemplary embodiments, a projection of the common electrode on the substrate substrate at least partially overlaps with a projection of the connecting portion of the second gate line on the substrate substrate, the projection of the common electrode and the connecting portion of the second gate line has a second overlapping width along the second direction, the second overlapping width is greater than or equal to 0.5 microns.

[0028] In another aspect, a display panel is provided, the display panel comprising the display substrate according to any one of the above.

[0029] In yet another aspect, a display device is provided, the display device comprising the display substrate according to any one of the above or the display panel according to the above. BRIEF DESCRIPTION OF DRAWINGS

[0030] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0031] FIG. 1 is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure;

[0032] FIG. 2 is an enlarged view of the portion enclosed by the dashed line in FIG. 1;

[0033] FIG. 3A is a cross-sectional view taken along line AA' in FIG. 2;

[0034] FIG. 3B is a cross-sectional view taken along line BB' in FIG. 2;

[0035] FIG. 4 is a plan view of a display substrate according to some exemplary embodiments of the present disclosure;

[0036] FIG. 5A is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure; FIG. 5B is a cross-sectional view taken along line A1-A1' in FIG. 5A; FIG. 5C is a cross-sectional view taken along line B1-B1' in FIG. 5A; FIG. 5D is a partial plan view of a display substrate according to other exemplary embodiments of the present disclosure; FIG. 5E is a cross-sectional view taken along line A2-A2' in FIG. 5D; FIG. 5F is a cross-sectional view taken along line B2-B2' in FIG. 5D; FIG. 5G is a partial plan view of a display substrate according to still other exemplary embodiments of the present disclosure; FIG. 5H is a cross-sectional view taken along line A3-A3' in FIG. 5G; FIG. 51 is a cross-sectional view taken along line B3-B3' in FIG. 5G;

[0037] FIG. 6 is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure;

[0038] FIG. 7 illustrates a partial plan view of a fourth conductive layer in FIG. 6;

[0039] FIG. 8 illustrates a partial plan view of a third insulating layer in FIG. 6;

[0040] FIG. 9 illustrates a partial plan view of a first conductive layer in FIG. 6;

[0041] FIG. 10 illustrates a partial plan view of a second conductive layer in FIG. 6;

[0042] FIG. 11 illustrates a plurality of vias in FIG. 6;

[0043] FIG. 12 illustrates a partial plan view of a third conductive layer in FIG. 6;

[0044] FIGS. 13A and 13B are each a partial enlarged view of a dashed area S in FIG. 6;

[0045] FIG. 14 shows a cross-sectional view taken along line CC’ in FIG. 13A;

[0046] FIG. 15 shows a cross-sectional view taken along line DD’ in FIG. 13A;

[0047] FIG. 16 is an SEM image of a display substrate in a first via region along a first direction according to some illustrative embodiments of the present disclosure;

[0048] FIG. 17 is a partial plan view of a display substrate according to some illustrative embodiments of the present disclosure;

[0049] FIG. 18 is a partial plan view of a display substrate according to some illustrative embodiments of the present disclosure;

[0050] FIG. 19A is a cross-sectional view of a display substrate taken along line EE’ in FIG. 17 according to some embodiments of the present disclosure; FIG. 19B is a cross-sectional view of a display substrate taken along line FF’ in FIG. 17 according to some embodiments of the present disclosure; FIG. 19C is a cross-sectional view of a display substrate taken along line GG’ in FIG. 18 according to some embodiments of the present disclosure; FIG. 19D is a cross-sectional view of a display substrate taken along line HH’ in FIG. 18 according to some embodiments of the present disclosure;

[0051] FIG. 20 is a structural schematic view of a display device according to some embodiments of the present disclosure;

[0052] FIG. 21 is a structural schematic view of a display device according to some embodiments of the present disclosure.

[0053] It should be noted that, for the sake of clarity, the size of a layer, structure, or region in the drawings can be exaggerated or reduced, i.e., the drawings are not necessarily drawn to scale relative to each other. DETAILED DESCRIPTION

[0054] In order to make the objects, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong within the scope of the present disclosure.

[0055] It should be noted that, in the drawings, the size and relative size of the elements can be exaggerated for the sake of clarity and / or description. Thus, the size and relative size of the elements are not necessarily limited to the size and relative size shown in the drawings. In the description and drawings, identical or similar reference numerals indicate identical or similar components.

[0056] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning as understood by a person of ordinary skill in the art. The terms "first", "second", and similar terms are used herein to distinguish one element from another, and are not necessarily used to describe a sequential or chronological order, unless otherwise indicated. The terms "comprises", "comprising", "includes", "including" and the like can mean the presence of the stated elements or objects and the like, but do not preclude the presence or addition of one or more other elements or objects.

[0057] In this document, unless otherwise specified, directional terms such as "upper", "lower", "left", "right", "inner", "outer", and the like are used to describe the orientation or positional relationship as shown in the drawings, and are only for the convenience of describing the present disclosure, and do not indicate or imply that the device, element or component referred to must have a particular orientation, be constructed or operated in a particular orientation. It should be understood that when the absolute position of the described object changes, the relative positional relationship they represent may also change accordingly. Therefore, these directional terms cannot be understood as a limitation on the present disclosure.

[0058] It should be noted that in this document, "the same layer" refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then patterning the film layer by a one-time patterning process using the same mask plate. Depending on the specific pattern, the one-time patterning process can include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, the plurality of elements, components, structures and / or parts located in "the same layer" are composed of the same material and formed by the same one-time patterning process. Generally, the plurality of elements, components, structures and / or parts located in "the same layer" have approximately the same thickness.

[0059] It should be understood by those skilled in the art that in this document, unless otherwise specified, the expression "height" or "thickness" refers to the dimension along the surface of each film layer disposed perpendicular to the display substrate, i.e. the dimension along the light output direction of the display substrate, or the dimension along the normal direction of the display device.

[0060] In this document, the directional expressions "first direction", "second direction" are used to describe different directions along the pixel unit, for example, the longitudinal direction and the transverse direction of the pixel unit, or the row direction and the column direction of the sub-pixel arrangement. It should be understood that such representation is only an exemplary description, and is not a limitation on the present disclosure.

[0061] In this document, the expression "transistor" can be a triode, a thin film transistor or a field effect transistor or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish two poles of the transistor except the control pole, one pole is called the first pole and the other pole is called the second pole. In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0062] The liquid crystal display is a kind of flat and ultra-thin display device, mainly including a backlight module and a display panel. The backlight module provides light for the display panel, and the display panel displays the picture. In actual application, only a small part of the light emitted by the backlight module transmits through the display panel, and the light utilization rate is low. In order to ensure that the liquid crystal display has high brightness, a large power consumption is required. The pixels provided on the display panel include a light-transmitting region and a non-light-transmitting region. The light-transmitting region includes a region where a pixel electrode is located, and the non-light-transmitting region includes a region where a data line, a gate line and a thin film transistor are located. The ratio of the area of the light-transmitting region to the area of the pixel is the aperture ratio. The larger the aperture ratio is, the higher the light utilization rate of the liquid crystal display is. Therefore, the light utilization rate can be improved by increasing the aperture ratio of the pixel, so that the liquid crystal display has high brightness with small power consumption.

[0063] However, as the resolution of the display product is higher and higher, the pixel size is smaller and smaller, and the aperture ratio is smaller and smaller. The factors affecting the aperture ratio include the gate line width, the data line width, the black matrix width and the pixel design structure. In high-resolution products, the pixel pitch is small, and the gate line width, the data line width and the black matrix width have a great influence on the aperture ratio. The limit values of the gate line width and pitch, the data line width and pitch are limited by the production line process and equipment, and have certain limit values and cannot be infinitely reduced. The black matrix width needs to consider the influence on the cell precision and light leakage.

[0064] Some example embodiments of the present disclosure provide a display substrate, the display substrate comprising a plurality of sub-pixels arranged in an array along a first direction and a second direction, the first direction and the second direction intersecting; the display substrate comprising: a substrate substrate; a first conductive layer located on a side of the substrate substrate, the first conductive layer comprising a plurality of data lines and a plurality of electrode lines arranged alternately along the first direction, each of the data lines and the electrode lines extending along the second direction, each column of sub-pixels being located between adjacent data lines and electrode lines; the first conductive layer further comprising a first electrode and a second electrode of a thin film transistor, wherein the data lines are connected to the first electrodes of the thin film transistors, and the second electrodes of the thin film transistors are located between adjacent data lines and electrode lines; a first insulating layer located on a side of the first conductive layer away from the substrate substrate; a second conductive layer located on a side of the first insulating layer away from the substrate substrate, the second conductive layer comprising a common electrode and a plurality of protection electrode blocks, the common electrode comprising a plurality of openings, wherein a footprint of at least one of the protection electrode blocks on the substrate substrate falls within a footprint of at least one of the openings of the common electrode on the substrate substrate; a second insulating layer located on a side of the second conductive layer away from the substrate substrate; and a third conductive layer located on a side of the second insulating layer away from the substrate substrate, the third conductive layer comprising a plurality of pixel electrodes, one pixel electrode being provided in a region where each sub-pixel is located, wherein the pixel electrodes are connected to the protection electrode blocks through first vias, and the pixel electrodes are connected to the second electrodes of the thin film transistors through the first vias. Wherein a footprint of the second electrode of the thin film transistor on the substrate substrate at least partially overlaps with a footprint of the protection electrode block on the substrate substrate; and an overlapping part of the footprints of the second electrode of the thin film transistor and the protection electrode block on the substrate substrate at least partially overlaps with a footprint of the first via on the substrate substrate.

[0065] In the limited wiring space of a high-resolution display substrate, by adopting a half-punching lap joint mode for the second electrode of the thin film transistor and increasing the protection electrode blocks, the wiring area of the second electrode of the thin film transistor can be reduced while avoiding the insulation layer punching through the gate insulation layer, resulting in the pixel electrode being connected to the gate line and causing display defects. At the same time, by adopting a top pixel design and optimizing the wiring design, the black matrix line width can be reduced, the pixel aperture ratio can be effectively improved, the storage capacitance can be effectively improved, and the display effect can be optimized. In addition, the display substrate in the embodiments of the present disclosure can adopt the existing mature process flow, without increasing the production and process cost.

[0066] FIGS. 1-4 show schematic diagrams of a display substrate according to one embodiment of the present disclosure, wherein FIG. 1 is a partial plan view of the display substrate, FIG. 2 is an enlarged view of the dashed box portion of FIG. 1, FIG. 3A is a cross-sectional view taken along line AA’ in FIG. 2, FIG. 3B is a cross-sectional view taken along line BB’ in FIG. 2, and FIG. 4 is a partial plan view of the display substrate.

[0067] As shown in the figure, the display substrate according to one embodiment of the present disclosure can include a substrate 1 and a plurality of sub-pixels P (as shown in FIG. 4) located on the substrate 1. The plurality of sub-pixels P are arranged in an array on the substrate 1, that is, including a plurality of rows of sub-pixels P and a plurality of columns of sub-pixels P. In this article, for the convenience of description, the horizontal direction in FIG. 1 is referred to as the first direction X (row direction), and the vertical direction in FIG. 1 is referred to as the second direction Y (column direction). In FIG. 1, 2 sub-pixels P adjacent in the row direction are schematically shown, which can be referred to as sub-pixel P01 and sub-pixel P02 for the convenience of description.

[0068] Specifically, the display substrate can include a plurality of gate lines GL extending in the row direction X, a plurality of data lines DL extending in the column direction Y, and a plurality of electrode lines CL extending in the column direction. For example, the plurality of data lines DL and the plurality of electrode lines CL are alternately arranged in the row direction, and both the plurality of data lines DL and the plurality of electrode lines CL cross the plurality of gate lines GL, respectively, to define the plurality of sub-pixels P.

[0069] Exemplarily, the data line DL can be connected with at least part of the transistors in the driving circuit, thereby providing a data signal for the corresponding sub-pixel.

[0070] Exemplarily, the electrode line CL is located between two adjacent sub-pixel regions, so that metal traces (data lines DL or electrode lines CL) are provided between every two adjacent columns of sub-pixel regions, which can ensure etching uniformity and improve etching effect during the preparation process.

[0071] In some embodiments, the display substrate includes a common electrode, and the electrode line CL can be connected with the common electrode to provide a common electrode signal.

[0072] Optionally, FIG. 4 shows a partial plan view of the display substrate in FIG. 1, schematically showing more sub-pixels P located on the substrate 1. As shown in FIG. 4, a double gate line driving type display substrate is shown, specifically, the display substrate includes a plurality of gate lines, the gate lines extend along the first direction X, the gate lines are located between two adjacent rows of sub-pixel regions, and two gate lines are provided between each two adjacent rows of sub-pixel regions. For example, the plurality of sub-pixels includes a plurality of rows of sub-pixels located in the i-th row and the i+1-th row respectively, and a plurality of columns of sub-pixels located in the j-th column and the j+1-th column respectively, where i is greater than or equal to 1, and j is greater than or equal to 1. The gate lines include a first gate line GL1 and a second gate line GL2 located between the region of the i-th row of sub-pixels and the region of the i+1-th row of sub-pixels, the first gate line GL1 is connected to the gate electrode of the thin film transistor of the sub-pixel in the i-th row and the j+1-th column, and the second gate line GL2 is connected to the gate electrode of the thin film transistor of the sub-pixel in the i+1-th row and the j-th column. Adjacent sub-pixels P01 and P02 in the row direction X can form a sub-pixel group, and one data line DL is provided between two adjacent sub-pixel groups in the row direction. One electrode line CL is provided between the two sub-pixels P01 and P02 in the sub-pixel group.

[0073] Referring to FIGS. 3A and 3B, the display substrate can further include a common electrode 2 and a pixel electrode 4 provided on the substrate 1. The common electrode 2 is configured to cooperate with the pixel electrode 4 to form an electric field for driving the deflection of liquid crystal molecules, thereby realizing the display of a specific gray scale. Specifically, the display substrate can further include an insulating layer 32 provided on the substrate 1 and located between the common electrode 2 and the pixel electrode 4. For example, the common electrodes 2 in each sub-pixel on the display substrate can be electrically connected to each other, and the pixel electrodes 4 in each sub-pixel on the display substrate can be independent of each other.

[0074] In the embodiments shown in FIGS. 1-4, the common electrode 2, the insulating layer 32 and the pixel electrode 4 are sequentially arranged on the substrate 1 in the direction away from the substrate 1, i.e., the common electrode 2 is below and the pixel electrode 4 is above. For example, the common electrode 2 is a planar electrode, the common electrode 2 in one sub-pixel group can be formed as one integral planar electrode, the orthographic projection of the common electrode 2 in one sub-pixel group on the substrate 1 can cover two sub-pixels P1, P2, and the orthographic projection of the common electrode 2 in one sub-pixel group on the substrate 1 can also cover the orthographic projection of the electrode line CL in one sub-pixel group on the substrate 1. For another example, the pixel electrode 4 is a comb-shaped electrode with multiple slits 42, i.e., the pixel electrode includes multiple pixel electrode strips 41 arranged in the region of the sub-pixel. Exemplarily, the display substrate is designed in the manner of common electrode above and pixel electrode below. In the display substrate with common electrode above and pixel electrode below, the arrangement of the pixel electrode can be similar to the pixel arrangement manner of the display substrate with common electrode below and pixel electrode above in the above-described embodiments. In order to prevent light leakage of the display substrate, the display substrate also adopts the design of arranging a black matrix on the side of the common electrode away from the substrate. The black matrix needs to have sufficient area to cover part of the transistors or signal lines in the driving circuit layer below, such as gate lines, data lines, electrode lines, etc., so as to reduce electrical light leakage.

[0075] Since the common electrode is arranged above the pixel electrode, the spacing distance between the common electrode and the components such as transistors, data lines and electrode lines located on the side of the common electrode close to the substrate is far in the light-emitting direction, and the potential on the common electrode has weak shielding effect on the transistors, data lines and electrode lines below. In this case, in order to prevent electrical light leakage, the width of the black matrix needs to be increased to ensure that the black matrix has sufficient coverage width for at least part of the transistors, data lines and electrode lines below, so as to reduce electrical light leakage. For example, the spacing distance between the boundary of the orthographic projection of the black matrix on the substrate and the boundary of at least part of the corresponding gate line is greater than or equal to 5 microns, so as to ensure sufficient shielding effect and reduce electrical light leakage.

[0076] In the display substrate with common electrode above and pixel electrode below, the design of increasing the wrapping width of the gate line wrapping the active layer in the corresponding transistor can reduce electrical light leakage, reduce the width of the black matrix, and also reduce the leakage current in the transistor of the display substrate under high brightness or high temperature environment.

[0077] FIG. 5A is a partial plan view of a display substrate according to some example embodiments of the present disclosure; FIG. 5B is a cross-sectional view taken along line A1-A1' in FIG. 5A; FIG. 5C is a cross-sectional view taken along line B1-B1' in FIG. 5A; FIG. 5D is a partial plan view of a display substrate according to some other example embodiments of the present disclosure; FIG. 5E is a cross-sectional view taken along line A2-A2' in FIG. 5D; FIG. 5F is a cross-sectional view taken along line B2-B2' in FIG. 5D; FIG. 5G is a partial plan view of a display substrate according to yet other example embodiments of the present disclosure; FIG. 5H is a cross-sectional view taken along line A3-A3' in FIG. 5G; FIG. 51 is a cross-sectional view taken along line B3-B3' in FIG. 5G.

[0078] In some display substrates with common electrodes on top and pixel electrodes on bottom, in combination with reference to FIGS. 5A-5I, the orthogonal projection of the active layer on the substrate falls into the orthogonal projection of the gate line on the substrate, and the boundary of the orthogonal projection of the gate line on the substrate is spaced apart from the boundary of the orthogonal projection of the adjacent corresponding active layer on the substrate by a distance m01 of about 2.75 microns.

[0079] Exemplarily, in combination with reference to FIGS. 5A-5C, the angle between the orthogonal projection of the data line DL or the electrode line CL on the substrate and the orthogonal projection of the gate line GL on the substrate can be about 90°. Exemplarily, the width d01 of the width of a portion of the data line DL or the electrode line CL in the first direction X is about 2.8 microns. The spacing distance M11 between one of the data line DL or the electrode line CL and the pixel electrode 4 can be about 4.22 microns. The common electrode 2 includes a common electrode first sub-portion 201 overlapping the projection of the data line DL or the electrode line CL, and the orthogonal projection of the common electrode first sub-portion 201 on the substrate has a width d10 in the first direction of about 7.4 microns. The common electrode first sub-portion 201 protrudes in the first direction X relative to one of the corresponding data line DL or the electrode line CL by a distance M10 of about 2.55 microns. By increasing the width of the common electrode first sub-portion in the first direction X at the cross line, the yield can be improved. Continuing to refer to FIGS. 5A-5C, the display substrate further includes a black matrix BM. The width of the black matrix BM needs to consider the effects of the precision of the cell and the light leakage. In order to ensure that the black matrix has sufficient light shielding effect, the orthogonal projection of the black matrix on the substrate needs to cover at least a portion of the data line, the electrode line and the gate line. For example, the orthogonal projection of the black matrix BM on the substrate has a width d11 in the first direction of about 4.5 microns and a width d12 in the second direction of about 28.1 microns.

[0080] Exemplarily, the gate line GL includes a widened portion GL11 and a connecting portion GL12. The widened portion GL11 has a width d13 of about 9.1 microns in the second direction Y, and the connecting portion GL12 has a width d14 of about 3 microns in the second direction Y. Exemplarily, the minimum interval distance M12 between two adjacent gate lines in the second direction Y is greater than or equal to 4 microns. The common electrode 2 protrudes from the corresponding gate line by a distance M13 of about 1.55 microns in the second direction Y. The interval distance M14 between the gate line and the corresponding pixel electrode in the second direction is about 2.4 microns. The black matrix BM protrudes from the corresponding gate line widened portion GL11 by a distance M15 of about 5 microns in the second direction. Through the above design, the aperture ratio of the display panel can reach about 44.8%.

[0081] Exemplarily, in combination with reference to FIGS. 5D-5F, the angle between the normal projection of the data line DL or the electrode line CL on the substrate and the normal projection of the gate line GL on the substrate can be greater than 90° or less than 90°. The pixel electrode can be substantially parallel to the data line DL. The interval distance M11 between one of the data line DL or the electrode line CL and the pixel electrode 4 can be between 3.5 microns and 4.22 microns. The common electrode 2 includes a common electrode first sub-portion 201 overlapping with the projection of the data line DL or the electrode line CL, and the normal projection of the common electrode first sub-portion 201 on the substrate has a width d10 of about 6.9 microns in the first direction. The common electrode first sub-portion 201 protrudes from one of the corresponding data line DL or the electrode line CL by a distance M10 of about 2.48 microns in the first direction X. Exemplarily, in order to ensure sufficient light shielding effect of the black matrix, the normal projection of the black matrix BM on the substrate has a width d11 of about 4.5 microns in the first direction and a width d12 of about 28.1 microns in the second direction.

[0082] Exemplarily, the gate line GL includes a widened portion GL11 and a connecting portion GL12. The widened portion GL11 has a width d13 of about 9.1 microns in the second direction Y, and the connecting portion GL12 has a width d14 of about 3 microns in the second direction Y. Exemplarily, the minimum interval distance M12 between two adjacent gate lines in the second direction Y is greater than or equal to 4 microns. The common electrode 2 protrudes from the corresponding gate line by a distance M13 of about 1.55 microns in the second direction Y. The interval distance M14 between the gate line and the corresponding pixel electrode in the second direction is about 2.4 microns. The black matrix BM protrudes from the corresponding gate line widened portion GL11 by a distance M15 of about 5 microns in the second direction. Through the above design, the aperture ratio of the display panel can be between 43.4% and 44.6%.

[0083] Exemplarily, the wrapping width of the gate line on the active layer can be reduced, thereby improving the aperture ratio of the display substrate.

[0084] For a display substrate with low resolution requirement, the space between the adjacent data line DL and the electrode line CL can be increased. For example, referring to FIGS. 5G-5I, the space between the adjacent data line DL and the electrode line CL can be increased, so that the aperture ratio can be improved. For example, the space between one of the data line DL or the electrode line CL and the pixel electrode can be about 4.5 microns. The common electrode includes a common electrode first sub-portion 201 which is overlapped with the data line DL or the electrode line CL in projection, and the width d10 of the common electrode first sub-portion 201 in the first direction on the substrate substrate in the projection is about 6.9 microns. The protruding distance M10 of the common electrode first sub-portion 201 relative to one of the corresponding data line DL or the electrode line CL in the first direction X can be about 3.4 microns. For example, in order to ensure sufficient light shielding effect of the black matrix, the width d11 of the black matrix BM in the first direction on the substrate substrate in the projection is about 4.5 microns, and the width d12 in the second direction is about 28.1 microns.

[0085] For example, the gate line GL includes a widened portion GL11 and a connecting portion GL12, the width d13 of the widened portion GL11 in the second direction Y is about 9.1 microns, and the width d14 of the connecting portion GL12 in the second direction Y is about 3 microns. For example, the minimum space M12 between the adjacent two gate lines in the second direction Y is greater than or equal to 4 microns. The protruding distance M13 of the common electrode 2 relative to the corresponding gate line in the second direction Y is about 1.55 microns. The space M14 between the gate line and the corresponding pixel electrode in the second direction is about 2.4 microns. The protruding distance M15 of the black matrix BM relative to the corresponding gate line widened portion GL11 in the second direction is about 5 microns. Through the above design, the aperture ratio of the display panel can be about 46.5%.

[0086] FIG. 6 is a partial plan view of a display substrate according to some example embodiments of the present disclosure; FIG. 7 shows a partial plan view of a fourth conductive layer in FIG. 6; FIG. 8 shows a partial plan view of a third insulating layer in FIG. 6; FIG. 9 shows a partial plan view of a first conductive layer in FIG. 6; FIG. 10 shows a partial plan view of a second conductive layer in FIG. 6; FIG. 11 shows a plurality of vias in FIG. 6; FIG. 12 shows a partial plan view of a third conductive layer in FIG. 6; FIGS. 13A and 13B are both partial enlarged views of a dashed area S in FIG. 6; FIG. 14 shows a cross-sectional view taken along line CC’ in FIG. 13A; and FIG. 15 shows a cross-sectional view taken along line DD’ in FIG. 13A.

[0087] Exemplarily, referring to FIG. 6, the pixel electrode further includes a first connecting part 411 and a second connecting part 412, the first connecting part 411 is located at one end of the plurality of pixel electrode strips 41 and connected to each of the plurality of pixel electrode strips 41, and the second connecting part 412 is located at the other end of the plurality of pixel electrode strips 41 and connected to each of the plurality of pixel electrode strips 41. The number of the plurality of pixel electrode strips 41 can include 2 pixel electrode strips, 3 pixel electrode strips or more, and FIG. 6 shows that the display substrate includes 2 pixel electrode strips. In some embodiments, the plurality of pixel electrode strips can extend along a third direction Y', wherein the third direction Y' and the second direction Y have a predetermined inclination angle. For example, the plurality of pixel electrode strips 41 can be substantially parallel to the data line DL. In the above display substrate, the planar common electrode 2 and the comb-shaped pixel electrode 4 are stacked on the substrate of the display substrate, and the multi-dimensional electric field is formed by the electric field generated by the edges of the comb-shaped pixel electrode in the same plane and the electric field generated between the comb-shaped pixel electrode layer and the planar common electrode layer, so that all the oriented liquid crystal molecules between the comb-shaped pixel electrodes in the liquid crystal cell and directly above the pixel electrode can rotate to realize the display of each gray scale.

[0088] For example, each sub-pixel P of the display substrate can further include a thin film transistor located on the substrate 1. The thin film transistor can include a gate, a first electrode and a second electrode, for example, the first electrode can be one of a source electrode and a drain electrode, and the second electrode can be the other of the source electrode and the drain electrode. The thin film transistor can further include a gate insulating layer and an active layer.

[0089] In combination with FIG. 4, in the same row of sub-pixels, the thin film transistors of the odd column of sub-pixels are connected to the same gate line, for example, the first gate line GL1, and the thin film transistors of the even column of sub-pixels are connected to the same gate line, for example, the second gate line GL2, and in the adjacent two columns of sub-pixels, the thin film transistors of the adjacent two columns of sub-pixels can be connected to the same data line DL. In operation, the effective signal can be input on the first gate line GL1 and the second gate line GL2 row by row to open the corresponding thin film transistors. Specifically, when the thin film transistors of the odd column of a certain row are opened, the pixel voltage is input to the thin film transistors of the odd column through the data line DL, and the pixel voltage is transmitted to the pixel electrode to perform the display of the corresponding gray scale. When the thin film transistors of the even column of a certain row are opened, the pixel voltage is input to the thin film transistors of the even column through the data line DL, and the pixel voltage is transmitted to the pixel electrode to perform the display of the corresponding gray scale. In the double gate line driving mode, the number of gate lines is doubled, and the number of data lines is reduced by half, which can reduce the cost of the driving IC; at the same time, the charging time is also reduced to half of that in the single gate line driving mode, which will affect the charging rate.

[0090] With the increase of the pixel density of the display substrate, the wiring space of the thin film transistor is getting smaller and smaller. For example, in some embodiments, one of the first and second poles of the thin film transistor is located between the adjacent data line DL and the electrode line CL, for example, referring to FIG. 9, the second pole D1 of the thin film transistor is located between the adjacent data line DL and the electrode line CL. The second pole of the thin film transistor can be located in the same layer as the data line DL, for example, both are located in the first conductive layer. In the pixel driving circuit, the second pole of the thin film transistor usually needs to form an electrical connection with the pixel electrode through a via hole, so as to write the driving signal into the pixel unit. Due to the decrease of the wiring space of the thin film transistor, the metal conductive part where the second pole D1 of the thin film transistor is located also decreases in the running width in the first direction X. However, limited by the process accuracy, for example, the alignment accuracy and the etching accuracy, a certain margin (via hole distance) needs to be ensured in the area where the via hole is formed, so as to prevent the via hole from punching through the insulating layer below the first conductive layer due to the etching deviation of the via hole, and to avoid the connection between the pixel electrode and the gate line to cause display defects.

[0091] Embodiments of the present disclosure provide a half-punching lap joint display substrate, by arranging a protection electrode block in the punching area, the protection electrode block can be used for via hole protection in the etching process, which can prevent the via hole from punching through the insulating layer below the first conductive layer when forming the via hole, and avoid the connection between the pixel electrode and the gate line. The protection electrode block can be located in a different film layer from the second pole of the thin film transistor, so as to fully utilize the vertical space and realize high-resolution display.

[0092] For example, the protection electrode block can be located in the same layer as the common electrode, without the need for additional film layers, which is beneficial to simplify the process.

[0093] For example, referring to FIG. 10, the protection electrode block 120 and the common electrode 2 can be arranged at intervals. For example, the protection electrode block 120 can be half-enclosed by the common electrode 2.

[0094] For example, the protection electrode block can be directly connected with the pixel electrode, and the pixel electrode is connected with other signal lines. For example, in combination with FIGS. 6-15, the display substrate 100 can include: a substrate 1; a first conductive layer 11 located on one side of the substrate, the first conductive layer 11 includes a plurality of data lines DL and electrode lines CL arranged alternately along the first direction X, each data line DL and electrode line CL extends along the second direction Y, and each column of sub-pixels is located between the adjacent data line DL and electrode line CL. The first conductive layer 11 can further include a first pole S1 and a second pole D1 of a thin film transistor, for example, a part of the data line DL can be connected with the first pole area of the thin film transistor to form the first pole S1; the second pole D1 of the thin film transistor is located between the adjacent data line DL and the electrode line CL.

[0095] The display substrate can further include a first insulating layer 31 located on a side of the first conductive layer 11 away from the base substrate 1, and a second conductive layer 12 located on a side of the first insulating layer 31 away from the base substrate 1, the second conductive layer 12 can include the common electrode 2 and a plurality of protective electrode blocks 120. The common electrode 2 can include a plurality of openings 21, wherein a footprint of at least one of the protective electrode blocks 120 on the base substrate falls within a footprint of at least one of the openings 21 of the common electrode 2 on the base substrate.

[0096] The display substrate can further include a second insulating layer 32 located on a side of the second conductive layer 12 away from the base substrate, and a third conductive layer 13 located on a side of the second insulating layer 32 away from the base substrate, the third conductive layer 13 includes a plurality of pixel electrodes 4, for example, one pixel electrode 4 is provided in each region where a sub-pixel is located. Exemplarily, the pixel electrode 4 can be connected with the protective electrode block 120 through a first via hole VH1. The pixel electrode 4 can also be connected with the second electrode D1 of the thin film transistor through the first via hole VH1, so as to realize the half-lap joint connection of the pixel electrode 4 and the second electrode D1 of the thin film transistor. For example, referring to FIG. 13A, a footprint of the second electrode D1 of the thin film transistor on the base substrate at least partially overlaps with a footprint of the protective electrode block 120 on the base substrate. The overlapping part of the footprints of the second electrode D1 of the thin film transistor and the protective electrode block 120 on the base substrate at least partially overlaps with a footprint of the first via hole VH1 on the base substrate. By providing the protective electrode block in the region near the second electrode D1 of the thin film transistor, the protective electrode block can be a transparent conductive film layer, for example, an ITO film layer. When the first via hole is formed, the protective electrode block can block the etching process to the film layer below the protective electrode block, so that the second electrode D1 of the thin film transistor and the protective electrode block 120 can jointly achieve sufficient via hole distance. Since the second electrode D1 of the thin film transistor and the protective electrode block 120 are located in different film layers, sufficient via hole distance can be ensured without increasing the width of the second electrode D1 of the thin film transistor, thereby avoiding the film layer below the second electrode D1 of the thin film transistor from being punched in the via hole etching step, so as to reduce the probability of short circuit between the pixel electrode and the gate line, and facilitate to improve the yield of the display substrate.

[0097] Exemplarily, referring to FIG. 14, the first via VH1 can include a first sub-via VH11 and a second sub-via VH12, wherein the first sub-via VH11 and the second sub-via VH12 are adjacently arranged in the first direction X. The first sub-via VH1 penetrates the first insulating layer 31 and the second insulating layer 32, and the pixel electrode 4 is connected to the second electrode D1 of the thin film transistor through the first sub-via VH11. The second sub-via VH2 penetrates the second insulating layer 32, and the pixel electrode 4 is connected to the protection electrode block 120 through the second sub-via VH2. The first via VH1 adopts a half-lap joint mode, and a part of the first via VH1 is located above the protection electrode block, so that a part of the first via VH1 is cut off in the protection electrode block area when the via is formed. For example, a specific via etching process can be used, and an etching process that can etch the insulating layer but cannot etch ITO is selected. In this way, the first sub-via VH11 penetrating the first insulating layer 31 and the second insulating layer 32 and the second sub-via VH12 penetrating the second insulating layer 32 can be formed in the process of forming the first via VH1. The pixel electrode 4 can be electrically connected to the second electrode D1 of the thin film transistor through the first sub-via VH11. The protection electrode block 120 makes the second sub-via VH12 cut off at the surface of the protection electrode block away from the substrate, so as to prevent the insulating layer GI below the second electrode D1 of the thin film transistor from being etched due to factors such as alignment accuracy deviation or etching accuracy deviation in the process of forming the first via VH1, so as to prevent the pixel electrode from being electrically connected to the gate line GL below the second electrode D1 of the thin film transistor, and causing display defects.

[0098] Exemplarily, in some embodiments of the present disclosure, referring to FIG. 14, the first sub-via VH11 has a first width M1 in the first direction, the second sub-via VH12 has a second width M2 in the first direction, and the first width M1 is smaller than the second width M2. In a limited wiring space, by setting the first width of the first sub-via VH11 in the first direction to be small, the second electrode D1 of the thin film transistor can have sufficient via passing distance, so as to prevent the first via from crossing the edge of the second electrode D1 of the thin film transistor due to process deviation and penetrating the insulating layer below the second electrode D1 of the thin film transistor.

[0099] Exemplarily, in some embodiments of the present disclosure, with reference to FIG. 13A, the orthogonal projection of the second electrode D1 of the thin film transistor on the substrate substrate includes a first side edge L1 and a second side edge L2 extending along the second direction Y. The orthogonal projection of the first via VH1 on the substrate substrate includes a third side edge L3 and a fourth side edge L4 extending along the second direction Y. The orthogonal projection of the protection electrode block 120 on the substrate substrate includes a fifth side edge L5 and a sixth side edge L6 extending along the second direction Y. The first side edge L1, the third side edge L3, the fifth side edge L5, the second side edge L2, the fourth side edge L4 and the sixth side edge L6 are sequentially and spaced apart in the first direction X. In order to ensure that the second electrode D1 of the thin film transistor and the protection electrode block 120 under the first via VH1 have sufficient via distance, a first preset distance d1 is provided between the first side edge L1 and the third side edge L3, for example, the first preset distance d1 can be greater than or equal to 9.6 um. By designing the via distance between the first side edge L1 of the second electrode D1 of the thin film transistor and the third side edge L3 of the first via VH1 to be large, it can be ensured that the orthogonal projection of the third side edge L3 of the first via on the substrate substrate still falls within the orthogonal projection of the second electrode D1 of the thin film transistor on the substrate substrate in the case of process errors such as etching deviation or alignment deviation, thereby avoiding the first via from penetrating the insulating layer under the second electrode D1 of the thin film transistor, causing the pixel electrode to be connected to the gate line.

[0100] Exemplarily, in some embodiments of the present disclosure, continuing to refer to FIG. 13A, a second preset distance d2 is provided between the fifth side edge L5 and the second side edge L2. In the first direction X, the second electrode D1 of the thin film transistor and the protection electrode block 120 include an overlapping portion, and the width of the overlapping portion is the second preset distance d2. By designing the width of the overlapping portion between the second electrode D1 of the thin film transistor and the protection electrode block 120 to be large, after the processes of etching the second electrode D1 of the thin film transistor, etching the protection electrode block 120, and aligning the second electrode D1 of the thin film transistor and the protection electrode block 120 are completed, the second electrode D1 of the thin film transistor and the protection electrode block 120 still have an overlapping portion, which can avoid the formation of a blank area without the protection electrode block and the second electrode D1 of the thin film transistor between the second electrode D1 of the thin film transistor and the protection electrode block 120 due to process deviation, and can prevent the via from penetrating the insulating layer under the second electrode D1 of the thin film transistor, causing the pixel electrode to be connected to the gate line.

[0101] Exemplarily, a third preset distance d3 is provided between the fourth side L4 and the sixth side L6. The third preset distance d3 is a protection electrode block over via distance. By designing the over via distance between the sixth side L6 of the protection electrode block 120 and the fourth side L4 of the first via VH1 to be large, it can be ensured that the orthographic projection of the fourth side L4 of the first via on the substrate substrate falls within the orthographic projection of the protection electrode block 120 on the substrate substrate, so that a part of the first via above the protection electrode block only penetrates the second insulating layer 32, thereby preventing the via from penetrating the insulating layer below the second electrode D1 of the thin film transistor, causing the pixel electrode to be connected to the gate line. For example, the third preset distance d3 can be greater than or equal to 9.6 um.

[0102] FIG. 16 is a SEM image of a display substrate in a first via region along a first direction according to some exemplary embodiments of the present disclosure.

[0103] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 14 and 16, the first insulating layer 31 includes a first portion 311 adjacent to the first sub-via VH11 and the orthographic projection of the first portion 311 on the substrate substrate does not overlap with the orthographic projection of the second sub-via VH12 on the substrate substrate. The first portion 311 includes a first side wall N1 close to the first sub-via VH11, and the first side wall N1 has a first slope angle a1. The second insulating layer 32 includes a second portion 321 adjacent to the first sub-via VH11 and the orthographic projection of the second portion 321 on the substrate substrate does not overlap with the orthographic projection of the second sub-via VH12 on the substrate substrate. The second portion 321 includes a second side wall N2 close to the first sub-via VH11, and the second side wall N2 has a second slope angle a2, and the first slope angle a1 is greater than the second slope angle a2. For example, the first slope angle a1 is about 67°, and the second slope angle a2 is about 42°.

[0104] Exemplarily, continuing to refer to FIGS. 14 and 16, the first insulating layer 31 further comprises a third portion 313 adjacent to the first sub-via VH11, and a projection of the third portion 313 on the substrate falls within a projection of the second electrode D1 of the thin film transistor on the substrate, and a projection of the third portion 313 on the substrate falls within a projection of the protective electrode block 120 on the substrate. The third portion 313 comprises a third side wall N3 away from the first sub-via VH11, and the third side wall N3 has a third slope angle a3. The protective electrode block 120 comprises a fourth portion 1204, and a projection of the fourth portion 1204 on the substrate falls within a projection of the third portion 313 of the first insulating layer on the substrate. The fourth portion 1204 of the protective electrode block 120 comprises a fourth side wall N4 away from the first sub-via VH11, and the fourth side wall N4 has a fourth slope angle a4. The third slope angle a3 is greater than the fourth slope angle a4. In some embodiments, the third slope angle a3 can be greater than or equal to twice the fourth slope angle a4. For example, the third slope angle a3 is about 52°, and the fourth slope angle is about 26°.

[0105] Exemplarily, continuing to refer to FIGS. 14 and 16, the second insulating layer 32 further comprises a fifth portion 325 adjacent to the second sub-via VH12, and a projection of the fifth portion 325 on the substrate at least partially overlaps with a projection of the protective electrode block 120 on the substrate. The fifth portion 325 comprises a fifth side wall N5 close to the second sub-via VH12, and the fifth side wall N5 has a fifth slope angle a5. The fifth slope angle a5 is greater than or equal to 30°. For example, the fifth slope angle a5 is about 38°.

[0106] By optimizing the etching process, the inclination angles of the side walls of the portions of the first insulating layer, the second insulating layer and the protective electrode block in the process of forming the first via can be adjusted to ensure that the inclination angle of the side wall of the film layer close to the substrate is greater than the inclination angle of the side wall of the film layer away from the substrate, so that in the area where the first via is located, the film layer close to the substrate, for example, the first insulating layer, can provide support for the film layer away from the substrate, for example, the film layer where the protective electrode block is located or the second insulating layer, which is conducive to improving the etching precision of the via and reducing the probability of over-etching of the via.

[0107] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 7, 8, 13A, 13B and 14, the display substrate can further include a third insulating layer GI located on the first conductive layer 11 close to the substrate substrate, which can be a gate insulating layer. The display substrate can further include a fourth conductive layer 14 located on the third insulating layer GI close to the substrate substrate, and a semiconductor layer 15 located between the third insulating layer 33 and the first conductive layer 11. The active layer ACT of the thin film transistor can be located in the semiconductor layer 15. The portion of the fourth conductive layer 14 overlapping with the active layer ACT is the gate electrode G1 of the thin film transistor, and the fourth conductive layer 14 further includes a gate line GL connected with the gate electrode G1. The gate line GL includes a widened portion GL11 and a connecting portion GL12, the gate electrode G1 is located in the widened portion GL11, and the orthographic projection of the second electrode D1 of the thin film transistor on the substrate substrate at least partially overlaps with the orthographic projection of the widened portion GL11 on the substrate substrate. The orthographic projection of the second electrode D1 of the thin film transistor on the substrate substrate does not overlap with the orthographic projection of the connecting portion GL12 on the substrate substrate. By designing the projection of the second electrode D1 of the thin film transistor on the substrate substrate to fall within the orthographic projection of the widened portion GL11 on the substrate substrate, the area of the second electrode D1 of the thin film transistor and the area of the gate electrode G1 can be increased, and the transmission performance of the thin film transistor can be improved.

[0108] Exemplarily, in some embodiments of the present disclosure, in combination with reference to FIGS. 7, 8, 13A, 13B and 14, the orthographic projection of the protective electrode block 120 on the substrate substrate at least partially overlaps with the orthographic projection of the widened portion GL11 on the substrate substrate. The orthographic projection of the protective electrode block 120 on the substrate substrate at least partially overlaps with the orthographic projection of the connecting portion GL12 on the substrate substrate.

[0109] Referring to FIG. 6, the first connecting portion 411 is connected with the second electrode D1 of the corresponding thin film transistor through the first via hole VH1, and the orthographic projection of the second connecting portion 412 on the substrate substrate at least partially overlaps with the orthographic projection of the gate line GL on the substrate substrate.

[0110] Exemplarily, in combination with reference to FIGS. 13B and 15, the first via hole VH1 further includes a seventh side L7 extending along the first direction X. For example, the seventh side L7 in the ith row of sub-pixels is located between the first gate line GL1 and the second gate line GL2, and a fourth preset distance d4 is provided between the seventh side L7 and the second gate line GL2. By optimizing the fourth preset distance d4, it can be ensured that the reserved distance between the seventh side L7 of the first via hole VH1 and the adjacent gate line is large enough, and the via hole can be prevented from being connected to the adjacent gate line.

[0111] The first via VH1 further includes an eighth side L8 extending along the first direction, a projection of the eighth side L8 on the substrate substrate falls within a projection of the gate line on the substrate substrate. The protection electrode block 120 includes a ninth side L9 extending along the first direction, a projection of the ninth side L9 on the substrate substrate at least partially overlaps with a projection of the widened part GL11 of the gate line on the substrate substrate. A fifth preset distance d5 is provided between the eighth side L8 and the ninth side L9. By designing the over-via distance of the electrode protection block in the second direction, it can be avoided that the via exceeds the range of the electrode protection block, and the via is connected to the gate line.

[0112] A projection of the protection electrode block 120 on the substrate substrate at least partially overlaps with a projection of the gate line GL on the substrate substrate. Among them, the protection electrode block includes a protruding part 1201 protruding relative to the gate line in the second direction, the protruding part 1201 is located between two adjacent gate lines, and the protruding part 1201 has a first protruding distance d6 in the second direction Y. By designing the protection electrode block to protrude relative to the gate line in the second direction, a part of the side of the gate line is covered, which can ensure that the via is punched on the protection electrode block and not on the gate line, and can prevent the pixel electrode from being connected to the gate line.

[0113] Exemplarily, in some embodiments of the present disclosure, continuing to combine with reference to FIG. 13B and FIG. 15, the first connecting part 411 in the pixel electrode includes a tenth side L10 extending along the first direction, and a seventh preset distance d7 is provided between the tenth side L10 and the seventh side L7 of the first via VH1. The seventh preset distance d7 can be the over-via distance of the pixel electrode, which can ensure that the pixel electrode covers the via and the reliability of the pixel electrode and the second electrode of the thin film transistor.

[0114] Exemplarily, in the embodiments of the present disclosure, referring to FIG. 6, the display substrate can include a first sub-pixel P1 located in the i-th row and the j-th column, a second sub-pixel P2 located in the i-th row and the j+1-th column, and a third sub-pixel P3 located in the i-th row and the j+2-th column, wherein the second sub-pixel P2 includes a second sub-pixel electrode 42. The display substrate further includes a first data line DL1 located between the j-th column of sub-pixels and the j+1-th column of sub-pixels, and a first electrode line CL1 located between the j+1-th column of sub-pixels and the j+2-th column of sub-pixels, and a projection of the second sub-pixel electrode 42 on the substrate substrate at least partially overlaps with a projection of the first electrode line CL1 on the substrate substrate.

[0115] The pixel electrode is located in the third conductive layer. By adopting the top pixel design, in the direction perpendicular to the substrate substrate, the pixel electrode is farther away from the first conductive layer where the source and drain of the thin film transistor are located, and the projection of the pixel electrode on the substrate substrate can partially overlap with the projection of at least one of the data line or the electrode line on the substrate substrate, which is beneficial to improve the storage capacitance in the thin film transistor and optimize the display effect.

[0116] FIG. 17 is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure.

[0117] Exemplarily, in some embodiments of the present disclosure, referring to FIG. 17, the data line DL includes a main body part DL10 and a connecting part DL20. The connecting part DL20 is connected with the first electrode S1 of the thin film transistor. The connecting part DL20 extends substantially along the second direction Y, and the connecting part DL20 can share a part of the conductive part with the main body part DL10. The connecting part DL20 has a third width M3 in the first direction X, and the main body part DL10 has a fourth width M4 in the first direction X, and the ratio of the third width M3 to the fourth width M4 is between 0.8-1.2. In some embodiments, the orthographic projection of the connecting part DL20 on the substrate can substantially overlap with the orthographic projection of the main body part DL10 on the substrate. Such design can reduce the maximum width of the data line in the first direction, and can reserve more space for the second electrode layout of the thin film transistor, which is conducive to realizing high-resolution display design.

[0118] FIG. 18 is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure.

[0119] Exemplarily, in some embodiments of the present disclosure, referring to FIG. 18, the layout space between adjacent data lines and electrode lines is large, and the design of the data line can be more flexible. For example, the data line DL includes a main body part DL10 and a connecting part DL20, and the connecting part DL20 is connected with the first electrode S1 of the thin film transistor. The connecting part DL20 protrudes from the main body part DL10 by a second protruding distance d8 in the first direction X, and the main body part DL10 has a fourth width M4 in the first direction X, and the second protruding distance d8 is greater than the fourth width M4. In a lower-resolution display substrate, the layout space between the data line and the electrode line is larger, and the design of the connecting part of the data line as a structure protruding along the first direction can make full use of the layout space and improve the reliability of data transmission.

[0120] FIG. 19A is a cross-sectional view of a display substrate according to some embodiments of the present disclosure taken along line EE’ in FIG. 17; FIG. 19B is a cross-sectional view of a display substrate according to some embodiments of the present disclosure taken along line FF’ in FIG. 17; FIG. 19C is a cross-sectional view of a display substrate according to some embodiments of the present disclosure taken along line GG’ in FIG. 18; and FIG. 19D is a cross-sectional view of a display substrate according to some embodiments of the present disclosure taken along line HH’ in FIG. 18.

[0121] For example, in some embodiments of the present disclosure, in combination with reference to FIGS. 6, 7, 10, 13B and 19A-19D, the projection of the common electrode 2 on the substrate substrate at least partially overlaps with the projection of the gate line GL on the substrate substrate. For example, the display substrate includes a plurality of gate lines GL extending along the first direction X. The gate line GL is located between two adjacent rows of sub-pixel regions, and the gate line includes a widened portion GL11 and a connecting portion GL12. Two gate lines are provided between each adjacent two rows of sub-pixel regions, for example, a plurality of sub-pixels include a plurality of rows of sub-pixels located in the i-th row and the i+1-th row, respectively, where i is greater than or equal to 1. The gate line includes a first gate line GL1 and a second gate line GL2 located between the region of the i-th row of sub-pixels and the region of the i+1-th row of sub-pixels. The projection of the common electrode 2 on the substrate substrate at least partially overlaps with the projection of the widened portion GL11 of the first gate line GL1 on the substrate substrate. For example, the overlapping portion of the projection of the common electrode 2 and the widened portion GL11 of the first gate line GL1 has a first overlap width M5 in the second direction Y, and the first overlap width M5 is greater than or equal to 0.85 microns.

[0122] For example, the projection of the common electrode 2 on the substrate substrate at least partially overlaps with the projection of the connecting portion GL12 of the second gate line GL2 on the substrate substrate. The overlapping portion of the projection of the common electrode 2 and the connecting portion GL12 of the second gate line GL2 has a second overlap width M6 in the second direction Y, and the second overlap width M6 is greater than or equal to 0.5 microns. The common electrode is located on the side of the pixel electrode close to the substrate substrate, so the spacing distance of the common electrode from the underlying transistor, gate line, data line, electrode line and the like in the light emitting direction is small, and the potential of the common electrode has a good shielding effect on the signal fluctuation in the transistor, gate line, data line and electrode line and the like. Since the potential of the common electrode can shield the influence of the signal in the gate line on the pixel unit, the more the overlapping portion of the common electrode and the gate line, the more significant the shielding effect of the common electrode. The wiring design in the second direction can be more compact. The display substrate also includes a black matrix BM, and the width of the black matrix BM needs to consider the influence on the sealing accuracy and light leakage. The better the shielding effect of the common electrode on the gate line signal, the smaller the wiring width of the pixel driving circuit in the second direction, and accordingly the width of the black matrix BM is also smaller, thereby reducing the area ratio of the non-light-transmitting area in the display substrate, which is conducive to improving the aperture ratio of the display substrate and improving the display effect of the display substrate. For example, the boundary of the projection of the black matrix on the substrate substrate is spaced from the boundary of at least a portion of the corresponding gate line by a distance M15 of about 3.9 microns, thereby ensuring sufficient shielding effect and reducing electrical light leakage. Compared with 5 microns in the above-mentioned embodiments, the spacing distance between the boundary of the black matrix and the boundary of the corresponding gate line can be reduced, for example, from 5 microns to 3.9 microns, thereby reducing the overall width of the black matrix and improving the aperture ratio of the display panel.

[0123] For example, referring to FIGS. 17, 19A and 19B, the width d01 of one of the data line DL or the electrode line CL in the first direction is about 2.8 microns. The spacing distance M12 of adjacent gate lines in the second direction Y is about 4 microns. The spacing distance M16 of adjacent pixel electrodes 4 in the first direction is about 9.36 microns. The spacing distance M11 between one of the data line DL or the electrode line CL and the pixel electrode 4 can be about 3.28 microns. The width d20 of the orthogonal projection of the electrode protection block 120 on the substrate in the second direction Y is about 5.75 microns. The spacing distance d30 of the electrode protection block 120 and the adjacent common electrode 2 in the second direction Y is about 4 microns. For example, in order to ensure sufficient light shielding effect of the black matrix, the width d11 of the orthogonal projection of the black matrix BM on the substrate in the first direction is about 4.5 microns, and the width d12 in the second direction is about 25.1 microns. By optimizing the pixel arrangement and reducing the width of the black matrix, the aperture ratio of the display panel in the example embodiment of the present disclosure can reach 45.9% to 47.3%.

[0124] Compared with the display substrate with the pixel electrode below and the common electrode above, in the display substrate with the pixel electrode above and the common electrode below combined with the electrode protection block in the example embodiment of the present disclosure, the width of the black matrix BM in the second direction can be reduced, for example, from 28.1 microns to 25.1 microns, so that the aperture ratio of the display panel can be improved, for example, from 44.6% to 47.3%, and the display effect can be improved.

[0125] In some display substrates with low pixel density, the wiring space between adjacent data lines and electrode lines is large. By optimizing the pixel wiring design, the aperture ratio of the display panel can be further improved.

[0126] For example, referring to FIGS. 19C and 19D, the spacing distance M11 between one of the data line DL or the electrode line CL and the pixel electrode can be about 3.21 microns. The width d20 of the orthogonal projection of the electrode protection block 120 on the substrate in the second direction Y is about 6.45 microns. The spacing distance d30 of the electrode protection block 120 and the adjacent common electrode 2 in the second direction Y is about 3.8 microns. For example, in order to ensure sufficient light shielding effect of the black matrix, the width d11 of the orthogonal projection of the black matrix BM on the substrate in the first direction is about 4.5 microns, and the width d12 in the second direction is about 25.1 microns. By optimizing the pixel arrangement and reducing the width of the black matrix, the aperture ratio of the display panel in the example embodiment of the present disclosure can reach 54.5%.

[0127] Compared with the display substrate with the pixel electrode below and the common electrode above, in the display substrate with the pixel electrode above and the common electrode below combined with the electrode protection block in the embodiments of the present disclosure, the width of the black matrix BM in the second direction can be reduced, for example, from 28.1 microns to 25.1 microns, at the same pixel density. Thus, the aperture ratio of the display panel can be improved, for example, from 46.5% to 54.5%, and the display effect is improved. FIG. 20 is a structural schematic diagram of a display device provided according to some embodiments of the present disclosure.

[0128] Optionally, the embodiments of the present disclosure further provide a display panel. Referring to FIG. 20, the display panel 200 can include the display substrate 100 described above.

[0129] FIG. 21 is a structural schematic diagram of a display device provided according to some embodiments of the present disclosure.

[0130] Optionally, the embodiments of the present disclosure further provide a display device. Referring to FIG. 21, the display device 300 can include the display substrate 100 or the display panel 200 described above. The display device can include, but is not limited to, electronic paper, mobile phones, tablet computers, displays, notebook computers, digital photo frames, navigation devices, and any product or component with display function. It should be understood that the display device has the same beneficial effects as the display substrate provided in the foregoing embodiments.

[0131] Although some embodiments of the general concept of the present disclosure have been shown and described, those of ordinary skill in the art will understand that changes can be made in these embodiments without departing from the principles and spirit of the general concept of the present disclosure, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, characterized in that, The display substrate includes a plurality of sub-pixels arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect. The display substrate includes: Substrate; A first conductive layer is located on one side of the substrate. The first conductive layer includes multiple data lines and electrode lines arranged alternately along a first direction. Each data line and electrode line extends along a second direction. Each column of sub-pixels is located between adjacent data lines and electrode lines. The first conductive layer also includes a first electrode and a second electrode of a thin-film transistor, wherein the data lines are connected to the first electrode of the thin-film transistor, and the second electrode of the thin-film transistor is located between adjacent data lines and electrode lines. A first insulating layer is located on the side of the first conductive layer away from the substrate. The second conductive layer is located on the side of the first insulating layer away from the substrate. The second conductive layer includes a common electrode and a plurality of protective electrode blocks. The common electrode includes a plurality of openings, wherein at least one of the protective electrode blocks has its orthographic projection on the substrate falling within the orthographic projection of at least one opening of the common electrode on the substrate. A second insulating layer is located on the side of the second conductive layer away from the substrate; and A third conductive layer is located on the side of the second insulating layer away from the substrate. The third conductive layer includes a plurality of pixel electrodes, one of which is disposed within the region of each sub-pixel. The pixel electrodes are connected to the protective electrode block via a first via and to the second electrode of the thin-film transistor via the first via. Wherein, the orthographic projection of the second electrode of the thin-film transistor on the substrate at least partially overlaps with the orthographic projection of the protective electrode block on the substrate; The overlapping portion of the orthographic projections of the second electrode of the thin-film transistor and the protective electrode block on the substrate at least partially overlaps with the orthographic projection of the first via on the substrate.

2. The display substrate according to claim 1, wherein, The first via includes a first sub-via and a second sub-via, wherein the first sub-via and the second sub-via are arranged adjacent to each other in a first direction; The first sub-via penetrates the first insulating layer and the second insulating layer, and the pixel electrode is connected to the second electrode of the thin-film transistor through the first sub-via; The second sub-via penetrates the second insulating layer, and the pixel electrode is connected to the protective electrode block through the second sub-via.

3. The display substrate according to claim 2, wherein, The first sub-via has a first width in a first direction, and the second sub-via has a second width in a first direction, wherein the first width is smaller than the second width.

4. The display substrate according to any one of claims 1-3, wherein, The orthogonal projection of the second electrode of the thin-film transistor onto the substrate includes a first side and a second side extending along a second direction; The orthographic projection of the first via onto the substrate includes a third side and a fourth side extending along the second direction. The orthographic projection of the protective electrode block onto the substrate includes a fifth side and a sixth side extending along the second direction, wherein, The first side, the third side, the fifth side, the second side, the fourth side, and the sixth side are arranged at intervals in a first direction.

5. The display substrate according to claim 4, wherein, A first preset distance is provided between the first side and the third side.

6. The display substrate according to claim 4 or 5, wherein, A second preset distance is provided between the fifth side and the second side.

7. The display substrate according to any one of claims 4-6, wherein, A third preset distance is provided between the fourth side and the sixth side.

8. The display substrate according to claim 2, wherein, The first insulating layer includes a first portion, which is adjacent to the first sub-via and the orthographic projection of the first portion on the substrate does not overlap with the orthographic projection of the second sub-via on the substrate. The first portion includes a first sidewall near the first sub-via, and the first sidewall has a first slope angle. The second insulating layer includes a second portion adjacent to the first sub-via, wherein the orthographic projection of the second portion on the substrate does not overlap with the orthographic projection of the second sub-via on the substrate. The second portion includes a second sidewall adjacent to the first sub-via, the second sidewall having a second slope angle. Wherein, the first slope angle is greater than the second slope angle.

9. The display substrate according to claim 8, wherein, The first insulating layer further includes a third portion, which is adjacent to the first sub-via, and the orthographic projection of the third portion on the substrate falls within the orthographic projection of the second electrode of the thin film transistor on the substrate, and the orthographic projection of the third portion on the substrate falls within the orthographic projection of the protective electrode block on the substrate, wherein the third portion includes a third sidewall away from the first sub-via, and the third sidewall has a third slope angle. The protective electrode block includes a fourth portion, the orthographic projection of which falls within the orthographic projection of the third portion of the first insulating layer on the substrate. The fourth portion of the protective electrode block includes a fourth sidewall away from the first sub-via, the fourth sidewall having a fourth slope angle. Wherein, the third slope angle is greater than or equal to twice the fourth slope angle.

10. The display substrate according to claim 9, wherein, The second insulating layer further includes a fifth portion, which is adjacent to the second sub-via and whose orthographic projection on the substrate at least partially overlaps with the orthographic projection of the protective electrode block on the substrate. The fifth portion includes a fifth sidewall near the second sub-via, the fifth sidewall having a fifth slope angle greater than or equal to 30°.

11. The display substrate according to any one of claims 1-10, wherein, The display substrate further includes: a third insulating layer located on the side of the first conductive layer near the substrate; and a fourth conductive layer located on the side of the third insulating layer near the substrate, the fourth conductive layer including the gate electrode of the thin film transistor and a gate line connected to the gate electrode, the gate line including a widened portion and a connecting portion, the gate electrode being located in the widened portion, the orthographic projection of the second electrode of the thin film transistor on the substrate at least partially overlapping the orthographic projection of the widened portion on the substrate; and the orthographic projection of the second electrode of the thin film transistor on the substrate not overlapping the orthographic projection of the connecting portion on the substrate.

12. The display substrate according to claim 11, wherein, The orthographic projection of the protective electrode block on the substrate at least partially overlaps with the orthographic projection of the widened portion on the substrate; The orthographic projection of the protective electrode block on the substrate at least partially overlaps with the orthographic projection of the connecting portion on the substrate.

13. The display substrate according to any one of claims 1-12, wherein, The display substrate includes multiple gate lines that extend along the first direction and are located between two adjacent rows of sub-pixel regions. The pixel electrode includes a plurality of pixel electrode strips located in the region where the sub-pixel is located and arranged at intervals. The pixel electrode also includes a first connecting portion and a second connecting portion. The first connecting portion is located at one end of the plurality of pixel electrode strips and is connected to all of the plurality of pixel electrode strips. The second connecting portion is located at the other end of the plurality of pixel electrode strips and is connected to all of the plurality of pixel electrode strips. The first connecting portion is connected to the second electrode of the corresponding thin film transistor through the first via. The orthographic projection of the second connecting portion on the substrate overlaps at least partially with the orthographic projection of the gate line on the corresponding side on the substrate.

14. The display substrate according to any one of claims 1-12, wherein, The display substrate includes multiple gate lines, which extend along the first direction and are located between two adjacent rows of sub-pixel regions. Two gate lines are provided between each two adjacent rows of sub-pixel regions. The plurality of sub-pixels includes multiple rows of sub-pixels located in the i-th row and the (i+1)-th row, and multiple columns of sub-pixels located in the j-th column and the (j+1)-th column, where i is greater than or equal to 1, j is greater than or equal to 1, and so on. The gate line includes a first gate line and a second gate line located between the region where the sub-pixel in the i-th row is located and the region where the sub-pixel in the (i+1)-th row is located. The first gate line is connected to the gate electrode of the thin-film transistor of the sub-pixel in the i-th row and (j+1)-th column. The second gate line is connected to the gate electrode of the thin-film transistor of the sub-pixel in the (i+1)-th row and (j)-th column.

15. The display substrate according to claim 14, wherein, The first via includes a seventh side extending along a first direction; The seventh side of the i-th row of sub-pixels is located between the first gate line and the second gate line, and a fourth preset distance is provided between the seventh side and the second gate line.

16. The display substrate according to claim 14 or 15, wherein, The first via also includes an eighth side extending along a first direction, the orthographic projection of the eighth side on the substrate falling within the orthographic projection of the gate line on the substrate; The protective electrode block includes a ninth side extending along a first direction, the orthographic projection of the ninth side onto the substrate at least partially overlapping the orthographic projection of the widened portion of the gate line onto the substrate. A fifth preset distance is provided between the eighth side and the ninth side.

17. The display substrate according to any one of claims 14-16, wherein, The orthographic projection of the protective electrode block on the substrate at least partially overlaps with the orthographic projection of the gate line on the substrate, wherein the protective electrode block includes a protrusion that protrudes relative to the gate line in a second direction, the protrusion being located between two adjacent gate lines, wherein the protrusion has a first protrusion distance in the second direction.

18. The display substrate according to any one of claims 1-17, wherein, The display substrate includes a first sub-pixel located in the i-th row and j-th column, a second sub-pixel located in the i-th row and j+1-th column, and a third sub-pixel located in the i-th row and j+2-th column, wherein the second sub-pixel includes a second sub-pixel electrode; The display substrate further includes a first data line located between the j-th column sub-pixel and the (j+1)-th column sub-pixel, and a first electrode line located between the (j+1)-th column sub-pixel and the (j+2)-th column sub-pixel. Wherein, the orthographic projection of the second sub-pixel electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode line on the substrate.

19. The display substrate according to any one of claims 1-18, wherein, The data line includes a main body and a connecting portion. The connecting portion is connected to a first electrode of the thin-film transistor. The connecting portion extends along a second direction. The orthographic projection of the connecting portion on the substrate at least partially overlaps with the orthographic projection of the main body on the substrate. The connecting portion has a third width in a first direction, and the main body has a fourth width in the first direction. The ratio of the third width to the fourth width is between 0.8 and 1.

2.

20. The display substrate according to any one of claims 1-18, wherein, The data line includes a main body and a connecting part. The connecting part is connected to the first electrode of the thin-film transistor. The connecting part protrudes a second distance from the main body in a first direction. The main body has a fourth width in the first direction. The second protrusion distance is greater than the fourth width.

21. The display substrate according to any one of claims 13-17, wherein, The orthographic projection of the common electrode on the substrate at least partially overlaps with the orthographic projection of the gate line on the substrate.

22. The display substrate according to any one of claims 1-12, wherein, The display substrate includes multiple gate lines extending along the first direction. The gate lines are located between two adjacent rows of sub-pixel regions. Each gate line includes a widened portion and a connecting portion. Two gate lines are provided between each two adjacent rows of sub-pixel regions. The plurality of sub-pixels includes multiple rows of sub-pixels located in the i-th row and the (i+1)-th row, respectively, where i is greater than or equal to 1. The gate line includes a first gate line and a second gate line located between the regions where the sub-pixels in the i-th row and the regions where the sub-pixels in the (i+1)-th row are located. Wherein, the orthographic projection of the common electrode on the substrate and the orthographic projection of the widened portion of the first gate line on the substrate at least partially overlap, and the overlapping portion of the projections of the common electrode and the widened portion of the first gate line has a first overlap width in a second direction, the first overlap width being greater than or equal to 0.85 micrometers.

23. The display substrate according to claim 22, wherein, The orthographic projection of the common electrode on the substrate and the orthographic projection of the connection portion of the second gate line on the substrate at least partially overlap, and the overlapping portion of the projections of the common electrode and the connection portion of the second gate line has a second overlap width in a second direction, the second overlap width being greater than or equal to 0.5 micrometers.

24. A display panel, wherein, The display panel includes a display substrate as described in any one of claims 1-23.

25. A display device, wherein, The display device includes a display substrate as described in any one of claims 1-23 or a display panel as described in claim 24.

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