Display substrate and preparation method therefor, and display apparatus

Abstract

A display substrate and a preparation method therefor, and a display apparatus. The display substrate comprises: a base (20) and a plurality of transistors. Each transistor comprises: a gate electrode (12), an active layer (11), a first electrode (13) and a second electrode (14). The active layer comprises: a channel portion (AR1), a first electrode connection portion (AR2), a second electrode connection portion (AR3), a first auxiliary portion (AR4) and a second auxiliary portion (AR5), wherein the first auxiliary portion (AR4) is separately connected to the channel portion (AR1) and the first electrode connection portion (AR2), and the second auxiliary portion (AR5) is separately connected to the channel portion (AR1) and the second electrode connection portion (AR3); orthographic projections of the channel portion (AR1) and the gate electrode (12) on the base (20) overlap; at least part of the first electrode connection portion (AR2) is electrically connected to the first electrode (13), and at least part of the second electrode connection portion (AR3) is electrically connected to the second electrode (14); and at least two of the channel portion (AR1), the first electrode connection portion (AR2), the second electrode connection portion (AR3), the first auxiliary portion (AR4) and the second auxiliary portion (AR5) have different thicknesses.

Description

Display substrate and its preparation method, display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, specifically to a display substrate and its preparation method, and a display device. Background Technology

[0002] In recent years, flat panel displays, such as thin film transistor liquid crystal displays (TFT-LCD) and active matrix organic light emitting diode displays (AMOLED), have been widely used in electronic products such as televisions and mobile phones due to their advantages of light weight, thinness and low power consumption.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure also provides a display substrate, comprising: a substrate and a plurality of transistors disposed on the substrate, the transistors comprising: a gate, an active layer, a first electrode, and a second electrode, wherein the active layer comprises: a channel portion, a first electrode connection portion, a second electrode connection portion, a first auxiliary portion, and a second auxiliary portion; the first auxiliary portion is connected to the channel portion and the first electrode connection portion respectively, the second auxiliary portion is connected to the channel portion and the second electrode connection portion respectively, the channel portion overlaps with the orthographic projection of the gate on the substrate, at least a portion of the first electrode connection portion is electrically connected to the first electrode, and at least a portion of the second electrode connection portion is electrically connected to the second electrode;

[0006] The thickness of at least two of the channel portion, the first electrode connection portion, the second electrode connection portion, the first auxiliary portion, and the second auxiliary portion is different.

[0007] In an exemplary embodiment, the first auxiliary part includes a first sub-auxiliary part and a second sub-auxiliary part, wherein the thickness of the first sub-auxiliary part is smaller than the thickness of the second sub-auxiliary part.

[0008] In an exemplary embodiment, the first electrode connection portion includes: a first sub-connection portion and a second sub-connection portion, and the second electrode connection portion includes: a third sub-connection portion, a fourth sub-connection portion and a fifth sub-connection portion;

[0009] The thickness of at least one of the second sub-connecting portion and the fourth sub-connecting portion is less than the thickness of at least one of the channel portion, the first sub-connecting portion, the second sub-auxiliary portion, the second auxiliary portion, the third sub-connecting portion and the fifth sub-connecting portion, and greater than the thickness of the first sub-auxiliary portion.

[0010] In an exemplary embodiment, the difference between the thickness of at least one of the channel portion, the first sub-connection portion, the second sub-auxiliary portion, the second auxiliary portion, the third sub-connection portion, and the fifth sub-connection portion and the thickness of at least one of the second sub-connection portion and the fourth sub-connection portion is in the range of 10 nanometers to 40 nanometers.

[0011] In an exemplary embodiment, the first electrode connection portion, the first auxiliary portion, the channel portion, the second auxiliary portion, and the second electrode connection portion are disposed in the same layer and arranged sequentially along the first direction;

[0012] The second sub-connecting part is connected to the first sub-connecting part and the first sub-auxiliary part respectively, the third sub-connecting part is connected to the second auxiliary part and the fourth sub-connecting part respectively, and the fourth sub-connecting part is also connected to the fifth sub-connecting part.

[0013] In an exemplary embodiment, the length of the third sub-connector along the first direction is greater than 0.2 micrometers.

[0014] In an exemplary embodiment, the length of the first sub-auxiliary part along the first direction is greater than 0.3 micrometers.

[0015] In an exemplary embodiment, the orthographic projection of the first electrode of at least one transistor on the substrate overlaps at least partially with the orthographic projection of the first electrode connection portion on the substrate, but does not overlap with the orthographic projection of the first auxiliary portion on the substrate.

[0016] The orthographic projection of the second electrode of at least one transistor on the substrate at least partially overlaps with the orthographic projection of the second electrode connection portion on the substrate, but does not overlap with the orthographic projection of the second auxiliary portion on the substrate.

[0017] In an exemplary embodiment, it further includes: a circuit structure layer disposed on the substrate, the circuit structure layer including: a semiconductor layer and a conductive layer;

[0018] The semiconductor layer includes at least: an active layer for at least one transistor;

[0019] The conductive layer includes at least: a gate, a first electrode, and a second electrode of at least one transistor.

[0020] In an exemplary embodiment, the circuit structure layer further includes: a first insulating layer disposed between the semiconductor layer and the conductive layer, the first insulating layer including: a first insulating structure, a second insulating structure, a third insulating structure and a fourth insulating structure;

[0021] The orthographic projection of the first insulating structure on the substrate at least partially overlaps with the orthographic projection of the gate of at least one transistor on the substrate, and does not overlap with the orthographic projections of the first auxiliary portion and the second auxiliary portion of at least one transistor on the substrate;

[0022] The orthographic projection of the second insulating structure on the substrate at least partially overlaps with the orthographic projection of the first sub-connection portion of at least one transistor on the substrate, but does not overlap with the orthographic projection of the second sub-connection portion of at least one transistor on the substrate;

[0023] The orthographic projection of the third insulating structure on the substrate at least partially overlaps with the orthographic projection of the third sub-connection portion of at least one transistor on the substrate, but does not overlap with the orthographic projections of the second auxiliary portion and the fourth sub-connection portion of at least one transistor on the substrate.

[0024] The orthographic projection of the fourth insulating structure on the substrate at least partially overlaps with the orthographic projection of the fifth sub-connection of at least one transistor on the substrate, but does not overlap with the orthographic projection of the fourth sub-connection of at least one transistor on the substrate.

[0025] In an exemplary embodiment, the first insulating layer has a first via and a second via, and the orthographic projections of the first via and the second via on the substrate are respectively located on both sides of the orthographic projection of the gate of at least one transistor on the substrate.

[0026] The first via exposes a second sub-connection portion and a first sub-auxiliary portion, and the second via exposes a fourth sub-connection portion. The area of ​​the orthographic projection of the first via on the substrate is different from the area of ​​the orthographic projection of the second via on the substrate.

[0027] In an exemplary embodiment, at least a portion of the first electrode of at least one transistor is disposed within a portion of the first via, and at least a portion of the second electrode of at least one transistor is disposed within the second via.

[0028] The orthographic projection of the first electrode of at least one transistor located in the first via onto the substrate covers the orthographic projection of the second sub-connection onto the substrate, and does not overlap with the orthographic projection of the first sub-auxiliary onto the substrate;

[0029] The orthogonal projection of the second electrode of at least one transistor located within the second via onto the substrate overlaps the orthogonal projection of the fourth sub-connection onto the substrate.

[0030] In an exemplary embodiment, the conductivity of the channel portion is less than the conductivity of the first auxiliary portion and the second auxiliary portion.

[0031] In an exemplary embodiment, the first auxiliary portion and the second auxiliary portion are conductor portions, and the channel portion is a semiconductor portion.

[0032] In an exemplary embodiment, the conductivity of the second sub-connection portion is greater than that of the first sub-connection portion, and the conductivity of the fourth sub-connection portion is greater than that of at least one of the third and fifth sub-connection portions.

[0033] In an exemplary embodiment, the second sub-connection portion and the fourth sub-connection portion are conductor portions, and the first sub-connection portion, the third sub-connection portion and the fifth sub-connection portion are semiconductor portions.

[0034] In an exemplary embodiment, the display substrate has a display area and a non-display area disposed on at least one side of the display area;

[0035] The transistor is located in at least one of the display area and the non-display area.

[0036] In an exemplary embodiment, the non-display area is provided with a shift register, which has a pull-up node, a pull-down node, and a noise reduction power supply terminal. The shift register includes a node noise reduction sub-circuit, which is electrically connected to the noise reduction power supply terminal and at least one of the pull-up node and the pull-down node, and is configured to provide the noise reduction power supply terminal signal to at least one of the pull-up node and the pull-down node.

[0037] The transistor is located in the node noise reduction sub-circuit, and the second terminal of at least one transistor in the node noise reduction sub-circuit is electrically connected to the pull-up node or the pull-down node.

[0038] In an exemplary embodiment, the number of pull-down nodes is at least one, and the shift register also has an output signal terminal;

[0039] The node noise reduction sub-circuit in the i-th stage shift register includes: multiple pull-up node noise reduction transistors, the gate of at least one pull-up node noise reduction transistor is electrically connected to one of the nodes in at least one pull-down node or the output signal terminal of the j-th stage shift register, the second terminal of at least one pull-up node noise reduction transistor is electrically connected to the pull-up node, and the first terminal of at least one pull-up node noise reduction transistor is electrically connected to the noise reduction power supply terminal, where j is a positive integer greater than i.

[0040] In an exemplary embodiment, the number of pull-down nodes is at least one, and the shift register also has an output signal terminal;

[0041] The node noise reduction sub-circuit in the i-th stage shift register includes: multiple pull-down node noise reduction transistors, the gate of at least one pull-down node noise reduction transistor is electrically connected to the pull-up node or the output signal terminal of the k-th stage shift register, the second terminal of at least one pull-down node noise reduction transistor is electrically connected to one of the at least one pull-down nodes, and the first terminal of at least one pull-down node noise reduction transistor is electrically connected to the noise reduction power supply terminal, where k is a positive integer less than i.

[0042] In an exemplary embodiment, the number of pull-down nodes is at least one, and the shift register also has an output signal terminal;

[0043] The node noise reduction sub-circuit in the i-th stage shift register includes: multiple pull-down node noise reduction transistors and multiple pull-up node noise reduction transistors;

[0044] The gate of at least one pull-up node noise reduction transistor is electrically connected to one of the nodes of at least one pull-down node or the output signal terminal of the j-th stage shift register, the second terminal of at least one pull-up node noise reduction transistor is electrically connected to the pull-up node, and the first terminal of at least one pull-up node noise reduction transistor is electrically connected to the noise reduction power supply terminal, where j is a positive integer greater than i.

[0045] The gate of at least one pull-down node noise reduction transistor is electrically connected to the output signal terminal of the pull-up node or the k-th stage shift register, the second terminal of at least one pull-down node noise reduction transistor is electrically connected to one of the nodes of at least one pull-down node, and the first terminal of at least one pull-down node noise reduction transistor is electrically connected to the noise reduction power supply terminal, where k is a positive integer less than i.

[0046] In an exemplary embodiment, the circuit structure layer further includes: a second insulating layer, a third insulating layer, and a light-shielding layer;

[0047] The second insulating layer is located on the side of the substrate closer to the semiconductor layer, the light-shielding layer is located on the side of the second insulating layer closer to the substrate, and the third insulating layer is located on the side of the conductive layer away from the substrate.

[0048] Secondly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0049] Thirdly, this disclosure also provides a method for preparing a display substrate, configured to prepare the above-mentioned display substrate, the method comprising:

[0050] Provide a base;

[0051] Multiple transistors are formed on the substrate.

[0052] In an exemplary embodiment, forming a plurality of transistors on the substrate includes:

[0053] A raw semiconductor layer is formed on a substrate using a first mask, the raw semiconductor layer comprising: a channel portion of at least one transistor, a first sub-connection portion, a third sub-connection portion, and a fifth sub-connection portion;

[0054] A first original insulating layer including a first via and a second via is formed on the original semiconductor layer through a second mask, and a second sub-connection portion, a first sub-auxiliary portion and a fourth sub-connection portion of at least one transistor are formed on the original semiconductor layer.

[0055] At least one transistor's gate, first electrode, and second electrode are formed on the first original insulating layer using a third mask;

[0056] The original semiconductor layer and the first original insulating layer are processed using the gate, first electrode and second electrode of at least one transistor as masks to form an active layer including a second sub-auxiliary portion and a second auxiliary portion, and a first insulating layer.

[0057] In an exemplary embodiment, prior to forming the original semiconductor layer on the substrate using a first mask, the method further includes:

[0058] A light-shielding layer is formed on the substrate using a fourth photomask;

[0059] A second insulating layer is formed on the light-shielding layer;

[0060] After forming a plurality of transistors on the substrate, the method further includes:

[0061] A third insulating layer is formed on the conductive layer.

[0062] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0063] Overview of the attached figures

[0064] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0065] Figure 1 is a schematic diagram of a planar structure of a display substrate;

[0066] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0067] Figure 3 is a schematic diagram of a planar structure of a display substrate;

[0068] Figure 4 is a schematic diagram of the structure of the transistor in the display substrate provided in the embodiment of this disclosure;

[0069] Figure 5 is a top view corresponding to Figure 4;

[0070] Figure 6 is a schematic diagram of the first insulating layer and the semiconductor layer;

[0071] Figure 7 is a schematic diagram after the formation of the light-shielding layer pattern;

[0072] Figure 8 is a top view corresponding to Figure 7;

[0073] Figure 9 is a schematic diagram of the formation of the original semiconductor layer pattern;

[0074] Figure 10 is a top view corresponding to Figure 9;

[0075] Figure 11 is a schematic diagram of the formation of the first original insulating layer pattern;

[0076] Figure 12 is a top view corresponding to Figure 11;

[0077] Figure 13 is a schematic diagram after the conductive layer pattern is formed;

[0078] Figure 14 is a top view corresponding to Figure 13;

[0079] Figure 15 is a schematic diagram after the formation of the first insulating layer pattern;

[0080] Figure 16 is a schematic diagram after the formation of the third insulating layer;

[0081] Figure 17 is a schematic diagram of a display device;

[0082] Figure 18 is a schematic diagram of a shift register;

[0083] Figure 19 is an equivalent circuit diagram of the shift register provided in Figure 18;

[0084] Figure 20 is the timing diagram of the shift register provided in Figure 19.

[0085] Detailed Explanation

[0086] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be arbitrarily combined with each other.

[0087] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" encompass the elements or objects listed after the term and their equivalents, without excluding other elements or objects.

[0088] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0089] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection via an intermediate component; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure in light of the specific circumstances.

[0090] In this disclosure, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain electrode (or drain terminal, drain connection region, or drain electrode) and the source electrode (or source terminal, source connection region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0091] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" can sometimes be interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged. The gate can also be called the control electrode.

[0092] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. The "component having a certain electrical function" can be, for example, an electrode or wiring, a switching element such as a transistor, or other functional elements such as a resistor, inductor, or capacitor.

[0093] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes a state in which the angle is greater than or equal to -5° and less than 5°. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes a state in which the angle is greater than or equal to 85° and less than 95°.

[0094] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0095] Figure 1 is a schematic diagram of a planar structure of a display substrate (one type), Figure 2 is a schematic diagram of a planar structure of a display substrate (two types), and Figure 3 is a schematic diagram of a planar structure of a display substrate (three types). As shown in Figures 1 to 3, the display substrate may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to a gate signal line and a data signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line under the control of the gate signal line and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0096] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 may be a green sub-pixel (G) that emits green light.

[0097] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, rhomboid, pentagonal or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side or in a triangular pattern, which is not limited in this disclosure.

[0098] In an exemplary embodiment, a pixel unit may include three sub-pixels. The three sub-pixels may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement, etc., and this disclosure does not limit the arrangement. Figures 1 and 2 are illustrated using the example of a pixel unit including three sub-pixels. The three sub-pixels in Figure 1 are arranged horizontally side by side, and the three sub-pixels in Figure 2 are arranged in a triangular arrangement.

[0099] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged horizontally side-by-side, vertically side-by-side, or in a square, etc., and this disclosure does not limit the arrangement. Figure 3 illustrates an example where a pixel unit includes four sub-pixels, and the four sub-pixels are arranged in a square.

[0100] The display substrate contains multiple transistors. Some transistors operate under high voltage for extended periods. This prolonged high voltage can cause some transistors to fail or their turn-on current to decrease drastically, reducing the performance of the shift register and ultimately degrading the display quality of the display product.

[0101] Figure 4 is a schematic diagram of the structure of the transistor in the display substrate provided in the embodiment of this disclosure, and Figure 5 is a top plan view corresponding to Figure 4. Figure 4 is a cross-sectional view along the AA direction of Figure 5. As shown in Figures 4 and 5, the display substrate provided in the embodiment of this disclosure may include: a substrate 20 and a plurality of transistors disposed on the substrate 20. The transistors include: a gate 12, an active layer 11, a first electrode 13, and a second electrode 14. The active layer 11 includes: a channel portion AR1, a first electrode connection portion AR2, a second electrode connection portion AR3, a first auxiliary portion AR4, and a second auxiliary portion AR5. The first auxiliary portion AR4 is connected to the channel portion AR1 and the first electrode connection portion AR2, and the second auxiliary portion AR5 is connected to the channel portion AR1 and the second electrode connection portion AR3, respectively. The channel portion AR1 and the gate 12 overlap in their orthographic projections on the substrate 20. At least a portion of the first electrode connection portion AR2 is electrically connected to the first electrode 13, and at least a portion of the second electrode connection portion AR3 is electrically connected to the second electrode 14.

[0102] As shown in Figure 4, at least two of the following have different thicknesses: the channel portion AR1, the first electrode connection portion AR2, the second electrode connection portion AR3, the first auxiliary portion AR4, and the second auxiliary portion AR5.

[0103] In an exemplary embodiment, the substrate 20 may be a rigid substrate or a flexible substrate. The rigid substrate may be one or more of glass and metal sheets, but is not limited to. The flexible substrate may be one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers, but is not limited to.

[0104] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films. The first and second inorganic material layers may be made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: firstly, coating a layer of polyimide on a glass substrate, curing it into a film to form a first flexible (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it into a film to form a second flexible (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the substrate preparation.

[0105] This disclosure ensures that the active layer of the transistor does not provide conductivity in different parts by setting at least two of the channel portion AR1, the first electrode connection portion AR2, the second electrode connection portion AR3, the first auxiliary portion AR4, and the second auxiliary portion AR5 in the transistor to have different thicknesses. This avoids some transistors being in a high voltage state for a long time, improves the performance of at least one transistor, or avoids the sharp decay of the turn-on current of at least one transistor, thereby improving the performance of the display substrate and the display effect of the display product.

[0106] In an exemplary embodiment, as shown in FIG4, the first auxiliary part AR4 includes a first sub-auxiliary part AR41 and a second sub-auxiliary part AR42. The thickness of the first sub-auxiliary part AR41 is smaller than the thickness of the second sub-auxiliary part AR42.

[0107] In an exemplary embodiment, as shown in FIG4, the first electrode connection portion AR2 includes a first sub-connection portion AR21 and a second sub-connection portion AR22, and the second electrode connection portion AR3 includes a third sub-connection portion AR31, a fourth sub-connection portion AR32 and a fifth sub-connection portion AR33.

[0108] In an exemplary embodiment, as shown in FIG4, the thickness h1 of at least one of the second sub-connecting portion AR22 and the fourth sub-connecting portion AR32 is less than the thickness h2 of at least one of the channel portion AR1, the first sub-connecting portion AR21, the second sub-auxiliary portion, the second auxiliary portion AR5, the third sub-connecting portion AR31 and the fifth sub-connecting portion AR33, and is greater than the thickness of the first sub-auxiliary portion.

[0109] In an exemplary embodiment, the thickness of the second sub-connector AR22 is approximately the same as the thickness of the fourth sub-connector AR32.

[0110] In an exemplary embodiment, at least two of the channel portion AR1, the first sub-connecting portion AR21, the second sub-auxiliary portion, the second auxiliary portion AR5, the third sub-connecting portion AR31, and the fifth sub-connecting portion AR33 have approximately the same thickness.

[0111] In an exemplary embodiment, the present disclosure can observe the cross-section of the transistor using a scanning electron microscope or a transmission electron microscope, and obtain the thickness h1 of at least one of the second sub-connection portion AR22 and the fourth sub-connection portion AR32, as well as the thickness h2 of at least one of the channel portion AR1, the first sub-connection portion AR21, the second sub-auxiliary portion, the second auxiliary portion AR5, the third sub-connection portion AR31, and the fifth sub-connection portion AR33 by taking the tangents of the upper and lower surfaces of the cross-section.

[0112] In an exemplary embodiment, as shown in FIG4, the difference between the thickness h2 of at least one of the channel portion AR1, the first sub-connecting portion AR21, the second sub-auxiliary portion, the second auxiliary portion AR5, the third sub-connecting portion AR31 and the fifth sub-connecting portion AR33 and the thickness h1 of at least one of the second sub-connecting portion AR22 and the fourth sub-connecting portion AR32 is in the range of 10 nanometers to 40 nanometers.

[0113] In an exemplary embodiment, as shown in FIG4, the first electrode connection portion AR2, the first auxiliary portion AR4, the channel portion AR1, the second auxiliary portion AR5, and the second electrode connection portion AR3 are disposed in the same layer and arranged sequentially along the first direction D1.

[0114] In an exemplary embodiment, as shown in FIG4, the second sub-connecting part AR22 is connected to the first sub-connecting part AR21 and the first sub-auxiliary part AR41 respectively, the third sub-connecting part AR31 is connected to the second auxiliary part AR5 and the fourth sub-connecting part AR32 respectively, and the fourth sub-connecting part AR32 is also connected to the fifth sub-connecting part AR33.

[0115] In an exemplary embodiment, as shown in FIG4, the first direction D1 intersects with the second direction D2, and the second direction D2 is the direction in which the substrate 20 and the transistor are stacked.

[0116] In an exemplary embodiment, as shown in FIG4, the length W1 of the third sub-connector AR31 along the first direction D1 is greater than 0.2 micrometers. Exemplarily, the length W1 of the third sub-connector AR31 along the first direction D1 can be greater than 0.3 micrometers.

[0117] In an exemplary embodiment, as shown in FIG4, the length of the first sub-auxiliary part AR41 along the first direction D1 is greater than 0.3 micrometers.

[0118] In an exemplary embodiment, as shown in Figures 4 and 5, the orthographic projection of the first electrode 13 of at least one transistor on the substrate 20 at least partially overlaps with the orthographic projection of the first electrode connection portion AR2 on the substrate 20, but does not overlap with the orthographic projection of the first auxiliary portion AR4 on the substrate 20.

[0119] In an exemplary embodiment, as shown in Figures 4 and 5, the orthographic projection of the second electrode 14 of at least one transistor on the substrate 20 at least partially overlaps with the orthographic projection of the second electrode connection portion AR3 on the substrate 20, but does not overlap with the orthographic projection of the second auxiliary portion AR5 on the substrate 20.

[0120] In an exemplary embodiment, the display substrate further includes: a circuit structure layer disposed on the substrate 20, the circuit structure layer including: a semiconductor layer and a conductive layer;

[0121] The semiconductor layer includes at least: an active layer 11 of at least one transistor;

[0122] The conductive layer includes at least: a gate 12, a first electrode 13, and a second electrode 14 of at least one transistor.

[0123] In an exemplary embodiment, the semiconductor layer may be made of various materials such as metal oxide materials and / or metal oxynitride materials, amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, etc. That is, this disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.

[0124] When the semiconductor layer employs at least one of a metal oxide material and a metal oxide nitride material, the metal oxide material includes, but is not limited to: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), rare earth doped oxide (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. The metal oxide nitride material includes, but is not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof.

[0125] In an exemplary embodiment, the material of the semiconductor layer may be amorphous, partially crystalline, monocrystalline, or polycrystalline.

[0126] In an exemplary embodiment, the semiconductor layer can be a single-layer or multi-layer structure.

[0127] In an exemplary embodiment, the conductive layer may be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0128] In an exemplary embodiment, the circuit structure layer further includes a first insulating layer 21, which is disposed between the semiconductor layer and the conductive layer.

[0129] In an exemplary embodiment, FIG6 is a schematic diagram of the first insulating layer and the semiconductor layer. As shown in FIG4 and FIG6, the circuit structure layer further includes: a first insulating layer 21, which is disposed between the semiconductor layer and the conductive layer.

[0130] In an exemplary embodiment, the first insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer. The first insulating layer may be referred to as a gate insulating layer.

[0131] As shown in Figure 6, the first insulating layer 21 includes: a first insulating structure 211, a second insulating structure 212, a third insulating structure 213 and a fourth insulating structure 214.

[0132] In an exemplary embodiment, as shown in FIG6, the orthographic projection of the first insulating structure 211 on the substrate 20 at least partially overlaps with the orthographic projection of the gate 12 of at least one transistor on the substrate 20, and does not overlap with the orthographic projections of the first auxiliary portion AR4 and the second auxiliary portion AR5 of at least one transistor on the substrate 20.

[0133] In an exemplary embodiment, as shown in FIG6, the orthographic projection of the second insulating structure 212 on the substrate 20 at least partially overlaps with the orthographic projection of the first sub-connection portion AR21 of at least one transistor on the substrate 20, and does not overlap with the orthographic projection of the second sub-connection portion AR22 of at least one transistor on the substrate 20.

[0134] In an exemplary embodiment, as shown in FIG6, the orthographic projection of the third insulating structure 213 on the substrate 20 at least partially overlaps with the orthographic projection of the third sub-connection portion AR31 of at least one transistor on the substrate 20, and does not overlap with the orthographic projections of the second auxiliary portion AR5 and the fourth sub-connection portion AR32 of at least one transistor on the substrate 20.

[0135] In an exemplary embodiment, as shown in FIG6, the orthographic projection of the fourth insulating structure 214 on the substrate 20 at least partially overlaps with the orthographic projection of the fifth sub-connection portion AR33 of at least one transistor on the substrate 20, and does not overlap with the orthographic projection of the fourth sub-connection portion AR32 of at least one transistor on the substrate 20.

[0136] In an exemplary embodiment, as shown in Figures 4 and 6, the first insulating layer 21 has a first via V1 and a second via V2. The orthogonal projections of the first via V1 and the second via V2 on the substrate 20 are respectively located on both sides of the orthogonal projection of the gate 12 of at least one transistor on the substrate 20.

[0137] In an exemplary embodiment, as shown in Figures 4 and 6, the first via V1 exposes the second sub-connection AR22 and the first sub-auxiliary AR41, and the second via V2 exposes the fourth sub-connection AR32. The area of ​​the orthographic projection of the first via V1 onto the substrate 20 is different from the area of ​​the orthographic projection of the second via V2 onto the substrate 20.

[0138] In an exemplary embodiment, as shown in Figures 4 and 6, at least a portion of the first electrode 13 of at least one transistor is disposed within a portion of the first via V1, and at least a portion of the second electrode 14 of at least one transistor is disposed within the second via V2.

[0139] In an exemplary embodiment, as shown in Figures 4 and 6, the orthographic projection of the first electrode 13 of at least one transistor located in the first via V1 onto the substrate 20 covers the orthographic projection of the second sub-connection portion AR22 onto the substrate 20, and does not overlap with the orthographic projection of the first sub-auxiliary portion AR41 onto the substrate 20, that is, the first electrode 13 of at least one transistor partially covers the first via V1.

[0140] In an exemplary embodiment, as shown in Figures 4 and 6, the orthogonal projection of the second electrode 14 of at least one transistor located within the second via V2 onto the substrate 20 covers the orthogonal projection of the fourth sub-connection AR32 onto the substrate 20.

[0141] In an exemplary embodiment, as shown in Figures 4 and 6, the first insulating layer 21 further comprises a third via V3 and a fourth via V4. The third via V3 exposes a second auxiliary portion AR5 located in at least one transistor. The fourth via V4 exposes a second sub-auxiliary portion AR42 located in at least one transistor.

[0142] In an exemplary embodiment, as shown in Figures 4 and 5, the circuit structure layer further includes a second insulating layer 22, a third insulating layer 23, and a light-shielding layer 24. The second insulating layer 22 is located on the side of the substrate 20 closest to the semiconductor layer, the light-shielding layer 24 is located on the side of the second insulating layer 22 closest to the substrate 20, and the third insulating layer 23 is located on the side of the conductive layer furthest from the substrate 20.

[0143] In an exemplary embodiment, the second insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer. The second insulating layer may be referred to as a buffer layer.

[0144] In an exemplary embodiment, the third insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer. The third insulating layer may be referred to as a passivation layer.

[0145] In an exemplary embodiment, the light-shielding layer 24 may be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, or the light-shielding layer may be made of black coating.

[0146] In an exemplary embodiment, the orthographic projection of the light-shielding layer 24 on the substrate covers the orthographic projection of the channel portion on the substrate.

[0147] In an exemplary embodiment, the conductivity of the channel portion AR1 is less than that of the first auxiliary portion AR4 and the second auxiliary portion AR5.

[0148] In an exemplary embodiment, the first auxiliary part AR4 and the second auxiliary part AR5 are conductor parts.

[0149] In an exemplary embodiment, the channel portion AR1 is a semiconductor portion.

[0150] In an exemplary embodiment, the conductivity of the second sub-connector AR22 is greater than that of the first sub-connector AR21, and the conductivity of the fourth sub-connector AR32 is greater than that of at least one of the third sub-connector AR31 and the fifth sub-connector AR33.

[0151] In an exemplary embodiment, the second sub-connection AR22 and the fourth sub-connection AR32 are conductor portions.

[0152] In an exemplary embodiment, the first sub-connection portion AR21, the third sub-connection portion AR31, and the fifth sub-connection portion AR33 are semiconductor portions.

[0153] The display substrate described in this embodiment can be used in display products of any resolution.

[0154] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0155] (1) Forming a light-shielding layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a light-shielding film on a substrate 20, and patterning the light-shielding film using a patterning process to form a light-shielding layer pattern. As shown in Figures 7 and 8, Figure 7 is a schematic diagram after the light-shielding layer pattern is formed, and Figure 8 is a top plan view corresponding to Figure 7.

[0156] (2) Forming the original semiconductor layer pattern. In an exemplary embodiment, forming the original semiconductor layer pattern may include: sequentially depositing a second insulating film and a semiconductor film on the light-shielding layer pattern, and patterning the semiconductor film using a patterning process to form a second insulating layer 22 covering the substrate and an original semiconductor layer pattern 110 disposed on the light-shielding layer pattern. As shown in Figures 9 and 10, Figure 9 is a schematic diagram of forming the original semiconductor layer pattern, and Figure 10 is a top plan view corresponding to Figure 9.

[0157] In an exemplary embodiment, as shown in FIG9, the original semiconductor layer pattern may include at least: a channel portion AR1, a first sub-connection portion AR21, a third sub-connection portion AR31, and a fifth sub-connection portion AR33 located in at least one transistor. The channel portion AR1, the first sub-connection portion AR21, the third sub-connection portion AR31, and the fifth sub-connection portion AR33 are spaced apart. The first sub-connection portion AR21 is located on a first side of the channel portion AR1, the third sub-connection portion AR31 and the fifth sub-connection portion AR33 are located on the side of the third sub-connection portion AR31 that is away from the channel portion AR1, and the fifth sub-connection portion AR33 is located on the side of the third sub-connection portion AR31 that is away from the channel portion AR1.

[0158] In an exemplary embodiment, as shown in FIG10, the original semiconductor layer pattern may include at least: a first conductive region BR1, a second conductive region BR2, a third conductive region BR3, and a fourth conductive region BR4 located in at least one transistor. Specifically, the first conductive region BR1 is located between the third sub-connection portion AR31 and the fifth sub-connection portion AR33, the second conductive region BR2 is located between the channel portion AR1 and the first sub-connection portion AR21, and the third conductive region BR3 is located between the channel portion AR1 and the third sub-connection portion AR3.

[0159] (3) Forming a first original insulating layer pattern. In an exemplary embodiment, forming a first original insulating layer pattern may include: depositing a first insulating film on an original semiconductor layer, patterning the first insulating film using a patterning process to form a first original insulating layer pattern 210, and forming a second sub-connection portion AR22, a first sub-auxiliary portion AR41, and a fourth sub-connection portion AR32 located on at least one transistor on the original semiconductor layer pattern. As shown in Figures 11 and 12, Figure 11 is a schematic diagram of forming a first original insulating layer pattern, and Figure 12 is a top plan view corresponding to Figure 11.

[0160] In an exemplary embodiment, the first original insulating layer 210 has a first via V1 and a second via V2. The first via V1 exposes the portion of the second conductive region BR2 near the first sub-connection AR21, and the second via V2 exposes the first conductive region BR1.

[0161] In an exemplary embodiment, when the first via V1 and the second via V2 are patterned to form the first insulating film, the portions of the first to be conductord region BR1 and the second to be conductord region BR2 near the first sub-connection portion AR21 are also conductord to form a second sub-connection portion AR22, a first sub-auxiliary portion AR41 and a fourth sub-connection portion AR32 located in at least one transistor.

[0162] (4) Forming a conductive layer pattern. In an exemplary embodiment, forming a conductive layer pattern may include: depositing a conductive thin film on a first original insulating layer pattern, and patterning the conductive thin film using a patterning process to form a conductive layer pattern. As shown in Figures 13 and 14, Figure 13 is a schematic diagram after forming the conductive layer pattern, and Figure 14 is a top plan view corresponding to Figure 13.

[0163] In an exemplary embodiment, as shown in Figures 13 and 14, the conductive layer pattern may include at least a gate 12, a first electrode 13, and a second electrode 14 located in at least one transistor.

[0164] (5) Forming an active layer pattern and a first insulating layer pattern. In an exemplary embodiment, forming an active layer pattern and a first insulating layer pattern includes: patterning a first original insulating layer pattern by a patterning process to form a first insulating layer pattern 21; doping a portion of the second region to be conductive near the channel region and a third region to be conductive to form an active layer 11 pattern including a second sub-auxiliary portion AR42 and a second auxiliary portion AR5 of at least one transistor. FIG15 is a schematic diagram after forming the first insulating layer pattern.

[0165] In an exemplary embodiment, the patterning process for forming the active layer pattern and the first insulating layer pattern uses the conductive layer pattern as a mask.

[0166] In an exemplary embodiment, as shown in FIG15, the pattern of the first insulating layer 21 further includes a third via V3 and a fourth via V4. The third via V3 exposes a third region to be conductiveized, and the fourth via V4 exposes a portion of the second region to be conductiveized BR2 near the channel portion.

[0167] (6) Forming a third insulating layer. In an exemplary embodiment, forming a third insulating layer includes depositing a third insulating film on a conductive layer to form a third insulating layer 23 covering the substrate. Figure 16 is a schematic diagram after the formation of the third insulating layer.

[0168] In an exemplary embodiment, the display substrate may have a display area and a non-display area disposed on at least one side of the display area. The transistor shown in FIG4 may be located in at least one region of the display area and the non-display area.

[0169] With the advancement of technology, high-resolution, narrow-bezel display panels have become a development trend, leading to the emergence of Gate Driver on Array (GOA) technology. GOA technology refers to the technique of placing the GOA circuits used to drive the gate lines on both sides of the effective display area of ​​the array substrate in the display panel.

[0170] Figure 17 is a schematic diagram of a display device. As shown in Figure 17, the display device may include a timing controller, a data driver, a gate driver, and a pixel array. The timing controller is connected to both the data driver and the gate driver. The data driver is connected to multiple data signal lines (D1 to Dn), and the gate driver is connected to multiple gate signal lines (G1 to Gm). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers.

[0171] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages that will be provided to the data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a pixel-row basis, where n can be a natural number.

[0172] In an exemplary embodiment, the gate driver can generate scan signals to be provided to gate signal lines G1, G2, G3, ... to Gm by receiving a clock signal, a gate start signal, etc., from a timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to the gate signal lines G1 to Gm. For example, the gate driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number.

[0173] In an exemplary embodiment, the timing controller, data driver, and gate driver may be located in a non-display area.

[0174] In an exemplary embodiment, the pixel array may be located in the display area.

[0175] In an exemplary embodiment, the gate driver may include a plurality of cascaded shift registers.

[0176] Figure 18 is a schematic diagram of a shift register. As shown in Figure 18, the i-th stage shift register may include: an input sub-circuit, an output sub-circuit, a pull-down node control sub-circuit, a node noise reduction sub-circuit, and an output noise reduction sub-circuit. The input sub-circuit is electrically connected to the signal input terminal IN and the pull-up node PU, and is configured to provide a signal to the pull-up node PU under the control of the signal input terminal IN. The output sub-circuit is electrically connected to the pull-up node PU, the clock signal terminal CLK, and the signal output terminal OUT(i), and is configured to provide the clock signal terminal CLK to the signal output terminal OUT(i) under the control of the signal from the pull-up node PU. The pull-down node control sub-circuit is electrically connected to the pull-down node PD and the control signal group, and is configured to provide a signal to the pull-down node PD under the control of the signal from the control signal group. The node noise reduction sub-circuit is electrically connected to the pull-up node PU, the pull-down node PD, and the first low-level power supply terminal VGL, and is configured to provide the first low-level power supply terminal VGL1 signal to the pull-up node PU and the pull-down node PD. The output noise reduction sub-circuit is electrically connected to the signal output terminal OUT(i) and the second low-level power supply terminal VGL2, respectively, and is configured to provide the signal of the second low-level power supply terminal VGL2 to the signal output terminal OUT(i).

[0177] In an exemplary embodiment, the node noise reduction sub-circuit can also be electrically connected to the signal output terminal OUT(j) of the j-th stage shift register and the signal output terminal OUT(k) of the k-th stage shift register.

[0178] In an exemplary embodiment, the output noise reduction sub-circuit can also be electrically connected to the pull-up node PU or the pull-down node PD.

[0179] In an exemplary embodiment, the control signal group may include at least one of a high-level power supply terminal VDD and a control clock signal terminal CLKE, or two AC signals that are inversely related to each other, without any limitation herein.

[0180] In an exemplary embodiment, the configuration of the node noise reduction subcircuit can reduce noise in the shift register caused by pull-up or pull-down nodes, thereby improving the reliability of the shift register. The configuration of the output noise reduction subcircuit can reduce noise in the shift register caused by the signal at the signal output terminal, thereby improving the reliability of the shift register.

[0181] In an exemplary implementation, the number of dropdown nodes (PDs) can be at least one. For example, the number of dropdown nodes (PDs) can be one or two.

[0182] In an exemplary embodiment, the signal output terminal can be a single signal terminal, which can provide cascaded signals to at least one shift register after the current shift register and drive signals to sub-pixels. Alternatively, the signal input terminal can include two signal terminals, one of which provides cascaded signals to at least one shift register after the current shift register and the other provides drive signals to sub-pixels. This disclosure does not impose any limitations on this.

[0183] Figure 19 is an equivalent circuit diagram of the shift register provided in Figure 18. As shown in Figure 19, the input sub-circuit includes a first transistor T1; the output sub-circuit may include a second transistor T2, a third transistor T3, and a capacitor C; the pull-down node control sub-circuit may include a ninth transistor T9 and a twelfth transistor T12; the output noise reduction sub-circuit includes a sixth transistor T6, a fourteenth transistor T14, a fifteenth transistor T15, a seventeenth transistor T17, and an eighteenth transistor T18; and the node noise reduction sub-circuit includes a fifth transistor T5, a seventh transistor T7, an eighth transistor T8, a tenth transistor T10, an eleventh transistor T11, a thirteenth transistor T13, and a sixteenth transistor T16. Figure 19 is illustrated using two signal output terminals, the first output terminal OUT1 and the second output terminal OUT2, and two pull-down nodes, the first pull-down node PD1 and the second pull-down node PD2.

[0184] In an exemplary embodiment, as shown in FIG19, the shift register may further include a reset sub-circuit. The reset sub-circuit includes a fourth transistor T4.

[0185] As shown in Figure 19, the control electrode of the first transistor T1 is electrically connected to the signal input terminal IN, the first electrode of the first transistor T1 is electrically connected to the second power supply V2 terminal, and the second electrode of the first transistor T1 is electrically connected to the pull-up node PU; the control electrode of the second transistor T2 is electrically connected to the pull-up node PU, the first electrode of the second transistor T2 is electrically connected to the clock signal terminal CLK, and the second electrode of the second transistor T2 is electrically connected to the first output terminal OUT1; the control electrode of the third transistor T3 is electrically connected to the pull-up node, the first electrode of the third transistor T3 is electrically connected to the clock signal terminal CLK, and the second electrode of the third transistor T3 is electrically connected to the second output terminal OUT2; the control electrode of the fourth transistor T4 is electrically connected to the total reset signal terminal TRST. The first terminal of transistor T4 is electrically connected to the pull-up node PU; the second terminal of transistor T4 is electrically connected to the first power supply terminal V1; the control terminal of transistor T5 is electrically connected to the first reset signal terminal RST1; the second terminal of transistor T5 is electrically connected to the pull-up node PU; and the first terminal of transistor T5 is electrically connected to the first power supply terminal V1; the control terminal of transistor T6 is electrically connected to the second reset signal terminal RST2; the first terminal of transistor T6 is electrically connected to the first output terminal; and the second terminal of transistor T6 is electrically connected to the third power supply terminal V3; the control terminal of transistor T7 is electrically connected to the signal input terminal IN; the second terminal of transistor T7 is electrically connected to the first pull-down node PD1; and the first terminal of transistor T7 is electrically connected to the first power supply terminal V1. The control terminal of the eighth transistor T8 is electrically connected to the pull-up node PU, the second terminal of the eighth transistor T8 is electrically connected to the first pull-down node PD1, and the first terminal of the eighth transistor T8 is electrically connected to the first power supply terminal V1; the control terminal and the first terminal of the ninth transistor T9 are electrically connected to the fourth power supply terminal V4, and the second terminal of the ninth transistor T9 is electrically connected to the first pull-down node PD1; the control terminal of the tenth transistor T10 is electrically connected to the signal input terminal IN, the second terminal of the tenth transistor T10 is electrically connected to the second pull-down node PD2, and the first terminal of the tenth transistor T10 is electrically connected to the first power supply terminal V1; the control terminal of the eleventh transistor T11 is electrically connected to the pull-up node PU, and the second terminal of the eleventh transistor T11 is electrically connected to the second pull-down node PD2. Node PD2 is electrically connected; the first terminal of the eleventh transistor T11 is electrically connected to the first power supply terminal V1; the control terminal and the first terminal of the twelfth transistor T12 are electrically connected to the fifth power supply terminal V5, and the second terminal of the twelfth transistor T12 is electrically connected to the second pull-down node PD2; the control terminal of the thirteenth transistor T13 is electrically connected to the first pull-down node PD1, the second terminal of the thirteenth transistor T13 is electrically connected to the pull-up node PU, and the first terminal of the thirteenth transistor T13 is electrically connected to the first power supply terminal V1; the control terminal of the fourteenth transistor T14 is electrically connected to the first pull-down node PD1, the first terminal of the fourteenth transistor T14 is electrically connected to the first output terminal OUT1, and the second terminal of the fourteenth transistor T14 is electrically connected to the third power supply terminal V3.The control electrode of the fifteenth transistor T15 is electrically connected to the first pull-down node PD1, the first terminal of the fifteenth transistor T15 is electrically connected to the second output terminal OUT2, and the second terminal of the fifteenth transistor T15 is electrically connected to the first power supply terminal V1; the control electrode of the sixteenth transistor T16 is electrically connected to the second pull-down node PD2, the second terminal of the sixteenth transistor T16 is electrically connected to the pull-up node PU, and the first terminal of the sixteenth transistor T16 is electrically connected to the first power supply terminal V1; the control electrode of the seventeenth transistor T17 is electrically connected to the second pull-down node PD2, the first terminal of the seventeenth transistor T17 is electrically connected to the first output terminal OUT1, and the second terminal of the seventeenth transistor T17 is electrically connected to the third power supply terminal V3; the control electrode of the eighteenth transistor T18 is electrically connected to the second pull-down node PD2, the first terminal of the eighteenth transistor T18 is electrically connected to the second output terminal OUT2, and the second terminal of the eighteenth transistor T18 is electrically connected to the first power supply terminal V1; the first terminal of capacitor C is electrically connected to the pull-up node PU, and the second terminal of capacitor C is electrically connected to the first output terminal OUT1.

[0186] In an exemplary embodiment, the first reset signal terminal RST1 and the second reset signal terminal RST2 are signal output terminals of at least one shift register located after the current shift register. The signal input terminal IN is the signal output terminal of at least one shift register located before the current shift register.

[0187] In an exemplary embodiment, the fifth transistor T5, the thirteenth transistor T13, and the sixteenth transistor T16 in the node noise reduction sub-circuit can be referred to as pull-up node noise reduction transistors. The control terminal of the pull-up node noise reduction transistor is electrically connected to the first pull-down node PD1, the second pull-down node PD2, or the first reset signal terminal RST1 (the signal output terminal of at least one shift register after this stage shift register), the second terminal of the pull-up node noise reduction transistor is electrically connected to the pull-up node PU, and the first terminal of the pull-up node noise reduction transistor is electrically connected to the first power supply terminal V1.

[0188] In an exemplary embodiment, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, and the eleventh transistor T11 in the node noise reduction sub-circuit can be referred to as pull-down node noise reduction transistors. The control terminal of the pull-down node noise reduction transistor is electrically connected to the pull-up node PU or the signal input terminal IN (the signal output terminal of at least one stage shift register located before this stage shift register), the second terminal of the pull-down node noise reduction transistor is electrically connected to the first pull-down node PD1 or the second pull-down node PD2, and the first terminal of the pull-down node noise reduction transistor is electrically connected to the first power supply terminal V1.

[0189] In an exemplary embodiment, the signal at the first output terminal OUT1 is a single pulse signal. The first output terminal OUT1 can output the drive signal for this stage.

[0190] In an exemplary embodiment, the clock signal terminal CLK is a clock signal, and the pulse width is adjustable.

[0191] In an exemplary embodiment, the first power supply terminal V1 and the third power supply terminal V3 are low-level power supply terminals and continuously provide low-level signals.

[0192] In an exemplary embodiment, the absolute value of the voltage of the signal at the first power supply terminal V1 is greater than the absolute value of the voltage of the signal at the third power supply terminal V3.

[0193] In an exemplary embodiment, the fourth power supply terminal V4 and the fifth power supply terminal V5 are inverted signals. The fourth power supply terminal V4 and the fifth power supply terminal V5 are not both high-level signals at the same time. For example, when the fourth power supply terminal V4 is a high-level signal, the fifth power supply terminal V5 is a low-level signal, or when the fourth power supply terminal V4 is a low-level signal, the fifth power supply terminal V5 is a high-level signal.

[0194] In an exemplary embodiment, the content displayed on the display substrate includes multiple display frames. Each display frame may include a first display frame and a second display frame, which may be alternately configured. In the first display frame, the signal at the fourth power terminal V4 is a high-level signal, and the signal at the fifth power terminal V5 is a low-level signal. In the second display frame, the signal at the fourth power terminal V4 is a low-level signal, and the signal at the fifth power terminal V5 is a high-level signal.

[0195] In an exemplary embodiment, transistors can be categorized into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0196] In an exemplary embodiment, all transistors in the shift register are N-type transistors. Exemplarily, all transistors in the shift register can be metal-oxide-semiconductor (MOS) transistors. Because MOS transistors have higher mobility and lower leakage current, using MOS transistors in the shift register can improve the refresh rate of the display product, enabling high-frequency displays, and also enabling low-frequency displays, thereby reducing power consumption.

[0197] For any shift register shown in Figure 19, the signals at the first power supply terminal V1 and the third power supply terminal V3 are low-level signals. The clock signal terminal CLK is the clock signal. The fourth power supply terminal V4 and the fifth power supply terminal V5 are constant voltage signals in any display frame. Specifically, in the first display frame, the fourth power supply terminal V4 is a high-level signal, the ninth transistor T9 is continuously turned on, the fifth power supply terminal V5 is a low-level signal, and the twelfth transistor T12 is continuously turned off. In the second display frame, the fourth power supply terminal V4 is a low-level signal, the ninth transistor T9 is continuously turned off, the fifth power supply terminal V5 is a high-level signal, and the twelfth transistor T12 is continuously turned on. The fourth power supply terminal V4 switches from a first-level signal to a second-level signal during the period when the total reset signal terminal TRST is an effective level signal, and the fifth power supply terminal V5 switches from a second-level signal to a first-level signal during the period when the total reset signal terminal TRST is an effective level signal. For example, when the first-level signal is high, the second-level signal is low, and when the first-level signal is low, the second-level signal is high.

[0198] Figure 20 is the timing diagram of the shift register shown in Figure 19. Figure 20 is illustrated using the example where all transistors in the shift register are N-type transistors.

[0199] Referring to Figures 19 and 20, the operation of the shift register shown in Figure 19 can include the following stages:

[0200] In the first stage P11, i.e., the input stage, the signal at the signal input terminal IN is a high-level signal, while the signals at the clock signal terminal CLK, the first reset signal terminal RST1, the second reset signal terminal RST2, and the total reset signal terminal TRST are low-level signals. When the signal at the signal input terminal IN is high, the first transistor T1 is turned on, and the high-level signal at the second power supply terminal V2 is written to the pull-up node PU, pulling PU high. The seventh transistor T7 and the tenth transistor T10 are turned on, and the low-level signal at the first power supply terminal V1 is written to the first pull-down node PD1 and the second pull-down node PD2. When the signal at the pull-up node PU is high, the second transistor T2 and the third transistor T3 are turned on, and the low-level signal at the clock signal terminal CLK is written to the first output terminal OUT1 and the second output terminal OUT2. The eighth transistor T8 and the eleventh transistor T11 are turned on, and the low-level signal at the first power supply terminal V1 is continuously written to the first pull-down node PD1 and the second pull-down node PD2. The first pull-down node PD1 and the second pull-down node PD2 remain at a low level, while the thirteenth transistor T13, fourteenth transistor T14, fifteenth transistor T15, sixteenth transistor T16, seventeenth transistor T17, and eighteenth transistor T18 are disconnected. During this stage, the signal of the pull-up node PU is a high level signal, while the signals of the first pull-down node PD1, the second pull-down node PD2, the first output terminal OUT1, and the second output terminal OUT2 are low level signals.

[0201] In the first stage, when the shift register is in the first display frame, transistor 9 T9 is turned on and transistor 12 T12 is turned off. Although transistor 9 T9 is on, the high-level signal at the fourth power supply terminal V4 will pull the signal of the first pull-down node PD1 high. However, because transistors 7 T7, 8 T8, 10 T10, and 11 T11 remain on, the signal of the first pull-down node PD1 will still be pulled low. Similarly, when the shift register is in the second display frame, transistor 9 T9 is turned off and transistor 12 T12 is turned on. Although transistor 12 T12 is on, the high-level signal at the fifth power supply terminal V5 will pull the signal of the second pull-down node PD2 high. However, because transistors 7 T7, 8 T8, 10 T10, and 11 T11 remain on, the signal of the second pull-down node PD2 will still be pulled low. Regardless of whether the shift register is in the first or second display frame, the first pull-down node PD1 and the second pull-down node PD2 remain low during the first stage.

[0202] In the second stage P12, i.e., the output stage, the clock signal terminal CLK is a high-level signal, while the signals at the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2, and the total reset signal terminal TRST are low-level signals. With the signal at the signal input terminal IN low-level, the first transistor T1, the seventh transistor T7, and the tenth transistor T10 are disconnected. Under the bootstrap effect of capacitor C, the pull-up node PU is pulled high, and the second transistor T2 and the third transistor T3 are turned on. The high-level signal of the clock signal terminal CLK is written to the first output terminal OUT1 and the second output terminal OUT2. The eighth transistor T8 and the eleventh transistor T11 are turned on, and the low-level signal of the first power supply terminal V1 is continuously written to the first pull-down node PD1 and the second pull-down node PD2. The first pull-down node PD1 and the second pull-down node PD2 remain low-level signals. The thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 are disconnected. During this phase, the signals of the pull-up node PU, the first output terminal OUT1, and the second output terminal OUT2 are high-level signals, while the signals of the first pull-down node PD1 and the second pull-down node PD2 are low-level signals.

[0203] In the second stage, when the shift register is in the first display frame, transistor T9 is turned on and transistor T12 is turned off. Although transistor T9 is on, the high-level signal at the fourth power supply terminal V4 will pull the signal of the first pull-down node PD1 high. However, because transistors T8 and T11 remain on, the signal of the first pull-down node PD1 is still pulled low. Similarly, when the shift register is in the second display frame, transistor T9 is turned off and transistor T12 is turned on. Although transistor T12 is on, the high-level signal at the fifth power supply terminal V5 will pull the signal of the second pull-down node PD2 high. However, because transistors T8 and T11 remain on, the signal of the second pull-down node PD2 is still pulled low. Regardless of whether the shift register is in the first or second display frame, the first pull-down node PD1 and the second pull-down node PD2 remain low in the second stage.

[0204] In the third stage P13, i.e. the reset stage, the first reset signal terminal RST1 and the second reset signal terminal RST2 are high-level signals, while the signal input terminal IN, the total reset signal terminal TRST, and the clock signal terminal CLK are low-level signals. The signals at the first reset signal terminal RST1 and the second reset signal terminal RST2 are high-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on. The low-level signal at the first power supply terminal V1 is written to the signal at the pull-up node PU, pulling the signal at pull-up node PU low. The low-level signal at the third power supply terminal V3 is written to the first output terminal OUT1, pulling the signal at the first output terminal OUT1 low. The signal at the signal input terminal IN is low-level. The first transistor T1, the seventh transistor T7, and the tenth transistor T10 are turned off. The pull-up node PU is low-level. The eighth transistor T8 and the eleventh transistor T11 are turned off. The first pull-down node PD1 and the second pull-down node PD2 are not pulled low by the low-level signal at the first power supply terminal V1. When the shift register is in the first display frame, the ninth transistor T9 is turned on. The high-level signal at the fourth power supply terminal V4 is written to the first pull-down node PD1. The thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are turned on. A low-level signal from power supply terminal V1 is written to pull-up node PU and second output terminal OUT2. A low-level signal from power supply terminal V3 is written to first output terminal OUT1. Twelfth transistor T12 is turned off. Second pull-down node PD2 maintains the low-level signal from the previous stage. Sixteenth transistor T16, seventeenth transistor T17, and eighteenth transistor T18 are turned off. Alternatively, when the shift register is in the second display frame, twelfth transistor T12 is turned on. A high-level signal from power supply terminal V5 is written to second pull-down node PD2. Sixteenth transistor T16, seventeenth transistor T17, and eighteenth transistor T18 are turned on. A low-level signal from power supply terminal V1 is written to pull-up node PU and second output terminal OUT2. A low-level signal from power supply terminal V3 is written to first output terminal OUT1. Ninth transistor T9 is turned off. First pull-down node PD1 maintains the low-level signal from the previous stage. Thirteenth transistor T13, fourteenth transistor T14, and fifteenth transistor T15 are turned off.

[0205] In the fourth stage P14, i.e., the first noise reduction stage, the clock signal CLK is high, while the signal input IN, the first reset signal RST1, the second reset signal RST2, and the total reset signal TRST are low. With the signal input IN low, the first transistor T1, the seventh transistor T7, and the tenth transistor T10 are off. The second power supply V2 or the signal input IN cannot be written to the pull-up node PU, and the pull-up node PU maintains the low level signal from the previous stage. The second transistor T2, the third transistor T3, the eighth transistor T8, and the eleventh transistor T11 are off, and the first pull-down node PD1 and the second pull-down node PD2 are not pulled low by the low level signal of the first power supply V1. When the shift register is in the first display frame, the ninth transistor T9 is on, and the high level signal of the fourth power supply V4 is written to the first pull-down node PD1. The thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are on, and the low level signal of the first power supply V1 is written to the pull-up node PU and the second output OUT2. The third power supply V3... The low-level signal of the first output terminal OUT1 is written, the twelfth transistor T12 is turned off, the second pull-down node PD2 maintains the low-level signal of the previous stage, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned off, or when the shift register is in the second display frame, the twelfth transistor T12 is turned on, the high-level signal of the fifth power supply terminal V5 is written to the second pull-down node PD2, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are turned on, the low-level signal of the first power supply terminal V1 is written to the pull-up node PU and the second output terminal OUT2, the low-level signal of the third power supply terminal V3 is written to the first output terminal OUT1, the ninth transistor T9 is turned off, the first pull-down node PD1 maintains the low-level signal of the previous stage, and the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are turned off.

[0206] In the fifth stage P15, i.e., the second noise reduction stage, the clock signal terminal CLK, the signal input terminal IN, the first reset signal terminal RST1, the second reset signal terminal RST2, and the total reset signal terminal TRST are all low-level signals. The signal input terminal IN is low-level, the first transistor T1, the seventh transistor T7, and the tenth transistor T10 are off, and the signal at the pull-up node PU remains low from the previous stage. The second transistor T2, the third transistor T3, the eighth transistor T8, and the eleventh transistor T11 are off, and the first pull-down node PD1 and the second pull-down node PD2 are not pulled low by the low-level signal at the first power supply terminal V1. When the shift register is in the first display frame, the ninth transistor T9 is turned on, the high-level signal at the fourth power supply terminal V4 is written to the first pull-down node PD1, and the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are turned on. The low-level signal at the first power supply terminal V1 is written to the pull-up node PU and the second output terminal OUT2, and the low-level signal at the third power supply terminal V3 is written to the first output terminal OUT2. T1, the twelfth transistor T12 is off, the second pull-down node PD2 maintains the low level signal of the previous stage, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are off, or when the shift register is in the second display frame, the twelfth transistor T12 is on, the high level signal of the fifth power supply terminal V5 is written to the second pull-down node PD2, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are on, the low level signal of the first power supply terminal V1 is written to the pull-up node PU and the second output terminal OUT2, the low level signal of the third power supply terminal V3 is written to the first output terminal OUT1, the ninth transistor T9 is off, the first pull-down node PD1 maintains the low level signal of the previous stage, the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are off.

[0207] The operation of the shift register also includes multiple fourth stages P14 and fifth stages P15, which work alternately.

[0208] The fourth stage P14 and the fifth stage P15 can ensure that the signals of the pull-up node PU, the first output terminal OUT1 and the second output terminal OUT2 of the shift register are always low-level signals, which can reduce the noise of the shift register and improve its reliability.

[0209] In an exemplary embodiment, the second electrode of at least one transistor in the node noise reduction sub-circuit is in a high voltage state for a long time, which causes the performance of at least one transistor in the node noise reduction sub-circuit to degrade or causes a sharp decay in the turn-on current of at least one transistor in the node noise reduction sub-circuit, affecting the performance of the shift register and reducing the display effect of the display product.

[0210] In an exemplary embodiment, the transistor provided in FIG4 may be at least one transistor in the node noise reduction sub-circuit, which may be the transistor provided in FIG4.

[0211] The display substrate provided in this disclosure has at least partial overlap between the orthographic projection of the second electrode of at least one transistor in the node noise reduction sub-circuit on the substrate and the orthographic projection of the third sub-connection portion on the substrate. That is, the side of the second electrode of at least one transistor in the node noise reduction sub-circuit near the channel portion overlaps with the third sub-connection portion. This results in a larger resistance of the active layer below the second electrode of at least one transistor in the node noise reduction sub-circuit, which is equivalent to having a resistor that can act as a voltage divider connected in series with the first electrode of at least one transistor in the node noise reduction sub-circuit. This increases the resistance of at least one transistor in the node noise reduction sub-circuit, reduces the current flowing through at least one transistor in the node noise reduction sub-circuit, and thus avoids the second electrode of at least one transistor in the node noise reduction sub-circuit being in a high voltage state for a long time. This improves the performance of at least one transistor in the node noise reduction sub-circuit or can avoid the sharp decay of the turn-on current in the first electrode of at least one transistor in the node noise reduction sub-circuit, thereby improving the performance of the shift register and the display effect of the display product.

[0212] Since the second electrode of at least one transistor in the node noise reduction sub-circuit is generally supplied with a negative voltage signal, and at least one transistor in the noise reduction sub-circuit is an N-type transistor that can only be turned on under a positive voltage signal, if the active layer connected to the first electrode of at least one transistor in the noise reduction sub-circuit includes a non-conductive region, at least one transistor in the node noise reduction sub-circuit cannot be turned on. Therefore, the active layer covered by the first electrode of at least one transistor in the node noise reduction sub-circuit of this disclosure is all conductive, which can ensure that at least one transistor in the node noise reduction sub-circuit can work normally.

[0213] In an exemplary embodiment, the number of pull-down nodes is at least one, the shift register also has an output signal terminal, and the transistor further includes a gate. The node noise reduction sub-circuit in the i-th stage shift register includes: a plurality of pull-up node noise reduction transistors; the gate of at least one pull-up node noise reduction transistor is electrically connected to one of the at least one pull-down nodes or the output signal terminal of the j-th stage shift register; the first terminal 13 of at least one pull-up node noise reduction transistor is electrically connected to the pull-up node; and the second terminal 14 of at least one pull-up node noise reduction transistor is electrically connected to the noise reduction power supply terminal, where j is a positive integer greater than i.

[0214] In an exemplary embodiment, the number of pull-down nodes is at least one, and the shift register also has an output signal terminal. The node noise reduction sub-circuit in the i-th stage shift register includes: a plurality of pull-down node noise reduction transistors; the gate of at least one pull-down node noise reduction transistor is electrically connected to a pull-up node or the output signal terminal of the k-th stage shift register; the first terminal 13 of at least one pull-down node noise reduction transistor is electrically connected to one of the at least one pull-down nodes; and the second terminal 14 of at least one pull-down node noise reduction transistor is electrically connected to a noise reduction power supply terminal, where k is a positive integer less than i.

[0215] In an exemplary embodiment, the number of pull-down nodes is at least one, and the shift register also has an output signal terminal. The node noise reduction sub-circuit in the i-th stage shift register includes: multiple pull-down node noise reduction transistors and multiple pull-up node noise reduction transistors. The gate of at least one pull-up node noise reduction transistor is electrically connected to one of the at least one pull-down nodes or the output signal terminal of the j-th stage shift register. The first terminal 13 of the at least one pull-up node noise reduction transistor is electrically connected to the pull-up node, and the second terminal 14 of the at least one pull-up node noise reduction transistor is electrically connected to the noise reduction power supply terminal, where j is a positive integer greater than i. The gate of at least one pull-down node noise reduction transistor is electrically connected to the pull-up node or the output signal terminal of the k-th stage shift register. The first terminal 13 of the at least one pull-down node noise reduction transistor is electrically connected to one of the at least one pull-down nodes, and the second terminal 14 of the at least one pull-down node noise reduction transistor is electrically connected to the noise reduction power supply terminal, where k is a positive integer less than i.

[0216] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with gate driving circuits, such as LCD, OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure is not limited thereto.

[0217] In an exemplary embodiment, when the display substrate is applied in an LCD display device, the display substrate is an array substrate, and the display substrate may further include at least one of a pixel electrode and a common electrode.

[0218] In an exemplary embodiment, when the display substrate is used in an OLED or QLED display device, the sub-pixel may include a pixel driving circuit and a light-emitting element. The pixel driving circuit may include a plurality of transistors and a storage capacitor. The pixel driving circuit may be disposed in a circuit structure layer. The display substrate may further include a light-emitting structure layer disposed on the side of the circuit structure layer away from the substrate. The light-emitting element is disposed in the light-emitting structure layer.

[0219] In an exemplary embodiment, the light-emitting element may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). The light-emitting element may include a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0220] The light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the drain electrode of the driving transistor in the pixel driving circuit through a via. The organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer 303. The organic light-emitting layer emits light of the corresponding color under the driving of the anode and the cathode.

[0221] In an exemplary embodiment, when the display substrate is used in an OLED or QLED display device, the display substrate may further include an encapsulation structure layer located on the side of the light-emitting structure layer away from the substrate. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0222] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In some exemplary embodiments, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0223] In an exemplary embodiment, when the display substrate is applied in a Micro LED or Mini LED display device, the display substrate can be a driving backplane.

[0224] This disclosure also provides a method for preparing a display substrate, configured to prepare the display substrate provided in any of the foregoing embodiments. The method for preparing the display substrate may include:

[0225] Step 100: Provide a substrate.

[0226] Step 200: Form multiple transistors on the substrate.

[0227] In an exemplary embodiment, step 200 may include:

[0228] Step 210: Form a raw semiconductor layer on the substrate using a first mask. The raw semiconductor layer includes: a channel portion, a first sub-connection portion, a third sub-connection portion, and a fifth sub-connection portion of at least one transistor.

[0229] Step 220: Form a first original insulating layer including a first via and a second via on the original semiconductor layer using a second mask, and form a second sub-connection portion, a first sub-auxiliary portion and a fourth sub-connection portion of at least one transistor on the original semiconductor layer.

[0230] Step 230: Form at least one transistor’s gate, first electrode, and second electrode on the first original insulating layer using a third mask.

[0231] Step 240: Using the gate, first electrode, and second electrode of at least one transistor as a mask, the original semiconductor layer and the first original insulating layer are processed to form an active layer including a second sub-auxiliary portion and a second auxiliary portion, as well as a first insulating layer.

[0232] Before step 210, before forming the original semiconductor layer on the substrate using a first mask, the method for fabricating the display substrate may further include:

[0233] A light-shielding layer is formed on the substrate using a fourth photomask;

[0234] A second insulating layer is formed on the light-shielding layer.

[0235] After step 200, the method for preparing the display substrate may further include: forming a third insulating layer on the conductive layer.

[0236] In order to test the performance of the transistors in the display substrate provided in this disclosure, the transistors in the display substrate provided in this disclosure are used as sample transistors, and the active layer of the transistor does not include the third sub-connection portion, and the second electrode portion of the transistor is covered by the second via is used as a reference transistor for testing.

[0237] Degradation tests were performed on the sample transistor and the reference transistor using pulse signals. The pulse signal period was 8.3 milliseconds, and the pulse width was 3.86 microseconds. Within each cycle, a high-voltage signal was applied to the gate and first electrode of the sample transistor and the reference transistor, respectively, for a duration of one pulse width. The total number of pulse widths was 100,000. The signal at the noise reduction power supply terminal had voltage values ​​of -20 volts and -35 volts.

[0238] In an exemplary embodiment, when the voltage value of the signal at the noise reduction power supply terminal is -20 volts, the voltage value of the high voltage signal applied to the gate and first terminal of the transistor is 20 volts, and at this time, the withstand voltage of the transistor is 40 volts.

[0239] In an exemplary embodiment, when the signal voltage at the noise reduction power supply terminal is -35 volts, the voltage of the high-voltage signal applied to the gate and first terminal of the transistor is 35 volts, and at this time, the transistor's withstand voltage is 70 volts.

[0240] Testing revealed that the reference transistor has a withstand voltage of 40 volts and a 90% attenuation of its conduction current. The sample transistor has a withstand voltage of 70 volts and a 20% attenuation of its conduction current. In other words, at least one transistor in the node noise reduction sub-circuit of the shift register in the display substrate provided in this embodiment can withstand a voltage of over 70 volts, and the attenuation of the conduction current of at least one transistor in the node noise reduction sub-circuit of the shift register is optimized to 20%. This ensures normal output of the shift register, significantly improves its reliability, and enhances the display effect of the display product.

[0241] In an exemplary embodiment, this disclosure also provides a display device, including: a display substrate provided in any of the foregoing embodiments.

[0242] In an exemplary embodiment, the display device can be a Liquid Crystal Display (LCD) or an Organic Light Emitting Diode (OLED) display device. This display device can be any product or component with display functionality, such as a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0243] In an exemplary embodiment, when the display device is an LCD display device, the display device may further include: a cell substrate disposed in conjunction with the display substrate provided in any of the foregoing embodiments, and a liquid crystal layer disposed between the display substrate and the cell substrate.

[0244] In an exemplary embodiment, when the display device is an LCD display device, the display device may further include a backlight module. The backlight module is disposed on the side of the display substrate away from the liquid crystal layer.

[0245] In an exemplary embodiment, pixel electrodes may be disposed on a display substrate, and common electrodes may be disposed on the display substrate and a cell substrate, without any limitation thereof.

[0246] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0247] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0248] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: A substrate and a plurality of transistors disposed on the substrate, each transistor comprising: a gate, an active layer, a first electrode, and a second electrode, wherein the active layer comprises: a channel portion, a first electrode connection portion, a second electrode connection portion, a first auxiliary portion, and a second auxiliary portion; the first auxiliary portion is connected to the channel portion and the first electrode connection portion respectively, the second auxiliary portion is connected to the channel portion and the second electrode connection portion respectively, the channel portion overlaps with the orthographic projection of the gate on the substrate, at least a portion of the first electrode connection portion is electrically connected to the first electrode, and at least a portion of the second electrode connection portion is electrically connected to the second electrode; The thickness of at least two of the channel portion, the first electrode connection portion, the second electrode connection portion, the first auxiliary portion, and the second auxiliary portion is different.

2. The display substrate according to claim 1, wherein, The first auxiliary part includes a first sub-auxiliary part and a second sub-auxiliary part, wherein the thickness of the first sub-auxiliary part is smaller than the thickness of the second sub-auxiliary part.

3. The display substrate according to claim 2, wherein, The first electrode connection portion includes: a first sub-connection portion and a second sub-connection portion; the second electrode connection portion includes: a third sub-connection portion, a fourth sub-connection portion and a fifth sub-connection portion. The thickness of at least one of the second sub-connecting portion and the fourth sub-connecting portion is less than the thickness of at least one of the channel portion, the first sub-connecting portion, the second sub-auxiliary portion, the second auxiliary portion, the third sub-connecting portion and the fifth sub-connecting portion, and greater than the thickness of the first sub-auxiliary portion.

4. The display substrate according to claim 3, wherein, The difference between the thickness of at least one of the channel portion, the first sub-connecting portion, the second sub-auxiliary portion, the second auxiliary portion, the third sub-connecting portion, and the fifth sub-connecting portion and the thickness of at least one of the second sub-connecting portion and the fourth sub-connecting portion is in the range of 10 nanometers to 40 nanometers.

5. The display substrate according to claim 3, wherein, The first electrode connection portion, the first auxiliary portion, the channel portion, the second auxiliary portion, and the second electrode connection portion are disposed in the same layer and arranged sequentially along the first direction; The second sub-connecting part is connected to the first sub-connecting part and the first sub-auxiliary part respectively, the third sub-connecting part is connected to the second auxiliary part and the fourth sub-connecting part respectively, and the fourth sub-connecting part is also connected to the fifth sub-connecting part.

6. The display substrate according to claim 5, wherein, The length of the third sub-connector along the first direction is greater than 0.2 micrometers.

7. The display substrate according to claim 5, wherein, The length of the first sub-auxiliary part along the first direction is greater than 0.3 micrometers.

8. The display substrate according to claim 1, wherein, The orthographic projection of the first electrode of at least one transistor on the substrate overlaps at least partially with the orthographic projection of the first electrode connection portion on the substrate, but does not overlap with the orthographic projection of the first auxiliary portion on the substrate; The orthographic projection of the second electrode of at least one transistor on the substrate at least partially overlaps with the orthographic projection of the second electrode connection portion on the substrate, but does not overlap with the orthographic projection of the second auxiliary portion on the substrate.

9. The display substrate according to claim 3, further comprising: A circuit structure layer disposed on the substrate, the circuit structure layer comprising: a semiconductor layer and a conductive layer; The semiconductor layer includes at least: an active layer for at least one transistor; The conductive layer includes at least: a gate, a first electrode, and a second electrode of at least one transistor.

10. The display substrate according to claim 9, wherein, The circuit structure layer further includes: a first insulating layer, which is disposed between the semiconductor layer and the conductive layer, and the first insulating layer includes: a first insulating structure, a second insulating structure, a third insulating structure and a fourth insulating structure; The orthographic projection of the first insulating structure on the substrate at least partially overlaps with the orthographic projection of the gate of at least one transistor on the substrate, and does not overlap with the orthographic projections of the first auxiliary portion and the second auxiliary portion of at least one transistor on the substrate; The orthographic projection of the second insulating structure on the substrate at least partially overlaps with the orthographic projection of the first sub-connection portion of at least one transistor on the substrate, but does not overlap with the orthographic projection of the second sub-connection portion of at least one transistor on the substrate; The orthographic projection of the third insulating structure on the substrate at least partially overlaps with the orthographic projection of the third sub-connection portion of at least one transistor on the substrate, but does not overlap with the orthographic projections of the second auxiliary portion and the fourth sub-connection portion of at least one transistor on the substrate. The orthographic projection of the fourth insulating structure on the substrate at least partially overlaps with the orthographic projection of the fifth sub-connection of at least one transistor on the substrate, but does not overlap with the orthographic projection of the fourth sub-connection of at least one transistor on the substrate.

11. The display substrate according to claim 10, wherein, The first insulating layer has a first via and a second via, and the orthographic projections of the first via and the second via on the substrate are respectively located on both sides of the orthographic projection of the gate of at least one transistor on the substrate. The first via exposes a second sub-connection portion and a first sub-auxiliary portion, and the second via exposes a fourth sub-connection portion. The area of ​​the orthographic projection of the first via on the substrate is different from the area of ​​the orthographic projection of the second via on the substrate.

12. The display substrate according to claim 11, wherein, The first via is provided with at least a portion of the first electrode of at least one transistor, and the second via is provided with at least a portion of the second electrode of at least one transistor; The orthographic projection of the first electrode of at least one transistor located in the first via onto the substrate covers the orthographic projection of the second sub-connection onto the substrate, and does not overlap with the orthographic projection of the first sub-auxiliary onto the substrate; The orthographic projection of the second electrode of at least one transistor located within the second via onto the substrate overlaps the orthographic projection of the fourth sub-connection onto the substrate.

13. The display substrate according to claim 1, wherein, The conductivity of the channel portion is less than that of the first auxiliary portion and the second auxiliary portion.

14. The display substrate according to claim 13, wherein, The first auxiliary portion and the second auxiliary portion are conductor portions, and the channel portion is a semiconductor portion.

15. The display substrate according to claim 3, wherein, The conductivity of the second sub-connector is greater than that of the first sub-connector, and the conductivity of the fourth sub-connector is greater than that of at least one of the third and fifth sub-connectors.

16. The display substrate according to claim 15, wherein, The second sub-connection portion and the fourth sub-connection portion are conductor portions, and the first sub-connection portion, the third sub-connection portion and the fifth sub-connection portion are semiconductor portions.

17. The display substrate according to claim 1, wherein, The display substrate has a display area and a non-display area disposed on at least one side of the display area; The transistor is located in at least one of the display area and the non-display area.

18. The display substrate according to claim 17, wherein, The non-display area is provided with a shift register, which has a pull-up node, a pull-down node, and a noise reduction power supply terminal. The shift register includes a node noise reduction sub-circuit, which is electrically connected to the noise reduction power supply terminal and at least one of the pull-up node and the pull-down node, and is configured to provide the noise reduction power supply terminal signal to at least one of the pull-up node and the pull-down node. The transistor is located in the node noise reduction sub-circuit, and the second terminal of at least one transistor in the node noise reduction sub-circuit is electrically connected to the pull-up node or the pull-down node.

19. The display substrate according to claim 18, wherein, The number of the pull-down nodes is at least one, and the shift register also has an output signal terminal; The node noise reduction sub-circuit in the i-th stage shift register includes: multiple pull-up node noise reduction transistors, the gate of at least one pull-up node noise reduction transistor is electrically connected to one of the nodes in at least one pull-down node or the output signal terminal of the j-th stage shift register, the second terminal of at least one pull-up node noise reduction transistor is electrically connected to the pull-up node, and the first terminal of at least one pull-up node noise reduction transistor is electrically connected to the noise reduction power supply terminal, where j is a positive integer greater than i.

20. The display substrate according to claim 18, wherein, The number of the pull-down nodes is at least one, and the shift register also has an output signal terminal; The node noise reduction sub-circuit in the i-th stage shift register includes: multiple pull-down node noise reduction transistors, the gate of at least one pull-down node noise reduction transistor is electrically connected to the pull-up node or the output signal terminal of the k-th stage shift register, the second terminal of at least one pull-down node noise reduction transistor is electrically connected to one of the at least one pull-down nodes, and the first terminal of at least one pull-down node noise reduction transistor is electrically connected to the noise reduction power supply terminal, where k is a positive integer less than i.

21. The display substrate according to claim 18, wherein, The number of the pull-down nodes is at least one, and the shift register also has an output signal terminal; The node noise reduction sub-circuit in the i-th stage shift register includes: multiple pull-down node noise reduction transistors and multiple pull-up node noise reduction transistors; The gate of at least one pull-up node noise reduction transistor is electrically connected to one of the nodes of at least one pull-down node or the output signal terminal of the j-th stage shift register, the second terminal of at least one pull-up node noise reduction transistor is electrically connected to the pull-up node, and the first terminal of at least one pull-up node noise reduction transistor is electrically connected to the noise reduction power supply terminal, where j is a positive integer greater than i. The gate of at least one pull-down node noise reduction transistor is electrically connected to the output signal terminal of the pull-up node or the k-th stage shift register, the second terminal of at least one pull-down node noise reduction transistor is electrically connected to one of the nodes of at least one pull-down node, and the first terminal of at least one pull-down node noise reduction transistor is electrically connected to the noise reduction power supply terminal, where k is a positive integer less than i.

22. The display substrate according to claim 10, wherein, The circuit structure layer further includes: a second insulating layer, a third insulating layer, and a light-shielding layer; The second insulating layer is located on the side of the substrate closer to the semiconductor layer, the light-shielding layer is located on the side of the second insulating layer closer to the substrate, and the third insulating layer is located on the side of the conductive layer away from the substrate.

23. A display device, comprising: The display substrate as described in any one of claims 1 to 22.

24. A method for preparing a display substrate, configured to prepare a display substrate as described in any one of claims 1 to 22, the method comprising: Provide a base; Multiple transistors are formed on the substrate.

25. The method according to claim 24, wherein, The formation of multiple transistors on the substrate includes: A raw semiconductor layer is formed on a substrate using a first mask, the raw semiconductor layer comprising: a channel portion of at least one transistor, a first sub-connection portion, a third sub-connection portion, and a fifth sub-connection portion; A first original insulating layer including a first via and a second via is formed on the original semiconductor layer through a second mask, and a second sub-connection portion, a first sub-auxiliary portion and a fourth sub-connection portion of at least one transistor are formed on the original semiconductor layer. At least one transistor's gate, first electrode, and second electrode are formed on the first original insulating layer using a third mask; The original semiconductor layer and the first original insulating layer are processed using the gate, first electrode and second electrode of at least one transistor as masks to form an active layer including a second sub-auxiliary portion and a second auxiliary portion, and a first insulating layer.

26. The method of claim 25, wherein, Before forming the original semiconductor layer on the substrate using a first mask, the method further includes: A light-shielding layer is formed on the substrate using a fourth photomask; A second insulating layer is formed on the light-shielding layer; After forming a plurality of transistors on the substrate, the method further includes: A third insulating layer is formed on the conductive layer.

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