Pressure sensor and preparation method therefor

Abstract

A pressure sensor, relating to the technical field of sensors. The pressure sensor comprises a first substrate (21) and a second substrate (22) arranged opposite to each other, and a cavity (23) located between the first substrate (21) and the second substrate (22). The first substrate (21) comprises a pressure-sensitive film (211), and bonding rings (212), piezoresistors (213) and conductive columns (214) which are arranged on the side of the pressure-sensitive film (211) close to the second substrate (22). In the orthographic projection on the second substrate (22), each piezoresistor (213) is located within the range of the cavity (23) and close to the edge of the cavity (23), the corresponding bonding rings (212) are arranged on the side of the piezoresistor (213) distant from the center of the cavity (23), the bonding rings (212) are at least partially adjacent to the piezoresistor (213), and the piezoresistor (213) is connected to the corresponding conductive column (214). In a direction in which the first substrate (21) points to the second substrate (22), the height of the bonding rings (212) is greater than that of the piezoresistors (213). Also disclosed is a preparation method for the pressure sensor.

Description

Pressure sensor and its fabrication method Technical Field

[0001] This disclosure relates to the field of sensor technology, and in particular to a pressure sensor and a method for its fabrication. Background Technology

[0002] A pressure sensor is a device that converts pressure signals into electrical signals. It can be mainly classified into four types: piezoresistive, capacitive, resonant, and piezoelectric. Among these, silicon pressure sensors are the most widely used type due to their simple manufacturing process, low cost, high reliability, and compatibility with CMOS technology.

[0003] Overview

[0004] This disclosure provides a pressure sensor, including a first substrate and a second substrate disposed opposite to each other, and a body cavity located between the first substrate and the second substrate;

[0005] The first substrate includes a pressure-sensitive film, and a bonding ring, a varistor, and a conductive post disposed on the side of the pressure-sensitive film near the second substrate. In the orthographic projection on the second substrate, the varistor is located within the cavity and is disposed near the edge of the cavity. The bonding ring is disposed on the side of the varistor away from the center of the cavity. The bonding ring is at least partially adjacent to the varistor. The varistor is connected to the conductive post.

[0006] In the direction from the first substrate to the second substrate, the height of the bonding ring is greater than the height of the varistor.

[0007] In some embodiments, the varistor, the bonding ring, and the conductive post are made of the same material.

[0008] In some embodiments, the ratio of the height of the varistor to the height of the bonding ring is greater than or equal to one-tenth and less than or equal to one-twentieth.

[0009] In some embodiments, the varistor includes two first line resistors disposed opposite each other along a first direction and two second line resistors disposed opposite each other along a second direction, wherein the second line resistors are respectively cross-connected to the two first line resistors, and the first line resistors are respectively cross-connected to the two second line resistors, and the first direction and the second direction intersect each other;

[0010] The first line resistance and the second line resistance have different projected areas on the second substrate. When the pressure-sensitive membrane is not subjected to external pressure, the resistance values ​​of the first line resistance and the second line resistance are the same.

[0011] In some embodiments, the second line stop includes a first sub-segment, a second sub-segment, and a third sub-segment. The first sub-segment is connected between the first line stop and the second sub-segment, and the third sub-segment is connected between two adjacent second sub-segments. The extension direction of the second sub-segment is parallel to the extension direction of the first line stop, and the extension directions of the first sub-segment and the third sub-segment intersect the extension direction of the second sub-segment.

[0012] In some embodiments, the main material of the varistor is silicon crystal, and the extension directions of the second sub-segment and the first line resistance are parallel to the silicon crystal. <110> Crystal orientation.

[0013] In some embodiments, the conductive post and the varistor are connected by a connecting line, and the connection point between the connecting line and the varistor is located at the intersection of the first line resistance and the second line resistance; and

[0014] At the intersection of the first line resistor and the second line resistor, the conductive pillars are spaced apart between the varistor and the bonding ring; at the non-intersection of the first line resistor and the second line resistor, the varistor and the bonding ring are arranged adjacent to each other.

[0015] In some embodiments, the bonding ring is a closed ring structure that surrounds the center of the body cavity.

[0016] In some embodiments, the second substrate includes:

[0017] The second substrate, lead posts, redistribution layer, isolation layer, and solder are arranged in the direction from the first substrate to the second substrate. The lead posts are disposed through the second substrate. The end of the lead post near the first substrate abuts against the conductive post. The end of the lead post away from the first substrate overlaps with the redistribution layer. The isolation layer is disposed on the side of the redistribution layer away from the second substrate. The solder is disposed on the side of the isolation layer away from the second substrate. The surface of the second substrate near the first substrate abuts against the bonding ring.

[0018] In some embodiments, the longitudinal cross-sectional shape of the lead post is trapezoidal, and the long side of the trapezoid is disposed close to the redistribution layer, wherein the longitudinal cross-section is the cross-section of the lead post perpendicular to the second substrate.

[0019] In some embodiments, the angle between the long side and the hypotenuse of the trapezoid is greater than or equal to 80° and less than or equal to 90°.

[0020] In some embodiments, the surface of the pressure-sensitive membrane facing away from the second substrate is planar.

[0021] This disclosure provides a method for fabricating a pressure sensor, comprising:

[0022] A first substrate and a second substrate are provided. The first substrate includes a first substrate, and a varistor and a conductive post disposed on one side surface of the first substrate. The varistor is connected to the conductive post. The second substrate includes a second substrate and a lead hole disposed through the second substrate. The lead hole is used to dispose of the lead post.

[0023] The first substrate and the second substrate are bonded together to form a cavity between the first substrate and the second substrate. The varistor and the conductive post are disposed close to the second substrate. The lead post overlaps with the conductive post. In the orthographic projection on the second substrate, the varistor is located within the cavity and is disposed close to the edge of the cavity.

[0024] A pressure sensor is obtained by using a dry process to thin the surface of the first substrate away from the second substrate. The thinned first substrate is the pressure-sensing film of the pressure sensor, and the surface of the pressure-sensing film away from the second substrate is planar.

[0025] In some embodiments, after the step of performing overall thinning of the surface of the first substrate away from the second substrate using a dry process, the method further includes:

[0026] The surface of the pressure-sensitive film facing away from the second substrate is partially etched to form a pressure-guiding cavity. In the orthogonal projection on the second substrate, the varistor is located within the range of the pressure-guiding cavity and is disposed close to the edge of the pressure-guiding cavity.

[0027] This disclosure provides a method for fabricating a pressure sensor, comprising:

[0028] A first substrate and a second substrate are provided. The first substrate includes a first substrate and a conductive post disposed on one side surface of the first substrate. The conductive post is connected to the first substrate. A first insulating layer is disposed on the surface of the conductive post away from the first substrate. The first insulating layer disposed on the conductive post has an opening. The second substrate includes a second substrate and a lead hole disposed through the second substrate. The lead hole is used to dispose of the lead post. The lead post is insulated from the second substrate.

[0029] The first substrate and the second substrate are bonded together to form a cavity between the first substrate and the second substrate. The conductive post is disposed close to the second substrate, and the lead post is connected to the conductive post through the opening.

[0030] A pressure sensor is obtained by using a dry process to thin the surface of the first substrate away from the second substrate. The thinned first substrate is the pressure-sensing membrane of the pressure sensor. The pressure-sensing membrane, the conductive pillar, and the first insulating layer constitute the first capacitor plate of the pressure sensor. The second substrate constitutes the second capacitor plate of the pressure sensor. The surface of the pressure-sensing membrane away from the second substrate is planar.

[0031] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below.

[0032] Brief description of the attached diagram

[0033] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the scale in the drawings is for illustration only and does not represent the actual scale.

[0034] Figure 1 illustrates a schematic cross-sectional structure of a pressure sensor in the related art;

[0035] Figure 2 illustrates, by way of example, a cross-sectional structural schematic diagram of a pressure sensor provided in this disclosure;

[0036] Figure 3 illustrates a schematic diagram of the planar structure of the first substrate;

[0037] Figure 4 shows an example of the equivalent circuit diagram of a varistor;

[0038] Figure 5 illustrates an exemplary schematic diagram of the fabrication process of the first type of pressure sensor;

[0039] Figure 6 illustrates a cross-sectional structural diagram of another pressure sensor;

[0040] Figure 7 illustrates an exemplary fabrication process for another pressure sensor;

[0041] Figure 8 illustrates a cross-sectional structural schematic diagram of yet another pressure sensor;

[0042] Figure 9 illustrates, for example, a schematic diagram of the fabrication process of another pressure sensor.

[0043] Detailed description

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0045] Figure 1 shows a cross-sectional view of a pressure sensor in the related art. As shown in Figure 1, the pressure sensor includes a pressure-sensing membrane 01, a piezoresistive resistor 02 located on one side of the pressure-sensing membrane 01, and a pressure-guiding groove 03 located on the side of the pressure-sensing membrane 01 opposite to and recessed towards the piezoresistive resistor 02. The bottom edge of the pressure-guiding groove 03 is the area of ​​greatest stress in the pressure sensor, i.e., the stress concentration region 04. To improve detection sensitivity, the orthographic projections of the piezoresistive resistor 02 and the stress concentration region 04 on the sensing membrane 01 need to overlap. However, since the piezoresistive resistor 02 and the pressure-guiding groove 03 forming the stress concentration region 04 are located on opposite sides of the pressure-sensing membrane 01, their alignment requires a back-alignment process, resulting in poor alignment accuracy and thus affecting the sensitivity and other performance characteristics of the pressure sensor.

[0046] This disclosure provides a pressure sensor, as shown in FIG2, which includes a first substrate 21 and a second substrate 22 disposed opposite to each other, and a body cavity 23 located between the first substrate 21 and the second substrate 22.

[0047] As shown in Figure 2, the first substrate 21 includes a pressure-sensitive film 211, and a bonding ring 212, a varistor 213, and a conductive post 214 disposed on the side of the pressure-sensitive film 211 near the second substrate 22. As shown in Figure 3, in the orthographic projection on the second substrate 22, the varistor 213 is located within the cavity 23 and is disposed near the edge of the cavity 23. The bonding ring 212 is disposed on the side of the varistor 213 away from the center of the cavity 23. The bonding ring 212 and the varistor 213 are at least partially adjacent to each other. The varistor 213 is connected to the conductive post 214.

[0048] As shown in Figure 2, in the direction from the first substrate 21 to the second substrate 22, the height of the bonding ring 212 is greater than the height of the varistor 213.

[0049] In actual use, when pressure is applied to the surface of the pressure-sensitive diaphragm 211 away from the second substrate 22, the pressure-sensitive diaphragm 211 deforms. This deformation is further transmitted to the piezoresistor 213, causing a change in the resistance value of the piezoresistor 213, thereby converting the pressure signal into an electrical signal. Finally, the electrical signal is transmitted out by the conductive post 214.

[0050] The cavity 23 provides deformation space for the pressure-sensitive membrane 211 and the piezoresistor 213. In the orthographic projection on the second substrate 22, the area in the pressure-sensitive membrane 211 that overlaps with the cavity 23 is a deformable area, that is, an area that can deform in response to external pressure, as shown in the dashed box in Figure 2.

[0051] Because the height of the bonding ring 212 is greater than the height of the varistor 213, the region of the pressure-sensitive diaphragm 211 closest to the bonding ring 212 experiences the greatest stress when pressure is applied to it; this is the stress concentration region. By placing the varistor 213 at least partially adjacent to the bonding ring 212, the varistor 213 is positioned within the stress concentration region, thus improving the sensitivity of the pressure sensor.

[0052] The phrase "the varistor 213 and the bonding ring 212 are arranged adjacently" means that no other components are placed between the varistor 213 and the bonding ring 212 in the area where the varistor 213 and the bonding ring 212 are arranged adjacently, and the two are arranged close to each other.

[0053] In this disclosure, since the piezoresistive 213 and the bonding ring 212 forming the stress concentration region are located on the same side of the pressure-sensitive membrane 211, the alignment between the piezoresistive 213 and the bonding ring 212 does not require a back alignment process, and the alignment accuracy between the two can reach below 0.5μm, which can greatly improve the sensitivity and linearity of the pressure sensor.

[0054] In addition, since the varistor 213 is located in the cavity 23 formed by the first substrate 21 and the second substrate 22, the influence of the external environment can be reduced, the risk of electrical performance drift or failure of the varistor 213 can be reduced, and the environmental adaptability and reliability of the pressure sensor can be improved.

[0055] The bonding ring 212 is used to bond the pressure-sensitive film 211 to the second substrate 22.

[0056] For example, the pressure value inside the body cavity 23 is the reference pressure for the pressure sensor to measure the pressure. When the external pressure value is equal to the pressure value inside the body cavity 23, the output of the pressure sensor is zero. When the external pressure is greater than the pressure inside the body cavity 23, the output of the pressure sensor is the external atmospheric pressure minus the pressure inside the body cavity 23.

[0057] Figure 2 is a schematic diagram of the cross-sectional structure of the pressure sensor shown in Figure 3 along AA'.

[0058] For example, as shown in FIG2, in the direction from the first substrate 21 to the second substrate 22, the bonding ring 212 and the conductive post 214 are approximately at the same height.

[0059] For example, as shown in FIG2, the bonding ring 212, the conductive post 214 and the varistor 213 are all arranged to protrude from the pressure-sensitive film 211.

[0060] For example, as shown in FIG2, when the pressure-sensitive membrane 211 is not subjected to external pressure, the height of the body cavity 23 is equal to the height of the bonding ring 212.

[0061] For example, the varistor 213, bonding ring 212, and conductive post 214 are made of the same material.

[0062] For example, the main materials of the varistor 213, the bonding ring 212, and the conductive post 214 are all silicon-based materials.

[0063] For example, the ratio of the height of the varistor 213 to the height of the bonding ring 212 is greater than or equal to one-tenth and less than or equal to one-twentieth.

[0064] For example, the sheet resistance of the varistor 213 is ≤1000Ω / square or ≤100Ω / square, for example ≥5Ω / square.

[0065] For example, as shown in FIG3, the varistor 213 is a closed ring structure that surrounds the center of the cavity 23.

[0066] For example, as shown in FIG3, the orthogonal projection of the varistor 213 on the second substrate 22 is a centrally symmetrical structure, with the center of symmetry being the center of the cavity 23.

[0067] In this disclosure, the height of the bonding ring 212 is the dimension of the bonding ring 212 in the direction from the first substrate 21 to the second substrate 22, the height of the varistor 213 is the dimension of the varistor 213 in the direction from the first substrate 21 to the second substrate 22, the height of the conductive post 214 is the dimension of the conductive post 214 in the direction from the first substrate 21 to the second substrate 22, and the height of the cavity 23 is the dimension of the cavity 23 in the direction from the first substrate 21 to the second substrate 22.

[0068] In some embodiments, as shown in FIG3, the varistor 213 includes two first line resistors 31 disposed opposite to each other along a first direction f1, and two second line resistors 32 disposed opposite to each other along a second direction f2. The second line resistors 32 are respectively cross-connected to the two first line resistors 31, and the first line resistors 31 are respectively cross-connected to the two second line resistors 32. The first direction f1 and the second direction f2 intersect each other.

[0069] For example, as shown in Figure 3, the first direction f1 and the second direction f2 are perpendicular to each other.

[0070] For example, as shown in FIG3, the first line resistor 31 and the second line resistor 32 have different projected areas on the second substrate 22. When the pressure-sensitive film 211 is not subjected to external pressure, the resistance values ​​of the first line resistor 31 and the second line resistor 32 are the same.

[0071] For example, as shown in FIG3, the extension direction of the first line stop 31 is the second direction f2.

[0072] In order to make the resistance values ​​of the first line resistor 31 and the second line resistor 32 the same, for example, as shown in FIG3, in the orthographic projection on the second substrate 22, the second line resistor 32 has a bent portion WZ that bends toward the center of the body cavity 23. The bent portion WZ can also be bent away from the center of the body cavity 23, which is not limited in this disclosure.

[0073] In some embodiments, as shown in FIG3, the second line stop 32 includes a first sub-segment XD1, a second sub-segment XD2, and a third sub-segment XD3. The first sub-segment XD1 is connected between the first line stop 31 and the second sub-segment XD2, and the third sub-segment XD3 is connected between two adjacent second sub-segments XD2. The extension direction of the second sub-segment XD2 is parallel to the extension direction of the first line stop 31, and the extension directions of the first sub-segment XD1 and the third sub-segment XD3 intersect with the extension direction of the second sub-segment XD2.

[0074] As shown in Figure 3, the two second sub-segments XD2 and the third sub-segment XD3 connecting the two second sub-segments XD2 constitute the bent portion WZ that bends toward the center of the body cavity 23.

[0075] In some embodiments, the main material of the varistor 213 is silicon crystal, and the extension directions of the second sub-segment XD2 and the first line resistor 31 are parallel to the silicon crystal. <110> Crystal orientation. Among them, parallel to... <110> The second sub-segment XD2 and the first line resistance 31, which are set in the crystal orientation, can generate increased resistance under pressure, thereby further improving the sensitivity of the pressure sensor.

[0076] For example, as shown in FIG3, the extension direction of the first sub-segment XD1 and the first line stop 31 is the second direction f2, and the extension direction of the second sub-segment XD2 and the third sub-segment XD3 is the first direction f1.

[0077] In some embodiments, as shown in FIG3, the conductive post 214 and the varistor 213 are connected by a connecting line 33, and the connection point of the connecting line 33 and the varistor 213 is located at the intersection of the first line resistor 31 and the second line resistor 32.

[0078] Referring to Figure 4, the equivalent circuit of the varistor 213 is shown. This equivalent circuit is a Wheatstone bridge. The resistance values ​​of the two first line resistors 31 are R1 and R3, and the resistance values ​​of the two second line resistors 32 are R2 and R4. R1, R2, R3, and R4 constitute the four arm resistors of the Wheatstone bridge. The two conductive posts 214 located on a diagonal line are connected to V... in+ and V in- The two conductive posts 214 located on the other diagonal are respectively connected to V out+ and V out- The input voltage V of the Wheatstone bridge in =V in+ -V in- The output voltage V of the Wheatstone bridge out =V out+ -V out- .

[0079] When the pressure-sensitive diaphragm 211 is not subjected to external pressure, R1 = R2 = R3 = R4 = R. When external pressure is applied to the pressure-sensitive diaphragm 211, the resistances R1 and R3 decrease by ΔR, meaning their resistances become R - ΔR, while the resistances R2 and R4 increase by ΔR, meaning their resistances become R + ΔR. Ultimately, this causes V to... out A change has occurred. V out The calculation formula is as follows:

[0080] According to the above calculation formula, V out The change in resistance is proportional to the change in resistance ΔR, which is determined by the pressure value applied to the pressure-sensitive diaphragm 211, thus converting the pressure signal into a voltage signal.

[0081] For example, as shown in FIG3, at the intersection of the first line resistor 31 and the second line resistor 32, the conductive post 214 is spaced between the varistor 213 and the bonding ring 212, and at the non-intersection of the first line resistor 31 and the second line resistor 32, the varistor 213 and the bonding ring 212 are arranged adjacent to each other.

[0082] For example, as shown in Figure 3, the bonding ring 212 is a closed ring structure that surrounds the center of the cavity 23. This forms a sealed cavity 23, which helps maintain a vacuum environment within the cavity 23. Of course, the bonding ring 212 can also be a non-closed structure, corresponding to an open cavity 23.

[0083] For example, as shown in FIG3, the orthographic projection of the bonding ring 212 on the second substrate 22 is a centrally symmetrical structure, with the center of symmetry being the center of the cavity 23.

[0084] For example, as shown in FIG2, the pressure-sensitive film 211 includes a silicon substrate 2111 and a silicon-based insulating layer 2112 disposed between the silicon substrate 2111 and the varistor 213. The silicon-based insulating layer 2112 may be a silicon oxide insulating layer, a silicon nitride insulating layer or other silicon-based insulating materials, and this disclosure does not specifically limit it.

[0085] In some embodiments, as shown in FIG2, the second substrate 22 includes: a second substrate 221, lead posts 222, a redistribution layer RDL, an isolation layer UBM, and solder SD. In the direction from the first substrate 21 to the second substrate 22, the lead posts 222 are disposed through the second substrate 221. The end of the lead post 222 near the first substrate 21 abuts against the conductive post 214, and the end of the lead post 222 away from the first substrate 21 overlaps with the redistribution layer RDL. The isolation layer UBM is disposed on the side of the redistribution layer RDL away from the second substrate 221, and the solder SD is disposed on the side of the isolation layer UBM away from the second substrate 221. The surface of the second substrate 221 near the first substrate 21 abuts against the bonding ring 212.

[0086] For example, the second substrate 221 may be a glass substrate or a silicon substrate, and this disclosure does not limit it to either.

[0087] For example, the main material of the lead post 222 is a metal material, or it can be low-resistivity silicon, etc., and this disclosure does not limit it.

[0088] As shown in Figure 2, lead post 222 is used to conduct the electrical signal of conductive post 214 to the redistribution layer RDL. The redistribution layer RDL is used to transmit the electrical signal of lead post 222 to the isolation layer UBM. The isolation layer UBM is disposed between the redistribution layer RDL and the solder SD, serving as a bonding layer for interconnecting the redistribution layer RDL and the solder SD. It is used to transmit the electrical signal of the isolation layer UBM to the solder SD and also to prevent the diffusion of solder SD atoms to the redistribution layer RDL. The solder SD is the input or output port of the pressure sensor. During packaging, the solder SD also serves as a bonding structure for flip-chip bonding with the packaging substrate.

[0089] In some embodiments, as shown in FIG2, the longitudinal cross-sectional shape of the lead post 222 is trapezoidal, and the long side of the trapezoid is located close to the redistribution layer RDL. The longitudinal cross-section is the cross-section of the lead post 222 perpendicular to the second substrate 221.

[0090] In some implementations, as shown in Figure 2, the angle θ between the long side and the hypotenuse of the trapezoid is greater than or equal to 80° and less than or equal to 90°.

[0091] In some embodiments, as shown in FIG2, the surface of the pressure-sensitive film 211 facing away from the second substrate 22 is planar.

[0092] In practical applications, sensitivity and linearity are two important performance indicators for pressure sensors. Sensitivity is directly proportional to the thickness of the pressure-sensing diaphragm 211, while linearity is inversely proportional. Therefore, to simultaneously ensure both sensitivity and linearity, the thickness tolerance of the pressure-sensing diaphragm 211 is generally required to be within ±3 μm. However, in related technologies, a wet etching process is typically used to thin the pressure-sensing diaphragm 211, controlling its thickness by adjusting the etching time. Since the thickness of the pressure-sensing diaphragm 211 cannot be detected during wet etching, multiple etching and measurement processes are required to strictly control its thickness. This results in low fabrication efficiency and poor thickness accuracy for the pressure-sensing diaphragm 211.

[0093] To address the aforementioned problems, referring to Figures 5 and 7, this disclosure provides a method for fabricating a pressure sensor, comprising:

[0094] Step S01: Provide a first substrate 21 and a second substrate 22. The first substrate 21 includes a first substrate 51, and a varistor 213 and a conductive post 214 disposed on one side surface of the first substrate 51. The varistor 213 is connected to the conductive post 214. The second substrate 22 includes a second substrate 221, and a lead hole HY disposed through the second substrate 221. The lead hole HY is used to set the lead post 222.

[0095] Step S02: Bond the first substrate 21 and the second substrate 22 to form a cavity 23 between the first substrate 21 and the second substrate 22. The varistor 213 and the conductive post 214 are disposed close to the second substrate 22. The lead post 222 overlaps with the conductive post 214. In the orthographic projection on the second substrate 22, the varistor 213 is located within the cavity 23 and is disposed close to the edge of the cavity 23.

[0096] Step S03: Using a dry process, the surface of the first substrate 51 facing away from the second substrate 22 is thinned as a whole to obtain a pressure sensor. The thinned first substrate 51 is the pressure-sensing film 211 of the pressure sensor, and the surface of the pressure-sensing film 211 facing away from the second substrate 22 is planar.

[0097] The piezoresistive pressure sensor provided in any of the above embodiments can be prepared using the preparation method provided in this disclosure.

[0098] Because the dry process equipment has an online thickness measurement function, the thickness of the pressure-sensitive membrane 211 can be precisely controlled. The thickness accuracy of the pressure-sensitive membrane 211 thinned by the dry process can be controlled within ±1μm, which is more than 3 times higher than that of the wet etching process. In addition, the average thinning speed of the dry process is greater than 20μm / min, and its efficiency is 20 times that of the traditional wet etching process.

[0099] The preparation method provided in this disclosure, which uses a dry process to thin the first substrate 51 to form a pressure-sensitive film 211, is beneficial to improving the thickness accuracy, sensitivity, linearity and production efficiency of the pressure-sensitive film 211.

[0100] For example, dry processes may include grinding processes, etc.

[0101] In some embodiments, as shown in FIG7, after step S03, the method may further include: partially etching the surface of the pressure-sensitive film 211 away from the second substrate 22 to form a pressure-sensing cavity 71, wherein the varistor 213 is located within the range of the pressure-sensing cavity 71 and is disposed close to the edge of the pressure-sensing cavity 71 in the orthogonal projection on the second substrate 22.

[0102] For example, the pressure chamber 71 can be formed using a dry etching or wet etching process.

[0103] In practice, a dry process can be used to thin the first substrate 51 as a whole, and then locally etch to form the pressure-sensing cavity 71. This can shorten the etching time, improve production efficiency and the thickness accuracy of the pressure-sensing film 211.

[0104] As shown in Figure 6, the orthographic projections of the pressure-applying cavity 71 and the body cavity 23 on the second substrate 22 at least partially overlap.

[0105] For example, the method for fabricating the pressure sensor shown in Figure 2 specifically includes the following steps:

[0106] Step 1: Fabrication of conductive pillar 214 and bonding ring 212, as shown in Figure 5a. Specifically, silicon-on-insulator (SOI) substrate can be used. First, the top silicon layer in the SOI is implanted (e.g., boron ions are implanted), and then the implanted SOI is annealed. After annealing, the sheet resistance of the varistor 213 is <100Ω / square. Then, the top silicon layer can be photolithographically and etched to form the initial resistor 52, conductive pillar 214, and bonding ring 212 located on one side of the first substrate 51. The initial resistor 52 and the bonding ring 212 have the same height.

[0107] Step 2: Fabrication of varistor 213, as shown in Figure 5b. The initial resistor 52 is etched using photolithography and etching to obtain varistor 213, so that the height of varistor 213 is lower than the height of conductive pillar 214 and bonding ring 212, thus obtaining the first substrate 21.

[0108] Step 3: Fabrication of the lead hole HY, as shown in Figure 5c. BF33 or 7740 glass can be selected as the second substrate 221. Laser-induced etching technology is used to pattern the glass to form the lead hole HY. The diameter of the lead hole HY is, for example, 10-1000 μm. Specifically, the area in the glass where the lead hole HY needs to be formed can first be modified using a laser. That is, the laser scans the area where the hole needs to be formed to create a modified area. Then, wet etching is used to etch the modified area into the lead hole HY.

[0109] Step 4: The first substrate 21 and the second substrate 221 are bonded, as shown in e of Figure 5. Specifically, the first substrate 21 and the second substrate 221 can be bonded anolytically. During the bonding process, the first substrate 21 is connected to the positive terminal of the power supply, and the second substrate 221 is connected to the negative terminal of the power supply. The voltage is 200-1500V and the temperature is 100-500℃.

[0110] Step 5: Fabrication of lead post 222. Copper is filled into the lead hole HY to form lead post 222, as shown in Figure 5f. Specifically, an adhesive layer and an electroplating layer can be sequentially deposited on the inner wall of the lead hole HY using PVD or CVD processes. The adhesive layer is, for example, titanium or chromium, with a thickness of, for example, 20–50 nm. The electroplating layer is, for example, copper. The electroplating layer fills the lead hole HY completely to obtain lead post 222.

[0111] Step 6: Redistribution layer (RDL) fabrication, as shown in g of Figure 5. Specifically, an adhesion layer and an electroplating layer can be sequentially deposited on the side of the second substrate 221 opposite to the first substrate 21 using PVD or CVD processes. The adhesion layer is, for example, titanium or chromium, with a thickness of, for example, 20–50 nm. The electroplating layer is, for example, copper, with a thickness of, for example, 0.2–0.5 μm. After electroplating, the adhesion layer and the electroplating layer are photolithographically formed to create the required redistribution layer (RDL).

[0112] Step 7: Preparation of the UBM isolation layer, as shown in h in Figure 5. Specifically, the UBM isolation layer material can be deposited by PVD or electroplating. The UBM isolation layer material can be indium or an alloy such as copper-tin, and the thickness of the UBM isolation layer is, for example, 2–15 μm.

[0113] Step 8: Fabrication of pressure-sensitive film 211, as shown in i in Figure 5. Specifically, the surface of the first substrate 51 facing away from the second substrate 221 can be thinned by grinding to form the pressure-sensitive film 211 structure.

[0114] Step 9: Solder SD preparation, as shown in j in Figure 5. Specifically, metal solder paste can be applied to the isolation layer UBM using screen printing, and then solder balls can be prepared by thermal reflow to obtain solder SD.

[0115] In this example, as shown in Figure 2, the bonding ring 212, the conductive post 214, and the varistor 213 all protrude from the pressure-sensitive film 211.

[0116] The pressure sensor shown in Figure 6 can also be fabricated using the fabrication method provided in this disclosure. As shown in Figure 6, the pressure sensor includes a first substrate 21 and a second substrate 22.

[0117] As shown in Figure 6, the first substrate 21 includes a pressure-sensitive film 211, a varistor 213 and a conductive post 214 disposed on the side of the pressure-sensitive film 211 near the second substrate 22, and a pressure-applying cavity 71 disposed on the surface of the pressure-sensitive film 211 away from the second substrate 22. The varistor 213 and the conductive post 214 are embedded within the pressure-sensitive film 211, and the varistor 213 is flush with the surface of the pressure-sensitive film 211.

[0118] As shown in Figure 6, the second substrate 22 includes a second substrate 221, lead posts 222, a redistribution layer RDL, an isolation layer UBM, and solder SD. In the direction from the first substrate 21 to the second substrate 22, the lead posts 222 are disposed through the second substrate 221. The end of the lead post 222 near the first substrate 21 abuts against a conductive post 214, and the end of the lead post 222 away from the first substrate 21 overlaps with the redistribution layer RDL. The isolation layer UBM is disposed on the side of the redistribution layer RDL away from the second substrate 221, and the solder SD is disposed on the side of the isolation layer UBM away from the second substrate 221. A groove recessed towards the redistribution layer RDL is also provided on the surface of the second substrate 221 near the first substrate 21. This groove forms a cavity 23 after the first substrate 21 and the second substrate 22 are mated.

[0119] For example, the method for fabricating the pressure sensor shown in Figure 6 specifically includes the following steps:

[0120] Step 11: Fabrication of varistor 213 and conductive pillar 214, as shown in Figure 7a. Using N(100) silicon as the first substrate 51, the required patterns for varistor 213 and conductive pillar 214 are fabricated on the surface of the first substrate 51. Specifically, photoresist can be used as a mask to implant ions (such as boron ions) into the surface of the first substrate 51. After implantation, the photoresist is removed, and the implanted silicon wafer is annealed to obtain the first substrate 21. After annealing, the sheet resistance of varistor 213 is, for example, 5–1000 Ω /

[0121] square.

[0122] In this example, the varistor 213 and the conductive post 214 are embedded in the first substrate 51, and both the varistor 213 and the conductive post 214 are flush with the surface of the first substrate 51.

[0123] This example uses a common silicon substrate 2111 to fabricate the first substrate 21, which can reduce costs.

[0124] Step 12: Fabrication of the lead hole HY, as shown in Figure 7b. BF33 or 7740 glass can be selected as the second substrate 221. Laser-induced etching technology is used to pattern the glass to form the lead hole HY. The diameter of the lead hole HY is, for example, 10-1000 μm. Specifically, the glass can first be modified by laser treatment, that is, the area to be drilled is scanned with a laser to form a modified region. Then, a wet etching method is used to etch the modified region into the desired lead hole HY.

[0125] Step 13: Fabrication of cavity 23, as shown in Figure 7c. Specifically, the second substrate 221 can be locally modified by laser, that is, the corresponding part of cavity 23 is scanned by laser to form a modified area, and then the laser modified area is etched into the desired cavity 23 by wet etching.

[0126] Step 14: The first substrate 21 and the second substrate 221 are bonded, as shown in d of Figure 7. Specifically, the first substrate 21 and the second substrate 221 can be bonded anolytically. During the bonding process, the first substrate 21 is connected to the positive terminal of the power supply, and the second substrate 221 is connected to the negative terminal of the power supply. The voltage is 200-1500V and the temperature is 100-500℃.

[0127] Step 15: Fabrication of lead post 222, as shown in Figure 7e. Specifically, an adhesive layer and an electroplating layer can be sequentially deposited on the inner wall of the lead hole HY using PVD or CVD processes. The adhesive layer is, for example, titanium or chromium, with a thickness of, for example, 20-50 nm. The electroplating layer is, for example, copper, and the electroplating layer fills the lead hole HY completely.

[0128] Step 16: Redistribution layer (RDL) fabrication, as shown in Figure 7f. Specifically, an adhesion layer and an electroplating layer can be sequentially deposited on the side of the second substrate 221 opposite to the first substrate 21 using PVD or CVD processes. The adhesion layer is, for example, titanium or chromium, with a thickness of, for example, 20–50 nm. The electroplating layer is, for example, copper, with a thickness of, for example, 0.2–0.5 μm. After electroplating, the adhesion layer and the electroplating layer are photolithographically formed to create the required redistribution layer (RDL).

[0129] Step 17: Preparation of the UBM isolation layer, as shown in g of Figure 7. Specifically, the UBM isolation layer material can be deposited by PVD or electroplating. The UBM isolation layer material can be indium or an alloy such as copper-tin, and the thickness of the UBM isolation layer is, for example, 2–15 μm.

[0130] Step 18: Fabrication of pressure-sensitive film 211. Specifically, the surface of the first substrate 51 facing away from the second substrate 221 can be thinned by grinding to obtain pressure-sensitive film 211. The thickness of pressure-sensitive film 211 is, for example, less than or equal to 300 μm, as shown in h in Figure 7. Then, the surface of pressure-sensitive film 211 facing away from the second substrate 221 is locally etched by dry or wet etching to form pressure-sensing cavity 71, as shown in i in Figure 7.

[0131] Step 19: Solder ball preparation, as shown in j in Figure 7. Specifically, solder paste can be applied to the UBM isolation layer using screen printing, and then the solder balls can be prepared by thermal reflow.

[0132] This disclosure provides a method for fabricating a pressure sensor, comprising:

[0133] Step S11: Provide a first substrate 21 and a second substrate 22. The first substrate 21 includes a first substrate 51 and a conductive post 214 disposed on one side surface of the first substrate 51. The conductive post 214 is connected to the first substrate 51. A first insulating layer 811 is disposed on the surface of the conductive post 214 away from the first substrate 51. The first insulating layer 811 disposed on the conductive post 214 has an opening. The second substrate 22 includes a second substrate 221 and a lead hole HY disposed through the second substrate 221. The lead hole HY is used to dispose of the lead post 222. The lead post 222 is insulated from the second substrate 221.

[0134] Step S12: Bond the first substrate 21 and the second substrate 22 to form a cavity 23 between the first substrate 21 and the second substrate 22. The conductive post 214 is disposed close to the second substrate 22, and the lead post 222 is connected to the conductive post 214 through an opening.

[0135] Step S13: Using a dry process, the surface of the first substrate 51 facing away from the second substrate 22 is thinned as a whole to obtain a pressure sensor. The thinned first substrate 51 is the pressure-sensing film 211 of the pressure sensor. The pressure-sensing film 211, the conductive pillar 214 and the first insulating layer 811 constitute the first capacitor plate 81 of the pressure sensor. The second substrate 22 constitutes the second capacitor plate 82 of the pressure sensor. The surface of the pressure-sensing film 211 facing away from the second substrate 22 is planar.

[0136] The preparation method provided in this disclosure, which uses a dry process to thin the first substrate 51 to form the first capacitor plate 81, is beneficial to improving the thickness accuracy, sensitivity, linearity and production efficiency of the capacitive pressure sensor.

[0137] The pressure sensor shown in Figure 8 can be prepared using the preparation method provided in this disclosure. As shown in Figure 8, the pressure sensor includes a first capacitor plate 81 and a second capacitor plate 82. The first capacitor plate 81 is a movable plate, and the second capacitor plate 82 is a fixed plate. The first capacitor plate 81 and the second capacitor plate 82, which are arranged opposite to each other, form a cavity 23.

[0138] As shown in Figure 8, the first capacitor plate 81 includes a pressure-sensitive film 211, a conductive post 214 and a bonding ring 212 disposed on the surface of the pressure-sensitive film 211 near the second capacitor plate 82, and a first insulating layer 811 disposed on the side of the conductive post 214 and the bonding ring 212 away from the pressure-sensitive film 211. The first insulating layer 811 is used to isolate the first capacitor plate 81 and the second capacitor plate 82. The first insulating layer 811 located on the conductive post 214 has a first opening H1.

[0139] As shown in Figure 8, the second capacitor plate 82 includes a second substrate 221, lead posts 222 disposed within the second substrate 221, a second insulating layer 821 disposed on the surface of the second substrate 221 facing away from the first capacitor plate 81, and a first redistribution layer RDL1, a first isolation layer UBM1, and a first solder SD1 sequentially stacked on the second insulating layer 821 facing away from the second substrate 221. The first redistribution layer RDL1 overlaps with the end of the lead post 222 facing away from the first capacitor plate 81. The end of the lead post 222 near the first capacitor plate 81 overlaps with a conductive post 214 through a first opening H1, allowing electrical signals on the first substrate 51 to be output sequentially through the conductive post 214, the lead post 222, the first redistribution layer RDL1, the first isolation layer UBM1, and the first solder SD1.

[0140] The second insulating layer 821 has a second opening H2, and the second capacitor plate 82 further includes a second redistribution layer RDL2, a second isolation layer UBM2, and a second solder SD2, which are sequentially stacked on the side of the second substrate 221 away from the first capacitor plate 81. The second redistribution layer RDL2 is connected to the second substrate 221 through the second opening H2, so that the electrical signal on the second substrate 221 is output sequentially through the second redistribution layer RDL2, the second isolation layer UBM2, and the second solder SD2.

[0141] The first isolation layer UBM1 is disposed between the first redistribution layer RDL1 and the first solder SD1, serving as a bonding layer for interconnecting the first redistribution layer RDL1 and the first solder SD1, and is used to prevent the diffusion of first solder SD1 atoms into the first redistribution layer RDL1. The second isolation layer UBM2 is disposed between the second redistribution layer RDL2 and the second solder SD2, serving as a bonding layer for interconnecting the second redistribution layer RDL2 and the second solder SD2, and is used to prevent the diffusion of second solder SD2 atoms into the second redistribution layer RDL2. The first solder SD1 and the second solder SD2 are the input or output ports of the pressure sensor, and during packaging, they also serve as a bonding structure for flip-chip bonding to the packaging substrate.

[0142] For example, the pressure value inside the body cavity 23 is the reference pressure for the pressure sensor to measure the pressure. When the external pressure value is equal to the pressure value inside the body cavity 23, the output of the pressure sensor is zero. When the external pressure is greater than the pressure inside the body cavity 23, the output of the pressure sensor is the external atmospheric pressure minus the pressure inside the body cavity 23.

[0143] For example, the method for fabricating the capacitive pressure sensor shown in Figure 8 specifically includes the following steps:

[0144] Step 21: Fabrication of the first insulating layer 811, bonding ring 212, and conductive pillar 214, as shown in Figure 9a. Low-resistivity silicon is used as the raw material for the first capacitor plate 81, and its front side is oxidized to form the first substrate 51 and the first insulating layer 811. The required bonding ring 212, conductive pillar 214, and groove for forming the cavity 23 are formed by photolithography and etching to obtain the first capacitor plate 81. The first insulating layer 811 on the conductive pillar 214 has a first opening H1.

[0145] Step 21: Fabrication of cavity 23, as shown in Figure 9b. A low-resistivity silicon substrate 88 is used as the raw material for the second capacitor plate 82, and it is hydrophilically bonded to the first capacitor plate 81 to form the cavity 23 structure.

[0146] Step 22: Fabrication of the second insulating layer 821, as shown in Figure 9c. The surface of the low-resistivity silicon substrate 88 is oxidized to form a second substrate 221 and a second insulating layer 821, the second insulating layer 821 having a second opening H2.

[0147] Step 23: Fabrication of lead post 222, as shown in d of Figure 9. A deep silicon etching process is performed on the second substrate 221 to form a through-hole structure. Then, thermal oxidation is performed inside the hole, followed by metal filling to form the lead post 222. The lead post 222 is insulated from the second substrate 221.

[0148] Step 24: Fabrication of the first redistribution layer RDL1 and the second redistribution layer RDL2, as shown in Figure 9e. Specifically, an adhesion layer and an electroplating layer can be sequentially deposited on the second insulating layer 821 using PVD or CVD processes. The adhesion layer is, for example, titanium or chromium, with a thickness of, for example, 20–50 nm. The electroplating layer is, for example, copper, with a thickness of, for example, 0.2–0.5 μm. After electroplating, the adhesion layer and the electroplating layer are photolithographically formed to create the first redistribution layer RDL1 and the second redistribution layer RDL2.

[0149] Step 25: Preparation of the first isolation layer UBM1 and the second isolation layer UBM2, as shown in Figure 9f. Specifically, the isolation layer UBM material can be deposited by PVD or electroplating. The isolation layer UBM material can be indium or an alloy material such as copper-tin. The thickness of the first isolation layer UBM1 and the second isolation layer UBM2 is, for example, 2 to 15 μm.

[0150] Step 26: Thin the first substrate 51, as shown in g in Figure 9. A dry thinning process is used to thin the surface of the first substrate 51 away from the second capacitor plate 82 using a polishing process to form a pressure-sensitive film 211.

[0151] Step 27: Solder ball preparation, as shown in h in Figure 9. Specifically, solder paste can be applied to the first isolation layer UBM1 and the second isolation layer UBM2 using screen printing, and then the solder balls are prepared by thermal reflow.

[0152] In this disclosure, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this disclosure.

[0153] In this disclosure, relational terms such as first and second are used merely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0154] In this specification, "electrical connection" and "coupling" include situations where components are connected together by elements that have some electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0155] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0156] The polygons used in this specification are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, etc. They may have minor deformations due to tolerances, and may include chamfers, fillets, curved edges, and other variations.

[0157] In this disclosure, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly specified. "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C," both including the following combinations of A, B, and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C. "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0158] The use of “for” or “configured to” in this disclosure implies an open and inclusive language that does not preclude applicability to or configuration to devices for performing additional tasks or steps.

[0159] As used in this disclosure, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0160] As used in this disclosure, "parallel," "perpendicular," "equal," and "flush" include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein an acceptable deviation range for approximate parallelism may be, for example, within 10° or 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein an acceptable deviation range for approximate perpendicularity may also be, for example, within 10° or 5°. "Equal" includes absolute equality and approximate equality, wherein an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one. "Flush" includes absolute flush and approximate flush, wherein an acceptable deviation range for approximate flush may be, for example, a distance between the flushes being less than or equal to 5% of either one's dimension.

[0161] It should be understood that when a layer or element is referred to as being disposed on one side of another layer or substrate, it may be that the layer or element is directly disposed on the other layer or substrate, or it may be that there is an intermediate layer between the layer or element and the other layer or substrate.

[0162] This disclosure describes exemplary embodiments with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown in this disclosure, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0163] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A pressure sensor, comprising a first substrate and a second substrate disposed opposite to each other, and a cavity located between the first substrate and the second substrate; The first substrate includes a pressure-sensitive film, and a bonding ring, a varistor, and a conductive post disposed on the side of the pressure-sensitive film near the second substrate. In the orthographic projection on the second substrate, the varistor is located within the cavity and is disposed near the edge of the cavity. The bonding ring is disposed on the side of the varistor away from the center of the cavity. The bonding ring is at least partially adjacent to the varistor. The varistor is connected to the conductive post. In the direction from the first substrate to the second substrate, the height of the bonding ring is greater than the height of the varistor.

2. The pressure sensor according to claim 1, wherein, The varistor, the bonding ring, and the conductive pillar are made of the same material.

3. The pressure sensor according to claim 1, wherein, The ratio of the height of the varistor to the height of the bonding ring is greater than or equal to one-tenth and less than or equal to one-twentieth.

4. The pressure sensor according to claim 1, wherein, The varistor includes two first line resistors arranged opposite each other along a first direction and two second line resistors arranged opposite each other along a second direction. The second line resistors are respectively cross-connected to the two first line resistors, and the first line resistors are respectively cross-connected to the two second line resistors. The first direction and the second direction intersect each other. The first line resistance and the second line resistance have different projected areas on the second substrate. When the pressure-sensitive membrane is not subjected to external pressure, the resistance values ​​of the first line resistance and the second line resistance are the same.

5. The pressure sensor according to claim 4, wherein, The second line stop includes a first sub-segment, a second sub-segment, and a third sub-segment. The first sub-segment is connected between the first line stop and the second sub-segment. The third sub-segment is connected between two adjacent second sub-segments. The extension direction of the second sub-segment is parallel to the extension direction of the first line stop. The extension directions of the first sub-segment and the third sub-segment intersect the extension direction of the second sub-segment.

6. The pressure sensor according to claim 5, wherein, The main material of the varistor is silicon crystal, and the extension directions of the second sub-segment and the first line resistance are parallel to the silicon crystal. <110> Crystal orientation.

7. The pressure sensor according to claim 4, wherein, The conductive post is connected to the varistor via a connecting line, and the connection point between the connecting line and the varistor is located at the intersection of the first line resistance and the second line resistance; and At the intersection of the first line resistor and the second line resistor, the conductive pillars are spaced apart between the varistor and the bonding ring; at the non-intersection of the first line resistor and the second line resistor, the varistor and the bonding ring are arranged adjacent to each other.

8. The pressure sensor according to any one of claims 1 to 7, wherein, The bonding ring is a closed ring structure that surrounds the center of the body cavity.

9. The pressure sensor according to any one of claims 1 to 7, wherein, The second substrate includes: The second substrate, lead posts, redistribution layer, isolation layer, and solder are arranged in the direction from the first substrate to the second substrate. The lead posts are disposed through the second substrate. The end of the lead post near the first substrate abuts against the conductive post. The end of the lead post away from the first substrate overlaps with the redistribution layer. The isolation layer is disposed on the side of the redistribution layer away from the second substrate. The solder is disposed on the side of the isolation layer away from the second substrate. The surface of the second substrate near the first substrate abuts against the bonding ring.

10. The pressure sensor according to claim 9, wherein, The longitudinal cross-section of the lead post is trapezoidal, and the long side of the trapezoid is located close to the redistribution layer. The longitudinal cross-section is the cross-section of the lead post perpendicular to the second substrate.

11. The pressure sensor according to claim 10, wherein, The angle between the long side and the hypotenuse of the trapezoid is greater than or equal to 80° and less than or equal to 90°.

12. The pressure sensor according to any one of claims 1 to 7, wherein, The surface of the pressure-sensitive membrane facing away from the second substrate is a plane.

13. A method for manufacturing a pressure sensor, comprising: A first substrate and a second substrate are provided. The first substrate includes a first substrate, and a varistor and a conductive pillar disposed on one surface of the first substrate. The varistor is connected to the conductive pillar. Next, the second substrate includes a second substrate and a lead hole disposed through the second substrate, the lead hole being used to provide lead posts; The first substrate and the second substrate are bonded together to form a cavity between the first substrate and the second substrate. The varistor and the conductive post are disposed close to the second substrate. The lead post overlaps with the conductive post. In the orthographic projection on the second substrate, the varistor is located within the cavity and is disposed close to the edge of the cavity. A pressure sensor is obtained by using a dry process to thin the surface of the first substrate away from the second substrate. The thinned first substrate is the pressure-sensing film of the pressure sensor, and the surface of the pressure-sensing film away from the second substrate is planar.

14. The preparation method according to claim 13, wherein, After the step of performing overall thinning of the surface of the first substrate away from the second substrate using a dry process, the method further includes: The surface of the pressure-sensitive film facing away from the second substrate is partially etched to form a pressure-guiding cavity. In the orthogonal projection on the second substrate, the varistor is located within the range of the pressure-guiding cavity and is disposed close to the edge of the pressure-guiding cavity.

15. A method for manufacturing a pressure sensor, comprising: A first substrate and a second substrate are provided. The first substrate includes a first substrate and a conductive post disposed on one side surface of the first substrate. The conductive post is connected to the first substrate. A first insulating layer is disposed on the surface of the conductive post away from the first substrate. The first insulating layer disposed on the conductive post has an opening. The second substrate includes a second substrate and a lead hole disposed through the second substrate. The lead hole is used to dispose of the lead post. The lead post is insulated from the second substrate. The first substrate and the second substrate are bonded together to form a cavity between the first substrate and the second substrate. The conductive post is disposed close to the second substrate, and the lead post is connected to the conductive post through the opening. A pressure sensor is obtained by using a dry process to thin the surface of the first substrate away from the second substrate. The thinned first substrate is the pressure-sensing membrane of the pressure sensor. The pressure-sensing membrane, the conductive pillar, and the first insulating layer constitute the first capacitor plate of the pressure sensor. The second substrate constitutes the second capacitor plate of the pressure sensor. The surface of the pressure-sensing membrane away from the second substrate is planar.

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